MAX3885ECB-T [MAXIM]
Serial to Parallel/Parallel to Serial Converter, 1-Func, PQFP64, TQFP-64;
| 型号： | MAX3885ECB-T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Serial to Parallel/Parallel to Serial Converter, 1-Func, PQFP64, TQFP-64 |
| 文件： | 总8页 (文件大小：127K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4767; Rev 2; 1/99
+3 .3 V, 2 .4 8 8 Gb p s , S DH/S ONET
1 :1 6 De s e ria lize r w it h LVDS Ou t p u t s
MAX385
Ge n e ra l De s c rip t io n
Fe a t u re s
The MAX3885 d e s e ria lize r is id e a l for c onve rting
2.488Gbps serial data to 16-bit wide, 155Mbps parallel
data in SDH/SONET applications. Operating from a sin-
g le +3.3V s up p ly, this d e vic e a c c e p ts PECL s e ria l
clock and data inputs, and delivers low-voltage differ-
ential-signal (LVDS) clock and data outputs for interfac-
ing with high-speed digital circuitry. It also provides an
LVDS synchronization input that enables data realign-
ment and reframing. The MAX3885 is available in the
extended temperature range (-40°C to +85°C) in a 64-
pin TQFP package.
♦ Single +3.3V Supply
♦ 2.488Gbps Serial to 155Mbps Parallel Conversion
♦ 660mW Operating Power
♦ LVDS Data Outputs and Synchronization Inputs
♦ Self-Biasing PECL Inputs Ease AC Coupling
♦ Synchronization Inputs for Data Realignment and
Reframing
Ap p lic a t io n s
2.488Gbps SDH/SONET Transmission Systems
Add/Drop Multiplexers
Ord e rin g In fo rm a t io n
PART
TEMP. RANGE
PIN-PACKAGE
MAX3885ECB
-40°C to +85°C
64 TQFP
Digital Cross Connects
Pin Configuration appears at end of data sheet.
Typ ic a l Op e ra t in g Circ u it
V
CC
= +3.3V
V
CC
= +3.3V
V
CC
V
CC
= +3.3V
PD15+
PD15-
133Ω
133Ω
100Ω*
SD+
SD-
OVERHEAD
TERMINATION
MAX3875
•
•
•
86.6Ω
86.6Ω
MAX3885
DATA
AND
PD0+
SERIAL DATA
INPUTS
CLOCK
RECOVERY
100Ω*
100Ω*
V
= +3.3V
CC
PD0-
133Ω
133Ω
PCLK+
SCLK+
SCLK-
PCLK-
SYNC+
SYNC-
86.6Ω
86.6Ω
GND
*REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION.
THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z = 50Ω.
0
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
+3 .3 V, 2 .4 8 8 Gb p s , S DH/S ONET
1 :1 6 De s e ria lize r w it h LVDS Ou t p u t s
ABSOLUTE MAXIMUM RATINGS
Positive Supply Voltage (V )...............................-0.5V to +7.0V
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-60°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
CC
Input Voltage Level (all inputs)...................-0.5V to (V + 0.5V)
CC
Output Current LVDS outputs .............................................10mA
Continuous Power Dissipation (T = +85°C)
A
TQFP (derate 24mW/°C above +85°C).......................1000mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
MAX385
DC ELECTRICAL CHARACTERISTICS
(V = +3.0V to +3.6V, differential loads = 100Ω ±1%, T = -40°C to +85°C, unless otherwise noted. Typical values are at V = +3.3V,
CC
A
CC
T
A
= +25°C.)
PARAMETER
Supply Current
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I
CC
200
280
mA
PECL INPUTS (SD+/-, SCLK+/-)
Input High Voltage
V
V
- 1.16
V - 0.88
CC
V
V
IH
CC
Input Low Voltage
V
IL
V
CC
- 1.81
V
- 1.48
CC
Input High Current
I
V
= V
IH(MAX)
-900
900
µA
µA
IH
IN
Input Low Current
I
V
IN
= V
IL(MIN)
-900
900
IL
LVDS INPUTS AND OUTPUTS (SYNC+/-, PCLK+/-, PD_+/-)
Input Voltage Range
V
Differential input voltage = 100mV
Common-mode voltage = 50mV
0
2.4
V
mV
mV
Ω
I
Differential Input Threshold
Threshold Hysteresis
V
-100
100
IDTH
V
78
HYST
Differential Input Resistance
Output High Voltage
R
85
100
115
IN
V
OH
1.475
V
Output Low Voltage
V
0.925
250
V
OL
OD
V
Differential Output Voltage
Figure 1
400
±25
1.275
±25
140
mV
Change in Magnitude of Differential
Output Voltage for Complementary
States
∆ V
mV
V
OD
Output Offset Voltage
V
OS
1.125
40
Change in Magnitude of Output
Offset Voltage for Complementary
States
∆V
mV
Ω
OS
O
Single-Ended Output Resistance
R
95
Change in Magnitude of Single-
Ended Output Resistance for
Complementary Outputs
∆R
±2.5
±10
%
O
AC ELECTRICAL CHARACTERISTICS
(V = +3.0V to +3.6V, differential loads = 100Ω ±1%, T = -40°C to +85°C, unless otherwise noted. Typical values are at V = +3.3V,
CC
A
CC
T
A
= +25°C.) (Note 1, Figure 4)
PARAMETER
SYMBOL
CONDITIONS
MIN
2.488
100
TYP
MAX
UNITS
GHz
ps
Maximum Serial Clock Frequency
Serial Data Setup Time
f
SCLK
t
SU
Serial Data Hold Time
t
100
ps
H
Parallel Clock-to-Data Output Delay
t
200
450
900
ps
CLK-Q
Note 1: AC Characteristics guaranteed by design and characterization.
_______________________________________________________________________________________
2
+3 .3 V, 2 .4 8 8 Gb p s , S DH/S ONET
1 :1 6 De s e ria lize r w it h LVDS Ou t p u t s
MAX385
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(V = +3.3V, T = +25°C, unless otherwise noted.)
CC
A
SERIAL DATA-HOLD TIME
vs. TEMPERATURE
MAXIMUM SERIAL CLOCK FREQUENCY
vs. TEMPERATURE
SERIAL DATA-SETUP TIME
vs. TEMPERATURE
0
-20
4.4
100
80
V
CC
= 3.6V
4.3
4.2
4.1
4.0
V
CC
= 3V
-40
60
40
20
0
-60
-80
-100
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
PARALLEL CLOCK TO DATA OUTPUT
PROPAGATION DELAY vs. TEMPERATURE
SUPPLY CURRENT vs. TEMPERATURE
300
250
200
700
600
V
= 3.6V
CC
500
400
300
200
V
= 3V
CC
150
100
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
3
+3 .3 V, 2 .4 8 8 Gb p s , S DH/S ONET
1 :1 6 De s e ria lize r w it h LVDS Ou t p u t s
P in De s c rip t io n
PIN
NAME
FUNCTION
1, 2, 8, 16, 17,
24, 32, 33, 41,
48, 49, 57, 64
GND
Ground
3, 5, 7, 9, 11,
13, 25, 34, 42,
47, 56
V
CC
+3.3V Supply Voltage
MAX385
Serial Data Noninverting PECL Input. Data is clocked on the SCLK signal’s positive transi-
tion.
4
SD+
6
SD-
Serial Data Inverting PECL Input. Data is clocked on the SCLK signal’s positive transition.
Serial Clock Noninverting PECL Input
10
12
SCLK+
SCLK-
Serial Clock Inverting PECL Input
Synchronizing Pulse Inverting LVDS Input. Pulse the SYNC signal high for at least four SCLK
periods to shift the data alignment by dropping one bit.
14
15
SYNC-
SYNC+
Synchronizing Pulse Noninverting LVDS Input. Pulse the SYNC signal high for at least four
SCLK periods to shift the data alignment by dropping one bit.
18
19
PCLK-
PCLK+
Parallel Clock Inverting LVDS Output
Parallel Clock Noninverting LVDS Output
20, 22, 26, 28,
30, 35, 37, 39,
43, 45, 50, 52,
54, 58, 60, 62
Parallel Data Inverting LVDS Outputs. Data is updated on the negative transition of the PCLK
signal.
PD0- to PD15-
PD0+ to PD15+
21, 23, 27, 29,
31, 36, 38, 40,
44, 46, 51, 53,
55, 59, 61, 63
Parallel Data Noninverting LVDS Outputs. Data is updated on the negative transition of the
PCLK signal.
PD+
V
V
OD
R = 100Ω
L
D
PD-
V
PD-
V
OH
V
SINGLE-ENDED OUTPUT
V
| OD|
OS
V
PD+
V
OL
+V
OD
V
- V
PD+ PD-
0V
0V (DIFF.)
V
OD, P - P
= V - V
PD+ PD-
DIFFERENTIAL OUTPUT
-V
OD
Figure 1. Driver Output Levels
4
_______________________________________________________________________________________
+3 .3 V, 2 .4 8 8 Gb p s , S DH/S ONET
1 :1 6 De s e ria lize r w it h LVDS Ou t p u t s
MAX385
shift register continuously clocks incoming data on the
positive transition of the serial clock (SCLK) input sig-
De t a ile d De s c rip t io n
The MAX3885 deserializer uses a 16-bit shift register,
nal. The 4-bit counter generates a parallel-output clock
(PCLK) by dividing the serial-clock frequency by 16.
The PCLK signal clocks the parallel-output register.
During normal operation, the counter divides the SCLK
frequency by 16, causing the output register to latch
every 16 bits of incoming serial data. The synchroniza-
tion inputs (SYNC+, SYNC-) realign and reframe data.
When the SYNC signal is pulsed high for at least four
SCLK cycles, the parallel output data is delayed by one
SCLK cycle. This realignment is guaranteed to occur
within two complete PCLK cycles of the SYNC signal’s
positive transition. As a result, the first incoming bit of
data during that PCLK cycle is dropped, shifting the
alignment between PCLK and data by one bit. See
Figure 3 for the timing diagram and Figure 4 for the tim-
ing parameters diagram.
16-bit parallel output register, 4-bit counter, PECL input
b uffe rs , a nd low-volta g e d iffe re ntia l-s ig na l (LVDS)
input/output buffers to convert 2.488Gbps serial data to
16-bit wide, 155Mbps parallel data (Figure 2). The input
PD15+
PD15-
SD+
SD-
PECL
PECL
LVDS
16-BIT
SHIFT
REGISTER
16-BIT
PARALLEL
OUTPUT
SCLK+
SCLK-
REGISTER
PD1+
PD1-
LVDS
LVDS
LVDS
MAX3885
Lo w -Vo lt a g e Diffe re n t ia l-S ig n a l (LVDS )
In p u t s a n d Ou t p u t s
PD0+
PD0-
The MAX3885 features LVDS inputs and outputs for
interfacing with high-speed digital circuitry. The LVDS
standard is based on the IEEE 1596.3 LVDS specifica-
tion. This technology uses 500mVp-p to 800mVp-p dif-
ferential low-voltage swings to achieve fast transition
times, minimize power dissipation, and improve noise
immunity. The parallel clock and data LVDS outputs
(PCLK+, PCLK-, PD_+, PD_-) require 100Ω differential
SYNC+
SYNC-
PCLK+
PCLK-
4-BIT
COUNTER
LVDS
100Ω
Figure 2. Functional Diagram
D15 D14
D13
SCLK
SD
SYNC
PCLK
D0
D1
D16
D32
D33
D48
D49
D65
D66
(LSB) PD0
PD1
D17
D31
•
•
•
ONE BIT HAS SLIPPED
IN THIS TIME SLICE
D15
D47
D64
D80
PD15
(MSB)
TRANSMITTED FIRST
Figure 3. Timing Diagram
_______________________________________________________________________________________
5
+3 .3 V, 2 .4 8 8 Gb p s , S DH/S ONET
1 :1 6 De s e ria lize r w it h LVDS Ou t p u t s
t
= 1 / f
SCLK
SCLK
SCLK
t
SU
t
H
SD
MAX385
PCLK
t
CLK-Q
PD0–PD15
NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-).
Figure 4. Timing Parameters
DC termination between the inverting and noninverting
outputs for proper operation. Do not terminate these
outputs to ground. The synchronization LVDS inputs
(SYNC+, SYNC-) are internally terminated with 100Ω
d iffe re ntia l inp ut re s is ta nc e a nd , the re fore , d o not
require external termination.
THEVENIN-EQUIVALENT TERMINATION
+3.3V
133Ω
133Ω
MAX3885
Z = 50Ω
O
P ECL In p u t s
Because of the self-biasing resistor networks, the serial
data and clock PECL inputs (SD+, SD-, SCLK+, SCLK-)
PECL
INPUTS
Z = 50Ω
O
require 53Ω termination to V
- 2V when interfacing
CC
with a PECL s ourc e (s e e Alte rna tive PECL Inp ut
Termination). This results in an equivalent input resis-
tance of 50Ω.
86.6Ω
86.6Ω
Ap p lic a t io n s In fo rm a t io n
ECL AC-COUPLING TERMINATION
Alt e rn a t ive P ECL In p u t Te rm in a t io n
Fig ure 5 s hows a lte rna tive PECL inp ut-te rmina tion
methods. Use Thevenin-equivalent termination when a
V
- 2V termination voltage is not available. When
CC
Z = 50Ω
O
interfacing with an ECL-output device, the MAX3885’s
internal self-biasing allows easy ECL AC-coupling ter-
mination.
MAX3885
53Ω
53Ω
PECL
INPUTS
La yo u t Te c h n iq u e s
For best performance, use good high-frequency layout
techniques. Filter voltage supplies and keep ground
connections short. Use multiple vias where possible.
Also, use controlled impedance transmission lines to
interface with the MAX3885 high-speed inputs and out-
puts.
-2V
-2V
Z = 50Ω
O
Figure 5. Alternative PECL Input Termination
6
_______________________________________________________________________________________
+3 .3 V, 2 .4 8 8 Gb p s , S DH/S ONET
1 :1 6 De s e ria lize r w it h LVDS Ou t p u t s
MAX385
P in Co n fig u ra t io n
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
GND 49
PD10- 50
PD10+ 51
PD11- 52
PD11+ 53
PD12- 54
PD12+ 55
32 GND
31 PD4+
30 PD4-
29 PD3+
28 PD3-
27 PD2+
26 PD2-
V
CC
56
25 V
CC
MAX3885
GND 57
PD13- 58
PD13+ 59
PD14- 60
PD14+ 61
PD15- 62
PD15+ 63
GND 64
24 GND
23 PD1+
22 PD1-
21 PD0+
20 PD0-
19 PCLK+
18 PCLK-
17 GND
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
TQFP
___________________Ch ip In fo rm a t io n
TRANSISTOR COUNT: 2820
_______________________________________________________________________________________
7
+3 .3 V, 2 .4 8 8 Gb p s , S DH/S ONET
1 :1 6 De s e ria lize r w it h LVDS Ou t p u t s
P a c k a g e In fo rm a t io n
MAX385
8
_______________________________________________________________________________________
相关型号：
MAX3886
Multirate CDR with Integrated Serializer/Deserializer for GPON and BPON ONT Applications
MAXIM
MAX3886ETN
Multirate CDR with Integrated Serializer/Deserializer for GPON and BPON ONT Applications
MAXIM
MAX3886ETN+
ATM/SONET/SDH Support Circuit, 1-Func, BICMOS, 8 X 8 MM, 0.80 MM HEIGHT, LEAD FREE, MO-220, TQFN-56
MAXIM
MAX388CPN+
Single-Ended Multiplexer, 1 Func, 8 Channel, CMOS, PDIP18, ROHS COMPLIANT, PLASTIC, DIP-18
MAXIM
MAX388CWG+T
Single-Ended Multiplexer, 1 Func, 8 Channel, CMOS, PDSO24, ROHS COMPLIANT, SOIC-24
MAXIM
©2020 ICPDF网 联系我们和版权申明