MAX3940 [MAXIM]
10Gbps EAM Driver with Integrated Bias Network ; 10Gbps EAM驱动器，带有偏置网络\n
| 型号： | MAX3940 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 10Gbps EAM Driver with Integrated Bias Network
|
| 文件： | 总13页 (文件大小：351K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2730; Rev 0; 1/03
10Gbps EAM Driver with Integrated
Bias Network
General Description
Features
The MAX3940 is designed to drive an electro-absorp-
tion modulator (EAM) at data rates up to 10.7Gbps. It
incorporates the functions of a biasing circuit and a
modulation circuit, with integrated control op amps
externally programmed by DC voltages.
ꢀ On-Chip Bias Network
ꢀ 23ps Edge Speed
ꢀ Programmable Modulation Voltage Up to 3V
P-P
ꢀ Programmable EAM Biasing Voltage Up to 1.25V
ꢀ Selectable Data-Retiming Latch
ꢀ Up to 10.7Gbps Operation
The integrated bias circuit provides a programmable
biasing current up to 50mA. This bias current reflects a
bias voltage of up to 1.25V on an external 50Ω load. The
bias and modulation circuits are internally connected on
chip, eliminating the need for an external bias inductor.
ꢀ Integrated Modulation and Biasing Functions
ꢀ 50Ω On-Chip Input and Output Terminations
ꢀ Pulse-Width Adjustment
A high-bandwidth, fully differential signal path is internally
implemented to minimize jitter accumulation. When a
clock signal is available, the integrated data-retiming
function can be selected to reject input-signal jitter.
ꢀ Enable and Polarity Controls
ꢀ ESD Protection
The MAX3940 receives differential CML signals (ground
referenced) with on-chip line terminations of 50Ω. The
output has a 50Ω resistor for back termination and is
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
able to deliver a modulation current of 40mA
to
P-P
MAX3940E/D
-40°C to +85°C
Dice*
120mA , with an edge speed of 23ps (typical, 20% to
P-P
*Dice are designed to operate over a -40°C to +120°C junction
temperature (T ) range, but are tested and guaranteed at
80%). This modulation current reflects an EAM modula-
J
tion voltage of 1.0V
to 3.0V
.
P-P
P-P
T
A
= +25°C only.
The MAX3940 also includes an adjustable pulse-width
control circuit to precompensate for asymmetrical EAM
characteristics.
Applications
SONET OC-192 and SDH STM-64 Transmission
Systems
DWDM Systems
Long/Short-Reach Optical Transmitters
10Gbps Ethernet
Typical Application Circuit
-5.2V
PLRT
MODEN
RTEN
GND
0.01µF
50Ω
50Ω
DATA+
DATA-
DATA+
DATA-
EAM
0.01µF
MAX3952
10Gbps
SERIALIZER
MAX3940
0.01µF
0.01µF
50Ω
50Ω
CLK+
CLK-
CLK+
50Ω
OUT
CLK-
PWC+
PWC-
MODSET BIASSET
V
EE
2kΩ
+
+
V
V
MODSET
-
BIASSET
-
-5.2V
330pF
0.1µF
-5.2V
-5.2V
REPRESENTS A CONTROLLED-IMPEDANCE TRANSMISSION LINE.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
10Gbps EAM Driver with Integrated
Bias Network
ABSOLUTE MAXIMUM RATINGS
Supply Voltage V
..............................................-6.0V to +0.5V
Current into or out of OUT..............................……………...80mA
Storage Temperature Range .....................……-55°C to +150°C
Operating Junction Temperature Range....……-55°C to +150°C
Processing Temperature (die)....................………………+400°C
EE
Voltage at MODEN,
RTEN, PLRT, MODSET, BIASSET ...........(V - 0.5V) to +0.5V
EE
Voltage at DATA+, DATA-, CLK+, and CLK-……-1.65V to +0.5V
Voltage at OUT .............................................……….-4V to +0.5V
Voltage at PWC+, PWC-...................(V - 0.5V) to (V + 1.7V)
EE
EE
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = -5.5V to -4.9V, T = -40°C to +85°C. Typical values are at V = -5.2V, I
= 30mA, I = 100mA, and T = +25°C, unless
MOD A
EE
A
EE
BIAS
otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
-4.9
170
195
UNITS
Power-Supply Voltage
V
-5.5
V
EE
Retime disabled
Retime enabled
122
139
12
Excluding I
and
BIAS
Supply Current
I
EE
mA
dB
I
(Note 1)
MOD
Power-Supply Noise Rejection
SIGNAL INPUT (Note 3)
Input Data Rates
PSNR
f ≤ 10MHz (Note 2), see Figure 4
NRZ
10.7
50
Gbps
Single-Ended Input Resistance
R
V
Input to GND (Note 3)
DC-coupled, Figure 1a
AC-coupled, Figure 1b
DC-coupled (Note 4)
AC-coupled (Note 4)
42.5
-1
58.5
0
Ω
IN
Single-Ended Input Voltage
Differential Input Voltage
Differential Input Return Loss
V
IS
-0.4
0.2
0.2
+0.4
2.0
1.6
V
V
P-P
ID
≤ 10GHz
17
10
RL
(Note 3)
dB
IN
10GHz < f ≤ 15GHz
EAM BIAS
Maximum Bias Current
Minimum Bias Current
BIASSET Voltage Range
Equivalent Bias Resistance
V
V
= V + 2V
50
55
mA
mA
V
BIASSET
BIASSET
EE
= V
0.3
1
EE
V
V
V
+ 2
EE
BIASSET
EE
R
(Note 5)
36.4
Ω
BSEQV
V
V
V
V
V
= V + 0.11V
2.1
8.8
3.9
BIASSET
BIASSET
BIASSET
BIASSET
BIASSET
EE
Bias-Current-Setting Accuracy
T
= +25°C
= V + 0.36V
11.2
58
mA
A
EE
= V + 2.0V
52
EE
< V + 0.36V
-1300
-480
+1300
+480
Bias-Current Temperature
Stability
EE
(Note 6)
ppm/°C
kΩ
≥ V + 0.36V
EE
BIASSET Input Resistance
20
5
50Ω driver load, V
Figure 2
= V + 0.55V,
EE
BIASSET
BIASSET Bandwidth
MHz
EAM MODULATION
Maximum Modulation Current
Minimum Modulation Current
MODSET Voltage Range
V
V
= V + 1V
120
127
38
mA
mA
MODSET
MODSET
EE
P-P
= V
40
EE
P-P
V
V
V + 1
EE
V
MODSET
EE
Equivalent Modulation Resistance
R
(Note 7)
11.1
Ω
MODEQV
2
_______________________________________________________________________________________
10Gbps EAM Driver with Integrated
Bias Network
ELECTRICAL CHARACTERISTICS (continued)
(V = -5.5V to -4.9V, T = -40°C to +85°C. Typical values are at V = -5.2V, I
= 30mA, I = 100mA, and T = +25°C, unless
MOD A
EE
A
EE
BIAS
otherwise noted.)
PARAMETER
Modulation Set Bandwidth
MODSET Input Resistance
SYMBOL
CONDITIONS
MIN
TYP
5
MAX
UNITS
MHz
Modulation depth 10%, 50Ω driver load,
see Figure 2
20
kΩ
Modulation-Current Temperature
Stability
(Note 6)
-480
+480
ppm/°C
Modulation-Current Setting Error
Output Resistance
50Ω driver load, T = +25°C
-5
+5
%
A
R
OUT to GND
42.5
50
58.5
Ω
OUT
BIASSET = V , MODEN = V , MODSET =
EE
EE
Total Off Current
1
mA
dB
V
, DATA+ = high, DATA- = low
EE
I
I
= 30mA,
= 50mA
BIAS
MOD
Output Return Loss
RL
≤ 5GHz
8
OUT
Output Edge Speed
20% to 80% (Notes 6, 8)
Figure 3 (Note 6)
(Notes 6, 8)
23
32
ps
ps
ps
Setup/Hold Time
t
, t
SU HD
25
20
Pulse-Width Adjustment Range
50
Pulse-Width Control Input Range
(Single Ended)
V
+
0.5
V
+
EE
1.5
EE
For PWC+ and PWC-
(PWC+) - (PWC-)
V
Pulse-Width Control Input Range
(Differential)
-0.5
-10
+0.5
V
Output Overshoot
δ
(Notes 6, 8)
+10
1.1
14
%
Driver Random Jitter
Driver Deterministic Jitter
CONTROL INPUTS
RJ
(Note 6)
0.3
6.8
ps
RMS
DR
DR
DJ
PWC- = GND (Notes 6, 9)
ps
P-P
V
+
2.0
EE
Input High Voltage
V
(Note 10)
V
IH
V
+
0.8
EE
Input Low Voltage
Input Current
V
(Note 10)
(Note 10)
V
IL
-80
+80
µA
Note 1: Supply current remains elevated once the retiming function has been enabled. Power must be cycled to reduce supply
current after the retiming function has been disabled.
Note 2: Power-supply noise rejection is specified as PSNR = 20Log(V
/ ∆V
). V
is the voltage across a 50Ω load.
OUT
noise (on Vcc)
OUT
V
= 100mV
.
noise (on Vcc)
P-P
Note 3: For DATA+, DATA-, CLK+, and CLK-.
Note 4: CLK input characterized at 10.7Gbps
Note 5: R
= (V
- V ) / I
with MODEN = V , DATA+ = high, and DATA- = low.
OUT EE
BSEQV
BIASSET
EE
Note 6: Guaranteed by design and characterization using the circuit shown in Figure 4.
Note 7: R = (V - V ) / (I - 37mA) with BIASSET = V
.
EE
MODEQV
MODSET
EE
OUT
Note 8: 50Ω load, characterized at 10.7Gbps with a 1111 1111 0000 0000 pattern.
Note 9: Deterministic jitter is defined as the arithmetic sum of PWD (pulse-width distortion) and PDJ (pattern-dependent jitter).
7
Measured with a 10.7Gbps 2 - 1 PRBS pattern with eighty 0s and eighty 1s inserted in the data pattern.
Note 10: For MODEN and PLRT.
_______________________________________________________________________________________
3
10Gbps EAM Driver with Integrated
Bias Network
Test Circuits and Timing Diagrams
0V
100mV
1.0V
(a) DC-COUPLED SINGLE-ENDED CML INPUT
800mV
-0.5V
-1.0V
0.4V
0V
100mV
-0.4V
(b) AC-COUPLED SINGLE-ENDED (CML OR PECL) INPUT
Figure 1. Definition of Single-Ended Input Voltage Range
0V
0V
V
V
V
OUT
OUT
BIASSET
(c) RESULT OF MODULATING BIASSET
AND MODSET 180° OUT OF PHASE
(a) MODULATING BIASSET
0V
V
V
mW
OUT
P
OUT
MODSET
(d) RESULTING OPTICAL OUTPUT
(b) MODULATING MODSET
NOTE: ALL AMPLITUDES ARE RELATIVE
Figure 2. Modulating BIASSET and MODSET pads
4
_______________________________________________________________________________________
10Gbps EAM Driver with Integrated
Bias Network
Test Circuits and Timing Diagrams (continued)
CLK+
V
V
= 0.1V TO 1V
P-P
IS
IS
P-P
DC-COUPLED
CLK-
t
t
HD
0.1V TO 0.8V
SU
P-P
P-P
AC-COUPLED
DATA-
DATA+
(DATA+) -
(DATA-)
V
= 0.2V TO 2V
P-P
DC-COUPLED
ID
P-P
0.2V TO 1.6V
P-P
P-P
AC-COUPLED
I
OUT
I
I
= 40mA TO 120mA
P-P
MOD
BIAS
P-P
= 0mA TO 50mA
NOTE: I
RELATES TO RETIMED DATA
OUT
Figure 3. Setup and Hold Timing Definition
GND
R
OUT
50Ω
50Ω
50Ω
OSCILLOSCOPE
OUT
50Ω
50Ω
50Ω
50Ω
50Ω
DATA+
PATTERN
GENERATOR
Z
L
50Ω
DATA-
I
I
BIAS
MOD
MAX3940
V
V
EE
EE
V
EE
MODSET
BIASSET
-5.2V
0.1µF
300pF
V
V
EE
EE
Figure 4. AC Characterization Circuit
_______________________________________________________________________________________
5
10Gbps EAM Driver with Integrated
Bias Network
Test Circuits and Timing Diagrams (continued)
VOLTAGE
GND
V
BIAS
V
MOD
V
OUT
USABLE RANGE
V
+ 1.67V
EE
BELOW USABLE RANGE
Figure 5. Bias and Modulation Relationship to EAM Voltage
Typical Operating Characteristics
(Typical values are at V = -5.2V, I
= 30mA, I
= 100mA, T = +25°C, unless otherwise noted.)
EE
BIAS
MOD A
10Gbps ELECTRICAL EYE DIAGRAM
10Gbps ELECTRICAL EYE DIAGRAM
= 1V , 231 - 1 PRBS)
P-P
(V
= 3V , 231 - 1 PRBS)
P-P
(V
10.3Gbps OPTICAL EYE DIAGRAM
MOD
MOD
ASIP, INC.
20ps/div
20ps/div
20ps/div
PULSE WIDTH vs. R
PWC
SUPPLY CURRENT vs. TEMPERATURE
R
(Ω)
PWC-
(50Ω LOAD, EXCLUDES I
, I
)
BIAS MOD
2000 1750 1500 1250 1000 750 500 250
0
170
160
150
140
130
120
110
100
850
840
830
820
810
800
790
780
770
760
750
MEASURED AT 1.25Gbps
WITH A 1010 PATTERN
RETIMING ENABLED
RETIMING DISABLED
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
0
250 500 750 1000 1250 1500 1750 2000
(Ω)
R
PWC+
TEMPERATURE (°C)
6
_______________________________________________________________________________________
10Gbps EAM Driver with Integrated
Bias Network
Typical Operating Characteristics (continued)
(Typical values are at V = -5.2V, I
= 30mA, I
= 100mA, T = +25°C, unless otherwise noted.)
EE
BIAS
MOD A
V
vs. V
MODSET
(Z = 50Ω)
L
PULSE-WIDTH DISTORTION
vs. TEMPERATURE
MOD
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
IS RELATIVE TO V
MODSET
EE
0
0.25
0.50
0.75
1.00
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
V
(V)
TEMPERATURE (°C)
MODSET
V
vs. V
BIASSET
(Z = 50Ω)
L
BIAS
POWER-SUPPLY NOISE REJECTION
vs. FREQUENCY
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
-1.6
30
V
IS RELATIVE TO V
EE
BIASSET
25
20
15
10
5
0
0
0.5
1.0
1.5
(V)
2.0
2.5
1000
0.1
1
10
100
10,000
V
FREQUENCY (kHz)
BIASSET
DIFFERENTIAL S
vs. FREQUENCY
S
vs. FREQUENCY
11
22
(DEVICE POWERED)
0
-5
0
-5
-10
-15
-20
-25
-30
-35
-40
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10
FREQUENCY (GHz)
FREQUENCY (GHz)
_______________________________________________________________________________________
7
10Gbps EAM Driver with Integrated
Bias Network
Pad Description
PAD
NAME
FUNCTION
BP1, BP2,
BP4, BP5,
BP7–BP12,
BP14, BP15,
BP17–BP24,
BP26, BP27,
BP28
GND
Ground. All pads must be connected to board ground.
BP3
BP6
DATA+
DATA-
CLK+
CLK-
Noninverting Data Input, with 50Ω On-Chip Termination
Inverting Data Input, with 50Ω On-Chip Termination
BP13
BP16
BP25
Noninverting Clock Input for Data Retiming, with 50Ω On-Chip Termination
Inverting Clock Input for Data Retiming, with 50Ω On-Chip Termination
OUT
Driver Output. Provides both modulation and bias output. DC-couple to EAM.
TTL/CMOS Modulation Enable Input. Set low or float for normal operation. Set high to put the EAM
BP29
MODEN
RTEN
in the absorption (logic 0) state. Contains an internal 100kΩ pulldown to V
.
EE
BP30
BP31
Data-Retiming Input. Connect to V for retimed data. Connect to GND to bypass retiming latch.
EE
BIASSET Bias Current Set. Apply a voltage to set the bias current of the driver output.
BP32
BP33–BP41
BP42
MODSET Modulation Current Set. Apply a voltage to set the modulation current of the driver output.
V
Negative Supply Voltage. All pads must be connected to V
.
EE
EE
PWC+
PWC-
Positive Input for Modulation Pulse-Width Adjustment (see the Design Procedure section).
Negative Input for Modulation Pulse-Width Adjustment. Ground to disable the pulse-width
adjustment feature (see the Design Procedure section).
BP43
BP44
Differential Data Polarity Swap Input. Set high or float for normal operation. Set low to invert the
differential signal polarity. Contains an internal 100kΩ pullup to GND.
PLRT
Polarity Switch
Detailed Description
The MAX3940 includes a polarity switch. When the
PLRT pad is high or left floating, the output maintains
the polarity of the input data. When the PLRT pad is
low, the output is inverted relative to the input data.
The MAX3940 EAM driver consists of two main parts: a
high-speed modulation driver and an EAM-biasing
block. The clock and data inputs to the driver are com-
patible with PECL and CML logic levels. The modula-
tion and bias current are output through the OUT pad.
Clock/Data Input Logic Levels
The MAX3940 is directly compatible with ground-refer-
ence CML. Either DC- or AC-coupling may be used for
CML referenced to ground. For all other logic types,
AC-coupling should be used.
The modulation output stage is composed of a high-
speed differential pair and a programmable current
source with a maximum modulation current of 120mA.
The rise and fall times are typically 23ps. The modulation
current is designed to produce an EAM voltage up to
Optional Data Input Latch
To reject pattern-dependent jitter in the input data, a syn-
chronous differential clock signal should be connected to
the CLK+ and CLK- inputs, and the RTEN control input
3.0V
when driving a 50Ω module. The 3.0V
results
P-P
P-P
from 120mA
through the parallel combination of the
P-P
50Ω EAM load and the internal 50Ω back termination.
should be connected to V
.
EE
8
_______________________________________________________________________________________
10Gbps EAM Driver with Integrated
Bias Network
The input data is retimed on the rising edge of CLK+. If
RTEN is connected to ground, the retiming function is dis-
abled and the input data is directly connected to the out-
put stage. Leave CLK+ and CLK- open when retiming is
disabled.
Z
Z
× R
OUT
+ R
OUT
L
L
V
≈ I
×
BIAS
BIAS
To program the desired bias current, force a voltage at
the BIASSET pad (see the Typical Application Circuit).
Pulse-Width Control
The pulse-width control circuit can be used to compen-
sate for pulse-width distortion introduced by the EAM.
The differential voltage between PWC+ and PWC-
adjusts the pulse-width compensation. The adjustment
range is typically 50ps. Optional single-ended opera-
tion is possible by forcing a voltage on the PWC+ pad
while leaving the PWC- pad unconnected. When PWC-
is connected to ground, the pulse-width control circuit
is automatically disabled.
The resulting I
current can be calculated by the fol-
BIAS
lowing equation:
V
BIASSET
36.4Ω
I
≈
BIAS
The input impedance of the BIASSET pad is typically
20kΩ. Note that the minimum output voltage is V
+
EE
1.67V (see Figure 5).
Programming the Pulse-Width Control
Three methods of control are possible when pulse predis-
tortion is desired to minimize distortion at the receiver.
The pulse width may be set with a 2kΩ potentiometer with
Modulation Output Enable
The MAX3940 incorporates a modulation current-
enable input. When MODEN is low or floating, the mod-
ulation/bias output (OUT) is enabled. When MODEN is
high, the output is switched to the logic 0 state. The
typical enable time is 2ns and the typical disable time
is 2ns.
the center tapped to V (or equivalent fixed resistors), or
EE
by applying a voltage to the PWC+ pad, or by applying a
differential voltage across the PWC+ and PWC- pads.
See Table 1 for the desired effect of the pulse-width set-
ting. Pulse width is defined as (positive pulse
width)/((positive pulse width + negative pulse width)/2).
Design Procedure
Input Termination Requirement
The MAX3940 data and clock inputs are CML compati-
ble. However, it is not necessary to drive the IC with a
standard CML signal. As long as the specified input
voltage swings are met, the MAX3940 will operate
properly.
Programming the Modulation Voltage
The EAM modulation voltage results from I
passing
MOD
through the EAM impedance (Z ) in parallel with the
L
internal 50Ω termination resistor (R
).
OUT
Z
Z
× R
+ R
L
OUT
OUT
V
≈ I
×
MOD
MOD
Applications Information
L
Layout Considerations
To minimize loss and crosstalk, keep the connections
between the MAX3940 output and the EAM module as
short as possible. Use good high-frequency layout
techniques and multilayer boards with an uninterrupted
ground plane to minimize EMI and crosstalk. Circuit
boards should be made using low-loss dielectrics. Use
controlled-impedance lines for the clock and data
inputs as well as for the data output. Wafer capacitors
To program the desired modulation current, force a
voltage at the MODSET pad (see the Typical
Application Circuit). The resulting I
current can be
MOD
calculated by the following equation:
V
MODSET
11.1Ω
I
≈
+ 37mA
MOD
An internal, independent current source drives a constant
37mA to the modulation circuitry and any voltage above
are required to filter the V supply. Connect the back-
EE
side of the die to GND.
V
on the MODSET pad adds to this. The input imped-
EE
ance of the MODSET pad is typically 20kΩ. Note that the
Table 1. Pulse-Width Control
minimum output voltage is V + 1.67V (see Figure 5).
EE
PULSE
WIDTH
R
, R
FOR
V
V
PWC+
-
PWC+ PWC-
PWC+
Programming the Bias Voltage
R
+ R
= 2kΩ (PWC- OPEN)
V
PWC+
PWC-
PWC-
As in the case of modulation, the EAM bias voltage
100%
>100%
<100%
R
R
R
= R
> R
< R
V
+ 1V
EE
0V
PWC+
PWC+
PWC+
PWC-
PWC-
PWC-
results from I
passing through the EAM impedance
BIAS
(Z ) in parallel with the internal 50Ω termination resistor
> V + 1V
>0V
<0V
L
EE
(R
OUT
).
< V + 1V
EE
_______________________________________________________________________________________
9
10Gbps EAM Driver with Integrated
Bias Network
RTEN
MODEN
PLRT
50Ω
R
OUT
50Ω
50Ω
50Ω
50Ω
50Ω
OUT
CLK+
CLK-
V
Z
L
EE
D
Q
0
1
POLARITY
MUX
PWC
DATA+
DATA-
I
I
MOD
BIAS
50Ω
50Ω
MAX3940
V
V
EE
EE
MODSET
BIASSET
PWC+
PWC-
+
+
V
V
MODSET
-
BIASSET
-
2kΩ
V
V
EE
EE
V
EE
Figure 6. Functional Diagram
Interface Schematics
Laser Safety and IEC 825
Figures 7 and 8 show simplified input and output cir-
cuits of the MAX3940 EAM driver.
Using the MAX3940 EAM driver alone does not ensure
that a transmitter design is compliant with IEC 825. The
entire transmitter circuit and component selections must
be considered. Each customer must determine the level
of fault tolerance required by their application, recogniz-
ing that Maxim products are not designed or authorized
for use as components in systems intended for surgical
implant into the body, for applications intended to sup-
port or sustain life, or for any other application where the
failure of a Maxim product could create a situation where
personal injury or death may occur.
Wire Bonding Die
For high-current density and reliable operation, the
MAX3940 uses gold metalization. Make connections to
the die with gold wire only, using ball-bonding techniques.
Minimize bond-wire lengths and ensure that the span
between the ends of the bond wire does not come clos-
er to the edge of the die than two times the bond-wire
diameter. The minimum length of the bond wires might
be constrained by the type of wire bonder used, as well
as the dimensions of the die.
To minimize inductance, keep the connections from
OUT, GND, and V as short as possible. This is crucial
EE
for optimal performance.
10 ______________________________________________________________________________________
10Gbps EAM Driver with Integrated
Bias Network
GND
GND
GND
MAX3940
50Ω
50Ω
MAX3940
50Ω
50Ω
GND
OUT
DATA+/CLK+
DATA-/CLK-
50Ω
GND
V
EE
V
EE
Figure 8. Simplified Output Circuit
Figure 7. Simplified Input Circuit
Chip Information
Chip Topography/
Pad Configuration
The origin for pad coordinates is defined as the bottom
left corner of the bottom left pad. All pad locations are
referenced from the origin and indicate the center of
the pad where the bond wire should be connected.
Refer to Maxim application note HFAN-08.0.1:
Understanding Bonding Coordinates and Physical Die
Size for detailed information.
TRANSISTOR COUNT: 2084
PROCESS: SiGe BIPOLAR
SUBSTRATE: SOI
DIE THICKNESS: 8 mils
Maxim characterized this circuit with gold wire (1-mil
diameter wire) ball bonded to the pads. Die pad size is
4 mils (102µm) square, and die thickness is 8 mils
(203µm).
______________________________________________________________________________________ 11
10Gbps EAM Driver with Integrated
Bias Network
Chip Topography
PLRT PWC-
PWC+
V
V
V
V
V
EE
V
V
EE
V
V
EE
MODSET BIASSET RTEN MODEN
EE
EE
EE
EE
EE
EE
GND
GND
GND
GND
GND
OUT
DATA+
1.6mm
(63 mils)
GND
GND
DATA-
GND
GND
GND
GND
GND
(0, 0)
GND
GND
GND
GND
CLK+ GND
GND
CLK-
GND
GND
GND
GND
GND
2.3mm
(90.6 mils)
12 ______________________________________________________________________________________
10Gbps EAM Driver with Integrated
Bias Network
Table 2. Bondpad Locations
COORDINATES (µm)
COORDINATES (µm)
PAD
NUMBER
PAD
NUMBER
PAD NAME
PAD NAME
X
Y
X
Y
BP1
BP2
GND
GND
DATA+
GND
GND
DATA-
GND
GND
GND
GND
GND
GND
CLK+
GND
GND
CLK-
GND
GND
GND
GND
GND
GND
51.2
933.2
807.2
681.2
555.2
429.2
303.2
177.2
51.2
BP23
BP24
BP25
BP26
BP27
BP28
BP29
BP30
BP31
BP32
BP33
BP34
BP35
BP36
BP37
BP38
BP39
BP40
BP41
BP42
BP43
BP44
GND
GND
2028
108.6
51.2
2028
234.6
BP3
51.2
OUT
2028
574.8
BP4
51.2
GND
2028
700.8
BP5
51.2
GND
2028
856.2
BP6
51.2
GND
2028
982.2
BP7
51.2
MODEN
RTEN
1953.8
1827.8
1701.8
1575.8
1449.8
1323.8
1197.8
1071.8
945.8
819.8
693.8
567.8
441.8
315.8
189.8
63.8
1140.4
1140.4
1140.4
1140.4
1140.4
1140.4
1140.4
1140.4
1140.4
1140.4
1140.4
1140.4
1140.4
1140.4
1140.4
1140.4
BP8
51.2
BP9
231.8
357.8
483.8
609.8
769.4
895.4
1021.4
1147.4
1305.2
1431.2
1606.2
1732.2
1874
2028
-63.6
-63.6
-63.6
-63.6
-63.6
-63.6
-63.6
-63.6
-63.6
-63.6
-63.6
-63.6
-63.2
-43.8
BIASSET
MODSET
BP10
BP11
BP12
BP13
BP14
BP15
BP16
BP17
BP18
BP19
BP20
BP21
BP22
V
V
V
V
V
V
V
V
V
EE
EE
EE
EE
EE
EE
EE
EE
EE
PWC+
PWC-
PLRT
Package Information
For the latest package outline information, go to
www.maxim-ic.com/packages.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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