MAX3942ETG+ [MAXIM]
10Gbps Modulator Driver; 10Gbps的调制器驱动器
| 型号： | MAX3942ETG+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 10Gbps Modulator Driver |
| 文件： | 总10页 (文件大小：228K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2934; Rev 1; 6/07
10Gbps Modulator Driver
MAX3942
General Description
Features
The MAX3942 is designed to drive high-speed optical
modulators at data rates up to 10.7Gbps. It functions as
a modulation circuit, with an integrated control op amp
externally programmed by a DC voltage.
♦ 23ps Edge Speed
♦ Single-Ended Modulation Voltage Up to 3V
P-P
♦ Differential Modulation Voltage Up to 6V
♦ Selectable Data-Retiming Latch
♦ Up to 10.7Gbps Operation
P-P
A high-bandwidth, fully differential signal path is inter-
nally implemented to minimize jitter accumulation. When
a clock signal is available, the integrated data-retiming
function can be selected to reject input-signal jitter.
♦ 50Ω On-Chip Input and Output Terminations
♦ Pulse-Width Adjustment
The MAX3942 receives differential CML signals (ground-
referenced) with on-chip line terminations of 50Ω. Each
of the differential outputs has an on-chip 50Ω resistor for
back termination. The driver is able to deliver a modula-
♦ Enable and Polarity Controls
♦ ESD Protection
tion current of 40mA
to 120mA , with an edge
P-P
P-P
Applications
speed of 23ps (typical 20% to 80%). This modulation
current reflects a modulation voltage of 1.0V to 3.0V
P-P
differential.
P-
Mach Zehnder Modulators
single ended or 2.0V
to 6.0V
P
P-P
P-P
Packaged Direct-Modulated Lasers
The MAX3942 also includes an adjustable pulse-width
control circuit to precompensate for asymmetrical mod-
ulator characteristics. It is available in a compact 4mm
✕ 4mm, 24-pin thin QFN package and operates over
the -40°C to +85°C temperature range.
SONET OC-192 and SDH STM-64 Transmission
Systems
DWDM Systems
Long/Short-Reach Optical Transmitters
10Gbps Ethernet
Ordering Information
PART
TEMP RANGE PIN-PACKAGE
MAX3942ETG -40°C to +85°C 24 Thin QFN (4mm ꢀ 4mm)
MAX3942ETG+ -40°C to +85°C 24 Thin QFN (4mm ꢀ 4mm)
+Denotes a lead-free package.
Pin Configuration appears at end of data sheet.
Typical Application Circuit
50Ω
-5.2V
L2
0.01μF
PLRT
MODEN
RTEN
GND
0.01μF
50Ω
OUT-
50Ω
50Ω
DATA+
DATA-
DATA+
DATA-
0.01μF
MACH ZEHNDER
MODULATOR
MAX3952
50Ω
10Gbps
SERIALIZER
MAX3942
0.01μF
0.01μF
50Ω
50Ω
CLK+
CLK-
CLK+
L1
0.01μF
50Ω
OUT+
CLK-
PWC+
PWC-
MODSET
+
V
EE
2kΩ
V
MODSET
-
-5.2V
1000pF
0.1μF
-5.2V
-5.2V
L1 AND L2 ARE HIGH-FREQUENCY FERRITE BEADS
REPRESENTS A CONTROLLED-IMPEDANCE TRANSMISSION LINE.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
10Gbps Modulator Driver
ABSOLUTE MAXIMUM RATINGS
Supply Voltage V
..............................................-6.0V to +0.5V
Continuous Power Dissipation (T = +85°C)
A
EE
Voltage at MODEN,
RTEN, PLRT, MODSET............................(V - 0.5V) to +0.5V
Voltage at DATA+, DATA-, CLK+, and CLK-……-1.65V to +0.5V
Voltage at OUT+, OUT- ................................……….-4V to +0.5V
24-Pin Thin QFN (derate 20.8mW/° above +85°C)....1354mW
Current into or out of OUT+, OUT-.................……………...80mA
Storage Temperature Range .....................……-55°C to +150°C
Operating Temperature Range ....................……-40°C to +85°C
Lead Temperature (soldering, 10s)............………………+300°C
EE
Voltage at PWC+, PWC-...................(V - 0.5V) to (V + 1.7V)
EE
EE
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
MAX3942
ELECTRICAL CHARACTERISTICS
(V = -5.5V to -4.9V, T = -40°C to +85°C. Typical values are at V = -5.2V, I
= 100mA, and T = +25°C, unless otherwise noted.)
A
EE
A
EE
MOD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
-4.9
175
200
UNITS
Power-Supply Voltage
V
-5.5
V
EE
Retime disabled
Retime enabled
125
140
15
Excluding I
(Note 1)
MOD
Supply Current
I
mA
dB
EE
Power-Supply Noise Rejection
SIGNAL INPUT (Note 3)
Input Data Rates
PSNR
f ꢀ 2MHz (Note 2); see Figure 3
NRZ
10.7
50
Gbps
Single-Ended Input Resistance
R
V
Input to GND
42.5
-1
58.5
0
ꢁ
IN
IS
DC-coupled, Figure 1a
AC-coupled, Figure 1b
DC-coupled (Note 4)
AC-coupled (Note 4)
ꢀ 15GHz
Single-Ended Input Voltage
Differential Input Voltage
V
-0.4
0.2
0.2
+0.4
2.0
1.6
V
V
P-P
ID
Differential Input Return Loss
MODULATION (Note 5)
RL
15
dB
IN
Maximum Modulation Current
Minimum Modulation Current
MODSET Voltage Range
Equivalent Modulation
112
120
37
mA
P-P
P-P
V
= V
41
mA
MODSET
EE
V
+
V
V
V
EE
MODSET
EE
R
(Note 7)
11.1
5
ꢁ
MODEQV
Modulation Set Bandwidth
MODSET Input Resistance
Modulation depth 10%, 50ꢁ driver load
MHz
kꢁ
20
Modulation-Current
Temperature Stability
(Note 6)
-980
0
ppm/°C
Modulation-Current-Setting Error
Output Resistance
50ꢁ driver load, T = +25°C
-10
+10
58.5
%
A
R
OUT+ and OUT- to GND
42.5
50
ꢁ
OUT
2
_______________________________________________________________________________________
10Gbps Modulator Driver
MAX3942
ELECTRICAL CHARACTERISTICS (continued)
(V = -5.5V to -4.9V, T = -40°C to +85°C. Typical values are at V = -5.2V, I
= 100mA, and T = +25°C, unless otherwise noted.)
A
EE
A
EE
MOD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MODEN = V , MODSET = V , DATA+ =
high, DATA- = low
EE
EE
Off Current
1.6
mA
Differential Output Return Loss
Output Edge Speed
RL
I
= 50mA
10GHz
10
23
dB
ps
ps
ps
OUT
MOD
20% to 80% (Notes 6, 8)
Figure 2 (Note 6)
(Notes 6, 8)
32
Setup/Hold Time
t
, t
SU HD
25
30
Pulse-Width Adjustment Range
50
Pulse-Width Control Input
Range (Single Ended)
V
+
0.5
V
+
EE
1.5
EE
For PWC+ and PWC-
(PWC+) - (PWC-)
V
Pulse-Width Control Input
Range (Differential)
-0.5
+0.5
V
Output Overshoot
ꢀ
(Notes 6, 8)
5
0.3
8
%
Driver Random Jitter
Driver Deterministic Jitter
CONTROL INPUTS
RJ
DJ
(Note 6)
0.8
13
ps
RMS
DR
PWC- = GND (Notes 6, 9)
ps
P-P
DR
V
+
2.0
EE
Input High Voltage
V
(Note 10)
V
IH
V
+
0.8
EE
Input Low Voltage
Input Current
V
(Note 10)
(Note 10)
V
IL
-80
+200
μA
Note 1: Supply current remains elevated once the retiming function has been enabled. Power must be cycled to reduce supply
current after the retiming function has been disabled.
Note 2: Power-supply noise rejection is specified as PSNR = 20Log(V
/ ΔV
). V
is the voltage across a 50Ω load.
noise (on Vcc)
OUT
OUT
V
= 100mV
.
P-P
noise (on Vcc)
Note 3: For DATA+, DATA-, CLK+, and CLK-.
Note 4: CLK input characterized at 10.7Gbps.
Note 5: Minimum voltage on OUT+ and OUT- is V + 1.9V.
EE
Note 6: Guaranteed by design and characterization using the circuit shown in Figure 3.
Note 7: R
= (V
- V ) / (I
- 37mA).
MODEQV
MODSET
EE
MOD
Note 8: 50Ω load, characterized at 10.7Gbps with a 1111 1111 0000 0000 pattern.
Note 9: Deterministic jitter is defined as the arithmetic sum of PWD (pulse-width distortion) and PDJ (pattern-dependent jitter).
7
Measured with a 10.7Gbps 2 - 1 PRBS pattern with 80 zeros and 80 ones inserted in the data pattern.
Note 10: For MODEN and PLRT.
_______________________________________________________________________________________
3
10Gbps Modulator Driver
Test Circuits and Timing Diagrams
0V
100mV
1.0V
-0.5V
MAX3942
-1.0V
(a) DC-COUPLED SINGLE-ENDED CML INPUT
0.4V
800mV
0V
100mV
-0.4V
(b) AC-COUPLED SINGLE-ENDED (CML OR PECL) INPUT
Figure 1. Definition of Single-Ended Input Voltage Range
CLK+
CLK-
V
= 0.1V TO 1V
P-P P-P
IS
DC-COUPLED
0.1V TO 0.8V
AC-COUPLED
P-P
P-P
t
SU
t
HD
DATA-
DATA+
V
= 0.2V
TO 2V
ID
P-P P-P
(DATA+) - (DATA-)
DC-COUPLED
0.2V TO 1.6V
P-P
P-P
AC-COUPLED
I
I
OUT+
I
= 40mA TO 120mA
P-P P-P
MOD
OUT-
NOTE: I
AND I
RELATE TO RETIMED DATA. SEE FIGURE 3 FOR POLARITY.
OUT+
OUT-
Figure 2. Setup and Hold Timing Definition
4
_______________________________________________________________________________________
10Gbps Modulator Driver
MAX3942
Test Circuits and Timing Diagrams (continued)
PLRT
RTEN
MODEN PWC+ PWC-
50Ω
50Ω
CLK+
CLK-
I
OUT-
OSCILLOSCOPE
50Ω
50Ω
OUT-
PATTERN
GENERATOR
MAX3942
OUT+
50Ω
50Ω
DATA+
DATA-
50Ω
I
OUT+
Z
L
V
EE
MODSET
GND
-5.2V
V
MODSET
0.1μF
1000pF
V
EE
Figure 3. AC Characterization Circuit
_______________________________________________________________________________________
5
10Gbps Modulator Driver
Typical Operating Characteristics
(Typical values are at V = -5.2V, I
= 100mA, T = +25°C, unless otherwise noted.)
A
EE
MOD
SUPPLY CURRENT vs. TEMPERATURE
10.7Gbps ELECTRICAL EYE DIAGRAM
= 2V DIFFERENTIAL, 231 - 1 PRBS)
10.7Gbps ELECTRICAL EYE DIAGRAM
MOD
(V
(V
= 6V DIFFERENTIAL, 231 - 1 PRBS)
P-P
(50Ω LOAD, EXCLUDES I
)
MOD
MOD
P-P
170
160
150
140
130
120
110
100
MAX3942
RETIMING ENABLED
RETIMING DISABLED
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
16ps/div
16ps/div
TEMPERATURE (°C)
PULSE WIDTH vs. R
PWC
PULSE-WIDTH DISTORTION
vs. TEMPERATURE
DIFFERENTIAL V
(Z = 50Ω ON OUT+ AND OUT-)
L
vs. V
MODSET
MOD
R
PWC-
(Ω)
2000 1750 1500 1250 1000 750 500 250
0
2.0
7
6
5
4
3
2
1
0
850
840
830
820
810
800
790
780
770
760
750
V
IS RELATIVE TO V
MEASURED AT 1.25Gbps
WITH A 1010 PATTERN
MODSET
EE
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
-50 -30 -10
10
30
50
70
90
0
250 500 750 1000 1250 1500 1750 2000
(Ω)
0
0.25
0.50
0.75
1.00
R
PWC+
TEMPERATURE (°C)
V
(V)
MODSET
DIFFERENTIAL S vs. FREQUENCY
11
DIFFERENTIAL S vs. FREQUENCY
22
POWER-SUPPLY NOISE REJECTION
vs. FREQUENCY
(DEVICE POWERED)
(DEVICE POWERED)
0
-5
0
-3
30
25
20
15
10
5
-6
-10
-15
-20
-25
-30
-35
-40
-9
-12
-15
-18
-21
-24
-27
-30
0
0
3
6
9
12
15
10
100
1k
0
3
6
9
12
15
1
10k
FREQUENCY (GHz)
FREQUENCY (GHz)
FREQUENCY (Hz)
6
_______________________________________________________________________________________
10Gbps Modulator Driver
MAX3942
Pin Description
PIN
NAME
DATA+
DATA-
GND
FUNCTION
1
Noninverting Data Input, with 50Ω On-Chip Termination
2
Inverting Data Input, with 50Ω On-Chip Termination
3, 4, 14, 17
Ground. All pins must be connected to board ground.
5
6
CLK+
CLK-
Noninverting Clock Input for Data Retiming, with 50Ω On-Chip Termination
Inverting Clock Input for Data Retiming, with 50Ω On-Chip Termination
7, 11, 12, 13,
18, 19, 21, 24
V
Negative Supply Voltage. All pins must be connected to board V
.
EE
EE
8
PWC+
PWC-
Positive Input for Modulation Pulse-Width Adjustment (see the Design Procedure section).
Negative Input for Modulation Pulse-Width Adjustment. Ground to disable the pulse-width
adjustment feature (see the Design Procedure section).
9
10
15
MODSET Modulation Current Set. Apply a voltage to set the modulation current of the driver output.
Inverting Driver Output. Provides modulation output with 50Ω back termination. Sinks current when
OUT-
PLRT is high and when differential data is high.
Noninverting Driver Output. Provides modulation output with 50Ω back termination. Sinks current
when PLRT is high and when differential data is low.
16
20
OUT+
Differential Data Polarity Swap Input. Set high or float for normal operation. Set low to invert the
differential signal polarity. Contains an internal 100kΩ pullup to GND.
PLRT
TTL/CMOS Modulation Enable Input. Set low or float for normal operation. Set high to put the EAM
22
23
EP
MODEN
in the absorption (logic 0) state. Contains an internal 100kΩ pulldown to V
.
EE
RTEN
Exposed Ground. Must be soldered to the circuit board ground for proper thermal and electrical performance.
Pad See the Layout Considerations section.
Data-Retiming Input. Connect to V for retimed data. Connect to GND to bypass retiming latch.
EE
Polarity Switch
The MAX3942 includes a polarity switch. When the
PLRT pin is high or left floating, the outputs maintain the
polarity of the input data. When the PLRT pin is low, the
outputs are inverted relative to the input data.
Detailed Description
The MAX3942 modulator driver accepts differential
clock and data inputs that are compatible with PECL
and CML logic levels.
The modulation output stage is composed of a high-
speed differential pair and a programmable current
source with a maximum modulation current of 120mA.
The rise and fall times are typically 23ps. The modulation
current is designed to produce a modulation voltage up
Clock/Data Input Logic Levels
The MAX3942 is directly compatible with ground-refer-
ence CML. Either DC- or AC-coupling may be used for
CML referenced to ground. For all other logic types,
AC-coupling should be used.
to 3.0V
single endedly, or 6.0V
differentially when
P-P
P-P
driving a 50Ω module. The 3.0V
results from 120mA
P-P
P-P
Optional Data Input Latch
To reject pattern-dependent jitter in the input data, a syn-
chronous differential clock signal should be connected to
the CLK+ and CLK- inputs, and the RTEN control input
through the parallel combination of the 50Ω modulator
load and the internal 50Ω back termination.
should be connected to V
.
EE
_______________________________________________________________________________________
7
10Gbps Modulator Driver
The input data is retimed on the rising edge of CLK+. If
RTEN is connected to ground, the retiming function is dis-
abled and the input data is directly connected to the out-
put stage. Leave CLK+ and CLK- open when retiming is
disabled.
An internal, independent current source drives a constant
37mA to the modulation circuitry and any voltage above
EE
ance of the MODSET pin is typically 20kΩ. Note that the
minimum output voltage is V + 1.9V.
EE
V
on the MODSET pin adds to this. The input imped-
Pulse-Width Control
The pulse-width control circuit can be used to compen-
sate for pulse-width distortion introduced by the modu-
lator. The differential voltage between PWC+ and PWC-
adjusts the pulse-width compensation. The adjustment
range is typically 50ps. Optional single-ended opera-
tion is possible by forcing a voltage on the PWC+ pin
while leaving the PWC- pin unconnected. When PWC-
is connected to ground, the pulse-width control circuit
is automatically disabled.
Programming the Pulse-Width Control
Three methods of control are possible when pulse predis-
tortion is desired to minimize distortion at the receiver.
The pulse width may be set with a 2kΩ potentiometer with
MAX3942
the center tapped to V (or equivalent fixed resistors), or
EE
by applying a voltage to the PWC+ pin, or by applying a
differential voltage across the PWC+ and PWC- pins. See
Table 1 for the desired effect of the pulse-width setting.
Pulse width is defined as (positive pulse width)/((positive
pulse width + negative pulse width)/2).
Modulation Output Enable
The MAX3942 incorporates a modulation current-
enable input. When MODEN is low or floating, the mod-
ulation outputs OUT+ and OUT- are enabled. When
MODEN is high, the drive current is switched to OUT+.
The typical enable time is 2ns and the typical disable
time is 2ns.
Input Termination Requirement
The MAX3942 data and clock inputs are CML compati-
ble. However, it is not necessary to drive the IC with a
standard CML signal. As long as the specified input volt-
age swings are met, the MAX3942 operates properly.
Applications Information
Layout Considerations
To minimize loss and crosstalk, keep the connections
between the MAX3942 output and the modulator as
short as possible. Use good high-frequency layout
techniques and multilayer boards with an uninterrupted
ground plane to minimize EMI and crosstalk. Circuit
boards should be made using low-loss dielectrics. Use
controlled-impedance lines for the clock and data
inputs, as well as for the data output.
Design Procedure
Programming the Modulation Voltage
The modulation voltage results from I
passing
MOD
through the load impedance (Z ) in parallel with the
L
internal 50Ω termination resistor (R
):
OUT
Z
Z
× R
+ R
L
OUT
OUT
V
≈ I
×
MOD
MOD
L
Table 1. Pulse-Width Control
To program the desired modulation current, force a
voltage at the MODSET pin (see the Typical Application
PULSE
WIDTH
(%)
V
V
-
PWC+
PWC+
Circuit). The resulting I
current can be calculated
MOD
R
, R
FOR
= 2kΩ
PWC+ PWC-
(PWC- OPEN)
(V)
V
PWC-
(V)
R
+ R
by the following equation:
PWC+
PWC-
V
100
R
R
R
= R
> R
< R
V + 1
EE
0
MODSET
11.1Ω
PWC+
PWC+
PWC+
PWC-
I
≈
+ 37mA
MOD
>100
<100
> V + 1
>0
<0
PWC-
PWC-
EE
< V + 1
EE
8
_______________________________________________________________________________________
10Gbps Modulator Driver
MAX3942
RTEN
MODEN
PLRT
50Ω
50Ω
50Ω
50Ω
50Ω
50Ω
OUT-
OUT+
CLK+
CLK-
V
EE
0
D
Q
POLARITY
PWC
MUX
DATA+
DATA-
1
I
MOD
50Ω
50Ω
V
EE
MAX3942
MODSET
PWC+
PWC-
+
2kΩ
V
-
MODSET
V
EE
V
EE
Figure 4. Functional Diagram
GND
Interface Schematics
Figures 5 and 6 show simplified input and output cir-
cuits of the MAX3942 modulator driver.
MAX3942
50Ω
50Ω
To minimize inductance, keep the connections from
OUT, GND, and V as short as possible. This is crucial
EE
for optimal performance.
DATA+/CLK+
DATA-/CLK-
Laser Safety and IEC 825
Using the MAX3942 EAM driver alone does not ensure
that a transmitter design is compliant with IEC 825. The
entire transmitter circuit and component selections must
be considered. Each customer must determine the level
of fault tolerance required by their application, recogniz-
ing that Maxim products are not designed or authorized
for use as components in systems intended for surgical
implant into the body, for applications intended to sup-
port or sustain life, or for any other application where the
failure of a Maxim product could create a situation where
personal injury or death may occur.
V
EE
Figure 5. Simplified Input Circuit
_______________________________________________________________________________________
9
10Gbps Modulator Driver
Exposed-Pad Package
The exposed pad on the 24-pin QFN provides a very
low thermal resistance path for heat removal from the
IC. The pad is also electrical ground on the MAX3942
and must be soldered to the circuit board ground for
proper thermal and electrical performance. Refer to
Maxim Application Note HFAN-08.1: Thermal
Considerations of QFN and Other Exposed-Paddle
Packages for additional information.
GND GND
MAX3942
50Ω
50Ω
GND
GND
MAX3942
OUT-
OUT+
Chip Information
TRANSISTOR COUNT: 1918
V
V
EE
EE
PROCESS: SiGe Bipolar
Figure 6. Simplified Output Circuit
Pin Configuration
TOP VIEW
Package Information
DATA+
1
2
3
4
5
6
18
17
V
EE
For the latest package outline information, go to
www.maxim-ic.com/packages.
DATA-
GND
GND
16 OUT+
PART
PACKAGE TYPE
PACKAGE CODE
MAX3942
15
14
13
GND
OUT-
GND
24 Thin QFN
(4mm ✕ 4mm ✕ 0.8mm)
MAX3942ETG
T2444-1
CLK+
CLK-
V
EE
Revision History
Pages changed at Rev 1: 1, 2, 10.
24 THIN QFN (4mm x 4mm)
EXPOSED PAD CONNECTED TO GROUND
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products.
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