MAX3950EGK-TD [MAXIM]
Serial to Parallel/Parallel to Serial Converter, 1-Func, Bipolar, 10 X 10 MM, 0.90 MM HEIGHT, QFN-68;
| 型号： | MAX3950EGK-TD |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Serial to Parallel/Parallel to Serial Converter, 1-Func, Bipolar, 10 X 10 MM, 0.90 MM HEIGHT, QFN-68 |
| 文件： | 总9页 (文件大小：256K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1853; Rev 2; 12/02
+3.3V, 10.7Gbps 1:16 Deserializer
with LVDS Outputs
General Description
Features
The MAX3950 deserializer is ideal for converting
10Gbps serial data to 16-bit-wide, 622Mbps parallel
data in SDH/SONET and DWDM applications.
Operating from a single +3.3V supply, this device
accepts CML serial clock and data inputs and delivers
low-voltage differential-signal (LVDS) clock and data
outputs for interfacing with high-speed digital circuitry.
ꢀ Supports Serial Data Rates Up to 10.7Gbps
ꢀ 10Gbps/10.7Gbps Serial to 622Mbps/667Mbps
Parallel Conversion
ꢀ Single +3.3V Supply
ꢀ 900mW Operating Power
The MAX3950 is available in the extended temperature
range (-40°C to +85°C) in a 68-pin QFN package. The
typical power dissipation is 900mW.
ꢀ CML Serial Clock and Data Inputs
ꢀ LVDS Parallel Clock and Data Outputs
ꢀ -40°C to +85°C Operating Temperature
Applications
SONET/OC-192 SDH/STM-64 Transmission Systems
Add/Drop Multiplexers
Ordering Information
Broadband Digital Cross-Connects
PART
TEMP RANGE
PIN-PACKAGE
MAX3950EGK
-40°C to +85°C
68 QFN
Pin Configuration appears at the end of data sheet.
Typical Application Circuit
V
CC
V
CC
622Mbps
PD15+
V
CC
100Ω**
10Gbps
V
CC
SD+
SD-
SDO+
SDO-
PD15-
PD0+
10Gbps
10Gbps
IN+
IN-
SDI+
SDI-
OUT+
OUT-
OUT+
OUT-
10Gbps
IN+
IN-
MAX3940*
MAX3920*
TIA
MAX3925*
AGC AMP
100Ω**
100Ω**
CDR
MAX3950
DESERIALIZER
PD0-
SCLK+
SCLK-
SCLKO+
SCLKO-
PCLK+
PCLK-
*FUTURE PRODUCTS.
**REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION.
THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z = 50Ω.
o
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
+3.3V, 10.7Gbps 1:16 Deserializer
with LVDS Outputs
ABSOLUTE MAXIMUM RATINGS
Positive Supply Voltage (V )...............................-0.5V to +5.0V
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-55°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
CC
CML Input Voltage Level.................(V
- 0.8V) to (V
+ 0.5V)
+ 0.5V)
CC
CC
CC
LVDS Output Voltage Level........................-0.5V to (V
Continuous Power Dissipation (T = +85°C)
A
68-Lead QFN (derate 43.5mW/°C above +85°C)......2800mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
CC
(V
= +3.0V to +3.6V, differential loads = 100Ω 1ꢀ, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
=
CC
A
+3.3V, T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Current
I
270
350
mA
CC
CML INPUTS (SD , SCLK )
Differential Input Voltage Swing
V
V
R
400
1200
mV
P-P
ID
IS
IN
Single-Ended Input Voltage
Range
V
-
V +
CC
0.3
CC
Figure 1
V
0.6
Input Termination to V
42.5
50
57.5
1.375
250
25
Ω
CC
LVDS OUTPUT SPECIFICATION (PD[15.0] , PCLK )
Output High Voltage
Output Low Voltage
V
V
V
OH
V
V
1.025
150
OL
Differential Output Voltage
Figure 2
mV
| OD|
Change in Magnitude of
Differential Output for
Complementary States
∆ V
| OD|
mV
V
Offset Output Voltage
1.15
80
1.25
25
Change in Magnitude of
Output Offset Voltage for
Complementary States
∆ V
| OS|
mV
Differential Output Impedance
Output Current
120
12
Ω
Short together
Short to ground
mA
24
2
_______________________________________________________________________________________
+3.3V, 10.7Gbps 1:16 Deserializer
with LVDS Outputs
AC ELECTRICAL CHARACTERISTICS
CC
(V
= +3.0V to +3.6V, differential loads = 100Ω 1ꢀ, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
=
A
CC
+3.3V, T = +25°C.) (Note 1)
A
PARAMETER
Serial Input Data Rate
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Gbps
ps
10
Serial Data Setup Time
t
25
25
SU
Serial Data Hold Time
t
ps
H
Parallel Output Data Rate
Parallel Output Clock Frequency
Parallel Clock-to-Q Delay
LVDS Output Rise/Fall Time
LVDS Differential Skew
622
622
Mbps
MHz
ps
t
(Note 2)
-200
+200
300
65
CLK-Q
20ꢀ to 80ꢀ
ps
t
t
Any differential pair
PD[15..0]
ps
SKEW1
SKEW2
LVDS Channel-to-Channel Skew
200
17
ps
100kHz ≤ f ≤ 5GHz
5GHz ≤ f ≤ 10GHz
10GHz ≤ f ≤ 15GHz
Input Return Loss
S
| 11|
dB
14
11
Note 1: AC specifications are guaranteed by design and characterization.
Note 2: Relative to the falling edge of PCLK+. See Figure 3.
V
+ 0.3V
CC
600mV
200mV
V
CC
V
- 0.3V
CC
(a) AC-COUPLED CML INPUT
V
CC
200mV
600mV
V
CC
- 0.6V
(b) DC-COUPLED CML INPUT
Figure 1. Input Amplitude
_______________________________________________________________________________________
3
+3.3V, 10.7Gbps 1:16 Deserializer
with LVDS Outputs
PD+
R = 100Ω
L
V
V
OD
PD-
V
V
V
PD-
OH
IV
I
SINGLE-ENDED OUTPUT
OD
OS
V
PD+
V
OL
V
- V
PD+
PD-
V
= 2IV I
OD
OD
P-P
DIFFERENTIAL OUTPUT
0
Figure 2. Driver Output Levels
t
CLK
SCLK+
t
t
H
SU
SD
PCLK+
t
CLK-Q
PD
Figure 3. Timing Parameters
4
_______________________________________________________________________________________
+3.3V, 10.7Gbps 1:16 Deserializer
with LVDS Outputs
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
OUTPUT EYE DIAGRAM
LVDS OUTPUT AMPLITUDE
OUTPUT RISE/FALL TIME
vs. TEMPERATURE
INPUT: 9.953Gbps, 213 - 1 +100 ZEROS PRBS
vs. TEMPERATURE
MAX3950 toc03
250
300
250
NOTE: MEASURED 20 TO 80%
.
PCLK+
240
230
220
210
200
190
180
170
160
150
200
150
100
50
PCLK-
PD
DATA
CLOCK
0
200ps/div
-40
-20
0
20
40
60
80
-40 -20
0
20
40
60
80
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
OUTPUT EYE DIAGRAM
INPUT: 10.7Gbps, 213 - 1 +100 ZEROS PRBS
INPUT RETURN LOSS
MAX3950 toc04
0
-5
NOTE: DATA IS FROM
SIMULATION AND INCLUDES
PACKAGE PARASITICS.
PCLK+
-10
-15
-20
-25
-30
PCLK-
PD
200ps/div
0
5
10
15
20
FREQUENCY (GHz)
Pin Description
PIN
NAME
FUNCTION
1, 2, 5, 13, 16, 17, 18,
26, 33–36, 42, 51, 52,
53, 60, 68
GND
Ground
6, 9, 12, 25, 31, 32,
37, 43, 50, 54, 55, 61
V
Positive Power Supply
CC
7
SD+
SD-
Positive Data Input. 9.953Gbps serial data stream, CML.
Negative Data Input. 9.953Gbps serial data stream, CML.
Positive Serial Clock Input. 9.953GHz, CML.
8
10
11
14
SCLK+
SCLK-
PCLK-
Negative Serial Clock Input. 9.953GHz, CML.
Negative Parallel Clock Output, 622.08MHz, LVDS.
_______________________________________________________________________________________
5
+3.3V, 10.7Gbps 1:16 Deserializer
with LVDS Outputs
Pin Description (continued)
PIN
NAME
FUNCTION
15
PCLK+
Positive Parallel Clock Output, 622.08MHz, LVDS.
19, 21, 23, 27, 29, 38,
40, 44, 46, 48, 56, 58,
62, 64, 66, 3
PD0- to
PD15-
Negative Parallel Data Output, 622.08Mbps, LVDS.
20, 22, 24, 28, 30, 39,
41, 45, 47, 49, 57, 59,
63, 65, 67, 4
PD0+ to
PD15+
Positive Parallel Data Output, 622.08Mbps, LVDS.
Exposed
Pad
Ground. This must be soldered to the circuit board ground for proper thermal and
electrical operation. See Layout Considerations.
EP
CP
Corner
Pins
N.C. Not Connected. Ensure that the solder mask is located below them so that
unintentional connections do not occur.
4-BIT SHIFT
REGISTER
MAX3950
CML INPUT
CML INPUT
4-BIT SHIFT
REGISTER
DATA
CLK
D FLIP-FLOP
DELAY
DIVIDE BY 4
4-BIT SHIFT
REGISTER
DATA
CLK
4-BIT SHIFT
REGISTER
DIVIDE BY 4
Figure 4. Functional Block Diagram
Note that the PCLK polarity on the MAX3950 is inverted
relative to OIF 1999.102, so that PCLK+ is equivalent to
RXCLK_N and PCLK- is equivalent to RXCLK_P.
Detailed Description
The MAX3950 deserializer implements a shift-register-
based demultiplexer to convert 9.953Gbps serial data
to 16-bit-wide, 622.08Mbps parallel data (Figure 4).
The allocation of the serial input bits to the parallel
LVDS outputs is displayed in Figure 5.
The MAX3950 uses 300mV
to 500mV
differential
P-P
P-P
low-voltage swings to achieve fast transition times, min-
imize power dissipation, and improve noise immunity.
The parallel clock and data LVDS outputs (PCLK+,
PCLK-, PD_+, PD_-) require 100Ω differential DC termi-
nation between the inverting and noninverting outputs
for proper operation. Do not terminate these outputs to
ground. For more information on interfacing with the
LVDS outputs, refer to Maxim Application Note HFAN-
1.0: Interfacing Between CML, PECL, and LVDS.
Applications Information
Low-Voltage Differential-Signal
Outputs
The MAX3950 features LVDS outputs for interfacing
with high-speed digital circuitry. This LVDS implementa-
tion is based on the IEEE 1596.3 LVDS reduced-range
link specification and is compatible with OIF 1999.102.
6
_______________________________________________________________________________________
+3.3V, 10.7Gbps 1:16 Deserializer
with LVDS Outputs
D15 D14
D13
SD
PCLK+
D0
D1
D16
D17
D32
D33
D48
D49
D64
D65
(LSB) PD0
PD1
•
•
•
D15
D31
D47
D63
D79
PD15
(MSB)
TRANSMITTED FIRST
Figure 5. Timing Diagram
V
CC
250fF
250fF
50Ω
50Ω
1.1nH
SD+
SD-
K = 0.4
1.1nH
HIGH Z
HIGH Z
70fF
70fF
NOTE: PARASITIC VALUES SHOWN ARE TYPICAL VALUES.
Figure 6. CML Input Model
Current Mode Logic (CML) Inputs
Layout Considerations
The differential serial inputs to the MAX3950 are CML
and have an input impedance of 50Ω on each of the
complementary inputs. For more information on inter-
facing with the CML inputs, refer to Maxim Application
Note HFAN-1.0: Interfacing Between CML, PECL, and
LVDS.
For best performance, use good high-frequency layout
techniques. Filter voltage supplies, keep ground con-
nections short, and use multiple vias where possible.
Use controlled-impedance transmission lines to inter-
face with the MAX3950’s high-speed inputs and out-
puts. Place power-supply decoupling as close to V
CC
as possible. To reduce feedthrough, isolate the input
signals from the output signals.
Interface Models
Figures 6 and 7 show the typical input/output models
for the MAX3950 deserializer.
_______________________________________________________________________________________
7
+3.3V, 10.7Gbps 1:16 Deserializer
with LVDS Outputs
Chip Information
v
cc
TRANSISTOR COUNT: 4800
v
cc
PD_+
PD_-
v
cc
MAX3950
Figure 7. LVDS Output Model
Pin Configuration
TOP VIEW
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
GND
GND
1
2
3
4
5
6
7
8
9
51 GND
50
V
CC
PD15-
PD15+
GND
49 PD9+
48 PD9-
47 PD8+
46 PD8-
45 PD7+
44 PD7-
V
CC
SD+
SD-
MAX3950
V
CC
43 V
CC
SCLK+ 10
SCLK- 11
42 GND
41 PD6+
40 PD6-
39 PD5+
38 PD5-
V
12
CC
GND 13
PCLK- 14
PCLK+ 15
GND 16
37
V
CC
36 GND
35 GND
GND 17
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
QFN*
*EXPOSED PAD IS CONNECTED TO GND.
8
_______________________________________________________________________________________
+3.3V, 10.7Gbps 1:16 Deserializer
with LVDS Outputs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
9 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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