MAX3980UGH [MAXIM]
3.125Gbps XAUI Quad Equalizer; 的3.125Gbps XAUI四路均衡器
| 型号： | MAX3980UGH |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 3.125Gbps XAUI Quad Equalizer |
| 文件： | 总9页 (文件大小：437K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2153; Rev 3; 12/08
3.125Gbps XAUI Quad Equalizer
MAX3980
General Description
Features
The MAX3980 quad equalizer provides compensation
for transmission medium losses for four “lanes” of digi-
tal NRZ data at a 3.125Gbps data rate in one package.
It is tailor-made for 10-Gigabit Ethernet (10GbE) back-
plane applications requiring attenuation of noise and jit-
ter that occur in communicating from MAC to PMD or
from MAC to Switch. In support of the IEEE-802.3ae for
the XAUI interface, the MAX3980 adaptively allows
XAUI lanes to reach up to 40in (1.0m) on FR-4 board
material.
♦ Four Differential Digital Data “Lanes” at
3.125Gbps
♦ Spans 40in (1.0m) of FR-4 PC Board
♦ Receiver Equalization Reduces Intersymbol
Interference (ISI)
♦ Low-Power, 175mW per Channel
♦ Standby Mode—Power-Down State
♦ Single +3.3V Supply
The equalizer has 100Ω differential CML data inputs
and outputs.
♦ Signal Detect
The MAX3980 is available in a 44-pin exposed-pad
QFN package. The MAX3980 consumes only 700mW at
+3.3V or 175mW per channel.
Ordering Information
PART
TEMP RANGE
0°C to +85°C
0°C to +85°C
PIN-PACKAGE
44 QFN-EP*
Applications
MAX3980UGH
MAX3980UTH+
44 TQFN-EP*
IEEE-802.3ae XAUI Interface (3.125Gbps)
SM
+Denotes a lead-free/RoHS-compliant package.
*EP = Exposed pad.
InfiniBand
(2.5Gbps)
Pin Configuration appears at end of data sheet.
Typical Application Circuit
SWITCH CARD
LINE CARD
PC BOARD
BACKPLANE
PMD
MAC
SWITCH
≤ 40in (1.0m)
4
4
4
Rx
Tx
Tx
Rx
Rx
Tx
Tx
Rx
Rx
IN
OUT
4 x 3.125Gbps
MAX3980
+3.3V
SUPPLY
4 x
3.125Gbps
10GbE
+3.3V
SUPPLY
4
4
4
Tx
OUT
IN
MAX3980
≤ 40in (1.0m)
InfiniBand is a trademark and service mark of the InfiniBand Trade Association.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
3.125Gbps XAUI Quad Equalizer
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V ..............................................-0.5V to +4.0V
Operating Ambient Temperature Range ................0°C to +85°C
Storage Temperature Range.............................-55°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
CC
Voltage at SDET, IN_ ................................-0.5V to (V
Current Out of OUT_ .......................................-25mA to +25mA
+ 0.5V)
CC
Continuous Power Dissipation (T = +85°C)
A
44-Pin QFN-EP (derate 26.3mW/°C above +85°C)...2105mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
MAX3980
ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, input data rate = 3.125Gbps, T = 0°C to +85°C. Typical values are at V
= +3.3V and T = +25°C, unless
CC A
A
otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
0.25
0.9
UNITS
EN = TTL low
EN = TTL high
Supply Power
W
0.7
100
40
10Hz < f < 100Hz
Supply Noise Tolerance
mVp-p
100Hz < f < 1MHz
1MHz < f < 2.5GHz
10
Signal Detect Assert
Signal Detect Deassert
Signal Detect Delay
Latency
Input signal level to assert SDET (Note 1)
Input signal level to deassert SDET (Note 1)
100
mVp-p
mVp-p
μs
30
10
From input to output
0.32
ns
CML RECEIVER INPUT
XAUI transmitter output measured
differentially at point A, Figure 1, using
K28.5 pattern
Input Voltage Swing
200
80
800
120
mVp-p
Return Loss
100MHz to 2.5GHz
Differential
12
dB
Input Resistance
EQUALIZATION
100
Ω
Total jitter (Note 2)
Deterministic jitter
(Note 2)
0.3
0.2
Residual Jitter
Random Jitter
UIp-p
1.5
ps
RMS
CML TRANSMITTER OUTPUT (into 100Ω 1Ω)
Output Voltage Swing
Differential swing
550
40
850
mVp-p
Common-Mode Voltage
V
- 0.3
V
CC
Transition Time
t , t
f
20% to 80% (Note 3)
60
130
12
ps
r
Difference in 50% crossing between OUT_+
and OUT_-
Differential Skew
Output Resistance
ps
Single ended
50
60
Ω
2
_______________________________________________________________________________________
3.125Gbps XAUI Quad Equalizer
MAX3980
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, input data rate = 3.125Gbps, T = 0°C to +85°C. Typical values are at V
= +3.3V and T = +25°C, unless
CC A
A
otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TTL CONTROL PINS
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage
Output Low Voltage
2.0
2.4
V
V
0.8
250
500
μA
μA
V
Internal 10kΩ pullup
Internal 10kΩ pullup
0.4
V
Note 1: K28.7 pattern is applied differentially at point A as shown in Figure 1.
Note 2: Total jitter does not include the signal source jitter. Total jitter (TJ) = [14.1 x RJ + DJ] where RJ is random RMS jitter and DJ
is maximum deterministic jitter. Signal source is a K28.5 pattern (00 1111 1010 11 0000 0101) for the deterministic jitter
test and K28.7 (0011111000) or equivalent for the random jitter test. Residual jitter is that which remains after equalizing
media-induced losses of the environment of Figure 1 or its equivalent. The deterministic jitter at point B must be from media-
induced loss and not from clock-source modulation. Jitter is measured at 0 at point C of Figure 1.
Note 3: Using K28.7 (0011111000) pattern.
C
B
A
FR-4 STRIPLINE
≤ 40in (1m)
MAX3980
OUT
IN
SMA
CONNECTOR
SMA
CONNECTOR
Figure 1. Test Conditions Referenced in the Electrical Characteristics Table
_______________________________________________________________________________________
3
3.125Gbps XAUI Quad Equalizer
Typical Operating Characteristics
7
(V
CC
= +3.3V, 3.125Gbps, 500mVp-p board input with 2 - 1 PRBS, T = +25°C, unless otherwise noted.)
A
EQUALIZER INPUT EYE DIAGRAM
BEFORE EQUALIZATION
(40in FR-4 6mil STRIPLINE)
EQUALIZER OUTPUT EYE DIAGRAM
AFTER EQUALIZATION
EQUALIZER OUTPUT EYE DIAGRAM
(20in BACKPLANE WITH TWO TERADYNE HSD
CONNECTORS AND 3in DAUGHTERBOARD)
(40in FR-4 6mil STRIPLINE)
MAX3980
50mV/
div
100mV/
div
100mV/
div
50ps/div
50ps/div
50ps/div
INPUT RETURN GAIN (S11, DIFFERENTIAL,
INPUT SIGNAL = -60dBm,
EQUALIZER DETERMINISTIC JITTER
vs. LENGTH
(FR-4 6mil STRIPLINE, K28.5 PATTERN)
EQUALIZER LATENCY
vs. TEMPERATURE
DEVICE POWERED OFF)
500
450
400
350
300
250
200
10
0
40
35
30
25
20
15
10
-10
-20
-30
-40
-50
5
0
0
10
20
30
0
10 20 30 40 50 60 70 80 90
50
1050
2050
3050
4050
5050
40
50
TEMPERATURE (°C)
FREQUENCY (MHz)
LENGTH (in)
EQUALIZER OPERATING
CURRENT vs. TEMPERATURE
210
190
170
150
130
110
90
NORMAL OPERATION
(EN = TTL HIGH)
STANDBY POWER
(EN = TTL LOW)
70
50
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
4
_______________________________________________________________________________________
3.125Gbps XAUI Quad Equalizer
MAX3980
Pin Description
PIN
NAME
FUNCTION
1, 5, 9, 13,
23, 27, 31,
35
V
CC
+3.3V Supply Voltage
2
3
IN1+
IN1-
Positive Equalizer Input Channel 1, CML
Negative Equalizer Input Channel 1, CML
4, 8, 12, 16,
26, 30, 34,
38
GND
Supply Ground
6
IN2+
IN2-
Positive Equalizer Input Channel 2, CML
Negative Equalizer Input Channel 2, CML
Positive Equalizer Input Channel 3, CML
Negative Equalizer Input Channel 3, CML
Positive Equalizer Input Channel 4, CML
Negative Equalizer Input Channel 4, CML
No Connection. Leave unconnected.
7
10
IN3+
11
IN3-
14
IN4+
15
IN4-
17–22, 39–42
N.C.
24
25
28
29
32
33
36
37
OUT4-
OUT4+
OUT3-
OUT3+
OUT2-
OUT2+
OUT1-
OUT1+
Negative Equalizer Output Channel 4, CML
Positive Equalizer Output Channel 4, CML
Negative Equalizer Output Channel 3, CML
Positive Equalizer Output Channel 3, CML
Negative Equalizer Output Channel 2, CML
Positive Equalizer Output Channel 2, CML
Negative Equalizer Output Channel 1, CML
Positive Equalizer Output Channel 1, CML
Enable Equalizer Input. A TTL high selects normal operation. A TTL low selects low-power
standby mode.
43
44
—
EN
SDET
EP
Signal Detect Output for Channel 1. Produces a TTL high output when a signal is detected.
Exposed Pad. The exposed pad must be soldered to the circuit board ground plane for proper
thermal and electrical performance.
_______________________________________________________________________________________
5
3.125Gbps XAUI Quad Equalizer
Functional Diagram
IP1, IN1 ONLY
SIGNAL
SDET
TTL
DETECT
IN1+
OUT1+
2
3
2
2
CML
3
3
MAX3980
4
4
LIMITING
AMP
EQUALIZER
IN1-
OUT1-
2
2
2
2
2
3
3
3
4
4
3
3
4
4
4
4
POWER
MANAGEMENT
EN
MAX3980
SDET FUNCTION IS
INDEPENDENT OF EN
short-run DC-balanced transmission codes such as
8b/10b codes.
Detailed Description
Receiver and Transmitter
CML Input and Output Buffers
The input and output buffers are implemented using
CML. Equivalent circuits are shown in Figures 2 and 3.
For details on interfacing with CML, see Maxim applica-
tion note HFAN-1.0, Interfacing Between CML, PECL,
and LVDS. The common-mode voltage of the input and
output is above 2.5V. AC-coupling capacitors are
required when interfacing this part. Values of 0.10µF or
greater are recommended.
The receiver accepts four lanes of 3.125Gbps current-
mode logic (CML) digital data signals. The adaptive
equalizer compensates each received signal for dielec-
tric and skin losses. The limiting amp shapes the output
of the equalizer. The regenerated XAUI lanes are trans-
mitted as CML signals. The source impedance and ter-
mination impedances are 100Ω differential.
General Theory of Operation
Internally, the MAX3980 comprises signal-detect cir-
cuitry, four matched equalizers, and one equalizer-
control loop. The four equalizers are made up of a mas-
ter equalizer and three slave equalizers. The adaptive
control is generated from only channel 1. It is assumed
that all channels have the same characterization in fre-
quency content, coding, and transmission length.
Media Equalization
Equalization at the input port compensates for the high-
frequency loss encountered with up to 40in (1.0m) of
FR-4 transmission lines. This part is optimized for 40in
and 3.125Gbps; however, the part reduces ISI for sig-
nals spanning longer distances and functions for data
rates from 2Gbps to 4Gbps, provided that short-length
balanced codes, such as 8b/10b, are used.
The master equalizer consists of the following functions:
signal detect, adaptive equalizer, equalizer control, and
limiting and output drivers. The signal detect indicates
input signal power. When the input signal level is suffi-
ciently high, the SDET output is asserted. This does not
directly control the operation of the part.
Applications Information
Standby Mode
The power-saver standby state allows reduced-power
operation. The TTL input, EN, must be set to TTL high
for normal operation. A TTL low at EN forces the equal-
izer into the standby state. The signal EN does not
affect the operation of the signal detect (SDET) func-
tion. For constant operation, connect the EN signal
The equalizer core reduces intersymbol interference
(ISI), compensating for frequency-dependent, media-
induced loss. The equalization control detects the
spectral contents of the input signal and provides a
control voltage to the equalizer core, adapting it to dif-
ferent media. The equalizer operation is optimized for
directly to V
.
CC
6
_______________________________________________________________________________________
3.125Gbps XAUI Quad Equalizer
MAX3980
V
CC
V
CC
50Ω
50Ω
1.2kΩ
OUT+
OUT-
50Ω
50Ω
IN+
IN-
Q1
Q2
DATA
ESD
STRUCTURES
200μA
ESD
STRUCTURES
Figure 2. CML Input Buffer
Figure 3. CML Output Buffer
Signal Detect with Standby Mode
Signal activity is detected on channel 1 only. When the
peak-to-peak differential voltage at IN1 is less than
30mVp-p, the TTL output SDET goes low. When the
peak-to-peak differential voltage becomes greater than
100mVp-p, SDET is asserted high. SDET can be used
to automatically force the equalizer into standby mode
by connecting SDET directly to the EN input. When not
used, SDET should not be connected.
Layout Considerations
Circuit-board layout and design can significantly affect
the MAX3980 performance. Use good high-frequency
design techniques, including minimizing ground induc-
tances and vias and using controlled-impedance trans-
mission lines for the high-frequency data signals.
Signals should be routed differentially to reduce EMI
susceptibility and crosstalk. Power-supply decoupling
capacitors should be placed as close as possible to
the V
pins.
CC
The signal-detect function continues to operate while
the part is in standby mode. While connected to the EN
pin, the signal detect can “wake up” the part and
resume normal operation.
_______________________________________________________________________________________
7
3.125Gbps XAUI Quad Equalizer
Pin Configuration
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
TOP VIEW
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
44 QFN
G4477-1
21-0092
21-0144
44 TQFN
T4477-3
V
1
2
3
4
5
6
7
8
9
33
32
31
30
29
28
27
26
25
24
23
OUT2+
OUT2-
CC
MAX3980
IN1+
IN1-
GND
V
CC
GND
V
CC
OUT3+
OUT3-
IN2+
IN2-
GND
MAX3980
V
CC
GND
V
CC
OUT4+
OUT4-
IN3+ 10
IN3- 11
*EP
V
CC
QFN-EP/TQFN-EP
*NOTE: THE EXPOSED PAD MUST BE SOLDERED TO SUPPLY GROUND.
8
_______________________________________________________________________________________
3.125Gbps XAUI Quad Equalizer
MAX3980
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
9/01
Initial release.
—
Added the package code to the Ordering Information table.
1
8, 9
1
1
5/03
Updated the 21-0092 package drawing in the Package Information section.
Added the TQFN package to the Ordering Information table.
2
3
1/05
Added the 21-0144 package drawing to the Package Information section.
10
Changed the Absolute Maximum Ratings of SDET, IN_± from +5.0V to (V to
CC
12/08
2
0.5V) to –5.0V to (V to 0.5V).
CC
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9
© 2008 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
相关型号：
MAX3980UTH+T
Interface Circuit, 7 X 7 MM, 0.80 MM HEIGHT, ROHS COMPLIANT, MO-220WKKD-1, TQFN-44
MAXIM
©2020 ICPDF网 联系我们和版权申明