MAX3981UGH-D [MAXIM]
Interface Circuit, 7 X 7 MM, 0.90 MM HEIGHT, MO-220, QFN-44;
| 型号： | MAX3981UGH-D |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Interface Circuit, 7 X 7 MM, 0.90 MM HEIGHT, MO-220, QFN-44 电信 电信集成电路 |
| 文件： | 总9页 (文件大小：358K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
21-2178; Rev 1; 5/03
3.125Gbps XAUI Quad Cable Equalizer
General Description
Features
The MAX3981 quad equalizer provides compensation
for transmission medium losses for four “lanes” of digi-
tal NRZ data at a data rate of 3.125Gbps in one
package. It is tailor-made for 10Gigabit Ethernet appli-
cations that require attenuation of noise and jitter that
occur in communicating with chassis-to-chassis inter-
connect. In support of IEEE-802.3ae for the XAUI inter-
face, the MAX3981 adaptively allows XAUI lanes to
reach 10m (33ft) with inexpensive twin-axial cable for
extended backplane applications.
♦ Four Differential Digital Data “Lanes” at
3.125Gbps
♦ Span 10m (33ft) of Twin-Axial Cable
♦ Receiver Equalization Reduces Intersymbol
Interference (ISI)
♦ Low Power, 175mW per Channel
♦ Standby Mode—Power-Down State
♦ Single 3.3V Supply
The equalizer has 100Ω differential CML data inputs
and outputs.
♦ Signal Detect
The MAX3981 is available in a 44-pin exposed-pad
QFN package. The MAX3981 consumes only 700mW at
3.3V or 175mW per channel.
Applications
Ordering Information
IEEE–802.3ae XAUI Interface (3.125Gbps)
TEMP
RANGE
PIN-
PACKAGE
PACKAGE
CODE
PART
InfiniBand (2.5Gbps)
MAX3981UGH
0°C to +85°C
44 QFN
G4477-1
Pin Configuration appears at end of data sheet.
Typical Operating Circuit
SWITCH CARD
LINE CARD
PMD
MAC
SWITCH
4
4
4
4
Rx
Tx
Tx
Rx
Rx
Tx
Tx
Rx
Rx
Tx
IN
OUT
4 x 3.125Gbps
MAX3981
3.3V
SUPPLY
10GbE
3.3V
SUPPLY
4
4
OUT
IN
MAX3981
10m (33ft)100Ω
TWIN-AX CABLE
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
3.125Gbps XAUI Quad Cable Equalizer
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V ..............................................-0.5V to +4.0V
Continuous Power Dissipation (T = +85°C)
A
CC
Voltage at SDET ........................................+0.5V to (V
Voltage at IN_ .........................................+0.5V to (V
Current Out of OUT_ .......................................-25mA to +25mA
+ 0.5V)
+ 0.5V)
44-Pin QFN-EP (derate 26.3mW/°C above +85°C)....2105mW
Operating Ambient Temperature Range ................0°C to +85°C
Storage Temperature Range.............................-55°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
CC
CC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
CC
(V
= +3.0V to +3.6V, input data rate = 3.125Gbps, T = 0°C to +85°C. Typical values are at V
= +3.3V and T = +25°C, unless
CC A
A
otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
0.25
0.9
UNITS
EN = TTL low
EN = TTL high
Supply Power
W
0.7
100
40
10Hz < f < 100Hz
Supply Noise Tolerance
mVp-p
100Hz < f < 1MHz
1MHz < f < 2.5GHz
10
Signal Detect Assert
Input signal level to assert SDET (Note 1)
Input signal level to deassert SDET (Note 1)
100
mVp-p
mVp-p
Signal Detect Deassert
30
10
Delay time in detecting a change in
presence of a signal (Note 4)
Signal Detect Delay
µs
ns
Latency
From input to output
0.32
CML RECEIVER INPUT
XAUI transmitter output measured
differentially at point A, Figure 1, using
K28.5 pattern (Note 4)
Input Voltage Swing
200
80
800
120
mVp-p
Return Loss
100MHz to 2.5GHz
Differential
12
dB
Input Resistance
EQUALIZATION
100
Ω
Total jitter (Notes 2, 4)
Deterministic jitter (Note 4)
(Note 2)
0.3
0.2
Residual Jitter
Random Jitter
UIp-p
1.5
ps
RMS
CML TRANSMITTER OUTPUT (into 100Ω 1Ω)
Output Voltage Swing
Differential swing
550
850
mVp-p
V
0.3
-
CC
Common-Mode Voltage
V
Transition Time
t , t
20% to 80% (Notes 3, 4)
60
130
12
ps
ps
Ω
f
r
Difference in 50% crossing between OUT_+
and OUT_- (Note 4)
Differential Skew
Output Resistance
Single ended
40
50
60
2
_______________________________________________________________________________________
3.125Gbps XAUI Quad Cable Equalizer
ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.0V to +3.6V, input data rate = 3.125Gbps, T = 0°C to +85°C. Typical values are at V
= +3.3V and T = +25°C, unless
CC A
CC
A
otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TTL CONTROL PINS
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage
Output Low Voltage
2.0
V
V
0.8
250
500
µA
µA
V
Internal 10kΩ pullup
Internal 10kΩ pullup
2.4
0.4
V
Note 1: K28.7 pattern is applied differentially at point A as shown in Figure 1.
Note 2: Total jitter does not include the signal source jitter. Total jitter (TJ) = (14.1 ✕ RJ + DJ) where RJ is random RMS jitter and DJ
is maximum deterministic jitter. Signal source is a K28.5 pattern (00 1111 1010 11 0000 0101) for the deterministic jitter
test and K28.7 (0011111000) or equivalent for the random jitter test. Residual jitter is that which remains after equalizing
media-induced losses of the environment of Figure 1 or its equivalent. The deterministic jitter at point B must be from media-
induced loss and not from clock source modulation. Jitter is measured at 0V at point C of Figure 1.
Note 3: Using K28.7 (0011111000) pattern.
Note 4: AC specifications are guaranteed by design and characterization.
C
B
FR4
2"
CABLE
FR4
2"
A
SIGNAL
SOURCE
≤ 10 FEET
MAX3981
SMA
CONNECTOR
SMA
CONNECTOR
MADISON #14487, 100Ω
SHIELDED TWISTED PAIR
OUT
IN
Figure 1. Test Conditions Referenced in the Electrical Characteristics Table
_______________________________________________________________________________________
3
3.125Gbps XAUI Quad Cable Equalizer
Typical Operating Characteristics
7
(V
= +3.3V, 3.125Gbps, 500mVp-p cable input with 2 - 1 PRBS, T = +25°C, unless otherwise noted. Note: Twin-axial cable
A
CC
used was Tensolite, Z-Skew, 100Ω, 28AWG. Shielded twisted pair used was Madison 100Ω, 30AWG, spec #14887.)
EQUALIZER INPUT EYE DIAGRAM
AFTER 10m (33ft) OF TWIN-AXIAL CABLE
EQUALIZER OUTPUT EYE DIAGRAM
AFTER 10m (33ft) OF TWIN-AXIAL CABLE
EQUALIZER OPERATING
CURRENT vs. TEMPERATURE
210
190
170
150
130
110
90
NORMAL OPERATION
(EN = TTL HIGH)
100mV/
div
100mV/
div
STANDBY POWER
(EN = TTL LOW)
70
50
0
10 20 30 40 50 60 70 80
50ps/div
50ps/div
TEMPERATURE (°C)
INPUT RETURN GAIN
(S11, DIFFERENTIAL, INPUT
SIGNAL = -60dBm, DEVICE POWERED OFF)
EQUALIZER INPUT EYE DIAGRAM AFTER
5m (16ft) OF SHIELDED TWISTED PAIR
EQUALIZER OUTPUT EYE DIAGRAM AFTER
5m (16ft) OF SHIELDED TWISTED PAIR
10
0
-10
-20
-30
-40
-50
100mV/
div
60mV/
div
50
1050
2050
3050
4050
5050
50ps/div
50ps/div
FREQUENCY (MHz)
EQUALIZER DETERMINISTIC JITTER vs.
CABLE LENGTH
EQUALIZER DETERMINISTIC JITTER vs.
CABLE LENGTH
EQUALIZER LATENCY
vs. TEMPERATURE
(K28.5 PATTERN, 3.125Gbps)
(K28.5 PATTERN, 2.5Gbps)
500
450
400
350
300
250
200
60
50
40
30
20
10
0
60
50
40
30
20
10
0
SHIELDED TWISTED PAIR
(MADISON)
SHIELDED TWISTED PAIR
(MADISON)
TWIN-AXIAL
(TENSOLITE)
TWIN-AXIAL
(TENSOLITE)
0
10 20 30 40 50 60 70 80 90
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
TEMPERATURE (°C)
LENGTH (m)
LENGTH (m)
4
_______________________________________________________________________________________
3.125Gbps XAUI Quad Cable Equalizer
Pin Description
PIN
NAME
FUNCTION
1, 5, 9, 13,
23, 27, 31, 35
V
+3.3V Supply Voltage
CC
4, 8, 12, 16,
26, 30, 34, 38
GND
Supply Ground
2
IN1+
IN1-
Positive Equalizer Input Channel 1, CML
Negative Equalizer Input Channel 1, CML
Positive Equalizer Input Channel 2, CML
Negative Equalizer Input Channel 2, CML
Positive Equalizer Input Channel 3, CML
Negative Equalizer Input Channel 3, CML
Positive Equalizer Input Channel 4, CML
Negative Equalizer Input Channel 4, CML
No Connection. Leave unconnected.
3
6
IN2+
7
IN2-
10
IN3+
11
IN3-
14
IN4+
15
IN4-
17–22, 39–42
N.C.
24
25
28
29
32
33
36
37
OUT4-
OUT4+
OUT3-
OUT3+
OUT2-
OUT2+
OUT1-
OUT1+
Negative Equalizer Output Channel 4, CML
Positive Equalizer Output Channel 4, CML
Negative Equalizer Output Channel 3, CML
Positive Equalizer Output Channel 3, CML
Negative Equalizer Output Channel 2, CML
Positive Equalizer Output Channel 2, CML
Negative Equalizer Output Channel 1, CML
Positive Equalizer Output Channel 1, CML
Enable Equalizer Input. A TTL high selects normal operation. A TTL low selects low-power standby
mode.
43
44
EP
EN
SDET
Signal Detect Output for Channel 1. Produces a TTL high output when a signal is detected.
Exposed Ground. The exposed pad must be soldered to the circuit board ground plane for proper thermal and
Pad electrical performance.
_______________________________________________________________________________________
5
3.125Gbps XAUI Quad Cable Equalizer
ferent media. The equalizer operation is optimized for
short-run DC-balanced transmission codes such as
8b/10b codes.
Detailed Description
Receiver and Transmitter
The adaptive equalizer accepts four lanes of
3.125Gbps CML digital data signals and compensates
each received signal for dielectric and skin losses. A
limiting amp shapes the output of the equalizer and the
output driver transmits the regenerated XAUI lanes as
CML signals. The source impedance and termination
impedance are 100Ω differential.
CML Input and Output Buffers
The input and output buffers are implemented using
current-mode logic (CML). Equivalent circuits are shown
in Figures 2 and 3. For details on interfacing with CML,
see Maxim application note HFAN-1.0, Interfacing
Between CML, PECL, and LVDS. The common-mode
voltages of the input and output are above 2.5V. AC-
coupling capacitors are required when interfacing this
part. Values of 0.10µF or greater are recommended.
General Theory of Operation
Internally, the MAX3981 is comprised of signal-detect
circuitry, four matched equalizers, and one equalizer
control loop. The four equalizers are made up of a mas-
ter equalizer and three slave equalizers. The adaptive
control is generated from only channel 1. It is assumed
that all channels have the same characterization in fre-
quency content, coding, and transmission length.
Media Equalization
Equalization at the input port compensates for the high-
frequency loss encountered with twin-axial cable or
shielded twisted pair. This part is optimized for 10ft
(3m) and 3.125Gbps; however, the part will reduce ISI
for signals spanning longer distances and functions for
data rates from 2Gbps to 4Gbps providing that short-
length balanced codes, such as 8b/10b, are used.
The master equalizer consists of the following func-
tions: signal detect, adaptive equalizer, equalizer con-
trol, limiting and output drivers. The signal detect
indicates input signal power. When the input signal
level is sufficiently high, the SDET output is asserted.
This does not directly control the operation of the part.
Applications Information
Standby Mode
The standby state allows reduced-power operation.
The TTL input, EN, must be set to TTL high for normal
operation. A TTL low at EN forces the equalizer into the
standby state. The signal EN does not affect the opera-
The equalizer core reduces intersymbol interference
(ISI), compensating for frequency-dependent, media-
induced loss. The equalization control detects the
spectral contents of the input signal and provides a
control voltage to the equalizer core, adapting it to dif-
Functional Diagram
IP1, IN1 ONLY
SIGNAL
SDET
TTL
DETECT
IN1+
OUT1+
2
2
2
CML
3
3
3
4
4
LIMITING
AMP
EQUALIZER
IN1-
2
OUT1-
2
2
2
2
3
3
3
4
4
3
3
4
4
4
4
POWER
MANAGEMENT
EN
MAX3981
SDET FUNCTION IS
INDEPENDENT OF EN
6
_______________________________________________________________________________________
3.125Gbps XAUI Quad Cable Equalizer
V
CC
V
CC
50Ω
50Ω
1.2kΩ
OUT+
OUT-
50Ω
50Ω
IN+
IN-
Q1
Q2
DATA
ESD
STRUCTURES
200µA
ESD
STRUCTURES
Figure 2. CML Input Buffer
Figure 3. CML Output Buffer
tion of the signal detect (SDET) function. For constant
operation, connect the EN signal directly to V
Pin Configuration
.
CC
TOP VIEW
Signal Detect with Standby Mode
Signal activity is detected on channel 1 only (IN1 ).
When the peak-to-peak differential voltage at IN1 is
less than 30mVp-p, the TTL output SDET goes low.
When the peak-to-peak differential voltage becomes
greater than 100mVp-p, SDET is asserted high. SDET
can be used to automatically force the equalizer into
standby mode by connecting SDET directly to the EN
input. When not used, SDET should not be connected.
V
CC
1
2
3
4
5
6
7
8
9
33
32
31
30
29
28
27
26
25
24
23
OUT2+
OUT2-
IN1+
IN1-
GND
V
CC
GND
V
CC
OUT3+
OUT3-
The signal-detect function continues to operate while
the part is in standby mode. While connected to the EN
pin, the signal detect can “wake up” the part and
resume normal operation.
IN2+
IN2-
GND
MAX3981
V
CC
GND
V
CC
OUT4+
OUT4-
IN3+ 10
IN3- 11
Layout Considerations
Circuit board layout and design can significantly affect
the MAX3981 performance. Use good high-frequency
design techniques, including minimizing ground induc-
tances and vias and using controlled-impedance trans-
mission lines for the high-frequency data signals.
Signals should be routed differentially to reduce EMI
susceptibility and crosstalk. Power-supply decoupling
capacitors should be placed as close as possible to
V
CC
QFN*
*Note: Exposed pad must be soldered to supply ground.
the V
pins.
CC
_______________________________________________________________________________________
7
3.125Gbps XAUI Quad Cable Equalizer
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
32,44,48L QFN, 7x7x0.90 MM
1
21-0092
H
2
8
_______________________________________________________________________________________
3.125Gbps XAUI Quad Cable Equalizer
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE,
32,44,48L QFN, 7x7x0.90 MM
2
21-0092
H
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
相关型号：
MAX3983UGK+
Telecom Circuit, 1-Func, Bipolar, 10 X 10 MM, 0.90 MM HEIGHT, ROHS COMPLIANT, MO-220, QFN-68
MAXIM
MAX3983UGK+TD
Telecom Circuit, 1-Func, Bipolar, 10 X 10 MM, 0.90 MM HEIGHT, ROHS COMPLIANT, MO-220, QFN-68
MAXIM
©2020 ICPDF网 联系我们和版权申明