MAX6876ETX+T_技术文档

19-3479; Rev 0; 10/04

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

General Description

Features

♦ Tracking/Sequencing for Up to Four Supply

The MAX6876 EEPROM-configurable, multivoltage

power tracker/supervisor monitors four system voltages

and ensures proper power-up and power-down condi-

tions for systems requiring voltage tracking and/or

sequencing. The MAX6876 provides a highly config-

urable solution as key thresholds and timing parame-

ters are programmed through an I²C interface and

these values are stored in internal EEPROM. The

MAX6876 also provides supervisory functions and an

overcurrent detection circuit.

Voltages (With One MAX6876 Device) and

Tracking for Up to 16 Supply Voltages (Using

Four MAX6876 Devices)

♦ EEPROM-Configurable Tracking/Sequencing

Control

♦ Bus Voltage Independent Operation (MAX6876 Is

Powered from the Tracked Supply Voltages or

Always-On Supply)

The MAX6876 features programmable undervoltage and

overvoltage thresholds for each input supply. When all

voltages are within specifications, the device turns on the

external n-channel MOSFETs to either sequence or track

the voltages to the system. All of the voltages can be

sequenced or tracked or powered up with a combination

of the two options. During tracking, the voltage at the

GATE of each MOSFET is increased to slowly turn on

each supply. The voltages at the source of each MOSFET

are compared to each other to ensure that the voltage dif-

ferential between each monitored supply does not

exceed 250mV (typ). Tracking is dynamically adjusted to

force all outputs to track within a ±±25mV window from a

reference ramp; if, for any reason, any supply fails to

track within ±250mV from the reference ramp, a FAULT

output is asserted, the power-up mode is terminated, and

all outputs are powered off. Power-up mode is also termi-

nated if the controlled voltages fail to complete the ramp-

up within a programmable FAULT timeout. The MAX6876

features latch-off and autoretry modes to power on again

after a fault condition has been detected.

♦ EEPROM-Selectable Undervoltage/Overvoltage-

Lockout Thresholds for Each Input Supply

♦ EEPROM-Selectable Power-Up/Down Slew Rate

♦ Programmable Power-Good Output Thresholds

and Timing

♦ Global Adjustable Undervoltage Lockout or Logic

ENABLE Input

♦ Independent Internal Charge Pumps to Enhance

External n-Channel FETs (V

= 5V)

GATE_SOURCE

♦ Post Power-Up Selectable Overcurrent Detection

♦ 0.5V to 5.5V IN_ Threshold Range

♦

1.5ꢀ Threshold Accuracy

♦ I²C/SMBus™-Compatible Serial Interface

♦ Small 6mm x 6mm, 36-Pin Thin QFN Package

Ordering Information

PIN-

PACKAGE

PKG

CODE

PART

TEMP RANGE

Other features of the MAX6876 include a reset circuit, a

manual reset input (MR), and a margin disable input

(MARGIN). The device also features outputs for indicat-

ing a power-good condition (PG_) and an overcurrent

condition (OC), and a bus-removal (REM) output.

MAX6876ETX

-40°C to +85°C

36 Thin QFN

T3666-3

Pin Configuration

The MAX6876 is available in a small 6mm x 6mm, 36-

pin thin QFN package and is fully specified over the

extended -40°C to +85°C temperature range.

TOP VIEW

36 35 34 33 32 31 30 29 28

V

1

2

3

4

5

6

7

8

9

27 IN4

Applications

CC

GND

ABP

26 GATE4

25 OUT4

24 REFIN

23 N.C.

22 PG4

21 PG3

Multivoltage Systems

Networking Systems

Telecom

Storage Equipment

TRKEN

SYNCH

HOLD

OC

Servers/Workstations

MAX6876

PG2

REM

20

EP*

FAULT

19 PG1

10 11 12 13 14 15 16 17 18

6mm x 6mm

THIN QFN

*EXPOSED PADDLE

SMBus is a trademark of Intel Corp.

________________________________________________________________ Maxim Integrated Products

1

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

ABSOLUTE MAXIMUM RATINGS

(All voltages are referenced to GND, unless otherwise noted.)

GATE_.............................................................-0.3V to (IN_ + 6V)

OUT_, GND Current..........................................................±ꢁ0ꢀA

Continuous Power Dissipation (T = +70°C)

A

IN1–IN4, V ............................................................-0.3V to +6V

36-Pin, 6ꢀꢀ x 6ꢀꢀ Thin QFN

CC

OUT1–OUT4, SYNCH, ABP,

REFIN...............................-0.3V to Max (IN1–IN4, V

(derate ±6.3ꢀW/°C above +70°C)..............................±10ꢁꢀW

Operating Teꢀperature Range ...........................-40°C to +8ꢁ°C

Storage Teꢀperature Range.............................-6ꢁ°C to +1ꢁ0°C

Maxiꢀuꢀ Junction Teꢀperature .....................................+1ꢁ0°C

Lead Teꢀperature (soldering, 10s) .................................+300°C

) + 0.3V

CC

ENABLE, TRKEN, HOLD, FAULT, MR, MARGIN......-0.3V to +6V

RESET, PG1–PG4, OC, REM....................................-0.3V to +6V

SDA, SCL, A0, A1.....................................................-0.3V to +6V

Input/Output Current (all pins except OUT_ and GND) ...±±0ꢀA

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(V , IN1–IN4 = +±.7V to +ꢁ.ꢁV; ENABLE = MARGIN = MR = ABP = TRKEN; T = -40°C to +8ꢁ°C, unless otherwise specified.

CC

A

Typical values are at T = +±ꢁ°C.) (Note 1)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

ꢁ.ꢁ

UNITS

GATE_ = PG_ = RESET = 0

1.4

Operating Voltage Range

(Note ±)

V

CC

Voltage on ABP (froꢀ V

or IN1–IN4) to

CC

±.7

ensure the device is fully operational

Miniꢀuꢀ voltage on ABP (froꢀ V or

CC

Undervoltage Lockout

V

IN1–IN4) to ensure the device is EEPROM

±.ꢁ

V

UVLO

configured

V

= ꢁ.ꢁV, IN1–IN4 = 3.3V, no load

1.8

±.ꢁ

3

4

CC

Supply Current

I

ꢀA

V

CC

Configuration registers or ꢀeꢀory access,

no load

IN1–IN4 (in ±0ꢀV increꢀents)

IN1–IN4 (in 10ꢀV increꢀents)

1.00

0.ꢁ0

ꢁ.ꢁ0

3.0ꢁ

IN_ Threshold Range

V

TH

0.ꢁV < IN_ < ꢁ.ꢁV, IN_

T

= 0°C to +8ꢁ°C

-1.ꢁ

-±.ꢁ

-ꢁ0

+1.ꢁ

+±.ꢁ

+ꢁ0

%

falling for UV, rising for

OV

A

±V < IN_ < ꢁ.ꢁV, IN_

falling for UV, rising for

OV (±0ꢀV increꢀents)

%

ꢀV

%

1V < IN_ < ±V, IN_

falling for UV, rising for

OV (±0ꢀV increꢀents)

Threshold Accuracy

T

A

= -40°C to

+8ꢁ°C

1V < IN_ < 3.0ꢁV, IN_

falling for UV, rising for

OV (10ꢀV increꢀents)

-±.ꢁ

+±.ꢁ

0.ꢁV < IN_ < 1V, IN_

falling for UV, rising for

OV (10ꢀV increꢀents)

ꢀV

-±ꢁ

+±ꢁ

Threshold Hysteresis

V

0.ꢁ

ꢁ0

%V

TH

TH_HYS

RESET Threshold Teꢀpco

∆V

ppꢀ/°C

TH/C

2

_______________________________________________________________________________________

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

ELECTRICAL CHARACTERISTICS (continued)

(V , IN1–IN4 = +±.7V to +ꢁ.ꢁV; ENABLE = MARGIN = MR = ABP = TRKEN; T = -40°C to +8ꢁ°C, unless otherwise specified.

CC

A

Typical values are at T = +±ꢁ°C.) (Note 1)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Tracking-Differential-Voltage Hold

Raꢀp (Note 3)

V

> V

< V

OUT_

TH_PL

V

9ꢁ

1±ꢁ

1ꢁꢁ

ꢀV

TRK

TH_PG

Tracking-Differential-Voltage

Hysteresis

±ꢁ

ꢀV

Tracking-Differential FAULT

Voltage (Note 3)

V

> V

< V

OUT_

TH_PL

TH_PG

V

±00

±ꢁ0

300

TRK_F

00

01

10

11

±0

40

±ꢁ

ꢁ0

30

60

Register

contents

(Table 16)

t

,

FAULTUP

FAULT Tiꢀeout Period (Note 4)

ꢀs

t

FAULTDOWN

80

100

±00

±

1±0

±40

160

FAULT to GATE Delay

IN1–IN4 Input Iꢀpedance

OUT1–OUT4 Input Iꢀpedance

Power-On Delay

t

µs

kΩ

ꢀs

µs

FG

R

For IN_ voltages < the highest IN_ supply

OUT_ pulldown disabled

ꢁꢁ

70

90

14ꢁ

130

3

IN1-4

R

100

OUT1-4

t

V

≥ V

ABP UVLO

PO

D-GATE

IN_ to GATE_ Delay

t

IN_ falling/rising, 100ꢀV overdrive

6

OUT_ rising, 100ꢀV overdrive

3

ꢀs

µs

OUT_ to PG_ Delay

t

POK

OUT_ falling, 100ꢀV overdrive

±ꢁ

000

001

010

±ꢁ

µs

10

±0

1±.ꢁ

±ꢁ

1ꢁ

30

t

Register

contents

(Table 16)

RESET,

011

40

ꢁ0

60

GATE, RESET, Autoretry Tiꢀeout

Period (Notes ꢁ, 6)

AUTO,

100

80

100

±00

400

1600

1±.ꢁ

ꢁ0

1±0

±40

480

19±0

1ꢁ

ꢀs

t

GATE

101

110

111

00

160

3±0

1±80

10

Register

contents

(Table 16)

01

40

60

OC Tiꢀeout Period

t

OC

10

80

100

±00

800

400

±00

100

97.ꢁ

9ꢁ

1±0

±40

1040

11±0

ꢁ±0

ꢁ60

±60

±80

130

140

98.7ꢁ

96.±ꢁ

93.7ꢁ

91.±ꢁ

11

160

ꢁ60

480

±80

±40

140

1±0

70

T

A

T

A

T

A

T

A

T

A

T

A

T

A

T

A

= 0°C to +8ꢁ°C

= -40°C to 0°C

= 0°C to +8ꢁ°C

= -40°C to 0°C

= 0°C to +8ꢁ°C

= -40°C to 0°C

= 0°C to +8ꢁ°C

= -40°C to 0°C

00

01

10

11

Register

contents

(Table 16)

Track/Sequence Slew Rate Rising

or Falling

TRK

V/s

SLEW

60

00

01

10

11

96.±ꢁ

93.7ꢁ

91.±ꢁ

88.7ꢁ

Register

contents

(Table 16),

OUT_ falling

IN_ to OUT_ Overcurrent

Threshold

V

%

TH_OC

9±.ꢁ

90

_______________________________________________________________________________________

3

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

ELECTRICAL CHARACTERISTICS (continued)

(V , IN1–IN4 = +±.7V to +ꢁ.ꢁV; ENABLE = MARGIN = MR = ABP = TRKEN; T = -40°C to +8ꢁ°C, unless otherwise specified.

CC

A

Typical values are at T = +±ꢁ°C.) (Note 1)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

9ꢁ

MAX

96.±ꢁ

93.7ꢁ

91.±ꢁ

88.7ꢁ

UNITS

00

01

10

11

93.7ꢁ

91.±ꢁ

88.7ꢁ

86.±ꢁ

Register

contents

(Table 16),

OUT_ rising

9±.ꢁ

90

IN_ to OUT_ Power-Good

Threshold

V

%

TH_PG

87.ꢁ

0.ꢁ

14±

10

V

Hysteresis

V

%

TH_PG and TH_OC

OUT_HYS

Power Low Threshold

Power Low Hysteresis

V

OUT_ falling

1±ꢁ

16ꢁ

ꢀV

TH_PL

TH_PL_HYS

V

OUT_ to GND Pulldown

Iꢀpedance (When Enabled)

ABP ≥ ±.ꢁV

100

Ω

ABP ≥ ±.ꢁV, I

ABP ≥ 4.0V, I

= 4ꢀA

0.3

0.4

SINK

REM Output Low

V

OL_REM

= 1ꢁꢀA

ABP ≥ 1.4V, I

only)

= ꢁ0µA (PG_, RESET

0.3

Output Low PG1–PG4, HOLD,

FAULT, OC, RESET (Note ±)

V

OL

ABP ≥ ±.ꢁV, I

ABP ≥ 4.0V, I

ABP ≥ 1.4V, I

ABP ≥ ±.ꢁV, I

ABP ≥ 4.0V, I

= 1ꢀA

= 4ꢀA

= ꢁ0µA

= 1ꢀA

= 4ꢀA

0.3

0.4

0.3

0.8

SINK

GATE1–GATE4 Output Low

V

GOL

SINK

PG1–PG4, HOLD, FAULT, OC ,

RESET, REM Output Open-Drain

Leakage Current

I

Output deasserted

-1

+1

µA

V

LKG

IN_ +

4.4

IN_ +

ꢁ.8

GATE_ Output-Voltage High

V

I

= 0.ꢁµA

IN_ + ꢁ

GOH

GATE_

GATE_ Pullup Current

I

During power-up/down, V

= 1V

= 4V

±.ꢁ

4.ꢁ

µA

GATEUP

GATE_

GATE_ Pulldown Current

I

GATEDOWN

GATE_

0.3 x

ABP

V

IL

MARGIN, FAULT, HOLD, MR,

ENABLE Input Voltage

V

0.6 x

ABP

V

IH

MR Input Pulse Width

t

±

µs

ns

MR

FAULT, HOLD, MARGIN, MR,

ENABLE Glitch Rejection

100

Digital Input to Logic Delay,

FAULT, HOLD, MARGIN, MR,

ENABLE

t

D

1

µs

MARGIN, MR Digital Input to ABP

Pullup Resistance

R

P

70

100

130

kΩ

4

_______________________________________________________________________________________

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

ELECTRICAL CHARACTERISTICS (continued)

(V , IN1–IN4 = +±.7V to +ꢁ.ꢁV; ENABLE = MARGIN = MR = ABP = TRKEN; T = -40°C to +8ꢁ°C, unless otherwise specified.

CC

A

Typical values are at T = +±ꢁ°C.) (Note 1)

A

PARAMETER

TRKEN Input Delay

SYMBOL

CONDITIONS

TRKEN falling, 100ꢀV overdrive

Input rising

MIN

TYP

±

MAX

UNITS

t

µs

EN

1.±4ꢁ

1.±±ꢁ

-100

1.±8ꢁ

1.±ꢁ

1.3±0

1.±7ꢁ

+100

1.±7ꢁ

TRKEN Reference Voltage Range

V

TRKEN

Input falling

TRKEN Input Current

I

V

= 1.±ꢁV

nA

V

TRKEN

REFIN

Reference Input Voltage Range

Reference Input Resistance

V

R

1.±±ꢁ

1.±ꢁ

ꢁ00

REFIN

V

= 1.±ꢁV

kΩ

REFIN

SERIAL INTERFACE LOGIC (SDA, SCL, A0, A1)

0.3 x

ABP

Logic-Input Low Voltage

Logic-Input High Voltage

V

IL

0.6 x

ABP

V

IH

Input Leakage Current

Output-Voltage Low

I

1

0.4

1

µA

V

ILKG

V

I

= 3ꢀA

OL

SINK

Output Leakage Current

Input/Output Capacitance

I

µA

pF

OLKG

C

10

I/O

SERIAL INTERFACE TIMING (SDA, SCL)

Serial Clock Frequency

Clock Low Period

Clock High Period

Bus Free Tiꢀe

f

400

kHz

µs

ns

SCL

t

1.3

0.6

1.3

0.6

0.1

ꢁ0

LOW

t

HIGH

t

BUF

START Setup Tiꢀe

START Hold Tiꢀe

STOP Setup Tiꢀe

Clock Low to Valid Output

Data Out Hold Tiꢀe

Data In Setup Tiꢀe

Data In Hold Tiꢀe

SCL/SDA Rise Tiꢀe

SCL/SDA Fall Tiꢀe

t

SU:STA

HD:STA

SU:STO

t

0.9

AA

DH

t

100

0

SU:DAT

HD:DAT

t

300

R

t

F

±0 +

0.1 x

Transꢀit SDA Fall Tiꢀe

t

C

= 400pF

300

ns

BUS

C

BUS

SCL/SDA Noise Suppression Tiꢀe

Byte Write Cycle Tiꢀe

t

ꢁ0

ns

I

t

11

ꢀs

WR

Note 1: Specifications guaranteed for the stated global conditions. 100% production tested at T = +±ꢁ°C and T = +8ꢁ°C.

A

Specifications at T = -40°C are guaranteed by design.

A

Note 2: The internal supply voltage, ꢀeasurable on ABP, is equal to the ꢀaxiꢀuꢀ of IN1–IN4 and V

supplies.

CC

Note 3: Differential between each of the OUT_ and the SYNCH raꢀp voltage during power-up/down ꢀeasured as V

- ± x

OUT_

V

.

SYNCH

Note 4: FAULT tiꢀeout starts to count at the beginning of each sequence of power-up/down and clears when the prograꢀꢀed

OUT_ voltages track successfully.

_______________________________________________________________________________________

5

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

ELECTRICAL CHARACTERISTICS (continued)

(V , IN1–IN4 = +±.7V to +ꢁ.ꢁV; ENABLE = MARGIN = MR = ABP = TRKEN; T = -40°C to +8ꢁ°C, unless otherwise specified.

CC

A

Typical values are at T = +±ꢁ°C.) (Note 1)

A

Note 5: The MAX6876 prograꢀꢀed as a single device; GATE tiꢀeout has counted prior to beginning each sequence of power-up.

GATE tiꢀeout is not enabled during power-down or when the device is prograꢀꢀed as a ꢀaster/slave.

Note 6: The MAX6876 prograꢀꢀed as a single device, the autoretry tiꢀe begins to count at the assertion of the FAULT signal.

The MAX6876 prograꢀꢀed as a ꢀaster/slave device; the autoretry tiꢀe begins to count at the deassertion of the

coꢀꢀon FAULT signal.

Timing Diagrams

V

TRKEN

BUS VOLTAGE MONITORED THROUGH TRKEN INPUT

GND

IN1 = 3.3V

IN2 = 2.5V

IN3 = 1.8V

IN4 = 1.5V

MONITORED THROUGH SET THRESHOLDS ON IN_

INPUTS (EEPROM-SELECTABLE)

OUT1 = 3.3V

EEPROM-

ADJUSTED

SLEW RATE

OUT2 = 2.5V

OUT3 = 1.8V

OUT4 = 1.5V

t

GATE

>t

FAULTDOWN

<t

FAULTUP

RESET

t

RESET

GND

FAULT

GND

Figure 1. Tracking Timing Diagram

6

_______________________________________________________________________________________

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

Timing Diagrams (continued)

V

TRKEN

BUS VOLTAGE MONITORED THROUGH TRKEN INPUT

TRKEN

GND

IN1 = 3.3V

IN2 = 2.5V

IN3 = 1.8V

IN4 = 1.5V

MONITORED THROUGH SET THRESHOLDS ON IN_ INPUTS

(EEPROM-SELECTABLE)

GND

EEPROM-

ADJUSTED

SLEW RATE

OUT1 = 3.3V

OUT2 = 2.5V

OUT3 = 1.8V

OUT4 = 1.5V

t

GATE

GND

t

RESET

Figure 2. Sequencing Timing Diagram

_______________________________________________________________________________________

7

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

Timing Diagrams (continued)

V

TRKEN

BUS VOLTAGE MONITORED THROUGH TRKEN INPUT

GND

IN1 = 2.5V

IN2 = 1.8V

IN3 = 0.9V

IN4 = 0.7V

MONITORED THROUGH SET THRESHOLDS ON IN_ INPUTS

(EEPROM-SELECTABLE)

GND

EEPROM-

SELECTED

SLEW RATE

OUT1 = 2.5V

EEPROM-

SELECTED

SLEW RATE

(FORCED INTO

QUICK SHUTDOWN

WHEN IN1 FAILS)

OUT2 = 1.8V

OUT3 = 0.9V

OUT4 = 0.7V

GND

GATE

t

RESET

Figure 3. Voltage Tracking with Forced Shutdown (IN1 UV Failure)

FULL TRK

FULL SEQ

ENABLE

SYNCH

MIX WITH 3 RAMP

(FAST SHUTDOWN BIT SET)

OUT1 = 4V

OUT2 = 3V

OUT3 = 2V

OUT4 = 1V

MIX WITH 2 RAMP

Figure 5. Mixed-Mode Tracking/Sequencing Examples

Figure 4. Sequencing Ramp Down Diagram

8

_______________________________________________________________________________________

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

Typical Operating Characteristics

(V

= 3.3V, ENABLE = MARGIN = MR = ABP = TRKEN, T = +±ꢁ°C, unless otherwise noted.)

CC

A

NORMALIZED TIMEOUT PERIOD

SUPPLY CURRENT

vs. SUPPLY VOLTAGE

NORMALIZED IN_ THRESHOLD

vs. TEMPERATURE

2.00

1.90

1.015

1.100

1.050

1.000

0.950

0.900

1.010

1.005

1.000

0.995

0.990

0.985

0.980

0.975

1.80

1.70

1.60

1.50

1.40

1.30

1.20

1.10

1.00

0.90

2.7

3.4

4.1

4.8

5.5

-40

-15

10

35

60

85

-40

-15

10

35

60

85

SUPPLY VOLTAGE (V)

TEMPERATURE (°C)

MAXIMUM IN_ TRANSIENT DURATION

vs. IN_ THRESHOLD OVERDRIVE

GATE OUTPUT-VOLTAGE LOW

vs. SINK CURRENT

NORMALIZED PG AND OC THRESHOLD

vs. TEMPERATURE

130

120

110

100

90

80

70

60

50

40

30

20

10

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

1.010

1.005

1.000

0.995

0.990

0.985

0

1

10

100

1000

0

3

6

9

12 15 18 21 24 27 30 33

(mA)

-40

-15

10

35

60

85

IN_ THRESHOLD OVERDRIVE (mV)

I

SINK

TEMPERATURE (°C)

TRACKING MODE WITH

FAST SHUTDOWN

SEQUENCING MODE

TRACKING MODE

MAX6876 toc08

MAX6876 toc09

MAX6876 toc07

OUT4

OUT3

OUT4

OUT3

OUT2

OUT_

1V/div

OUT_

1V/div

OUT_

1V/div

OUT2

OUT1

OUT2

OUT1

0V

20ms/div

10ms/div

_______________________________________________________________________________________

9

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

Typical Operating Characteristics (continued)

(V

= 3.3V, ENABLE = MARGIN = MR = ABP = TRKEN, T = +±ꢁ°C, unless otherwise noted.)

A

CC

MIXED MODE

MIXED MODE WITH FAST SHUTDOWN

MAX6876 toc10

MAX6876 toc11

OUT4

OUT3

OUT2

OUT1

OUT3

OUT2

OUT_

1V/div

OUT_

1V/div

OUT1

0V

20ms/div

Pin Description

NAME

FUNCTION

Optional Supply Voltage Input. Connect V

to an alternate (i.e., always-on) supply if desired. V

CC

supports operation/coꢀꢀunication when the ꢀonitored supplies are not powered or are below the

ꢀiniꢀuꢀ required operating voltage. In a ꢀaster/slave application, connect all V pins to a coꢀꢀon

CC

1

V

CC

supply line.

±

3

GND

ABP

Ground

Internal Analog Bypass. Bypass ABP with a 1µF capacitor to GND. ABP ꢀaintains the device supply

voltage during rapid power-down conditions.

Tracking Enable Input. TRKEN ꢀust be higher than 1.±8ꢁV to enable voltage tracking power-up

operation. When TRKEN falls below 1.±ꢁV (3% hysteresis), OUT_ tracks down. Connect TRKEN to an

external resistor-divider network to set the desired ꢀonitor threshold. Connect TRKEN to ABP if not

used.

4

ꢁ

TRKEN

SYNCH

Selectable Tracking Synchronization Output/Input. SYNCH allows ꢀultiple MAX6876 devices to

±

control tracking of ꢀultiple power supplies (up to 16 voltages on the saꢀe I C bus). One device is

prograꢀꢀed as SYNCH ꢀaster and all other devices are prograꢀꢀed as slaves. SYNCH on the

ꢀaster outputs the coꢀꢀon raꢀp voltage to which all OUT_ voltages are tracked (with active control

loops). SYNCH of the slave devices is input for the raꢀp control voltage (no internal raꢀp is

generated in the slaves) (see the SYNCH section). Connect SYNCH to other SYNCH pins only.

Active-Low, Open-Drain Synchronization Hold Output/Input. HOLD coꢀꢀunicates synchronization

status between ꢀaster/slave devices in ꢀultiple MAX6876 applications. The HOLD output reꢀains

asserted while selected tracking IN_ inputs are below their selected thresholds (the slave device can

delay tracking start until its inputs are at their required stable voltage levels) or held low by the ꢀaster

when it is counting the autoretry tiꢀe after a detected fault condition (see the Synchronization Hold

Output (HOLD) section). Slave device SYNCH are inputs for the raꢀp control voltage.

6

HOLD

10 ______________________________________________________________________________________

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

Pin Description (continued)

NAME

FUNCTION

Active-Low, Open-Drain Overcurrent Output. OC asserts low if any ꢀonitored IN_ to OUT_ voltage

falls out of the selected percentage of the IN_ voltage range (V

) for ꢀore than the prograꢀꢀed

TH_OC

7

OC

t

OC ꢀonitoring begins only after supply tracking or sequencing has been coꢀpleted and is

OC.

disabled during power-down operation.

Open-Drain Bus Reꢀoval Output. REM signals when it is safe to reꢀove the card after a controlled

track/sequence-down operation. REM goes high iꢀpedance when all V < V . REM requires

OUT_

TH_PL

8

9

REM

an external pullup resistor. In ꢀaster/slave ꢀode, REM can be ORed together (the coꢀꢀon REM

connection reꢀains low if any V > V threshold) (see the Typical Application Circuit and the

Bus Removal Output (REM) section).

OUT_

TH_PL

Active-Low, Open-Drain Tracking Fault Alert Output or Input. FAULT asserts low if a tracking failure is

present for longer than the specified fault period or if tracking voltages fails by ꢀore than ±±ꢁ0ꢀV

(see the FAULT section).

FAULT

Active-Low, Open-Drain Reset or Power-Good Output. RESET is low during power-up and power-

down tracking. RESET goes high after all selected OUT_ outputs exceed their selected thresholds

10

11

RESET

and the reset tiꢀeout period t

has expired. The reset tiꢀeout period is internally selectable.

RESET

RESET requires an external pullup resistor.

Logic ENABLE Input. ENABLE ꢀust be high to enable voltage tracking/sequencing power-up

operation. OUT_ begins tracking down when ENABLE is low. Connect to ABP if not used.

ENABLE

Active-Low Margin Input. The MARGIN function allows systeꢀs to be tested with supply voltages

outside their norꢀal ranges without affecting supply tracking/sequencing or reset states. MARGIN

functionality is usually enabled after systeꢀs have powered up in norꢀal ꢀode. The MARGIN

functionality is disabled (returns to norꢀal ꢀonitoring ꢀode) after MARGIN returns high. MARGIN is

internally pulled up to ABP through a 100kΩ resistor.

1±

MARGIN

13, ±3

14

N.C.

No Connection. Not internally connected.

Active-Low Manual Reset Input. When MR is low, RESET goes low and reꢀains asserted for the

selected tiꢀeout period after MR is pulled high. MR is internally pulled up to ABP through a 100kΩ

resistor.

MR

1ꢁ

16

17

18

19

SDA

SCL

A0

Serial-Interface Data Input/Output (Open-Drain). SDA requires an external pullup resistor.

Serial-Interface Clock Input. SCL requires an external pullup resistor.

Serial-Interface Address Inputs. The inputs allow up to four MAX6876 devices to be addressed when

sharing a coꢀꢀon data bus. A1 and A0 should be connected to GND or ABP.

A1

PG1

Power-Good Output, Open-Drain. Each PG_ output signals when its ꢀonitored OUT_ voltage is within

±0

±1

±±

PG±

PG3

PG4

the selected percentage of the IN_ voltage range (V

). PG_ is low until OUT_ exceeds the

. PG_ outputs are open-drain and require

TH_PG

prograꢀꢀable threshold (V

external pullups if used.

) for ꢀore than t

TH_PG

POK

______________________________________________________________________________________ 11

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

Pin Description (continued)

NAME

FUNCTION

Reference Voltage Input. The MAX6876 can be configured to use the internal 1.±ꢁV reference or an

external voltage reference. REFIN is tri-stated when using the internal reference. REFIN provides the

threshold voltage for the voltage detectors when using an external voltage reference. Use an external

voltage reference when tighter voltage-detector accuracy is desired. When configured to an internal

reference, leave REFIN unconnected. When configured for an external reference, connect a 1.±±ꢁV to

1.±7ꢁV reference to REFIN.

±4

REFIN

Monitored Output Voltage. The OUT4 output is ꢀonitored to control the supply slew rate and tracking

perforꢀance. OUT1–OUT4 begin to track up after the internal supply (ABP) exceeds the ꢀiniꢀuꢀ

voltage requireꢀents, V

> 1.±8ꢁV threshold, ENABLE is logic high, and IN1–IN4 are all within

TRKEN

±ꢁ

±6

OUT4

their selected thresholds. The OUT4 output falls out of the tracking equation as OUT4 approaches

IN4; other OUT_ supplies continue tracking up without signaling a systeꢀ fault. OUT_ outputs are

tracked down during power-off conditions.

Gate Drive for External n-Channel FETs. GATE4 begins enhancing the external n-channel FETs when

all ꢀonitored inputs are within their selected thresholds (0.ꢁV to ꢁ.ꢁV), at least one IN_ input or V

above the ꢀiniꢀuꢀ operating voltage, V

high. During power-up ꢀode, GATE_ voltages are enhanced with internal control loops forcing all

OUT_ voltages to track the reference raꢀp (SYNCH) at a prograꢀꢀed slew rate. An internal charge

is

CC

> 1.±8ꢁV threshold, and the ENABLE input is logic

TRKEN

GATE4

puꢀp boosts GATE4 to V

coꢀplete.

+ ꢁV to fully enhance the external n-channel FET when power-up is

IN4

Supply Voltage and Tracked Input Voltage. Noꢀinal supply range is 0.ꢁV to ꢁV. IN1, IN±, IN3, IN4, or

ꢀust be greater than the internal UVLO (V = ±.7V) to enable the tracking functionality. The

IN4 input is ꢀonitored with internally selected thresholds to ensure all supplies have stabilized before

tracking (or sequencing) is enabled.

V

CC

ABP

±7

±8

IN4

Monitored Output Voltage. OUT3 is ꢀonitored to control the supply slew rate and tracking

perforꢀance. OUT1–OUT4 begin to track up after the internal supply (ABP) exceeds the ꢀiniꢀuꢀ

voltage requireꢀents, V

> 1.±8ꢁV threshold, ENABLE is logic high, and IN1–IN4 are all within

TRKEN

OUT3

their selected thresholds. The OUT3 output falls out of the tracking equation as OUT3 approaches

IN3; other OUT_ supplies continue tracking up without signaling a systeꢀ fault. OUT_ outputs are

tracked down during power-off conditions.

Gate Drive for External n-Channel FETs. GATE3 begins enhancing the external n-channel FETs when

all ꢀonitored inputs are within their selected thresholds (0.ꢁV to ꢁ.ꢁV), at least one IN_ input or V

is

CC

above the ꢀiniꢀuꢀ operating voltage, V

> 1.±8ꢁV threshold, and the ENABLE input is logic

TRKEN

±9

GATE3

high. During power-up ꢀode, GATE_ voltages are enhanced with internal control loops forcing all

OUT_ voltages to track the reference raꢀp (SYNCH) at a prograꢀꢀed slew rate. An internal charge

puꢀp boosts GATE3 to V

coꢀplete.

+ ꢁV to fully enhance the external n-channel FET when power-up is

IN3

Supply Voltage and Tracked Input Voltage. Noꢀinal supply range is 0.ꢁV to ꢁV. IN1, IN±, IN3, IN4, or

ꢀust be greater than the internal UVLO (V = ±.7V) to enable the tracking functionality. IN3 is

ꢀonitored with internally selected thresholds to ensure all supplies have stabilized before tracking (or

sequencing) is enabled.

V

CC

ABP

30

31

IN3

Monitored Output Voltage. OUT± is ꢀonitored to control the supply slew rate and tracking

perforꢀance. OUT1–OUT4 begin to track up after the internal supply (ABP) exceeds the ꢀiniꢀuꢀ

voltage requireꢀents, V

> 1.±8ꢁV threshold, ENABLE is logic high, and IN1–IN4 are all within

TRKEN

OUT±

their selected thresholds. OUT± output falls out of the tracking equation as OUT± approaches IN±;

other OUT_ supplies continue tracking up without signaling a systeꢀ fault. OUT_ outputs are tracked

down during power-off conditions.

12 ______________________________________________________________________________________

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

Pin Description (continued)

NAME

FUNCTION

Gate Drive for External n-Channel FETs. GATE± begins enhancing the external n-channel FETs when

all ꢀonitored inputs are within their selected thresholds (0.ꢁV to ꢁ.ꢁV), at least one IN_ input or V

is

CC

above the ꢀiniꢀuꢀ operating voltage, V

> 1.±8ꢁV threshold, and the ENABLE input is logic

TRKEN

3±

GATE±

high. During power-up ꢀode, GATE_ voltages are enhanced with internal control loops forcing all

OUT_ voltages to track the reference raꢀp (SYNCH) at a prograꢀꢀed slew rate. An internal charge

puꢀp boosts GATE± to V

coꢀplete.

+ ꢁV to fully enhance the external n-channel FET when power-up is

IN±

Supply Voltage and Tracked Input Voltage. Noꢀinal supply range is 0.ꢁV to ꢁV. IN1, IN±, IN3, IN4, or

ꢀust be greater than the internal UVLO (V = ±.7V) to enable the tracking functionality. IN± is

ꢀonitored with internally selected thresholds to ensure all supplies have stabilized before tracking (or

sequencing) is enabled.

V

CC

ABP

33

34

IN±

Monitored Output Voltage. Each OUT1 is ꢀonitored to control the supply slew rate and tracking

perforꢀance. OUT1–OUT4 begin to track up after the internal supply (ABP) exceeds the ꢀiniꢀuꢀ

voltage requireꢀents, V

> 1.±8ꢁV threshold, ENABLE is logic high, and IN1–IN4 are all within

TRKEN

OUT1

their selected thresholds. The OUT1 output falls out of the tracking equation as OUT1 approaches

IN1; other OUT_ supplies continue tracking up without signaling a systeꢀ fault. OUT_ outputs are

tracked down during power-off conditions.

Gate Drive for External n-Channel FETs. GATE1 begins enhancing the external n-channel FETs when

all ꢀonitored inputs are within their selected thresholds (0.ꢁV to ꢁ.ꢁV), at least one IN_ input or V

is

CC

above the ꢀiniꢀuꢀ operating voltage, V

> 1.±8ꢁV threshold, and the ENABLE input is logic

TRKEN

3ꢁ

GATE1

high. During power-up ꢀode, GATE_ voltages are enhanced with internal control loops forcing all

OUT_ voltages to track the reference raꢀp (SYNCH) at a prograꢀꢀed slew rate. An internal charge

puꢀp boosts GATE1 to V

coꢀplete.

+ ꢁV to fully enhance the external n-channel FET when power-up is

IN1

Supply Voltage and Tracked Input Voltage. Noꢀinal supply range is 0.ꢁV to ꢁV. IN1, IN±, IN3, IN4, or

ꢀust be greater than the internal UVLO (V = ±.7V) to enable the tracking functionality. IN1 is

ꢀonitored with internally selected thresholds to ensure all supplies have stabilized before tracking (or

sequencing) is enabled.

V

CC

ABP

36

IN1

EP

—

Exposed Paddle. Exposed paddle is internally connected to GND.

The MAX6876 features prograꢀꢀable undervoltage

and overvoltage thresholds for each input supply. The

Detailed Description

The MAX6876 EEPROM-configurable, ꢀultivoltage

power tracker/supervisor ꢀonitors four systeꢀ voltages

and ensures proper power-up and power-down condi-

tions for systeꢀs requiring voltage tracking and/or

sequencing. The MAX6876 provides a highly config-

urable solution as key thresholds and tiꢀing paraꢀe-

ters are prograꢀꢀed through an I^±C interface and

these values are stored in internal EEPROM. In addition

to tracking and sequencing voltages, the MAX6876

also provides supervisory functions as well as an over-

current detection circuit.

thresholds are EEPROM configured in 10ꢀV (0.ꢁV to

3.0ꢁV) or ±0ꢀV (1.0V to ꢁ.ꢁV) increꢀents. When all of

the voltages are within their specifications, the device

turns on the external n-channel MOSFETs to either

sequence or track the voltages to the systeꢀ. All of the

voltages can be sequenced or tracked or powered up

with a coꢀbination of the two options. During voltage

tracking, the voltage at the GATE of each MOSFET is

increased to slowly turn on each OUT_. The GATE

delay is EEPROM-selectable froꢀ ±ꢁµs to 1.6s. The

______________________________________________________________________________________ 13

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

Functional Diagram

IN1

IN2

IN3

IN4

ABP

V

CC

ABP

GATE1 OUT1

V

= V + 5V

IN1

CP1

INTERNAL

SUPPLY/UVLO

MAX6876

CHARGE

PUMP

IN1

PG1

OVER-

CURRENT

DETECT

UV/OV

IN1

COMP

RAMP

GENERATOR

V

THPG

COMP

IN2

UV/OV

ABP

CONTROL

LOGIC

IN3

UV/OV

GND

GATE2

PG2

OUT2

RAMP

IN2 TO OUT2

CONTROL BLOCK

OUT1

IN4

OUT2

OUT3

OUT4

IN1

IN2

IN3

COMP

1.25V

UV/OV

GATE3

PG3

OUT3

IN3 TO OUT3

CONTROL BLOCK

TRACKING

MONITORS

EEPROM/

CONFIGURATION

REGISTERS

GATE4

PG4

OUT4

REF

IN4 TO OUT4

CONTROL BLOCK

IN4

voltages at the sources of the MOSFETs are coꢀpared

to each other to ensure that the voltage differential

between each ꢀonitored supply does not exceed

±ꢁ0ꢀV (typ). Tracking is dynaꢀically adjusted to force

all outputs to track within a ±1±ꢁꢀV window froꢀ a ref-

erence raꢀp; if, for any reason, any supply fails to track

within ±±ꢁ0ꢀV froꢀ the reference raꢀp, the FAULT

output is asserted, the power-up ꢀode is terꢀinated,

and all outputs are powered off. Power-up ꢀode is in

the saꢀe way terꢀinated if the controlled voltages fail

to coꢀplete the raꢀp up within a prograꢀꢀable FAULT

tiꢀeout. The MAX6876 generates all required voltages

(with internal charge puꢀps) and tiꢀing to control up to

four external n-channel MOSFETs for the OUT1–OUT4

supply voltages.

A synchronization feature allows up to 16 voltages to

be tracked siꢀultaneously. In addition, HOLD and

SYNCH coꢀꢀunicate synchronization status between

ꢀaster/slave devices in ꢀultiple MAX6876 applications.

Other features of the MAX6876 include a reset circuit

with an I^±C-prograꢀꢀable tiꢀeout feature. A ꢀanual

reset input (MR) and a ꢀargin disable input (MARGIN)

allow for ꢀore control during the ꢀanufacturing process.

The device also features four power-good outputs (PG_),

an overcurrent output (OC), and a bus-reꢀoval safe

(REM) output. The device has an accurate internal 1.±ꢁV

reference; for greater accuracy, connect an external

+1.±ꢁV reference to REFIN.

14 ______________________________________________________________________________________

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

Table 1. Master/Slave Settings

REGISTER

ADDRESS

EEPROM MEMORY

ADDRESS

BIT RANGE

DESCRIPTION

If “00,” the device configuration is a single device.

If “01,” the device configuration is ꢀultiple devices, slave.

If “10,” the device configuration is ꢀultiple devices, slave.

If “11,” the device configuration is ꢀultiple devices, ꢀaster.

09h

±9h

[7:6]

Modes of Operation

RAMP 1

RAMP 2

RAMP 3

RAMP 4

The MAX6876 provides three different ꢀodes of opera-

tion: tracking, sequencing, and ꢀixed ꢀodes. The

ꢀixed ꢀode is a coꢀbination of both tracking and

sequencing ꢀodes (see the Mixed Mode (Tracking/

Sequencing) section).

OUT1

OUT2

OUT3

OUT4

BIT 0

BIT 4

BIT 0

BIT 4

Tracking

When all selected inputs exceed their selected thresh-

BIT 1

BIT 2

BIT 3

BIT 5

BIT 6

BIT 1

BIT 2

BIT 3

BIT 5

BIT 6

olds, V

> 1.±8ꢁV, and ENABLE is logic high, the

TRKEN

tracking process is initialized. The MAX6876 generates

an internal raꢀp voltage that drives the control loops

for the desired tracked voltage. The tracking functional-

ity is ꢀonitored with a coꢀparator control block (see

the Functional Diagram and Figure ꢁ). The coꢀparators

ꢀonitor and control each output voltage with respect to

the coꢀꢀon tracking raꢀp voltage to stay within a

±1±ꢁꢀV differential window, ꢀonitor each tracked out-

put voltage with respect to its input voltage, and ꢀoni-

tor each output voltage with respect to GND during

power-up/retry cycles. Under norꢀal conditions each

OUT_ voltage will track the raꢀp voltage until the OUT_

voltage approxiꢀates the IN_ voltage (the external

n-channel FET is saturated). The slew rate for the raꢀp

voltage is selected through EEPROM.

BIT 7

(MSB)

BIT 7

(MSB)

R0Bh[7:0]

R0Ch[7:0]

Figure 6. Mapping Tracking and Sequencing Modes

intended to provide only tracking for the four supplies

(only one raꢀp is generated). To control one particular

channel, insert a “1” in any of the four possible posi-

tions (one row for each channel contains 4 bits) and the

circuit will generate the proper signals (see Figure 6).

Master/Slave Operation (Tracking Only)

To support voltage tracking for ꢀore than four supplies,

coꢀbine ꢀultiple MAX6876 devices. Two MAX6876

devices (one ꢀaster/one slave) track up to eight supply

voltages and four MAX6876 devices (one ꢀaster and

three slaves) track up to 16 supply voltages. Each

device ꢀust be prograꢀꢀed to act in ꢀaster or slave

ꢀode (only one ꢀaster is allowed); the default state is

single device (see Table 1). The MAX6876 outputs the

raꢀp control voltage with the SYNCH output when con-

figured as a ꢀaster device. This raꢀp allows ꢀultiple

devices to synchronize with the ꢀaster when slave

SYNCHs are configured as inputs. For proper function-

ality control, connect all ENABLE pins together. In ꢀas-

ter/slave ꢀode, all controlled supplies are tracked

up/down (no ꢀixed sequencing/tracking ꢀodes are

supported). In ꢀaster-slave application, the part is

For ꢀultiple MAX6876 operations, the raꢀp control volt-

age is brought out of the ꢀaster’s SYNCH (prograꢀꢀed

as an output) and into the slave’s SYNCH (prograꢀꢀed

as an input). The highest tracked supply ꢀust be con-

nected to one of the ꢀaster’s IN_ inputs. When all IN_

threshold conditions are ꢀet (on ꢀaster and slaves), the

ꢀaster raꢀp begins rising at the selected raꢀp slew rate.

During norꢀal operation all OUT_ voltages (for ꢀaster

and slave) track the raꢀp voltage. If the slave’s OUT_

voltages do not properly follow the raꢀp voltage (exceed

1±ꢁꢀV differential), the slave device asserts HOLD low.

The ꢀaster recognizes the HOLD and holds the raꢀp

voltage, allowing the slave’s slower OUT_ voltages to

______________________________________________________________________________________ 15

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

catch up. When the slave’s voltages approach the raꢀp

voltage, the slave releases HOLD and the ꢀaster allows

the raꢀp voltage to begin rising again. All tracking ꢀust

be coꢀpleted by the selected tracking fault tiꢀeout peri-

od or the supplies are powered down. The slave HOLD

output is asserted low until the selected tracking IN_ volt-

ages are within their selected thresholds. This ensures

that the ꢀaster does not begin the tracking operation until

the slave’s input voltages (IN_) have properly stabilized.

Configuring Tracking and Sequencing

Modes

To configure tracking and sequencing ꢀodes, insert

“1” and “0” into the 0Bh and 0Ch registers (see Table

±). Figure 6 shows how to ꢀap for tracking and

sequencing ꢀodes. Each OUT_ output can follow one

of the four possible raꢀps in tracking or sequencing

ꢀode (16 bits are available) and one bit set to “1,”

ꢀeans that the channel of the interested row is pow-

ered up/down by the corresponding raꢀp (see Figure

6).

Sequencing

The sequencing operation can be initialized by proper-

ly setting the bit of registers 0Bh and 0Ch. During a

sequencing power-up phase, each OUT_ is indepen-

dently powered on with a controlled slew rate. No ꢀore

than one supply is powered on for each generated

raꢀp. The bits of registers 0Bh and 0Ch establish the

turn-on order. During each phase, the raꢀp is enabled

1) If the depicted table (in Figure 6) is ꢀade by all “1s,”

the part siꢀply generates a single raꢀp (all channels

in tracking ꢀode since the first coluꢀn is full of “1s,”)

and it ignores the reꢀaining values of the other 1± bits.

±) If one row contains ꢀore than one syꢀbol “1,” only

the first encountered (coluꢀns starting with R0Bh

[3:0]) is taken into account and the channel is pow-

ered up/down with the corresponding raꢀp.

to start only after the t

tiꢀeout has been counted.

GATE

The sequencing phase will be considered coꢀplete

when all the channels prograꢀꢀed to power on reach

the independently set PG_ thresholds (see Figure ꢁ).

3) If there is one (or ꢀore) row in which all 4 bits are

set to “0,” it ꢀeans that the device will not control

that particular channel.

Mixed Mode (Tracking/Sequencing)

The MAX6876 is fully prograꢀꢀable to generate up to

four raꢀps during power-up or power-down ꢀodes.

Each OUT_ voltage independently is prograꢀꢀed to

follow any of the control raꢀps generated by the

MAX6876. To do the latter, set the bits on register 0Bh

and 0Ch to “1” for each channel. The following are pro-

graꢀꢀing exaꢀples of different power-up ꢀodes (ꢀ =

sequence, / = track):

4) If there is one (or ꢀore) coluꢀn where all 4 bits are

set to “0,” the device skips that raꢀp and its associ-

ate t

D-GATE.

In ꢀaster-slave applications, the device is intended to

provide only tracking for the four supplies (only one

raꢀp can be generated). To control one particular

channel, only insert a “1” in any of the four possible

positions (one row for each channel contains 4 bits)

and the device generates the proper signals. When

three or less raꢀps are needed, use consecutive

raꢀps starting with raꢀp 1.

0Bh = 0000 1111 0Ch = 0000 0000 tracking ꢀode:

OUT1/OUT±/OUT3/OUT4 on Raꢀp1

0Bh = 1000 0100 0Ch = 0010 0001 sequencing

ꢀode: OUT3 ꢀ OUT4 ꢀ OUT1 ꢀ OUT± on Raꢀp1,

Raꢀp±, Raꢀp3, Raꢀp4

Power-Down and Power-Up

When all the IN_ inputs are within the selected threshold

range and the internal enable is logic high (Figure 7), the

device initiates a power-up phase. During power-up, the

OUT_ outputs are forced by an internal loop that controls

the GATE_ of the external MOSFET to follow the reference

raꢀp voltage. This phase for each individual raꢀp ꢀust

be coꢀpleted within the prograꢀꢀable fault tiꢀeout tiꢀe;

otherwise, the part will force a shutdown on the GATE_.

Once the power-up is coꢀpleted, a power-down phase

can be initiated by forcing the internal enable low. Two

power-down options are available: a fast-shutdown option

where all GATE_ gates are quickly turned off or a reverse-

order option. This reverse-order option allows the OUT_

voltage to be powered down with a controlled slew rate

and in the reverse order they have been powered up (see

Figure ±).

0Bh = 1100 0001 0Ch = 0010 0000 ꢀix ꢀode*: OUT1

ꢀ OUT4/OUT3 ꢀ OUT± on Raꢀp1, Raꢀp±, Raꢀp4

*(Raꢀp3 is not considered because no OUT_ outputs

are selected by bit [0:3] of 0Ch.)

Drive ENABLE or TRKEN low or use a software coꢀ-

ꢀand to initiate a controlled power-down. The MAX6876

powers down the OUT_ voltages in a reverse sequence

froꢀ the one at power-up when this option is selected.

For exaꢀple, with the following power-up sequence:

OUT1 ꢀ OUT4/OUT3 ꢀ OUT±

then the power-down sequence will be:

OUT± ꢀ OUT4/OUT3 ꢀ OUT1

16 ______________________________________________________________________________________

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

Table 2. Configuring Tracking and Sequencing Modes

REGISTER

ADDRESS

EEPROM MEMORY

ADDRESS

BIT RANGE

DESCRIPTION

Bit 7—If 1, OUT4 on raꢀp ±

Bit 6—If 1, OUT3 on raꢀp ±

Bit ꢁ—If 1, OUT± on raꢀp ±

Bit 4—If 1, OUT1 on raꢀp ±

Bit 3—If 1, OUT4 on raꢀp 1

Bit ±—If 1, OUT3 on raꢀp 1

Bit 1—If 1, OUT± on raꢀp 1

Bit 0—If 1, OUT1 on raꢀp 1

Bit 7—If 1, OUT4 on raꢀp 4

Bit 6—If 1, OUT3 on raꢀp 4

Bit ꢁ—If 1, OUT± on raꢀp 4

Bit 4—If 1, OUT1 on raꢀp 4

Bit 3—If 1, OUT4 on raꢀp 3

Bit ±—If 1, OUT3 on raꢀp 3

Bit 1—If 1, OUT± on raꢀp 3

Bit 0—If 1, OUT1 on raꢀp 3

0Bh

±Bh

[7:0]

0Ch

±Ch

[7:0]

To speed up the discharge of the OUT_ voltage, an

optional 100Ω pulldown resistor can be selected (see

Table 3).

ed. Toggle ENABLE, I^±C coꢀꢀand bit, and TRKEN or

cycle device power to clear the latch. Set bit ꢁ of regis-

ter 09h to “1” to prograꢀ the MAX6876 in latch-off

ꢀode, or “0” to prograꢀ for autoretry ꢀode. The

autoretry tiꢀe can be prograꢀꢀed with bits ±, 3, and 4

of register 09h (see Table ꢁ). During autoretry, the gate

drive reꢀains off and FAULT reꢀains asserted. In a

ꢀaster-slave application, FAULT is asserted low until all

the OUT_ outputs of each device are discharged to

GND, and only the ꢀaster counts the autoretry tiꢀe

while HOLD reꢀains low (see Table ꢁ).

Slew-Rate Control

The reference raꢀp voltage slew rate during any con-

trolled power-up/down phase can be prograꢀꢀed in

the 100V/s to 800V/s range. Before any power-up or

retry cycle, the MAX6876 ꢀust first ensure that all

OUT_ voltages are near ground (below the V

TH_PL

power low threshold). An internal prograꢀꢀable track-

ing tiꢀeout period can be selected to signal a fault and

shut down the output voltages if tracking takes too long

(see Table 4).

Stability Comment

No external coꢀpensation is required for tracking or

slew-rate control.

Power-supply tracking operation should be coꢀpleted

within the selected fault tiꢀeout period. For selected

control raꢀps of 100V/s the norꢀal tracking tiꢀe

should be approxiꢀately ꢁ0ꢀs (ꢁV supply, SR =

100V/s). The total tracking tiꢀe is extended when the

MAX6876 ꢀust vary the control slew rate to allow slow

supplies to catch up. If the external FET is too sꢀall

(RDS is too high for the selected load current and IN_

source current), the OUT_ voltage ꢀay never reach the

control raꢀp voltage.

Powering the MAX6876

The MAX6876 derives power froꢀ V

or the voltage-

CC

detector inputs: IN1–IN4 (see the Functional Diagram).

V

(if being used) or one of the IN_ inputs ꢀust be at

CC

least +±.7V to ensure full device operation.

The highest input voltage on IN1–IN4 or V

supplies

CC

power to the device. Internal hysteresis ensures that

the supply input that initially powers the device contin-

ues to power the device when ꢀultiple input voltages

are within ꢁ0ꢀV (typ) of each other.

Autoretry and Latch-Off Functions

The MAX6876 features latch-off or autoretry ꢀode to

power on again after a fault condition has been detect-

______________________________________________________________________________________ 17

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

Table 3. Program Power-Down and Power-Up

REGISTER

ADDRESS

EEPROM MEMORY

ADDRESS

BIT RANGE

DESCRIPTION

Bit 7—If 1, reverse order of track/sequence power-down

If 0, GATE_ fast pulldown

Bit 6—If 1, OUT1 charges with internal pulldown

If 0, no pulldown is allowed

Bit ꢁ—If 1, OUT± charges with internal pulldown

If 0, no pulldown is allowed

13h

33h

[7:3]

Bit 4—If 1, OUT3 charges with internal pulldown

If 0, no pulldown is allowed

Bit 3—If 1, OUT4 charges with internal pulldown

If 0, no pulldown is allowed

“00” fault power-up tiꢀer value = ±ꢁꢀs

“01” fault power-up tiꢀer value = ꢁ0ꢀs

“10” fault power-up tiꢀer value = 100ꢀs

“11” fault power-up tiꢀer value = ±00ꢀs

“00” fault power-down tiꢀer value = ±ꢁꢀs

“01” fault power-down tiꢀer value = ꢁ0ꢀs

“10” fault power-down tiꢀer value = 100ꢀs

“11” fault power-down tiꢀer value = ±00ꢀs

[7:6]

[ꢁ:4]

0Ah

±Ah

Table 4. Setting the Slew Rate

REGISTER

ADDRESS

EEPROM MEMORY

ADDRESS

BIT RANGE

DESCRIPTION

“00” track/sequence slew rate (rise or fall) = 800V/s

“01” track/sequence slew rate (rise or fall) = 400V/s

“10” track/sequence slew rate (rise or fall) = ±00V/s

“11” track/sequence slew rate (rise or fall) = 100V/s

1±h

3±h

Bit [7:6]

Inputs

IN1–IN4

V

- 0.ꢁV

TH

x =

0.01V

for +0.ꢁV to +3.0ꢁV range.

The IN1–IN4 voltage detectors ꢀonitor voltages froꢀ

1V to ꢁ.ꢁV in ±0ꢀV increꢀents, or +0.ꢁV to +3.0ꢁV in

10ꢀV increꢀents. Use the following equations to set

the threshold voltages for IN_:

where V is the desired threshold voltage and x is the

TH

deciꢀal code for the desired threshold (Table 6). For

the +1V to +ꢁ.ꢁV range, x ꢀust equal ±±ꢁ or less; oth-

erwise, the threshold exceeds the ꢀaxiꢀuꢀ operating

voltage of IN1–IN4 (Table 6). An overvoltage or under-

voltage failure on an IN_ input iꢀꢀediately shuts down

all the OUT_ outputs and generates a FAULT in the

ꢀaster/slave condition.

V

-1V

TH

x =

0.0±V

for +1V to +ꢁ.ꢁV range.

18 ______________________________________________________________________________________

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

Table 5. Program Autoretry/Latch off

REGISTER

ADDRESS

EEPROM MEMORY

ADDRESS

BIT RANGE

DESCRIPTION

If 1, latch-on fault

If 0, autoretry

ꢁ

“000” autoretry tiꢀer value = ±ꢁµs

“001” autoretry tiꢀer value = 1±.ꢁꢀs

“010” autoretry tiꢀer value = ±ꢁ.0ꢀs

“011” autoretry tiꢀer value = ꢁ0.0ꢀs

“100” autoretry tiꢀer value = 100.0ꢀs

“101” autoretry tiꢀer value = ±00.0ꢀs

“110” autoretry tiꢀer value = 400.0ꢀs

“111” autoretry tiꢀer value = 1600.0ꢀs

09h

±9h

[4:±]

Table 6. IN1–IN4 Threshold Settings

REGISTER

ADDRESS

EEPROM MEMORY

ADDRESS

BIT

RANGE

DESCRIPTION

IN1 Undervoltage Threshold

V

= 1.0 + n x ±0ꢀV (if R08[7] = 0)

= 0.ꢁ + n x 10ꢀV (if R08[7] = 1)

TH

00h

01h

±0h

±1h

[7:0]

TH

where n is the register content deciꢀal representation. Note that V ranges

TH

ꢀust be 1V to ꢁ.ꢁV and 0.ꢁV to 3.0ꢁV, respectively.

IN± Undervoltage Threshold

V

= 1.0 + n x ±0ꢀV (if R08[6] = 0)

= 0.ꢁ + n x 10ꢀV (if R08[6] = 1)

TH

where n is the register content deciꢀal representation. Note that V ranges

TH

ꢀust be 1V to ꢁ.ꢁV and 0.ꢁV to 3.0ꢁV, respectively.

IN3 Undervoltage Threshold

V

= 1.0 + n x ±0ꢀV (if R08[ꢁ] = 0)

= 0.ꢁ + n x 10ꢀV (if R08[ꢁ] = 1)

TH

0±h

03h

04h

±±h

±3h

±4h

[7:0]

where n is the register content deciꢀal representation. Note that V ranges

TH

ꢀust be 1V to ꢁ.ꢁV and 0.ꢁV to 3.0ꢁV, respectively.

IN4 Undervoltage Threshold

V

where n is the register content deciꢀal representation. Note that V ranges

TH

ꢀust be 1V to ꢁ.ꢁV and 0.ꢁV to 3.0ꢁV, respectively.

= 1.0 + n x ±0ꢀV (if R08[4] = 0)

= 0.ꢁ + n x 10ꢀV (if R08[4] = 1)

TH

IN1 Overvoltage Threshold

V

= 1.0 + n x ±0ꢀV (if R08[7] = 0)

= 0.ꢁ + n x 10ꢀV (if R08[7] = 1)

TH

where n is the register content deciꢀal representation. Note that V ranges

TH

ꢀust be 1V to ꢁ.ꢁV and 0.ꢁV to 3.0ꢁV, respectively.

______________________________________________________________________________________ 19

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

Table 6. IN1–IN4 Threshold Settings (continued)

REGISTER

ADDRESS

EEPROM MEMORY

ADDRESS

BIT

RANGE

DESCRIPTION

IN± Overvoltage Threshold

V

= 1.0 + n x ±0ꢀV (if R08[6] = 0)

= 0.ꢁ + n x 10ꢀV (if R08[6] = 1)

TH

0ꢁh

06h

±ꢁh

±6h

[7:0]

where n is the register content deciꢀal representation. Note that V ranges

TH

ꢀust be 1V to ꢁ.ꢁV and 0.ꢁV to 3.0ꢁV, respectively.

IN3 Overvoltage Threshold

V

= 1.0 + n x ±0ꢀV (if R08[ꢁ] = 0)

= 0.ꢁ + n x 10ꢀV (if R08[ꢁ] = 1)

TH

where n is the register content deciꢀal representation. Note that V ranges

TH

ꢀust be 1V to ꢁ.ꢁV and 0.ꢁV to 3.0ꢁV, respectively.

IN4 Overvoltage Threshold

V

= 1.0 + n x ±0ꢀV (if R08[4] = 0)

= 0.ꢁ + n x 10ꢀV (if R08[4] = 1)

TH

07h

08h

±7h

±8h

[7:0]

[7:4]

where n is the register content deciꢀal representation. Note that V ranges

TH

ꢀust be 1V to ꢁ.ꢁV and 0.ꢁV to 3.0ꢁV, respectively.

Bit 7—If 0, ±0ꢀV steps in V setting for IN1

If 1, 10ꢀV steps in V setting for IN1

TH

Bit 6—If 0, ±0ꢀV steps in V setting for IN±

If 1, 10ꢀV steps in V setting for IN±

TH

Bit ꢁ—If 0, ±0ꢀV steps in V setting for IN3

TH

If 1, 10ꢀV steps in V setting for IN3

TH

Bit 4—If 0, ±0ꢀV steps in V setting for IN4

TH

If 1, 10ꢀV steps in V setting for IN4

TH

ENABLE low to initiate tracking/sequencing power-down

operation. When ENABLE is not used, connect to ABP.

Manual Reset Input (MR)

The ꢀanual reset (MR) input initiates a reset condition.

MR is internally pulled up to ABP through a 100kΩ

resistor. When MR is low, RESET reꢀains low for the

selected reset tiꢀeout period after MR transitions froꢀ

low to high (see the Reset Output (RESET) section).

When the MAX6876 is configured to use the I^±C on/off

coꢀꢀand, a valid I^±C signal ꢀust be received before

the device begins the power-up tracking/sequencing

routine. The internal enable logic is an AND function of

the ENABLE logic, the TRKEN logic, and the I^±C con-

trol/coꢀꢀand logic (Figure 7). When all three AND gate

input variables are true (and the ꢀonitored IN/OUT volt-

ages ꢀeet their required thresholds), turn-on is allowed.

When any AND input variable becoꢀes false, the turn-

off cycle (track/sequence down) begins iꢀꢀediately.

Drive ENABLE and TRKEN high if only the I^±C coꢀ-

ꢀand is to be used to turn on/off the device. The detec-

tors ꢀonitoring IN_ and OUT_ voltages, and

overcurrent conditions have a higher priority after a

power-on routine has been initiated by the internal

enable logic. If a fault occurs during the power-up

cycle, the device is powered down iꢀꢀediately, inde-

pendent of ENABLE, TRKEN, and the I^±C shutdown

Margin Input (MARGIN)

MARGIN allows systeꢀ-level testing while power sup-

plies exceed the norꢀal ranges. Drive MARGIN low

before varying systeꢀ voltages below/above the select-

ed threshold without signaling an error. MARGIN ꢀakes

it possible to vary the supplies without a need to repro-

graꢀ the IN_ or PG_ thresholds and prevents

tracker/sequencer alerts or faults. Drive MARGIN high

or leave it floating for norꢀal operating ꢀode.

ENABLE

Drive logic ENABLE input high to initiate voltage track-

ing/sequencing during power-up operation. Drive logic

20 ______________________________________________________________________________________

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

Table 7. Program ENABLE

REGISTER

ADDRESS

EEPROM MEMORY

ADDRESS

BIT RANGE

DESCRIPTION

±

Bit 1—If 1, check ENABLE with I C enable control bit

±

If 0, ignore ENABLE with I C

09h

±9h

[1:0]

±

Bit 0—If 0, enable with I C = 0, I C enable coꢀꢀand bit

±

If 1, enable with I C = 1

Table 8. Select External Reference

REGISTER

ADDRESS

EEPROM MEMORY

ADDRESS

BIT RANGE

DESCRIPTION

11h

31h

0

Bit 0—If 1, selects external reference; 0 selects internal reference

coꢀꢀand (Table 7). If a latch-on fault ꢀode is chosen,

a toggle on the internal enable clears the latch condi-

tion and restarts the device after a fault condition

(Figure 7).

ENABLE

TRKEN

INTERNAL

ENABLE

Reference Voltage Input (REFIN)

The MAX6876 features an internal +1.±ꢁV voltage refer-

ence. The voltage reference sets the threshold of the

voltage detectors. Leave REFIN unconnected when

using the internal reference. REFIN accepts an external

reference in the +1.±±ꢁV to +1.±7ꢁV range. Use Table

8 coꢀꢀands to select the external reference.

V

TRKEN

I²C ENABLE CONTROL BIT

(RAM REGISTER)

1 = YES

I²C ENABLE COMMAND BIT

(RAM REGISTER)

0 = OFF

09h[1]

0 = NO

09h[0]

1 = ON

Track Enable Input (TRKEN)

The track enable (TRKEN) ꢀonitor input is another fea-

ture of the MAX6876. To enable voltage-tracking

power-up operation, drive TRKEN higher than 1.±8ꢁV.

When TRKEN goes below 1.±ꢁV, OUT_ outputs start

tracking down. Connect TRKEN to an external resistor-

divider network to set the desired ꢀonitor threshold.

Connect TRKEN to ABP if not used.

Figure 7. Logic ENABLE

Monitored Outputs

OUT1–OUT4

The MAX6876 ꢀonitors four OUT_ outputs to control

the tracking/sequencing perforꢀance. After the internal

supply (ABP) exceeds the ꢀiniꢀuꢀ voltage (±.7V)

requireꢀents, TRKEN > 1.±ꢁV, the internal ENABLE

input is logic high, and IN1–IN4 are all within their

selected thresholds, OUT1–OUT4 will begin to track or

sequence.

SYNCH

The MAX6876 provides selectable tracking synchro-

nization output or input (SYNCH). SYNCH allows track-

ing of up to 16 power supplies on the saꢀe I^±C bus.

One device is prograꢀꢀed as the SYNCH ꢀaster and

the other devices are prograꢀꢀed as slaves. SYNCH

of the ꢀaster device outputs the coꢀꢀon raꢀp voltage

to which all OUT_ voltages are tracked. The SYNCH

pins of the slave devices are inputs for the raꢀp control

voltage (no internal raꢀp is generated in the slave

devices) (see Table 1).

During power-up ꢀode, the MAX6876 drives the gates

of the external n-channel FETs to force the OUT_ volt-

ages to track the internally set raꢀp voltage. If OUT_

voltages vary froꢀ the raꢀp voltage by ꢀore than

±1±ꢁꢀV, an internal coꢀparator signals an alert that

dynaꢀically adjusts the raꢀp voltage (stops the raꢀp

until the slow OUT_ catches up). During power-down

ꢀode, an internal pulldown resistor (100Ω) on OUT_

can be enabled to help discharge load capacitance.

______________________________________________________________________________________ 21

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

Table 9. GATE-Delay Time Settings

REGISTER

ADDRESS

EEPROM MEMORY

ADDRESS

BIT RANGE

DESCRIPTION

“000” gate-delay tiꢀer value = ±ꢁµs

“001” gate-delay tiꢀer value = 1±.ꢁꢀs

“010” gate-delay tiꢀer value = ±ꢁ.0ꢀs

“011” gate-delay tiꢀer value = ꢁ0.0ꢀs

“100” gate-delay tiꢀer value = 100.0ꢀs

“101” gate-delay tiꢀer value = ±00.0ꢀs

“110” gate-delay tiꢀer value = 400.0ꢀs

“111” gate-delay tiꢀer value = 1600.0ꢀs

0Fh

±Fh

[7:ꢁ]

Table 10. FAULT Power-Up and Power-Down Time Settings

REGISTER

ADDRESS

EEPROM MEMORY

ADDRESS

BIT RANGE

DESCRIPTION

Bit [7:6] “00” fault power-up tiꢀer value = ±ꢁꢀs

“01” fault power-up tiꢀer value = ꢁ0ꢀs

“10” fault power-up tiꢀer value = 100ꢀs

“11” fault power-up tiꢀer value = ±00ꢀs

[7:6]

0Ah

±Ah

Bit [ꢁ:4] “00” fault power-down tiꢀer value = ±ꢁꢀs

“01” fault power-down tiꢀer value = ꢁ0ꢀs

“10” fault power-down tiꢀer value = 100ꢀs

“11” fault power-down tiꢀer value = ±00ꢀs

[ꢁ:4]

FAULT

Outputs

The MAX6876 offers an open-drain, active-low tracking

fault alarꢀ (FAULT). FAULT asserts low when a power-

up phase is not coꢀpleted within the specified fault

period or if tracking voltages fail by ꢀore than ±±ꢁ0ꢀV.

For ꢀultiple MAX6876 applications, FAULT is an

input/output pin and coꢀꢀunicates fault inforꢀation

between ꢀaster/slave devices. Connect all FAULT pins

in an ORed configuration to force siꢀultaneous shut-

down on all MAX6876s (Table 10.) See the Typical

Application Circuit.

GATE_

The MAX6876 features four GATE_ outputs to drive four

external n-channel FET gates. The following conditions

ꢀust be ꢀet before GATE_ begins enhancing the

external n-channel FET_:

1) All ꢀonitored inputs (IN1–IN4) are above their

selected thresholds (0.ꢁV to ꢁ.ꢁV)

±) At least one IN_ input or V

3) Drive ENABLE high

4) TRKEN > 1.±ꢁV

is above ±.7V

CC

Power-Good Outputs (PG_)

The MAX6876 features four power-good (PG_) outputs.

PG_ outputs are open-drain and require external

pullups.

At power-up ꢀode, GATE_ voltages are enhanced con-

trol loops so all OUT_ voltages track together at a user-

selected slew rate. Each GATE_ is internally pulled up

to ꢁV above its relative IN_ voltage to fully enhance the

external n-channel FET when power-up is coꢀplete. In

sequencing/tracking ꢀode, a gate delay tiꢀeout is

internally counted prior to the start of each control raꢀp

(see Figures 1 and ± and Table 9).

When the OUT_ output is within the selected percent-

age of the IN_ voltage range (V

), the correspond-

TH_PG

ing PG_ output goes high iꢀpedance. PG_ stays low

until the OUT_ voltage exceeds the prograꢀꢀable

V

threshold for ꢀore than t

(Table 11).

POK

TH_PG

22 ______________________________________________________________________________________

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

Table 11. PG Threshold Settings

REGISTER

ADDRESS

EEPROM MEMORY

ADDRESS

BIT RANGE

DESCRIPTION

“00” IN4 to OUT4 power-good threshold = 9ꢁ%

“01” IN4 to OUT4 power-good threshold = 9±.ꢁ%

“10” IN4 to OUT4 power-good threshold = 90%

“11” IN4 to OUT4 power-good threshold = 87.ꢁ%

“00” IN3 to OUT3 power-good threshold = 9ꢁ%

"01" IN3 to OUT3 power-good threshold = 9±.ꢁ%

“10” IN3 to OUT3 power-good threshold = 90%

“11” IN3 to OUT3 power-good threshold = 87.ꢁ%

“00” IN± to OUT± power-good threshold = 9ꢁ%

“01” IN± to OUT± power-good threshold = 9±.ꢁ%

“10” IN± to OUT± power-good threshold = 90%

“11” IN± to OUT± power-good threshold = 87.ꢁ%

“00” IN1 to OUT1 power-good threshold = 9ꢁ%

“01” IN1 to OUT1 power-good threshold = 9±.ꢁ%

“10” IN1 to OUT1 power-good threshold = 90%

“11” IN1 to OUT1 power-good threshold = 87.ꢁ%

[7:6]

10h

30h

[ꢁ:0]

Bus Removal Output (REM)

Reset Output (RESET)

The reset output, RESET, is an open-drain output that

ꢀonitors the selected OUT_ voltages. The selected

OUT_ voltages ꢀust exceed their selected PG_ thresh-

The MAX6876 features an open-drain bus reꢀoval

(REM) output. REM signals when it is safe to reꢀove

the card after a controlled track/sequence power-down

operation. To initiate a power-down, drive ENABLE low

or send an I^±C power-down coꢀꢀand. REM ꢀonitors

OUT_ and when any of the OUT_ voltages are above

olds for the selected reset tiꢀeout period (t ) before

RP

RESET is deasserted. A ꢀanual reset input (MR) can

assert RESET. RESET reꢀains low while MR is low.

RESET reꢀains low for the selected reset tiꢀeout peri-

the V

threshold, REM stays low. When all OUT_

TH_PL

outputs are below V

, REM goes high iꢀpedance.

od (t ) after MR transitions froꢀ low to high (Table 13).

TH_PL

RP

Connect REM to an external pullup resistor/LED chain

to visually signal when it is safe to reꢀove a powered

board froꢀ the bus.

Synchronization Hold Output (HOLD)

The MAX6876 features an open-drain, active-low syn-

chronization alert output/input. HOLD coꢀꢀunicates

synchronization status between ꢀaster/slave devices in

ꢀultiple MAX6876 applications. When a slave device

detects a tracking probleꢀ with respect to the ꢀaster

SYNCH signal, the slave asserts HOLD low. When

tracking is back under control, the slave’s HOLD is

deasserted and goes high again. The HOLD output

reꢀains asserted while selected tracking IN_ inputs are

below their selected thresholds (the slave device can

delay a tracking start until its inputs are at their required

stable voltage levels) or held low by the ꢀaster when it

is counting the autoretry tiꢀe after a detected fault con-

dition. Connect HOLD pins only to other MAX6876

HOLD pins.

In tracking ꢀode when REM is used in ꢀaster/slave

operations, connect all REM pins together. The coꢀ-

ꢀon REM connection reꢀains low if any OUT_ supply

is above the V

threshold.

TH_PL

Overcurrent Output (OC)

The open-drain, active-low OC output asserts low if an

overcurrent condition is detected in any selected channel

for longer than t . Overcurrent conditions are deter-

OC

ꢀined as a differential voltage between IN_ and OUT_.

OC ꢀonitoring begins only after supply tracking or

sequencing has been coꢀpleted and is disabled during

power-down operation (Table 1±).

______________________________________________________________________________________ 23

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

Table 12. OC Threshold Settings

REGISTER

ADDRESS

EEPROM MEMORY

ADDRESS

BIT RANGE

DESCRIPTION

Bit [7:6] “00” IN4 to OUT4 overcurrent threshold = 97.ꢁ%

“01” IN4 to OUT4 overcurrent threshold = 9ꢁ%

“10” IN4 to OUT4 overcurrent threshold = 9±.ꢁ%

“11” IN4 to OUT4 overcurrent threshold = 90%

[7:6]

Bit [ꢁ:4] “00” IN3 to OUT3 overcurrent threshold = 97.ꢁ%

“01” IN3 to OUT3 overcurrent threshold = 9ꢁ%

“10” IN3 to OUT3 overcurrent threshold = 9±.ꢁ%

“11” IN3 to OUT3 overcurrent threshold = 90%

0Dh

±Dh

Bit [3:±] “00” IN± to OUT± overcurrent threshold = 97.ꢁ%

“01” IN± to OUT± overcurrent threshold = 9ꢁ%

“10” IN± to OUT± overcurrent threshold = 9±.ꢁ%

“11” IN± to OUT± overcurrent threshold = 90%

[ꢁ:0]

Bit [1:0] “00” IN1 to OUT1 overcurrent threshold = 97.ꢁ%

“01” IN1 to OUT1 overcurrent threshold = 9ꢁ%

“10” IN1 to OUT1 overcurrent threshold = 9±.ꢁ%

“11” IN1 to OUT1 overcurrent threshold = 90%

Bit [7:6] “00” overcurrent tiꢀer value = 1±.ꢁꢀs

“01” overcurrent tiꢀer value = ꢁ0ꢀs

“10” overcurrent tiꢀer value = 100ꢀs

“11” overcurrent tiꢀer value = ±00ꢀs

Bit ꢁ—If 1, overcurrent ꢀonitoring on OUT1 is enabled

If 0, no overcurrent ꢀonitoring on OUT1

0Eh

±Eh

[7:1]

Bit 4—If 1, overcurrent ꢀonitoring on OUT± is enabled

If 0, no overcurrent ꢀonitoring on channel 1

Bit 3—If 1, overcurrent ꢀonitoring on OUT3 is enabled

If 0, no overcurrent ꢀonitoring on OUT3

Bit ±—If 1, overcurrent ꢀonitoring on OUT4 is enabled

If 0, no overcurrent ꢀonitoring on OUT4

ABP

to ensure the device is configured properly. After coꢀ-

pleting the setup procedure, use the read word proto-

col to read back the data froꢀ the configuration

registers. Lastly, use the write word protocol to write

this data to the EEPROM registers. After coꢀpleting the

EEPROM register configuration, apply full power to the

systeꢀ to begin norꢀal operation. The nonvolatile

EEPROM stores the latest configuration upon reꢀoval

of power (Table 14).

ABP powers the analog circuitry. Bypass ABP to GND

with a 1µF ceraꢀic capacitor installed as close to the

device as possible. Do not use ABP to provide power

to external circuitry.

Configuring the MAX6876

The MAX6876 factory-default configuration sets all reg-

isters to 00h. This device requires configuration before

full power is applied to the systeꢀ. To configure the

MAX6876, first apply an input voltage greater than ±.7V

Software Reboot

A coꢀꢀand code of C4h initiates a software reboot. A

software reboot allows the user to restore the EEPROM

configuration to the volatile registers without cycling the

power supplies.

to one of IN1–IN4 or V

(see the Powering the

CC

MAX6876 section). Next, transꢀit data with the serial

interface. Use the block write protocol to quickly config-

ure the device. Write to the configuration registers first,

24 ______________________________________________________________________________________

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

Table 13. Program RESET

REGISTER

ADDRESS

EEPROM MEMORY

ADDRESS

BIT RANGE

DESCRIPTION

Bit 7—If 1, OUT1 also controls RESET

If 0, OUT1 does not control RESET

Bit 6—If 1, OUT± also controls RESET

If 0, OUT± does not control RESET

Bit ꢁ—If 1, OUT3 also controls RESET

If 0, OUT3 does not control RESET

Bit 4—If 1, OUT4 also controls RESET

If 0, OUT4 does not control RESET

11h

31h

[7:1]

Bit [3:1] “000” reset tiꢀer value = ±ꢁµs

“001” reset tiꢀer value = 1±.ꢁꢀs

“010” reset tiꢀer value = ±ꢁ.0ꢀs

“011” reset tiꢀer value = ꢁ0.0ꢀs

“100” reset tiꢀer value = 100.0ꢀs

“101” reset tiꢀer value = ±00.0ꢀs

“110” reset tiꢀer value = 400.0ꢀs

“111” reset tiꢀer value = 1600.0ꢀs

SMBus/I²C-Compatible Serial Interface

The MAX6876 features an I^±C/SMBus-coꢀpatible ±-

wire serial interface consisting of a serial data line

(SDA) and a serial clock line (SCL). SDA and SCL facili-

tate bidirectional coꢀꢀunication between the

MAX6876 and the ꢀaster device at clock rates up to

400kHz. Figure 10 shows the ±-wire interface tiꢀing

diagraꢀ. The MAX6876 is transꢀit/receive slave-only,

relying upon a ꢀaster device to generate a clock sig-

nal. The ꢀaster device (typically a ꢀicrocontroller) initi-

ates a data transfer on the bus and generates SCL to

perꢀit that transfer.

Bit Transfer

Each clock pulse transfers one data bit. The data on

SDA ꢀust reꢀain stable while SCL is high (Figure 11);

otherwise, the MAX6876 registers a START or STOP

condition (Figure 1±) froꢀ the ꢀaster. SDA and SCL

idle high when the bus is not busy.

Start and Stop Conditions

Both SCL and SDA idle high when the bus is not busy.

A ꢀaster device signals the beginning of a transꢀis-

sion with a START (S) condition (Figure 8) by transition-

ing SDA froꢀ high to low while SCL is high. The ꢀaster

device issues a STOP (P) condition (Figure 8) by transi-

tioning SDA froꢀ low to high while SCL is high. A STOP

condition frees the bus for another transꢀission. The

bus reꢀains active if a REPEATED START condition is

generated, such as in the block read protocol (see

Figure 11).

A ꢀaster device coꢀꢀunicates to the MAX6876 by

transꢀitting the proper address followed by coꢀꢀand

and/or data words. Each transꢀit sequence is fraꢀed

by a START (S) or REPEATED START (SR) condition

and a STOP (P) condition. Each word transꢀitted over

the bus is 8 bits long and is always followed by an

acknowledge pulse.

Early STOP Conditions

The MAX6876 recognizes a STOP condition at any point

during transꢀission except if a STOP condition occurs in

the saꢀe high pulse as a START condition. This condi-

tion is not a legal I^±C forꢀat; at least one clock pulse

ꢀust separate any START and STOP condition.

SCL is a logic input, while SDA is an open-drain

input/output. SCL and SDA both require external pullup

resistors to generate the logic-high voltage. Use 4.7kΩ

for ꢀost applications.

______________________________________________________________________________________ 25

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

Table 14. Registers Summary

REGISTERS

DESCRIPTIONS

Input Undervoltage Thresholds

(Registers 00h to 03h)

Input undervoltage thresholds (0.ꢁV to 3.04V in 10ꢀV increꢀents or 1.0V to ꢁ.ꢁV in ±0ꢀV

increꢀents). Each channel’s range is selected with register 08h.

Input Overvoltage Thresholds

(Registers 04h to 07h)

Input overvoltage thresholds (0.ꢁV to 3.04V in 10ꢀV increꢀents or 1.0V to ꢁ.ꢁV in ±0ꢀV

increꢀents). Each channel’s range is selected with register 08h.

Selects if outputs are to be sequenced or tracked. Sequencing/tracking ꢀodes are defined

by 4 bits for each OUT voltage of register 0Bh and 0Ch (see the Track/Sequence section).

Tracking/Sequencing Modes

Tracking/Sequencing

Power-Up/Down Slew Rate

Selectable output slew rate for power-up/down ꢀode. Selected slew is overwritten during

tracking faults. Power-up/down slew rate is selected by bit [6:7] of register 1±h.

Power-up sequencing delay. Selects delay tiꢀe for sequencing each supply.

Prograꢀꢀable delays are selected with bit [ꢁ:7] of register 0Fh.

Power-Up Delay Period

Selectable power-down operation. Chooses if output voltages should be brought down in

the reverse sequence froꢀ power-up ꢀode selections or if power supplies should be

siꢀultaneously fast powered down (selected with bit 7 register 13h).

Power-Down Sequence/Track

Behavior

Selects if OUT_ should be internally pulled to GND when in fast shutdown or tracking fault

ꢀode (selected with bit [6:3] register 13h).

OUT Pulldown Enable

Selects if the device will be used alone or in a ꢀaster/slave application. If a single

application, the device can be operated in ꢀixed sequencing/tracking ꢀodes. If ꢀulti-

device application, the device can be operated in tracking ꢀode only (selected with bit

[7:6] register 09h).

Single/Multiple Device Application

00: single device 11: ꢀaster device 01 or 10: slave device

Overcurrent Threshold

Selects IN_-to-OUT_ threshold voltage for overcurrent ꢀonitoring for each channel (register 0Dh).

Selects IN_-to-OUT_ threshold voltage for power-good ꢀonitoring for each channel

(register 10h).

Power-Good Threshold

Overcurrent Assert Select

Overcurrent Filter Period

Selects which overcurrent ꢀonitors will assert the OC output (selected by bit [ꢁ:±] of reg. 0Eh).

Selects the filter tiꢀe for the overcurrent ꢀonitors. OC will not assert until the overcurrent

condition has existed longer than the selected filter period (selected by bit [7:6] of reg. 0Eh).

Selects the tiꢀeout period for sequencing/tracking coꢀpletion. If sequencing/tracking

operation is not coꢀplete before the fault tiꢀeout period, a FAULT alert will be signaled

and all supplies will be powered down (selected by bit [7:4] of reg. 0Ah).

Fault Tiꢀeout Period

Fault Behavior

Selects how the device should operate during faults. Options include latch-off after fault or

autoretry after fault. Autoretry delay is selectable (selected by bit ꢁ of reg. 09h).

Reset Assert Select

Selects which OUT detectors will assert the RES E T output (selected by bit [7:4] of reg. 11h).

Reset Tiꢀeout Period Select

Selects the reset tiꢀeout period (selected by bit [3:1] of reg. 11h).

Bit 0 and bit 1 of register 09h allows a ꢀicro to turn the MAX6876 on/off with the I^±C

interface. While 09h[1] is 0, the part will ignore any enable coꢀꢀand froꢀ I^±C. If 09h[1] is

set to 1, then 09h[0] has to be 1 to enable the part to power on.

Enable the Part with I^±C Interface

26 ______________________________________________________________________________________

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

SDA

t

BUF

t

SU:DAT

t

SU:STA

t

SU:STO

HD:DAT

t

LOW

HD:STA

SCL

t

HIGH

t

HD:STA

t

F

R

START

CONDITION

STOP

CONDITION

START

CONDITION

REPEATED START

CONDITION

Figure 10. Serial-Interface Timing Details

SDA

SCL

S

P

START

CONDITION

STOP

CONDITION

CHANGE OF

DATA ALLOWED

DATA LINE STABLE,

DATA VALID

Figure 12. Start and Stop Conditions

Figure 11. Bit Transfer

Repeated START Conditions

erates an ACK. The MAX6876 generates an ACK when

receiving an address or data by pulling SDA low during

the 9th clock period (Figure 13). When transꢀitting

data, such as when the ꢀaster device reads data back

froꢀ the MAX6876, the device waits for the ꢀaster

device to generate an ACK. Monitoring ACK allows for

detection of unsuccessful data transfers. An unsuc-

cessful data transfer occurs if the receiving device is

busy or if a systeꢀ fault has occurred. In the event of

an unsuccessful data transfer, the bus ꢀaster should

reatteꢀpt coꢀꢀunication at a later tiꢀe. The MAX6876

generates a NACK after the slave address during a

software reboot, while writing to the EEPROM, or when

receiving an illegal ꢀeꢀory address.

A REPEATED START (SR) condition ꢀay indicate a

change of data direction on the bus. Such a change

occurs when a coꢀꢀand word is required to initiate a

read operation (see Figure 1±). SR ꢀay also be used

when the bus ꢀaster is writing to several I^±C devices

and does not want to relinquish control of the bus. The

MAX6876 serial interface supports continuous write

operations with or without an SR condition separating

theꢀ. Continuous read operations require SR condi-

tions because of the change in direction of data flow.

Acknowledge

The acknowledge bit (ACK) is the 9th bit attached to

any 8-bit data word. The receiving device always gen-

______________________________________________________________________________________ 27

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

START

CLOCK PULSE FOR ACKNOWLEDGE

CONDITION

2

1

8

9

SCL

SDA BY

TRANSMITTER

S

SDA BY

RECEIVER

Figure 13. Acknowledge

Slave Address

The MAX6876 slave address conforꢀs to the following

table:

sends C4h, this signifies a software reboot. The send

byte procedure follows:

1) The ꢀaster sends a start condition.

SA7

(MSB)

SA0

(LSB)

±) The ꢀaster sends the 7-bit slave address and a

write bit (low).

SA6 SAꢁ SA4 SA3 SA± SA1

A1 A0

1

0

1

0

X

R/W

3) The addressed slave asserts an ACK on SDA.

4) The ꢀaster sends an 8-bit data byte.

X = Don’t care.

ꢁ) The addressed slave asserts an ACK on SDA.

6) The ꢀaster sends a stop condition.

SA7–SA4 represent the standard ±-wire interface

address (1010) for devices with EEPROM. SA3 and

SA± correspond to the A1 and A0 address inputs of the

MAX6876 (hardwired as logic low or logic high). SA0 is

a read/write flag bit (0 = write, 1 = read).

Write Byte/Word

The write byte/word protocol allows the ꢀaster device

to write a single byte in the register bank, preset an

EEPROM (configuration or user) address for a subse-

quent read, or to write a single byte to the configuration

EEPROM (see Figure 1ꢁ). The write byte/word proce-

dure follows:

The A0 and A1 address inputs allow up to four

MAX6876s to connect to one bus. Connect A0 and A1

to GND or to HBP (see Figure 14).

Send Byte

The send byte protocol allows the ꢀaster device to send

one byte of data to the slave device (see Figure 1ꢁ). The

send byte presets a register pointer address for a sub-

sequent read or write. The slave sends a NACK instead

of an ACK if the ꢀaster tries to send an address that is

not allowed. If the ꢀaster sends C0h or C1h, the data is

ACK, because this could be the start of the write block

or read block. If the ꢀaster sends a stop condition, the

internal address pointer does not change. If the ꢀaster

1) The ꢀaster sends a start condition.

±) The ꢀaster sends the 7-bit slave address and a

write bit (low).

3) The addressed slave asserts an ACK on SDA.

4) The ꢀaster sends an 8-bit coꢀꢀand code.

ꢁ) The addressed slave asserts an ACK on SDA.

6) The ꢀaster sends an 8-bit data byte.

7) The addressed slave asserts an ACK on SDA.

28 ______________________________________________________________________________________

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

SDA

1

0

A1

A0

X

R/W

ACK

0

1

START

MSB

LSB

SCL

Figure 14. Slave Address

8) The ꢀaster sends a stop condition or sends another

8-bit data byte.

4) The ꢀaster sends the 8-bit coꢀꢀand code for

block write (83h).

9) The addressed slave asserts an ACK on SDA.

10) The ꢀaster sends a stop condition.

ꢁ) The addressed slave asserts an ACK on SDA.

6) The ꢀaster sends the 8-bit byte count (1 to 16

bytes), N.

To write a single byte to the register bank, only the 8-bit

coꢀꢀand code and a single 8-bit data byte are sent.

The coꢀꢀand code ꢀust be in the range of 00h to 13h

to write on RAM or ±0h to 33h to write on EEPROM. The

data byte is written to the register bank if the coꢀꢀand

code is valid. The slave generates a NACK at step ꢁ if

the coꢀꢀand code is invalid.

7) The addressed slave asserts an ACK on SDA.

8) The ꢀaster sends 8 bits of data.

9) The addressed slave asserts an ACK on SDA.

10) Repeat steps 8 and 9 N - 1 tiꢀes.

11) The ꢀaster generates a stop condition.

Block Write

The block write protocol allows the ꢀaster device to

write a block of data (1 to 16 bytes) to the EEPROM or

to the register bank (see Figure 1ꢁ). The destination

address ꢀust already be set by the send byte or write

byte protocol. If the nuꢀber of bytes to be written caus-

es the address pointer to exceed 13h for the configura-

tion register (or 33h for the configuration EEPROM), the

address pointer stays at 13h (or 33h), overwriting this

ꢀeꢀory address with the reꢀaining bytes of data. The

last data byte sent is stored at register address 13h (or

33h). The block write procedure follows:

Block Read

The block read protocol allows the ꢀaster device to

read a block of 16 bytes froꢀ the EEPROM or register

bank (see Figure 1ꢁ). Read fewer than 16 bytes of data

by issuing an early STOP condition froꢀ the ꢀaster, or

by generating a NACK with the ꢀaster. The send byte

or write byte protocol predeterꢀines the destination

address with a coꢀꢀand code of C1h. The block read

procedure follows:

1) The ꢀaster sends a start condition.

±) The ꢀaster sends the 7-bit slave address and a

write bit (low).

1) The ꢀaster sends a start condition.

3) The addressed slave asserts an ACK on SDA.

±) The ꢀaster sends the 7-bit slave address and a

write bit (low).

4) The ꢀaster sends 8 bits of the block read coꢀ-

ꢀand (C1h).

3) The addressed slave asserts an ACK on SDA.

ꢁ) The slave asserts an ACK on SDA, unless busy.

______________________________________________________________________________________ 29

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

SEND BYTE FORMAT

WRITE WORD FORMAT

ADDRESS WR

S

ADDRESS

WR

0

ACK

DATA

8 bits

ACK

P

S

ACK COMMAND ACK

DATA ACK

8 bits

DATA ACK

8 bits

P

7 bits

0

8 bits

Data Byte–

Slave Address–

Data Byte–presets the

internal address pointer.

Slave Address–

Write Address of

Data Byte–

Data goes into

the register you are Data goes into

equivalent to chip-

select line of a 3-

wire interface.

equivalent to chip-

select line of a 3-

wire interface.

the next register set by

the command.

writing to.

the register set by

the command.

WRITE BYTE FORMAT

S

ADDRESS

WR

0

ACK

COMMAND

8 bits

ACK

DATA

8 bits

ACK

P

7 bits

Slave Address–

Command Byte–

selects register

you are writing to.

Data Byte–data goes into the

register set by the command.

equivalent to chip-

select line of a 3-

wire interface.

BLOCK WRITE FORMAT

BYTE

DATA BYTE

1

DATA BYTE

...

DATA BYTE

N

S

ADDRESS

7 bits

WR

0

ACK COMMAND ACK

8 bits

ACK

P

COUNT= N

8 bits

Slave Address–

equivalent to chip-

select line of a 3-

wire interface.

Command Byte–

prepares device

for block

Data Byte–data goes into the register set by the

command byte.

operation.

BLOCK READ FORMAT

ADDRESS WR ACK COMMAND ACK SR ADDRESS WR

BYTE

COUNT= 16

DATA BYTE

1

DATA BYTE

...

DATA BYTE

N

S

ACK

P

7 bits

0

8 bits

7 bits

0

10h

8 bits

Slave Address–

equivalent to chip-

select line of a 3-

wire interface.

Command Byte–

prepares device

for block

Slave Address–

Data Byte–data goes into the register set by the

command byte.

equivalent to chip-

select line of a 3-

wire interface.

operation.

S = Start condition.

P = Stop condition.

Shaded = Slave transmission.

SR = Repeated start condition.

Figure 15. SMBus/I²C Protocols

30 ______________________________________________________________________________________

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

Table 15. Configuration of Lock Bit

REGISTER

ADDRESS

EEPROM MEMORY

ADDRESS

BIT RANGE

DESCRIPTION

If 1, configuration registers are locked

If 0, configuration registers unlocked

13h

33h

±

6) The ꢀaster generates a repeated start condition.

Configuration EEPROM

The configuration EEPROM addresses range froꢀ ±0h

to 33h. Write data to the configuration EEPROM to auto-

ꢀatically set up the MAX6876 upon power-up. Data

transfers froꢀ the configuration EEPROM to the config-

uration registers when ABP exceeds UVLO during

power-up. After ABP exceeds UVLO, an internal 1MHz

clock starts after a ꢁµs delay, and data transfer begins.

Data transfer disables access to the configuration reg-

isters and EEPROM. The data transfer froꢀ EEPROM to

the configuration registers takes ±ꢀs (ꢀax). Read con-

figuration EEPROM data at any tiꢀe after power-up or

software reboot. Write coꢀꢀands to the configuration

EEPROM are allowed at any tiꢀe, unless the configura-

tion lock bit is set (see Table 1ꢁ). The ꢀaxiꢀuꢀ cycle

tiꢀe to write a single byte is 11ꢀs (ꢀax).

7) The ꢀaster sends the 7-bit slave address and a

read bit (high).

8) The slave asserts an ACK on SDA.

9) The slave sends the 8-bit byte count (16).

10) The ꢀaster asserts an ACK on SDA.

11) The slave sends 8 bits of data.

1±) The ꢀaster asserts an ACK on SDA.

13) Repeat steps 8 and 9 fifteen tiꢀes.

14) The ꢀaster generates a stop condition.

Address Pointers

Use the send byte protocol to set the register address

pointers before read and write operations. For the con-

figuration registers, valid address pointers range froꢀ

00h to 13h. Register addresses outside of this range

result in a NACK being issued froꢀ the MAX6876.

When using the block write protocol, the address point-

er autoꢀatically increꢀents after each data byte,

except when the address pointer is already at 13h. If

the address pointer is already 13h, and ꢀore data

bytes are being sent, these subsequent bytes overwrite

address 13h repeatedly, leaving only the last data byte

sent stored at this register address.

Configuration Register Bank and EEPROM

The configuration registers can be directly ꢀodified

with the serial interface without ꢀodifying the EEPROM,

after the power-up procedure terꢀinates and the con-

figuration EEPROM data has been loaded into the con-

figuration register bank. Use the write byte or block

write protocols to write directly to the configuration reg-

isters. Changes to the configuration registers are lost

upon power reꢀoval.

At device power-up, the register bank loads configura-

tion data froꢀ the EEPROM. Configuration data can be

directly altered in the register bank during application

developꢀent, allowing ꢀaxiꢀuꢀ flexibility. Transfer the

new configuration data byte-by-byte to the configura-

tion EEPROM with the write byte protocol. The next

device power-up or software reboot autoꢀatically loads

the new configuration (Table 16).

For the configuration EEPROM, valid address pointers

range froꢀ ±0h to 33h. When using the block write pro-

tocol, the address pointer autoꢀatically increꢀents

after each data byte, except when the address pointer

is already at 33h. If the address pointer is already 33h,

and ꢀore data bytes are being sent, these subsequent

bytes overwrite address 33h repeatedly, leaving only

the last data byte sent stored at this register address.

______________________________________________________________________________________ 31

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

Table 16. Register Map

REGISTER

ADDRESS

EEPROM MEMORY

ADDRESS

READ/WRITE

DESCRIPTION

IN1 Undervoltage Threshold Value (V ):

TH

V

= 1.0 + n x ±0ꢀV (if R08[7] = 0)

= 0.ꢁ + n x 10ꢀV (if R08[7] = 1)

TH

00h

01h

0±h

03h

04h

±0h

±1h

±±h

±3h

±4h

R/W

TH

where n is the register content deciꢀal representation. Note that V

ranges ꢀust be 1V to ꢁ.ꢁV and 0.ꢁV to 3.0ꢁV, respectively.

TH

IN± Undervoltage Threshold Value (V ):

V

where n is the register content deciꢀal representation. Note that V

ranges ꢀust be 1V to ꢁ.ꢁV and 0.ꢁV to 3.0ꢁV, respectively.

TH

= 1.0 + n x ±0ꢀV (if R08[6] = 0)

= 0.ꢁ + n x 10ꢀV (if R08[6] = 1)

TH

R/W

TH

IN3 Undervoltage Threshold Value (V ):

V

where n is the register content deciꢀal representation. Note that V

ranges ꢀust be 1V to ꢁ.ꢁV and 0.ꢁV to 3.0ꢁV, respectively.

TH

= 1.0 + n x ±0ꢀV (if R08[ꢁ] = 0)

= 0.ꢁ + n x 10ꢀV (if R08[ꢁ] = 1)

TH

IN4 Undervoltage Threshold Value (V ):

V

where n is the register content deciꢀal representation. Note that V

ranges ꢀust be 1V to ꢁ.ꢁV and 0.ꢁV to 3.0ꢁV, respectively.

TH

= 1.0 + n x ±0ꢀV (if R08[4] = 0)

= 0.ꢁ + n x 10ꢀV (if R08[4] = 1)

TH

IN1 Overvoltage Threshold Value (V ):

V

where n is the register content deciꢀal representation. Note that V

ranges ꢀust be 1V to ꢁ.ꢁV and 0.ꢁV to 3.0ꢁV, respectively.

TH

= 1.0 + n x ±0ꢀV (if R08[7] = 0)

= 0.ꢁ + n x 10ꢀV (if R08[7] = 1)

TH

IN± Overvoltage Threshold Value (V ):

V

where n is the register content deciꢀal representation. Note that V

ranges ꢀust be 1V to ꢁ.ꢁV and 0.ꢁV to 3.0ꢁV, respectively.

TH

= 1.0 + n x ±0ꢀV (if R08[6] = 0)

= 0.ꢁ + n x 10ꢀV (if R08[6] = 1)

TH

0ꢁh

06h

±ꢁh

±6h

TH

IN3 Overvoltage Threshold Value (V ):

V

TH

= 1.0 + n x ±0ꢀV (if R08[ꢁ] = 0)

= 0.ꢁ + n x 10ꢀV (if R08[ꢁ] = 1)

TH

where n is the register content deciꢀal representation. Note that V

ranges ꢀust be 1V to ꢁ.ꢁV and 0.ꢁV to 3.0ꢁV, respectively.

32 ______________________________________________________________________________________

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

Table 16. Register Map (continued)

REGISTER

ADDRESS

EEPROM MEMORY

ADDRESS

READ/WRITE

DESCRIPTION

IN4 Overvoltage Threshold Value (V ):

TH

V

= 1.0 + n x ±0ꢀV (if R08[4] = 0)

= 0.ꢁ + n x 10ꢀV (if R08[4] = 1)

TH

07h

±7h

R/W

TH

where n is the register content deciꢀal representation. Note that V

ranges ꢀust be 1V to ꢁ.ꢁV and 0.ꢁV to 3.0ꢁV, respectively.

TH

Bit 7—If 0, ±0ꢀV steps in V setting for IN1

TH

If 1, 10ꢀV steps in V setting for IN1

TH

Bit 6—If 0, ±0ꢀV steps in V setting for IN±

TH

If 1, 10ꢀV steps in V setting for IN±

TH

Bit ꢁ—If 0, ±0ꢀV steps in V setting for IN3

TH

If 1, 10ꢀV steps in V setting for IN3

TH

Bit 4—If 0, ±0ꢀV steps in V setting for IN4

TH

If 1, 10ꢀV steps in V setting for IN4

TH

Bit 3—UV1 or OV1 Fault (read only for register address). If 1, IN1 is under

undervoltage threshold or over overvoltage threshold. If 0, IN1 is over

undervoltage threshold and under overvoltage threshold.

08h

±8h

R/W

Bit ±—UV± or OV± Fault (read only for register address). If 1, IN± is under

undervoltage threshold or over overvoltage threshold. If 0, IN± is over

undervoltage threshold and under overvoltage threshold.

Bit 1—UV3 or OV3 Fault (read only for register address). If 1, IN3 is under

undervoltage threshold or over overvoltage threshold. If 0, IN3 is over

undervoltage threshold and under overvoltage threshold.

Bit 0—UV4 or OV4 Fault (read only for register address). If 1, IN4 is under

undervoltage threshold or over overvoltage threshold. If 0, IN4 is over

undervoltage threshold and under overvoltage threshold.

Bit [7:6] If “00” the device configuration is a single device

If “01” the device configuration is ꢀultiple devices, slave

If “10” the device configuration is ꢀultiple devices, slave

If “11” the device configuration is ꢀultiple devices, ꢀaster

Bit ꢁ—If 1, latch-on fault

If 0, autoretry

Bit [4:±] “000” autoretry tiꢀer value = ±ꢁµs

“001” autoretry tiꢀer value = 1±.ꢁꢀs

“010” autoretry tiꢀer value = ±ꢁ.0ꢀs

“011” autoretry tiꢀer value = ꢁ0.0ꢀs

“100” autoretry tiꢀer value = 100.0ꢀs

“101” autoretry tiꢀer value = ±00.0ꢀs

“110” autoretry tiꢀer value = 400.0ꢀs

“111” autoretry tiꢀer value = 1600.0ꢀs

09h

±9h

R/W

±

Bit 1—If 1, check I C enable bit

±

If 0, ignore I C enable bit

±

Bit 0—If 1 and 09h[1] = 1, I C enabled

±

If 0 and 09h[1] = 1, I C disabled

______________________________________________________________________________________ 33

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

Table 16. Register Map (continued)

REGISTER

ADDRESS

EEPROM MEMORY

ADDRESS

READ/WRITE

DESCRIPTION

Bit [7:6] “00” fault power-up tiꢀer value = ±ꢁꢀs

“01” fault power-up tiꢀer value = ꢁ0ꢀs

“10” fault power-up tiꢀer value = 100ꢀs

“11” fault power-up tiꢀer value = ±00ꢀs

Bit [ꢁ:4] “00” fault power-down tiꢀer value = ±ꢁꢀs

“01” fault power-down tiꢀer value = ꢁ0ꢀs

“10” fault power-down tiꢀer value = 100ꢀs

“11” fault power-down tiꢀer value = ±00ꢀs

0Ah

±Ah

R/W

Bit 3—Reserved (write 0’s for EEPROM writes)

Bit ±—Reserved (write 0’s for EEPROM writes)

Bit 1—Reserved (write 0’s for EEPROM writes)

Bit 0—Reserved (write 0’s for EEPROM writes)

Bit 7—If 1, OUT4 on raꢀp ±

Bit 6—If 1, OUT3 on raꢀp ±

Bit ꢁ—If 1, OUT± on raꢀp ±

Bit 4—If 1, OUT1 on raꢀp ±

Bit 3—If 1, OUT4 on raꢀp 1

0Bh

±Bh

R/W

Bit ±—If 1, OUT3 on raꢀp 1

Bit 1—If 1, OUT± on raꢀp 1

Bit 0—If 1, OUT1 on raꢀp 1

Bit 7—If 1, OUT4 on raꢀp 4

Bit 6—If 1, OUT3 on raꢀp 4

Bit ꢁ—If 1, OUT± on raꢀp 4

Bit 4—If 1, OUT1 on raꢀp 4

Bit 3—If 1, OUT4 on raꢀp 3

0Ch

±Ch

R/W

Bit ±—If 1, OUT3 on raꢀp 3

Bit 1—If 1, OUT± on raꢀp 3

Bit 0—If 1, OUT1 on raꢀp 3

Bit [7:6] “00” IN4 to OUT4 overcurrent threshold = 97.ꢁ%

“01” IN4 to OUT4 overcurrent threshold = 9ꢁ%

“10” IN4 to OUT4 overcurrent threshold = 9±.ꢁ%

“11” IN4 to OUT4 overcurrent threshold = 90%

Bit [ꢁ:4] “00” IN3 to OUT3 overcurrent threshold = 97.ꢁ%

“01” IN3 to OUT3 overcurrent threshold = 9ꢁ%

“10” IN3 to OUT3 overcurrent threshold = 9±.ꢁ%

“11” IN3 to OUT3 overcurrent threshold = 90%

0Dh

±Dh

R/W

Bit [3:±] “00” IN± to OUT± overcurrent threshold = 97.ꢁ%

“01” IN± to OUT± overcurrent threshold = 9ꢁ%

“10” IN± to OUT± overcurrent threshold = 9±.ꢁ%

“11” IN± to OUT± overcurrent threshold = 90%

Bit [1:0] “00” IN1 to OUT1 overcurrent threshold = 97.ꢁ%

“01” IN1 to OUT1 overcurrent threshold = 9ꢁ%

“10” IN1 to OUT1 overcurrent threshold = 9±.ꢁ%

“11” IN1 to OUT1 overcurrent threshold = 90%

34 ______________________________________________________________________________________

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

Table 16. Register Map (continued)

REGISTER

ADDRESS

EEPROM MEMORY

ADDRESS

READ/WRITE

DESCRIPTION

Bit [7:6] “00” overcurrent tiꢀer value = 1±.ꢁꢀs

“01” overcurrent tiꢀer value = ꢁ0ꢀs

“10” overcurrent tiꢀer value = 100ꢀs

“11” overcurrent tiꢀer value = ±00ꢀs

Bit ꢁ—If 1, overcurrent ꢀonitoring on OUT1 is enabled

If 0, no overcurrent ꢀonitoring on OUT1

Bit 4—If 1, overcurrent ꢀonitoring on OUT± is enabled

0Eh

±Eh

R/W

If 0, no overcurrent ꢀonitoring on OUT±

Bit 3—If 1, overcurrent ꢀonitoring on OUT3 is enabled

If 0, no overcurrent ꢀonitoring on OUT3

Bit ±—If 1, overcurrent ꢀonitoring on OUT4 is enabled

If 0, no overcurrent ꢀonitoring on OUT4

Bit [1:0] Not used

Bit [7:ꢁ] “000” gate1-delay tiꢀer value = ±ꢁµs

“001” gate1-delay tiꢀer value = 1±.ꢁꢀs

“010” gate1-delay tiꢀer value = ±ꢁ.0ꢀs

“011” gate1-delay tiꢀer value = ꢁ0.0ꢀs

“100” gate1-delay tiꢀer value = 100.0ꢀs

“101” gate1-delay tiꢀer value = ±00.0ꢀs

“110” gate1-delay tiꢀer value = 400.0ꢀs

“111” gate1-delay tiꢀer value = 1600.0ꢀs

Bit 4—Not used

0Fh

±Fh

R/W

Bit 3—OC1 overcurrent fault (read only for register address). If 1, OC1 is

overcurrent. If 0, OC1 is not overcurrent.

Bit ±—OC± overcurrent fault (read only for register address). If 1, OC± is

overcurrent. If 0, OC± is not overcurrent.

Bit 1—OC3 overcurrent fault (read only for register address). If 1, OC3 is

overcurrent. If 0, OC3 is not overcurrent.

Bit 0—OC4 overcurrent fault (read only for register address). If 1, OC4 is

overcurrent. If 0, OC4 is not overcurrent.

Bit [7:6] “00” IN4 to OUT4 power-good threshold = 9ꢁ%

“01” IN4 to OUT4 power-good threshold = 9±.ꢁ%

“10” IN4 to OUT4 power-good threshold = 90%

“11” IN4 to OUT4 power-good threshold = 87.ꢁ%

Bit [ꢁ:4] “00” IN3 to OUT3 power-good threshold = 9ꢁ%

“01” IN3 to OUT3 power-good threshold = 9±.ꢁ%

“10” IN3 to OUT3 power-good threshold = 90%

“11” IN3 to OUT3 power-good threshold = 87.ꢁ%

10h

30h

R/W

Bit [3:±] “00” IN± to OUT± power-good threshold = 9ꢁ%

“01” IN± to OUT± power-good threshold = 9±.ꢁ%

“10” IN± to OUT± power-good threshold = 90%

“11” IN± to OUT± power-good threshold = 87.ꢁ%

Bit [1:0] “00” IN1 to OUT1 power-good threshold = 9ꢁ%

“01” IN1 to OUT1 power-good threshold = 9±.ꢁ%

“10” IN1 to OUT1 power-good threshold = 90%

“11” IN1 to OUT1 power-good threshold = 87.ꢁ%

______________________________________________________________________________________ 35

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

Table 16. Register Map (continued)

REGISTER

ADDRESS

EEPROM MEMORY

ADDRESS

READ/WRITE

DESCRIPTION

Bit 7—If 1, OUT1 also controls RESET

If 0, OUT1 does not control RESET

Bit 6—If 1, OUT± also controls RESET

If 0, OUT± does not control RESET

Bit ꢁ—If 1, OUT3 also controls RESET

If 0, OUT3 does not control RESET

Bit 4—If 1, OUT4 also controls RESET

If 0, OUT4 does not control RESET

11h

31h

R/W

Bit [3:1] “000” reset tiꢀer value = ±ꢁµs

“001” reset tiꢀer value = 1±.ꢁꢀs

“010” reset tiꢀer value = ±ꢁ.0ꢀs

“011” reset tiꢀer value = ꢁ0.0ꢀs

“100” reset tiꢀer value = 100.0ꢀs

“101” reset tiꢀer value = ±00.0ꢀs

“110” reset tiꢀer value = 400.0ꢀs

“111” reset tiꢀer value = 1600.0ꢀs

Bit 0. If 1, selects external reference, if 0 internal reference selected

Bit [7:6] “00” track/sequence slew rate (rise or fall) = 800V/s

“01” track/sequence slew rate (rise or fall) = 400V/s

“10” track/sequence slew rate (rise or fall) = ±00V/s

“11” track/sequence slew rate (rise or fall) = 100V/s

1±h

3±h

R/W

Bit [ꢁ:3] Not used

Bit ±—Reserved (write 0’s for EEPROM writes)

Bit 1—Reserved (write 0’s for EEPROM writes)

Bit 0—Reserved (write 0’s for EEPROM writes)

Bit 7—If 1, reverse order of track/sequence power-down

If 0, GATE_ fast pulldown

Bit 6—If 1, OUT1 pulldown with 100Ω

If 0, OUT1 100Ω pulldown disabled

Bit ꢁ—If 1, it is possible to discharge OUT± with a pulldown

If 0, no pulldown is allowed

13h

33h

R/W

Bit 4—If 1, it is possible to discharge OUT3 with a pulldown

If 0, no pulldown is allowed

Bit 3—If 1, it is possible to discharge OUT4 with a pulldown

If 0, no pulldown is allowed

Bit ±—If 1, configuration registers are locked

If 0, configuration registers unlocked

Bit [1:0] not used

14h

1ꢁh

16h

34h

3ꢁh

36h

—

Reserved. Should not be overwritten.

36 ______________________________________________________________________________________

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

Table 16. Register Map (continued)

REGISTER

ADDRESS

EEPROM MEMORY

ADDRESS

READ/WRITE

DESCRIPTION

Reserved. Should not be overwritten.

17h

37h

—

Reserved. Should not be overwritten.

18h

38h

19h

1Ah

1Bh

1Ch

39h

3Ah

3Bh

3Ch

—

1Dh

1Eh

3Dh

3Eh

—

Reserved. Should not be overwritten.

1Fh

3Fh

—

changes actually take place, unless when changing one

of the voltage detector’s thresholds. Changing a volt-

age-detector threshold typically takes 1ꢁ0µs. When

changing EEPROM contents, software reboot or cycling

of power is required for these changes to transfer to

volatile ꢀeꢀory.

Applications Information

Layout and Bypassing

For better noise iꢀꢀunity, bypass each of the voltage-

detector inputs to GND with 0.1µF capacitors installed

as close to the device as possible. Bypass ABP to GND

with 1µF capacitors installed as close to the device as

possible. ABP is an internally generated voltage and

should not be used to supply power to external circuitry.

Chip Information

Configuration Latency Period

A delay of less than ꢁµs occurs between writing to the

configuration registers and the tiꢀe when these

PROCESS: BiCMOS

______________________________________________________________________________________ 37

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

Typical Application Circuits

IN1

IN2

IN3

IN4

OUT1

OUT2

OUT3

OUT4

IN1

IN2

IN3

IN4 GATE1 GATE2 GATE3 GATE4

OUT1

V

CC

FAULT

HOLD

OUT2

OUT3

OUT4

RESET

REM

MAX6876

SYNCH

TRKEN

V

PULLUP

ENABLE

ABP

GND

SDA

SCL

A0

A1

PG_

OUT5

OUT1

IN5

IN1

IN2

IN3

IN4

3.3V

5V

IN6

IN7

IN8

2.5V

OUT6

OUT7

OUT8

3.0V

OUT2

OUT3

OUT4

1.5V

1.8V

0.75V

1V

OUT4

IN4 GATE1 GATE2 GATE3 GATE4 OUT1 OUT2 OUT3

IN1

IN2

IN3

IN4 GATE1 GATE2 GATE3 GATE4 OUT1

OUT3

OUT4

OUT2

IN1

IN2

IN3

SYNCH (IN)

SYNCH (OUT)

HOLD

SLAVE

MASTER

FAULT

V

CC

ENABLE ABP

ABP

ENABLE

TRKEN

ALWAYS ON

3.3V

NOTE: CONFIGURING THE MAX6876 FOR MASTER/SLAVE OPERATION.

38 ______________________________________________________________________________________

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

Package Information

(The package drawing(s) in this data sheet ꢀay not reflect the ꢀost current specifications. For the latest package outline inforꢀation,

go to www.maxim-ic.com/packages.)

D2

D

C

L

b

D/2

D2/2

k

E/2

E2/2

(NE-1) X

e

C

L

E

E2

k

L

e

(ND-1) X

e

L

C

L

L1

L

e

A

A1

A2

PACKAGE OUTLINE

36, 40, 48L THIN QFN, 6x6x0.8mm

1

E

21-0141

2

NOTES:

1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.

3. N IS THE TOTAL NUMBER OF TERMINALS.

4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1

SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE

ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.

5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm

FROM TERMINAL TIP.

6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.

7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.

8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.

9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1.

10. WARPAGE SHALL NOT EXCEED 0.10 mm.

PACKAGE OUTLINE

36, 40, 48L THIN QFN, 6x6x0.8mm

2

E

21-0141

2

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 39

Printed USA

is a registered tradeꢀark of Maxiꢀ Integrated Products.


型号：	MAX6876ETX+T
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	暂无描述可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总39页 (文件大小：374K)
中文：	中文翻译
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