MAX9423EHJ [MAXIM]
LVECL-TO-LVPECL TRANSLATOR|BIPOLAR|TQFP|32PIN|PLASTIC ; LVECL至LVPECL翻译|双极| TQFP | 32引脚|塑料\n
| 型号： | MAX9423EHJ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | LVECL-TO-LVPECL TRANSLATOR|BIPOLAR|TQFP|32PIN|PLASTIC
|
| 文件： | 总13页 (文件大小：341K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2285; Rev 0; 1/02
Quad Differential LVECL-to-LVPECL Translators
General Description
Features
The MAX9420–MAX9423 are extremely fast, low-skew
quad LVECL-to-LVPECL translators designed for high-
speed signal and clock driver applications. The
devices feature ultra-low propagation delay of 336ps
and channel-to-channel skew of 17ps.
ꢀ >500mV Differential Output at 3.0GHz Clock
ꢀ 336ps (typ) Propagation Delay in Asynchronous
Mode
ꢀ 17ps (typ) Channel-to-Channel Skew
The four channels can be operated synchronously with
an external clock, or in asynchronous mode, deter-
mined by the state of the SEL input. An enable input
provides the ability to force all the outputs to a differen-
tial low state.
ꢀ Integrated 50Ω Outputs (MAX9421/MAX9423)
ꢀ Integrated 100Ω Inputs (MAX9422/MAX9423)
ꢀ Synchronous/Asynchronous Operation
These devices operate with a negative supply voltage
of -2.0V to -3.6V, compatible with LVECL input signals.
The positive supply range is 2.375V to 3.6V for differen-
tial LVPECL output signals.
Ordering Information
TEMP
RANGE
PIN-
DATA
PART
OUTPUT
PACKAGE INPUT
A variety of input and output terminations are offered for
maximum design flexibility. The MAX9420 has open
inputs and open-emitter outputs. The MAX9421 has
open inputs and 50Ω series outputs. The MAX9422 has
100Ω differential input impedance and open-emitter
outputs. The MAX9423 has 100Ω differential input
impedance and 50Ω series outputs.
The MAX9420–MAX9423 are specified for operation
from -40°C to +85°C, and are offered in space-saving
32-pin 5mm ✕ 5mm TQFP and 32-lead 5mm ✕ 5mm
QFN packages.
MAX9420EHJ -40°C to +85°C 32 TQFP
MAX9420EGJ* -40°C to +85°C 32 QFN
MAX9421EHJ -40°C to +85°C 32 TQFP
MAX9421EGJ* -40°C to +85°C 32 QFN
MAX9422EHJ -40°C to +85°C 32 TQFP
MAX9422EGJ* -40°C to +85°C 32 QFN
MAX9423EHJ -40°C to +85°C 32 TQFP
MAX9423EGJ* -40°C to +85°C 32 QFN
Open
Open
Open
Open
100Ω
100Ω
100Ω
100Ω
Open
Open
50Ω
50Ω
Open
Open
50Ω
50Ω
*Future product—contact factory for availability.
Applications
Data and Clock Driver and Buffer
Central Office Backplane Clock Distribution
DSLAM Backplane
Pin Configurations
TOP VIEW
Base Station
32 31 30 29 28 27 26 25
ATE
V
1
2
3
4
5
6
7
8
24
23
V
CC
EE
OUT1
SEL
SEL
CLK
CLK
22 OUT1
21 GND
20 GND
19 OUT2
18 OUT2
MAX9420
MAX9421
MAX9422
MAX9423
EN
EN
Functional Diagram appears at end of data sheet.
V
17 V
CC
EE
9
10 11 12 13 14 15 16
TQFP (5mm x 5mm)
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Quad Differential LVECL-to-LVPECL Translators
ABSOLUTE MAXIMUM RATINGS
V
V
to GND...........................................................-0.3V to +4.1V
to GND............................................................-4.1V to +0.3V
Junction-to-Ambient Thermal Resistance with 500
LFPM Airflow
CC
EE
Inputs to GND .............................................(V - 0.3V) to +0.3V
32-Pin 5mm ✕ 5mm TQFP.........................................+73°C/W
Junction-to-Case Thermal Resistance
EE
Differential Input Voltage ....................................................... 3V
Continuous Output Current.................................................50mA
Surge Output Current........................................................100mA
32-Pin 5mm ✕ 5mm TQFP.........................................+25°C/W
32-Lead 5mm ✕ 5mm QFN .........................................+2°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
ESD Protection
Human Body Model (IN_, IN_) ........................................500V
Others.............................................................................1.2kV
Lead Temperature (soldering, 10s) .................................+300°C
Continuous Power Dissipation (T = +70°C)
A
Single-Layer PC Board
32-Pin 5mm ✕ 5mm TQFP
(derate 9.5mW/°C above +70°C)................................761mW
32-Lead 5mm ✕ 5mm QFN
(derate 21.3mW/°C above +70°C).................................1.7W
Junction-to-Ambient Thermal Resistance in Still Air
32-Pin 5mm ✕ 5mm TQFP......................................+105°C/W
32-Lead 5mm ✕ 5mm QFN ......................................+47°C/W
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V = -2.0V to -3.6V, V = 2.375V to 3.6V, GND = 0, MAX9420/MAX9422 outputs terminated with 50Ω 1ꢀ to V - 2.0V. Typical val-
EE
CC
CC
CC
ues are at V = -3.3V, V = 3.3V, T = +25°C, V
= -0.9V, V = -1.7V, unless otherwise noted.) (Notes 1, 2, and 3)
EE
A
IHD
ILD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LVECL INPUTS (IN_, IN_, CLK, CLK, EN, EN, SEL, SEL)
V
+
1.4
EE
Differential Input High Voltage
Differential Input Low Voltage
Differential Input Voltage
V
Figure 1
Figure 1
Figure 1
0
V
V
V
IHD
V
V
-0.2
3.0
ILD
EE
V
V
≤ -3.0V
0.2
0.2
EE
EE
V
ID
> -3.0V
V
EE
MAX9420/
MAX9421
EN, EN, SEL, SEL , IN_, IN_,
CLK, or CLK = V or V
-10
-10
86
25
IHD
ILD
Input Current
I
, I
µA
IH IL
MAX9422/
MAX9423
EN, EN, SEL, SEL, CLK, or
CLK = V or V
25
IHD
ILD
Differential Input Resistance
(IN, IN)
R
MAX9422/MAX9423
100
114
Ω
IN
LVPECL OUTPUTS (OUT_, OUT_)
V
V
-
OH
Differential Output Voltage
Figure 1
Figure 1
600
660
mV
V
OL
V
-
V
1.25
-
V
-
CC
CC
CC
Output Common-Mode Voltage
V
OCM
1.5
1.1
Internal Current Source
Output Impedance
I
MAX9421/MAX9423, Figure 2
MAX9421/MAX9423, Figure 2
6.5
40
8.2
50
10.0
60
mA
SINK
R
Ω
OUT
2
_______________________________________________________________________________________
Quad Differential LVECL-to-LVPECL Translators
DC ELECTRICAL CHARACTERISTICS (continued)
(V = -2.0V to -3.6V, V = 2.375V to 3.6V, GND = 0, MAX9420/MAX9422 outputs terminated with 50Ω 1ꢀ to V - 2.0V. Typical val-
EE
CC
CC
CC
ues are at V = -3.3V, V = 3.3V, T = +25°C, V
= -0.9V, V = -1.7V, unless otherwise noted.) (Notes 1, 2, and 3)
EE
A
IHD
ILD
PARAMETER
POWER SUPPLY
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OUT_, OUT_
open
MAX9421/MAX9422/
MAX9423
Negative Supply Current
Positive Supply Current
I
7
10
mA
mA
EE
MAX9421/MAX9423
MAX9420/MAX9422
153
87
-180
105
OUT_, OUT_
open
I
CC
AC ELECTRICAL CHARACTERISTICS
(V = -2.0V to -3.6V, V
= 2.375V to 3.6V, GND = 0, outputs terminated with 50Ω 1ꢀ to V
- 2.0V. For SEL = high, CLK = high
CC
EE
CC
or low, f = 2.0GHz. For SEL = low, F = 1.5GHz, CLK = 3.0GHz, input transition time = 125ps (20ꢀ to 80ꢀ), V
= V + 1.4V to
IN
IN
IHD
EE
0, V
= +25°C, V
= V to -0.2V, V
- V
= 0.2V to the smaller of 3.0V or |V |. Typical values are at V = -3.3V, V
= 3.3V, GND = 0, T
CC A
ILD
ILD
EE
IHD
ILD
EE
EE
= -0.9V, V
= -1.7V, unless otherwise noted.) (Note 4)
IHD
PARAMETER
SYMBOL
CONDITIONS
MIN
250
350
TYP
336
506
MAX
450
UNITS
ps
IN-to-OUT Differential
CLK-to-OUT Differential
t
t
SEL = high, Figure 3
SEL = low, Figure 4
PLH1, PHL1
t
t
575
ps
PLH2, PHL2
IN-to-OUT Channel-to-Channel
Skew (Note 5)
t
SEL = high
SEL = low
17
17
60
55
ps
ps
SKD1
SKD2
CLK-to-OUT Channel-to-
Channel Skew (Note 5)
t
Maximum Clock Frequency
Maximum Data Frequency
f
V
V
-V ≥ 500mV, SEL = low
OH OL
3.0
2
GHz
GHz
CLK(MAX)
f
-V ≥ 400mV, SEL = high
OH OL
IN(MAX)
SEL = low, f
= 3.0GHz, f = 1.5GHz
0.65
0.53
1.0
1.0
ps
CLK
IN
(RMS)
(RMS)
Added Random Jitter (Note 6)
t
RJ
SEL = high, f = 2GHz
ps
IN
SEL = low, f
= 3.0GHz, IN_ = 3.0Gbps,
CLK
28
23
45
45
223 - 1 PRBS pattern
Added Deterministic Jitter
(Note 6)
t
DJ
ps
(P-P)
SEL = high, IN_ = 3.0Gbps 223 - 1 PRBS
pattern
IN-to-CLK Setup Time
CLK-to-IN Hold Time
Output Rise Time
t
Figure 4
Figure 4
Figure 3
80
80
ps
ps
ps
S
t
H
t
R
90
120
_______________________________________________________________________________________
3
Quad Differential LVECL-to-LVPECL Translators
AC ELECTRICAL CHARACTERISTICS (continued)
(V = -2.0V to -3.6V, V
= 2.375V to 3.6V, GND = 0, outputs terminated with 50Ω 1ꢀ to V
- 2.0V. For SEL = high, CLK = high
CC
EE
CC
or low, f = 2.0GHz. For SEL = low, F = 1.5GHz, CLK = 3.0GHz, input transition time = 125ps (20ꢀ to 80ꢀ), V
= V + 1.4V to
IN
IN
IHD
EE
0, V
= +25°C, V
= V to -0.2V, V
- V
= 0.2V to the smaller of 3.0V or |V |. Typical values are at V = -3.3V, V
= 3.3V, GND = 0, T
CC A
ILD
ILD
EE
IHD
ILD
EE
EE
= -0.9V, V
= -1.7V, unless otherwise noted.) (Note 4)
IHD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Fall Time
t
Figure 3
90
120
ps
F
Propagation Delay Temperature
Coefficient
∆t
∆T
/
PD
0.2
1
ps/°C
Note 1: Measurements are made with the device in thermal equilibrium.
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3: DC parameters are production tested at +25°C. DC limits are guaranteed by design and characterization over the full oper-
ating temperature range.
Note 4: Guaranteed by design and characterization. Limits are set to 6 sigma.
Note 5: Measured between outputs of the same part at the signal crossing points for a same-edge transition.
Note 6: Device jitter added to the input signal.
Typical Operating Characteristics
(V = -3.3V, V
= 3.3V, GND = 0, MAX9420/MAX9422 outputs terminated with 50Ω 1ꢀ to V
- 2.0V, SEL = high, f
= 3.0GHz,
EE
CC
CC
CLK
f
IN
= 1.5GHz, input transition time = 125ps (20ꢀ to 80ꢀ), V
= -0.9V, V
= -1.7V, T = +25°C, unless otherwise noted.)
ILD A
IHD
OUTPUT AMPLITUDE (V - V
OH
)
SUPPLY CURRENT (I
vs. TEMPERATURE
)
SUPPLY CURRENT (I
vs. TEMPERATURE
)
OL
CC
EE
vs. FREQUENCY
1000
800
100
95
90
85
80
75
70
9
8
7
6
5
4
MAX9420/MAX9422
SEL = HIGH
MAX9420/MAX9422
MAX9420/MAX9422
SEL = HIGH
SEL = HIGH
OUTPUTS NOT TERMINATED
OUTPUTS NOT TERMINATED
600
400
200
0
0
500 1000 1500 2000 2500 3000 3500
IN_ FREQUENCY (MHz)
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
IN-TO-OUT PROPAGATION DELAY
vs. TEMPERATURE
CLK-TO-OUT PROPAGATION DELAY
vs. TEMPERATURE
OUTPUT RISE/FALL TIME
vs. TEMPERATURE
100
95
90
85
80
75
370
360
350
340
330
320
310
300
290
600
575
550
525
500
475
450
425
MAX9420/MAX9422
SEL = HIGH
MAX9420/MAX9422
SEL = HIGH
MAX9420/MAX9422
SEL = LOW
t
R
t
PLH1
t
PLH2
t
F
t
PHL1
t
PHL2
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4
_______________________________________________________________________________________
Quad Differential LVECL-to-LVPECL Translators
Pin Description
PIN
NAME
FUNCTION
Negative Supply Voltage. Bypass V to GND with 0.1µF and 0.01µF ceramic capacitors. Place the
EE
capacitors as close to the device as possible with the smaller value capacitor closest to the device.
1, 8
V
EE
Noninverting Differential Select Input. Setting SEL = high and SEL = low (differential high) enables all four
channels to operate asynchronously. Setting SEL = low and SEL = high (differential low) enables all four
channels to operate in synchronous mode.
2
SEL
3
4
5
6
SEL
CLK
CLK
EN
Inverting Differential Select Input
Inverting Differential Clock Input. A rising edge on CLK (and falling on CLK) transfers data from the inputs to
the outputs when SEL = differential low.
Noninverting Differential Clock Input
Noninverting Differential Output Enable Input. Setting EN = high and EN = low (differential high) enables the
outputs. Setting EN = low and EN = high (differential low) drives the output low.
7
9
EN
IN3
IN3
Inverting Differential Output Enable Input
Noninverting Differential Input 3
Inverting Differential Input 3
10
11, 17,
24, 30
Positive Supply Voltage. Bypass V
capacitors as close to the device as possible with the smaller value capacitor closest to the device.
to GND with 0.1µF and 0.01µF ceramic capacitors. Place the
CC
V
CC
12
13
OUT3
Inverting Differential Output 3
OUT3
Noninverting Differential Output 3
14, 20,
21, 27
GND
Ground
15
16
18
19
22
23
25
26
28
29
31
32
—
IN2
IN2
Noninverting Differential Input 2
Inverting Differential Input 2
OUT2
OUT2
OUT1
OUT1
IN1
Inverting Differential Output 2
Noninverting Differential Output 2
Noninverting Differential Output 1
Inverting Differential Output 1
Inverting Differential Input 1
IN1
Noninverting Differential Input 1
Noninverting Differential Output 0
Inverting Differential Output 0
Inverting Differential Input 0
OUT0
OUT0
IN0
IN0
Noninverting Differential Input 0
EP
Exposed Paddle (MAX942_EGJ only). Connected to V internally. See package dimensions.
EE
_______________________________________________________________________________________
5
Quad Differential LVECL-to-LVPECL Translators
Outputs
Detailed Description
The MAX9421/MAX9423 have internal 50Ω series out-
The MAX9420–MAX9423 are extremely fast, low-skew
put termination resistors and 8mA internal pulldown
quad LVECL-to-LVPECL translators designed for high-
current sources. Using integrated resistors reduces
speed signal and clock driver applications. The
external component count.
devices feature ultra-low propagation delay of 336ps
and channel-to-channel skew of 17ps.
The MAX9420/MAX9422 have open-emitter outputs. An
external termination is required. See the Output
Termination section.
The four channels can be operated synchronously with
an external clock, or in asynchronous mode, deter-
mined by the state of the SEL input. An enable input
provides the ability to force all the outputs to a differen-
tial low state.
Enable
Setting EN = high and EN = low enables the device.
Setting EN = low and EN = high forces the outputs to a
differential low. All changes on CLK, SEL, and IN_ are
ignored.
These devices operate with a negative supply voltage
of -2.0V to -3.6V, compatible with LVECL input signals.
The positive supply range is 2.375V to 3.6V for differen-
tial LVPECL output signals.
Asynchronous Operation
Setting SEL = high and SEL = low enables the four
channels to operate independently as LVECL-to-
LVPECL translators. The CLK signal is ignored in this
mode. In asynchronous mode, the CLK signal should
be set to either logic low or high state to minimize noise
coupling.
A variety of input and output terminations are offered
for maximum design flexibility. The MAX9420 has open
inputs and open-emitter outputs. The MAX9421 has
open inputs and 50Ω series outputs. The MAX9422 has
100Ω differential input impedance and open-emitter
outputs. The MAX9423 has 100Ω differential input
impedance and 50Ω series outputs.
Synchronous Operation
Setting SEL = low and SEL = high enables all four
channels to operate in synchronized mode. In this
mode, buffered inputs are clocked into flip-flops simul-
taneously on the rising edge of the differential clock
input (CLK and CLK).
Supply Voltages
For interfacing to differential LVECL input levels, the
V
range is -2.0V to -3.6V with GND = 0. The V
CC
EE
range is from 2.375V to 3.6V, compatible with LVPECL
logic. Output levels are referenced to V
.
CC
Differential Signal Input Limit
The maximum signal magnitude of all the differential
inputs is 3.0V.
Data Inputs
The MAX9420/MAX9421 have open inputs and require
external termination. The MAX9422/MAX9423 have inte-
grated 100Ω differential input termination resistors from
IN_ to IN_, reducing external component count.
GND
V
IHD
(MAX)
V
CC
V
V = 0
ID
ID
V
V
OH
V
V
(MAX)
(MIN)
ILD
V - V
OH OL
V
OCM
IHD
OL
V
ID
V = 0
ID
V
EE
GND
V
ILD
(MIN)
INPUT VOLTAGE DEFINITION
OUTPUT VOLTAGE DEFINITION
Figure 1. Input and Output Voltage Definitions
_______________________________________________________________________________________
6
Quad Differential LVECL-to-LVPECL Translators
IN_
IN_
100kΩ
IN_
IN_
MAX9420/MAX9421
MAX9422/MAX9423
V
CC
V
CC
R
R
OUT
OUT_
OUT_
OUT_
OUT_
OUT
I
I
SINK
SINK
V
EE
MAX9420/MAX9422
MAX9421/MAX9423
Figure 2. Input and Output Configurations
IN_
IN_
V
- V
ILD
IHD
t
t
PHL1
PLH1
OUT_
OUT_
V
- V
OH
OH
OL
OL
V
V
- V
- V
80%
80%
20%
20%
OH
OL
DIFFERENTIAL OUTPUT
WAVEFORM
OUT_ - OUT_
t
t
F
R
SEL = HIGH
EN = HIGH
Figure 3. IN-to-OUT Propagation Delay Timing Diagram
_______________________________________________________________________________________
7
Quad Differential LVECL-to-LVPECL Translators
CLK
V
- V
ILD
IHD
CLK
t
t
t
H
H
S
IN_
IN_
V
- V
ILD
IHD
t
t
PHL2
PLH2
OUT_
OUT_
V
- V
OL
OH
SEL = LOW
EN = HIGH
Figure 4. CLK-to-OUT Propagation Delay Timing Diagram
ple parallel vias for ground-plane connection to mini-
mize inductance.
Applications Information
Input Bias
Unused inputs should be biased or driven as shown in
Figure 5. This avoids noise coupling that might cause
toggling at the unused outputs.
Circuit Board Traces
Input and output trace characteristics affect the perfor-
mance of the MAX9420–MAX9423. Connect each of the
inputs and outputs to a 50Ω characteristic impedance
trace. Avoid discontinuities in differential impedance
and maximize common-mode noise immunity by main-
taining the distance between differential traces and
avoid sharp corners. Minimize the number of vias to
prevent impedance discontinuities. Reduce the reflec-
tions by maintaining 50Ω characteristic impedance
through connectors and across cables. Minimize skew
by matching the electrical length of the traces.
Output Termination
Terminate open-emitter outputs (MAX9420/MAX9422)
through 50Ω to V
- 2V or use an equivalent Thevenin
CC
termination. Terminate outputs using identical termina-
tion on each for the lowest output-to-output skew. When
a single-ended signal is taken from a differential output,
terminate both outputs. For example, if OUT_ is used as
a single-ended output, terminate both OUT_ and OUT_.
Ensure that the output currents do not exceed the cur-
rent limits as specified in the Absolute Maximum
Ratings table. Under all operating conditions, the
device’s total thermal limits should be observed.
Chip Information
TRANSISTOR COUNT: 927
PROCESS: Bipolar
Power-Supply Bypassing
Adequate power-supply bypassing is necessary to
maximize the performance and noise immunity. Bypass
V
to GND and V to GND with high-frequency sur-
EE
CC
face-mount ceramic 0.1µF and 0.01µF capacitors in
parallel as close to the device as possible, with the
0.01µF capacitor closest to the device pins. Use multi-
8
_______________________________________________________________________________________
Quad Differential LVECL-to-LVPECL Translators
GND
V
V
CC
CC
IN_
100Ω
IN_
IN_
IN_
OUT_
OUT_
OUT_
OUT_
100Ω
MAX9420
MAX9421
MAX9422
MAX9423
1kΩ
1kΩ
1/4
1/4
V
V
EE
EE
Figure 5. Input Bias Circuits for Unused Inputs
Pin Configurations (continued)
TOP VIEW
*
*
V
1
2
3
4
5
6
7
8
24
V
CC
EE
SEL
SEL
CLK
CLK
EN
23 OUT1
22 OUT1
21 GND
20 GND
19 OUT2
18 OUT2
MAX9420
MAX9421
MAX9422
MAX9423
EN
V
EE
17
V
CC
*
*
QFN-EP*
*EXPOSED PADDLE AND CORNER PINS ARE CONNECTED TO V
LEAD UNDER PACKAGE.
EE
_______________________________________________________________________________________
9
Quad Differential LVECL-to-LVPECL Translators
Functional Diagram
IN0
IN0
1
OUT0
OUT0
D
D
Q
Q
0
CK
CK
IN1
IN1
1
0
OUT1
OUT1
D
Q
Q
D
CK
CK
IN2
IN2
1
0
OUT2
OUT2
D
Q
Q
D
CK
CK
IN3
IN3
1
0
OUT3
OUT3
D
Q
Q
D
CK
CK
CLK
CLK
SEL
SEL
EN
EN
10 ______________________________________________________________________________________
Quad Differential LVECL-to-LVPECL Translators
Package Information
______________________________________________________________________________________ 11
Quad Differential LVECL-to-LVPECL Translators
Package Information (continued)
12 ______________________________________________________________________________________
Quad Differential LVECL-to-LVPECL Translators
Package Information (continued)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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