MAX96700 [MAXIM]
14-Bit GMSL Deserializer with Coax or STP Cable Input;型号: | MAX96700 |
厂家: | MAXIM INTEGRATED PRODUCTS |
描述: | 14-Bit GMSL Deserializer with Coax or STP Cable Input |
文件: | 总73页 (文件大小:1174K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
Click here for production status of specific part numbers.
MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
General Description
Benefits and Features
● Ideal for Safety Camera Applications
The MAX96700 is a compact deserializer especially suit-
ed for automotive camera applications. Features include
adaptive equalization and an output crosspoint switch. An
embedded control channel operates at 9.6kbps to 1Mbps
• Works with Low-Cost 50Ω Coax (100Ω STP) Cables
• Error Detection of Video/Control Data
• High-Immunity Mode for Robust Control-Channel
EMC Tolerance
• Retransmission of Control Data Upon Error
• Best-in-Class Supply Current: 190mA (max)
• Adaptive Equalization for 15m Cables at Full Speed
• 32-Pin (5mm x 5mm) TQFN Package
• Horizontal- and Vertical-Sync Encoding
and Tracking
2
2
in UART, I C, and mixed UART/I C modes, allowing pro-
gramming of serializer, deserializer (SerDes), and camera
registers, independent of video timing.
The deserializer can track data from a spread-
spectrum serial input. The serial input meets ISO 10605
and IEC 61000-4-2 ESD standards. The core supply
range is 1.7V to 1.9V and the I/O supply range is 1.7V
to 3.6V. The device is available in a 32-pin (5mm x 5mm)
TQFN package with 0.5mm lead pitch, and operates over
the -40°C to +115°C temperature range.
● High-Speed Deserialization for Megapixel Cameras
• Up to 1.74Gbps Serial-Bit Rate
• 6.25MHz to 87MHz x 12-Bit + H/V Data
• 36.66MHz to 116MHz x 12-Bit + H/V Data
(through Internal Encoding)
Applications
● Automotive Camera Applications
● Multiple Modes for System Flexibility
2
• 9.6kbps to 1Mbps Control Channel in UART, I C
2
(with Clock Stretch), or UART-to-I C Modes
• 2:1 Input Mux for Camera Selection
• 15 Hardware-Selectable I C-Device Addresses
Simplified Block Diagram
2
• Pairs with Any Maxim GMSL Serializer
• Crosspoint Switch Maps Data to Any Output
● Reduces EMI and Shielding Requirements
VIDEO
VIDEO
• Spread-Spectrum Serial-Input Tracking and Transfer
to the Parallel Output
CAM
MAX96701
MAX96700
GPU
• 1.7V to 1.9V Core and 1.7V to 3.6V I/O Supply
● Peripheral Features for System Verification
2
2
I C
I C
• Built-In PRBS Receiver for BER Testing
• Eye-Width Monitor Allows In-System Test of
High-Speed Serial Link
• Dedicated “Up/Down” GPI for Camera Frame-Sync
Trigger and Other Uses
● Meets AEC-Q100 Automotive Specification
• -40°C to +115°C Operating Temperature Range
• ±8kV Contact and ±15kV Air IEC 61000-4-2 and
ISO 10605 ESD Protection
Ordering Information appears at end of data sheet.
19-100065; Rev 0; 6/17
MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
32-Pin TQFN-EP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Functional Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Serial Link Signaling and Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Video/Configuration Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Single and Double Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
HS/VS Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Error Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Bus Widths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Control Channel and Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Forward Control Channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Reverse Control Channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2
I C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Remote-End Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Clock-Stretch Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2
Packet-Based I C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Packet Protocol Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Control-Channel Error Detection and
Packet Retransmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
GPO/GPI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Adaptive Line Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Eye-Width Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Spread-Spectrum Tracking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Cable-Type Configuration and Input MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Crosspoint Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Maxim Integrated
│ 2
www.maximintegrated.com
MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
(
)
TABLE OF CONTENTS CONTINUED
Shutdown/Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Configuration Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Serialization Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Power-Down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Link-Startup Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Parallel Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Bus Data Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Bus Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Crossbar Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Crossbar Switch Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Recommended Crossbar Switch Programming Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Control-Channel Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
2
I C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
2
I C Bit Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Software Programming of the Device Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
2
I C Address Translation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Configuration Blocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Cascaded/Parallel Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Dual μC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
2
Packet-Based Control-Channel I C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Base Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
2
UART-to-I C Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
UART Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Device Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Cable Equalizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
ERRB Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Auto-Error Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Board Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Power-Supply Circuits and Bypassing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
High-Frequency Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Compatibility with Other GMSL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Device Configuration and Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Maxim Integrated
│ 3
www.maximintegrated.com
MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
(
)
TABLE OF CONTENTS CONTINUED
Internal Input Pulldowns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Multifunction Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2
I C/UART Pullup Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
AC-Coupling Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Cables and Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
PRBS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
GPI/GPO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Fast Detection of Loss-of-Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Providing a Frame Sync (Camera Applications) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Entering/Exiting Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Legacy Control Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
LIST OF FIGURES
Figure 1. Reverse Control-Channel Output Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 2. Test Circuit for Differential Input Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 4. Line Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 3. Test Circuit for Single-Ended Input Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 5. Worst-Case Pattern Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2
Figure 6. I C Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 7. Output Rise-and-Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 8. Deserializer Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 9. GPI-to-GPO Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 10. Lock Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 11. Power-Up Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12. Active Output to High-Impedance Time, High Impedance to Active-Output Time Test Circuit . . . . . . . . . 25
Figure 13. Active Output to High-Impedance Time, High Impedance to Active-Output Time . . . . . . . . . . . . . . . . . . 25
Figure 14. 24-Bit Mode Serial-Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 15. 27-Bit High-Bandwidth Mode Serial-Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 16. 32-Bit Mode Serial-Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 17. Coax Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 18. Crosspoint-Switch Dataflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 19. State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 20. GMSL-UART Data Format for Base Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
(
)
LIST OF FIGURES CONTINUED
Figure 21. GMSL-UART Protocol for Base Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 22. Sync Byte (0x79). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 23. ACK Byte (0xC3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2
Figure 24. Format Conversion Between GMSL UART and I C with Register Address (I2CMETHOD = 0). . . . . . . . 67
2
Figure 25. Format Conversion Between GMSL UART and I C with Register Address (I2CMETHOD = 1). . . . . . . . 67
Figure 26. Human Body Model ESD Test Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 27. IEC 61000-4-2 Contact Discharge ESD Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 28. ISO 10605 Contact Discharge ESD Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
LIST OF TABLES
Table 1. Reverse Control-Channel Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 2. Link-Startup Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 3. Output-Data Width Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 4. Data-Rate Selection Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 5. Output Map (DBL = 0 or DBL = 1, First Word) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 6. Output Map (DBL = 1, Second Word) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 7. Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 8. Default-Device Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 9. Cable-Equalizer Boost Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 10. Feature Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 11. Suggested Connectors and Cables for GMSL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
Absolute Maximum Ratings
AVDD to EP* ........................................................-0.5V to +1.9V
DVDD to EP*........................................................-0.5V to +1.9V
IOVDD to EP*.......................................................-0.5V to +3.9V
LMN_ to EP* (15mA current limit)........................-0.5V to +3.9V
IN_+, IN_- to EP*..................................................-0.5V to +1.9V
All Other Pins to EP*......................... -0.5V to (IOVDD + 0.5V)V
IN_+, IN_- Short Circuit to Ground or Supply ...........Continuous
Operating Temperature Range..........................-40°C to +115°C
Junction Temperature......................................................+150°C
Storage Temperature Range............................ -40°C to +150°C
Soldering Temperature (reflow).......................................+260°C
Continuous Power Dissipation, T = +70°C, 32-pin TQFN
A
(derate 34.5 mW/°C above +70°C.) .......................2758.6mW
*EP connected to IC ground.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics
32-Pin TQFN
PACKAGE CODE
T3255+8
Outline Number
21-0140
90-0013
Land Pattern Number
Thermal Resistance, Single-Layer Board:
Junction-to-Ambient (θ
)
47
JA
Junction-to-Case Thermal Resistance (θ
)
1.7
JC
Thermal Resistance, Four-Layer Board:
Junction-to-Ambient (θ
)
29
JA
Junction-to-Case Thermal Resistance (θ
)
1.7
JC
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
DC Electrical Characteristics
(V
= V
= 1.7V to 1.9V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected to PCB ground, T = -40°C to
DVDD
AVDD
IOVDD L A
+115°C. Typical values are at V
= V
= V
= 1.8V, T = +25°C, unless otherwise noted.) (Note 1)
DVDD
AVDD
IOVDD A
SYM-
BOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SINGLE-ENDED INPUTS (GPI, CXTP, I2CSEL, ADD_, HIM, PWDNB, MS)
0.65 x
High-Level Input Voltage
V
V
IH1
V
IOVDD
0.35 x
Low-Level Input Voltage
Input Current
V
V
IL1
V
IOVDD
+20
I
V
IN
= 0 to V
IOVDD
-20
μA
IN1
SINGLE-ENDED OUTPUTS (DOUT_, VS, HS, DE, PCLKOUT)
V
V
IOVDD
- 0.3
I
I
= -2mA, DCS = 0
= -2mA, DCS = 1
OH
High-Level Output Voltage
V
V
OH1
IOVDD
- 0.2
OH
I
I
= 2mA, DCS = 0
= 2mA, DCS = 1
0.3
0.2
OL
Low-Level Output Voltage
V
I
V
OL1
OL
High-Impedance
Output Current
OUTENB = 1, V
= 0V or V
-20
15
3
+20
39
13
63
21
50
17
97
32
μA
OZ
OUT
IOVDD
DOUT_, V = 0V, DCS = 0,
V
O
25
7
= 3.0V to 3.6V
IOVDD
DOUT_, V = 0V, DCS = 0,
V
O
= 1.7V to 1.9V
IOVDD
DOUT_, V = 0V, DCS = 1,
V
O
20
5
35
10
33
10
54
16
= 3.0V to 3.6V
IOVDD
DOUT_, V = 0V, DCS = 1,
V
O
= 1.7V to 1.9V
IOVDD
Output Short-Circuit Current
I
mA
OS
PCLKOUT_, V = 0V, DCS = 0,
V
O
15
5
= 3.0V to 3.6V
IOVDD
PCLKOUT_, V = 0V, DCS = 0,
V
O
= 1.7V to 1.9V
IOVDD
PCLKOUT_, V = 0V, DCS = 1,
V
O
30
9
= 3.0V to 3.6V
IOVDD
PCLKOUT_, V = 0V, DCS = 1,
V
O
= 1.7V to 1.9V
IOVDD
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
DC Electrical Characteristics (continued)
(V
= V
= 1.7V to 1.9V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected to PCB ground, T = -40°C to
DVDD
AVDD
IOVDD L A
+115°C. Typical values are at V
= V
= V
= 1.8V, T = +25°C, unless otherwise noted.) (Note 1)
DVDD
AVDD
IOVDD A
SYM-
BOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
2
UART/I C and GENERAL-PURPOSE I/Os (RX/SDA, TX/SCL, GPIO_, ERRB, LOCK, LFLTB) with OPEN-DRAIN OUTPUTS
0.7 x
High-Level Input Voltage
Low-Level Input Voltage
V
V
V
IH2
V
IOVDD
0.3 x
V
IL2
V
IOVDD
V
= 0 to V
(Note 2),
IN
IOVDD
I
-110
-80
5
5
IN2
RX/SDA, TX/SCL
Input Current
μA
V
= 0 to V
(Note 2), GPIO_,
= 1.7V to 1.9V
IOVDD
IN
IOVDD
I
IN
ERRB, LOCK
I
I
= 3mA, V
= 3mA, V
0.4
0.3
10
Low-Level Open-Drain Output
Voltage
OL
V
V
OL
= 3.0V to 3.6V
OL
IOVDD
Input Capacitance
C
Each pin (Note 3)
pF
IN
OUTPUTS FOR REVERSE CONTROL CHANNEL (IN0+, IN0-, IN1+, IN1-)
Forward channel disabled,
normal-immunity mode (Figure 1)
30
50
60
100
-30
-50
60
Differential High-Output Peak
Voltage (V - V
V
mV
mV
mV
mV
RODH
)
IN-
Forward channel disabled, high-immunity
mode (Figure 1)
IN+
Forward channel disabled,
normal-immunity mode (Figure 1)
-60
-100
30
Differential Low-Output Peak
Voltage (V - V
V
RODL
)
IN-
Forward channel disabled, high-immunity
mode (Figure 1)
IN+
Forward channel disabled,
normal-immunity mode (Figure 1)
Single-Ended High-Output
Peak Voltage
V
ROSH
Forward channel disabled, high-immunity
mode (Figure 1)
50
100
-30
-50
Forward channel disabled,
normal-immunity mode (Figure 1)
-60
-100
Single-Ended Low-Output
Peak Voltage
V
ROSL
Forward channel disabled, high-immunity
mode (Figure 1)
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
DC Electrical Characteristics (continued)
(V
= V
= 1.7V to 1.9V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected to PCB ground, T = -40°C to
DVDD
AVDD
IOVDD L A
+115°C. Typical values are at V
= V
= V
= 1.8V, T = +25°C, unless otherwise noted.) (Note 1)
DVDD
AVDD
IOVDD A
SYM-
BOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
mV
DIFFERENTIAL INPUTS (IN0+, IN0-, IN1+, IN1-)
Activity detector, medium threshold
(0x22 D[6:5] = 01) (Figure 2)
60
49
Differential High-Input-
Threshold Peak Voltage
V
IDH(P)
Activity detector, low threshold
(0x22 D[6:5] = 00) (Figure 2)
(V
- V
)
IN+
IN-
Activity detector, medium threshold
(0x22 D[6:5] = 01) (Figure 2)
-60
-49
1
Differential Low-Input-
Threshold Peak Voltage
V
mV
IDL(P)
Activity detector, low threshold
(0x22 D[6:5] = 00) (Figure 2)
(V
- V
)
IN+
IN-
Input Common-Mode Voltage
(V + V )/2
V
1.3
1.6
V
CMR
IN+
IN-
Differential-Input Resistance
(Internal)
R
80
100
130
Ω
I
SINGLE-ENDED INPUTS (IN0+, IN0-, IN1+, IN1-)
Activity detector, medium threshold
(0x22 D[6:5] = 01) (Figure 3)
43
33
Single-Ended, High-Input-
Threshold Peak Voltage
V
mV
ISH(P)
Activity detector, low threshold
(0x22 D[6:5] = 00) (Figure 3)
Activity detector, medium threshold
(0x22 D[6:5] = 01) (Figure 3)
-43
Single-Ended, Low-Input-
Threshold Peak Voltage
V
mV
ISL(P)
Activity detector, low threshold
(0x22 D[6:5] = 00) (Figure 3)
-33
40
Input Resistance (Internal)
R
50
65
Ω
I
LINE FAULT DETECTION INPUTS (LMN0, LMN1)
Short-to-Ground Threshold
Normal Threshold
V
V
(Figure 4)
(Figure 4)
0.3
V
V
TG
0.57
1.45
1.07
TN
V
+
IO
Open Threshold
V
(Figure 4)
V
TO
0.06
Open-Input Voltage
V
(Figure 4)
(Figure 4)
1.47
2.47
1.75
V
V
IO
Short-to-Battery Threshold
V
TE
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
DC Electrical Characteristics (continued)
(V
= V
= 1.7V to 1.9V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected to PCB ground, T = -40°C to
DVDD
AVDD
IOVDD L A
+115°C. Typical values are at V
= V
= V
= 1.8V, T = +25°C, unless otherwise noted.) (Note 1)
DVDD
AVDD
IOVDD A
SYM-
BOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY
f
= 116MHz, HIBW = 1, BWS = 0,
PCLKOUT
100
95
120
115
double output, AVDD + DVDD (1.9V)
f
= 116MHz, HIBW = 0, BWS = 0,
PCLKOUT
double output, AVDD + DVDD (1.9V)
f
= 116MHz, BWS = 0, double
PCLKOUT
output, IOVDD (1.9V) C = 5pF
(DCS = 0) (Note 3)
22
31
44
63
95
17
24
33
44
25
35
49
70
115
19
27
36
49
L
f
= 116MHz, BWS = 0, double
PCLKOUT
output, IOVDD (1.9V), C = 10pF
L
(DCS = 1) (Note 3)
f
= 116MHz, BWS = 0, double
PCLKOUT
output, IOVDD (3.6V), C = 5pF
L
(DCS = 0) (Note 3)
f
= 116MHz, BWS = 0, double
PCLKOUT
output, IOVDD (3.6V), C = 10pF
L
(DCS = 1) (Note 3)
f
= 87MHz, BWS = 1, double
PCLKOUT
output, IOVDD (1.9V), AVDD + DVDD
(1.9V)
f
= 87MHz, BWS = 1, double
PCLKOUT
Worst-Case Supply Current
(Figure 5)
I
output, IOVDD (1.9V), C = 5pF (DCS = 0)
mA
WCS
L
(Note 3)
f
= 87MHz, BWS = 1, double
PCLKOUT
output, IOVDD (1.9V), C = 10pF
L
(DCS = 1) (Note 3)
f
= 87MHz, BWS = 1, double
PCLKOUT
output, IOVDD (3.6V), C = 5pF (DCS = 0)
L
(Note 3)
f
= 87MHz, BWS = 1, double
PCLKOUT
output, IOVDD (3.6V), C = 10pF
L
(DCS = 1) (Note 3)
f
= 58MHz, HIBW = 1, BWS = 0,
PCLKOUT
70
70
84
84
single output, AVDD + DVDD (1.9V)
f
= 58MHz, HIBW = 0, BWS = 0,
PCLKOUT
single output, AVDD + DVDD (1.9V)
f
= 58MHz, BWS = 0, single
PCLKOUT
output, IOVDD (1.9V), C = 5pF
(DCS = 0) (Note 3)
11
15
13
18
L
f
= 58MHz, BWS = 0, single
PCLKOUT
output, IOVDD (3.6V), C = 10pF
L
(DCS = 1) (Note 3)
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
DC Electrical Characteristics (continued)
(V
= V
= 1.7V to 1.9V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected to PCB ground, T = -40°C to
DVDD
AVDD
IOVDD L A
+115°C. Typical values are at V
= V
= V
= 1.8V, T = +25°C, unless otherwise noted.) (Note 1)
DVDD
AVDD
IOVDD A
SYM-
BOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY (continued)
f
= 58MHz, BWS = 0, single
PCLKOUT
output, IOVDD (3.6V), C = 5pF
22
25
L
(DCS = 0) (Note 3)
f
= 58MHz, BWS = 0, single
PCLKOUT
output, IOVDD (3.6V), C = 10pF
(DCS = 1) (Note 3)
30
70
8
34
84
10
L
f
= 43.5MHz, BWS = 1, single
PCLKOUT
output, AVDD + DVDD (1.9V)
f
= 43.5MHz, BWS = 1, single
PCLKOUT
Worst-Case Supply Current
(Figure 5) (continued)
output, IOVDD (1.9V), C = 5pF
L
I
mA
WCS
(DCS = 0) (Note 3)
f
= 43.5MHz, BWS = 1, single
PCLKOUT
output, IOVDD (1.9V), C = 10pF
(DCS = 1) (Note 3)
12
16
22
14
18
25
L
f
= 43.5MHz, BWS = 1, single
PCLKOUT
output, IOVDD (3.6V), C = 5pF
L
(DCS = 0) (Note 3)
f
= 43.5MHz, BWS = 1, single
PCLKOUT
output, IOVDD (3.6V), C = 10pF
L
(DCS = 1) (Note 3)
Wake-up receivers enabled
Wake-up receivers disabled
PWDNB = low
54
15
15
160
100
100
Sleep-Mode Supply Current
I
μA
μA
CCS
Power-Down Supply Current
I
CCZ
ESD PROTECTION
Human Body Model, R = 1.5kΩ,
D
±8
C
= 100pF
S
IEC 61000-4-2, R = 330Ω, C = 150pF,
Contact discharge
D
S
±10
±15
±10
±30
IEC 61000-4-2, R = 330Ω, C = 150pF,
D
S
IN+, IN- (Note 4)
V
V
kV
ESD
Air discharge
ISO 10605, R = 2kΩ, C = 330pF,
D
S
Contact discharge
ISO 10605, R = 2kΩ, C = 330pF,
D
S
Air discharge
Human Body Model, R = 1.5kΩ,
D
±4
kV
V
C
= 100pF
All Other Pins (Note 5)
S
ESD
Machine Model
250
Maxim Integrated
│ 11
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
AC Electrical Characteristics
(V
= V
= 1.7V to 1.9V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected to PCB ground, T = -40°C to
DVDD
AVDD
IOVDD L A
+115°C. Typical values are at V
= V
= V
= 1.8V, T = +25°C, unless otherwise noted.) (Note 1)
DVDD
AVDD
IOVDD A
SYM-
BOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
PARALLEL CLOCK OUTPUT (PCLKOUT)
BWS = 1, DRS = 1, single output
BWS = 0, DRS = 1, single output
BWS = 1, DRS = 0, single output
6.25
8.33
12.5
12.5
16.66
43.5
BWS = 0, HIBW = 0, DRS = 0,
single output
16.66
58
BWS = 0, HIBW = 1, DRS = 0,
single output
Clock Frequency
f
MHz
36.66
25
58
87
PCLKOUT
BWS = 1, DRS = 0, double output
BWS = 0, HIBW = 0, DRS = 0,
double output
33.33
116
BWS = 0, HIBW = 1, DRS = 0,
double output
73.33
0.4T
116
PCLKOUT and DOUT_, DCS = 1,
C = 10pF or DCS = 0, C = 5pF,
0.5T
0.4T
0.4T
0.35T
0.05
0.01
L
L
nonstaggered DOUT_
Data Valid Before Clock
Data Valid After Clock
Clock Jitter
t
ns
DVB
PCLKOUT and DOUT_, DCS = 1,
C = 10pF or DCS = 0, C = 5pF,
0.35T
0.35T
0.3T
L
L
staggered DOUT_
PCLKOUT and DOUT_, DCS = 1,
C = 10pF or DCS = 0, C = 5pF,
L
L
nonstaggered DOUT_
t
ns
UI
DVA
PCLKOUT and DOUT_, DCS = 1, C =
L
10pF or DCS = 0, C = 5pF,
L
staggered DOUT_
RMS period jitter, spread off, 1.74Gbps
PRBS pattern, UI = 1/f
DBL = 1,
PCLKOUT,
double output
t
J
Period jitter; peak-to-peak, spread off,
1.74Gbps, PRBS pattern, UI = 1/f
PCLKOUT,
DBL = 0, single output
2
I C/UART PORT TIMING
2
I C/UART Bit Rate
9.6
20
1000
150
kbps
ns
30% to 70%, C = 10pF to 100pF,
1kΩ pullup to IOVDD
L
Output Rise Time
Output Fall Time
t
R
70% to 30%, C = 10pF to 100pF,
L
t
20
150
ns
F
1kΩ pullup to IOVDD
2
I C TIMING (Figure 6)
Low f
I2CSLVSH = 10)
range: (I2CMSTBT = 010,
SCL
9.6
100
400
Mid f range: (I2CMSTBT 101,
SCL
SCL Clock Frequency
f
> 100
> 400
kHz
SCL
I2CSLVSH = 01)
High f range: (I2CMSTBT = 111,
I2CSLVSH = 00)
SCL
1000
Maxim Integrated
│ 12
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
AC Electrical Characteristics (continued)
(V
= V
= 1.7V to 1.9V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected to PCB ground, T = -40°C to
DVDD
AVDD
IOVDD L A
+115°C. Typical values are at V
= V
= V
= 1.8V, T = +25°C, unless otherwise noted.) (Note 1)
DVDD
AVDD
IOVDD A
SYM-
BOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
range, Low
range, Mid
range, High
range, Low
range, Mid
range, High
range, Low
range, Mid
range, High
range, Low
range, Mid
range, High
range, Low
range, Mid
range, High
range, Low
range, Mid
range, High
range, Low
range, Mid
range, High
range, Low
range, Mid
range, High
range, Low
range, Mid
range, High
range, Low
range, Mid
range, High
range, Low
range, Mid
range, High
4
0.6
0.26
4.7
1.3
0.5
4
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
t
µs
HD:STA
t
µs
µs
µs
ns
ns
µs
µs
µs
µs
LOW
t
0.6
0.26
4.7
0.6
0.26
0
HIGH
Repeated START Condition
Setup Time
t
SU:STA
HD:DAT
Data Hold Time
Data Setup Time
t
0
0
250
100
50
t
SU:DAT
SU:STO
4
Setup Time for STOP
Condition
t
0.6
0.26
4.7
1.3
0.5
Bus Free Time
t
BUF
3.45
0.9
Data Valid Time
t
VD:DAT
VD:ACK
0.45
3.45
0.9
Data Valid Acknowledge Time
t
0.45
50
Pulse Width of Spikes
Suppressed
t
50
ns
SP
50
Capacitive load each bus line
C
B
100
pF
Maxim Integrated
│ 13
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
AC Electrical Characteristics (continued)
(V
= V
= 1.7V to 1.9V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected to PCB ground, T = -40°C to
DVDD
AVDD
IOVDD L A
+115°C. Typical values are at V
= V
= V
= 1.8V, T = +25°C, unless otherwise noted.) (Note 1)
DVDD
AVDD
IOVDD A
SYM-
BOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SWITCHING CHARACTERISTICS (Note 3)
20% to 80%, V
= 1.7V to 1.9V,
IOVDD
0.4
0.5
0.25
0.3
0.5
0.6
0.3
0.4
2.2
2.8
1.8
2
DCS = 1, C = 10pF
L
20% to 80%, V
= 1.7V to 1.9V,
= 3.0V to 3.6V,
= 3.0V to 3.6V,
= 1.7V to 1.9V,
= 1.7V to 1.9V,
= 3.0V to 3.6V,
= 3.0V to 3.6V,
IOVDD
DCS = 0, C = 5pF
PCLKOUT Rise-and-Fall Time
(Figure 7)
L
t
t
ns
R, F
20% to 80%, V
IOVDD
DCS = 1, C = 10pF
L
20% to 80%, V
IOVDD
DCS = 0, C = 5pF
L
20% to 80%, V
IOVDD
3.1
3.8
2.2
DCS = 1, C = 10pF
L
20% to 80%, V
IOVDD
DCS = 0, C = 5pF
Parallel Data Rise-and-Fall
Time (Figure 7)
L
t
t
ns
R, F
20% to 80%, V
IOVDD
DCS = 1, C = 10pF
L
20% to 80%, V
DCS = 0, C = 5pF
L
IOVDD
2.4
2160
400
Deserializer Delay
t
(Figure 8) (Note 6)
Bits
ns
SD
Reverse Control-Channel
Output Rise Time
t
No forward-channel data transmission
No forward-channel data transmission
180
180
R
Reverse Control-Channel
Output Fall Time
t
400
ns
µs
F
Deserializer GPI to serializer GPO
(Figure 9)
GPI-to-GPO Delay
t
350
1.6
GPIO
(Figure 10) AEQ on, packet CC off
(Figure 10) AEQ on, packet CC on
(Figure 10) AEQ off, packet CC off
(Figure 10) AEQ off, packet CC on
(Figure 11)
4.1
1
Lock Time (Note 3)
t
ms
LOCK
3.5
6.5
Power-Up Time
t
ms
ns
PU
Active Output to High-Imped-
ance Time
(Figure 12, Figure 13)
CC write OUTENB = 1
t
t
250
250
OAZ
OZA
Active High-Impedance to
Output Time
(Figure 12, Figure 13)
CC write OUTENB = 0
ns
Note 1: Limits are 100% production tested at T = +115°C. Limits over the operating temperature range are guaranteed by design
A
and characterization, unless otherwise noted.
Note 2: I min is due to voltage drop across the internal pullup resistor.
IN
Note 3: Not production tested. Guaranteed by design.
Note 4: Specified pin to ground.
Note 5: Specified pin to all supply/ground.
Note 6: Measured in serial-link bit times. Bit time = 1/(30 x f
) for BWS = GND. Bit time = 1/(40 x f
) for BWS = 1.
PCLKOUT
PCLKOUT
Maxim Integrated
│ 14
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
Typical Operating Characteristics
(V
= V
= V = 1.8V, T = +25°C, unless otherwise noted.)
IOVDD A
AVDD
DVDD
SUPPLY CURRENT vs.
PIXEL CLOCK FREQUENCY (BWS = 0, HIBW = 1)
SUPPLY CURRENT vs.
PIXEL CLOCK FREQUENCY (BWS = 0, HIBW = 0)
toc01
toc02
100
90
80
70
60
50
40
100
90
80
70
60
50
40
PRBS ON,
COAX MODE
PRBS ON,
COAX MODE
EQ ON
EQ OFF
DBL = 0
DBL = 0
DBL = 1
DBL = 1
EQ OFF
75
EQ OFF
15
35
55
95
115
15
35
55
75
95
115
PIXEL CLOCK FREQUENCY (MHz)
PIXEL CLOCK FREQUENCY (MHz)
MAXIMUM PIXEL CLOCK FREQUENCY vs.
STP CABLE LENGTH (BER < 10-10
SUPPLY CURRENT vs.
PIXEL CLOCK FREQUENCY (BWS = 1, HIBW = 0)
)
toc03
toc04
100
90
80
70
60
50
40
70
60
50
40
30
20
10
0
PRBS ON,
DBL = 1
EQ ON
NO PE, DBL = 0
AEQ
COAX MODE
DBL = 0
9.7dB EQ
NO EQ
4.3dB EQ
BER CAN BE AS LOW AS 10-12 FOR
CABLE LENGTHS LESS THAN 15m
EQ OFF
10
30
50
70
90
0
5
10
15
20
25
PIXEL CLOCK FREQUENCY (MHz)
STP CABLE LENGTH (m)
MAXIMUM PIXEL CLOCK FREQUENCY vs.
COAX CABLE LENGTH (BER < 10-10
)
toc05
70
NO PE, DBL = 0
AEQ
60
50
40
30
20
10
0
NO EQ
4.3dB EQ
BER CAN BE AS LOW AS 10-12 FOR
CABLE LENGTHS LESS THAN 15m
0
10
20
30
40
COAX CABLE LENGTH (m)
Maxim Integrated
│ 15
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
Pin Configuration
TOP VIEW
24 23 22 21 20 19 18 17
25
26
27
28
29
30
31
32
16
DOUT4
DOUT3
DOUT11/CXTP/DE
15
14
13
12
11
10
9
DOUT12/HS
DOUT13/VS
DVDD
PWDNB
LFLTB
DOUT2
DOUT1
DOUT0
MS
MAX96700
LOCK
ERRB
TX/SCL
RX/SDA
+
1
2
3
4
5
6
7
8
TQFN
(5mm x 5mm)
Maxim Integrated
│ 16
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
Pin Description
REF SUP-
TYPE
PIN
NAME
FUNCTION
PLY
POWER
1.8V Analog Power Supply. Bypass AVDD to EP with 0.1μF and
0.001μF capacitors placed as close as possible to the device, with
the smaller-value capacitor closest to AVDD.
5
AVDD
DVDD
Power
Power
1.8V Digital Power Supply. Bypass DVDD to EP with 0.1μF and
0.001μF capacitors placed as close as possible to the device, with
the smaller-value capacitor closest to DVDD.
13
I/O Supply Voltage. 1.8V to 3.3V logic I/O power supply. Bypass
IOVDD to EP with 0.1μF and 0.001μF capacitors placed as close
as possible to the device, with the smaller-value capacitor closest
to IOVDD.
22
IOVDD
—
Power
Power
Exposed Pad. EP is internally connected to device ground. Must
connect EP to the PCB ground plane through a via array for proper
thermal and electrical performance.
EP
HIGH-SPEED DIGITAL
High-Speed Digital / Multifunction
Parallel-Data/Vertical-Sync Output. Defaults to parallel-data
14
DOUT13/VS output on power-up. Vertical-sync output when HS/VS encoding is
enabled, or when in high-bandwidth mode.
IOVDD
IOVDD
Digital
Digital
Parallel-Data/Horizontal-Sync Output. Defaults to parallel-data
DOUT12/HS output on power-up. Horizontal-sync output when HS/VS encoding
is enabled, or when in high-bandwidth mode.
15
Parallel-Data Output/Cable-Type Input/Data-Enable Output with
internal pulldown to EP. CX/TP is latched at power-up, or when
DOUT11/
CXTP/DE
resuming from power-down mode (PWDNB = low), and switches
to parallel/data-enable output after power-up. Connect CXTP to
IOVDD with a 30kΩ resistor to set high (coax mode), or leave open
to set low (twisted-pair mode). Data-enable output when HIBW = 1.
16
IOVDD
Digital
2
Parallel-Data Output/I C-Select Input with Internal Pulldown to EP.
I2CSEL is latched at power-up, or when resuming from power-
down mode (PWDNB = low), and switches to parallel-data output
after power-up. Connect I2CSEL to IOVDD with a 30kΩ resistor to
DOUT10/
I2CSEL
17
18
19
IOVDD
IOVDD
IOVDD
Digital
Digital
Digital
2
set high (I C interface), or leave open to set low (UART interface).
Parallel-Data Output/Address Input with Internal Pulldown to EP.
ADD3 is latched at power-up, or when resuming from power-down
mode (PWDNB = low), and switches to parallel-data output after
power-up. Connect ADD3 to IOVDD with a 30kΩ resistor to set
high, or leave open to set low.
DOUT9/
ADD3
Parallel-Data Output/Address Input with Internal Pulldown to EP.
ADD2 is latched at power-up, or when resuming from power-down
mode (PWDNB = low), and switches to parallel-data output after
power-up. Connect ADD2 to IOVDD with a 30kΩ resistor to set
high, or leave open to set low.
DOUT8/
ADD2
Maxim Integrated
│ 17
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
Pin Description (continued)
REF SUP-
TYPE
PIN
NAME
FUNCTION
PLY
Parallel-Data Output/Address Input with Internal Pulldown to EP.
ADD1 is latched at power-up, or when resuming from power-down
mode (PWDNB = low), and switches to parallel-data output after
power-up. Connect ADD1 to IOVDD with a 30kΩ resistor to set
high, or leave open to set low.
DOUT7/
ADD1
20
IOVDD
IOVDD
Digital
Digital
Parallel-Data Output/Address Input with Internal Pulldown to EP.
ADD0 is latched at power-up, or when resuming from power-down
mode (PWDNB = low), and switches to parallel-data output after
power-up. Connect ADD0 to IOVDD with a 30kΩ resistor to set
high, or leave open to set low.
DOUT6/
ADD0
23
24
Parallel-Data Output/High-Immunity Mode Input with Internal
Pulldown to EP. HIM input latched at power-up, or when resuming
from power-down mode (PWDNB = low), and switches to parallel-
data output after power-up. Connect HIM to IOVDD with a 30kΩ
resistor to set high, or leave open to set low. HIGHIMM in the
serializer must be set to the same value.
DOUT5/HIM
IOVDD
IOVDD
Digital
Digital
High-Speed Digital / Single-Function
Parallel-Clock Output. Provides timing signal to latch parallel-data
outputs to the input of another device.
21
PCLKOUT
25
DOUT4
DOUT3
DOUT2
DOUT1
DOUT0
Parallel-Data Output
Parallel-Data Output
Parallel-Data Output
Parallel-Data Output
Parallel-Data Output
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
Digital
Digital
Digital
Digital
Digital
26
29
30
31
LINE FAULT
2
8
LMN1
LMN0
Line-Fault Monitor Input 1 (see Figure 4)
Line-Fault Monitor Input 0 ) (see Figure 4)
Analog
Analog
Line-Fault Output. LFLTB is active low, and has a 60kΩ internal pullup
to IOVDD. LFLTB low indicates a line-fault condition at LMN0, or
LMN1. LFLTB is output high when PWDNB is low.
28
LFLTB
IOVDD
Digital
Maxim Integrated
│ 18
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
Pin Description (continued)
REF SUP-
TYPE
PIN
OTHER PINS
1
NAME
FUNCTION
PLY
General-Purpose Input with Internal Pulldown to EP. Serializer
GPO (or INT) output follows the state of GPI.
GPI
IOVDD
Digital
Noninverting CML Serial-Data Input 1. Coax input when CXTP is
high.
3
4
6
7
IN1+
IN1-
IN0+
IN0-
Inverting CML Serial-Data Input 1
Noninverting CML Serial-Data Input 0. Coax input when CXTP is
high.
Inverting CML Serial-Data Input 0
Receive/Serial Data Input/Output with Internal 30kΩ Pullup to
IOVDD. In UART mode, RX/SDA is the Rx input of the serializer's
2
9
RX/SDA
TX/SCL
ERRB
UART. In I C mode, RX/SDA is the SDA input/output of the serial-
IOVDD
IOVDD
IOVDD
Digital
Digital
Digital
2
izer's I C master/slave. RX/SDA has an open-drain driver and
requires a pullup resistor.
Transmit/Serial Clock Input/Output with Internal 30kΩ Pullup to
IOVDD. In UART mode, TX/SCL is the Tx output of the serializer's
2
10
11
UART. In I C mode, TX/SCL is the SCL input/output of the serial-
2
izer's I C master/slave. TX/SCL has an open-drain driver and
requires a pullup resistor.
Error Output. Active-low, open-drain video data error output with
internal pullup to IOVDD. ERRB goes low when decoding errors
during normal operation exceed a programmed threshold, or when
at least one PRBS error is detected during a PRBS test. ERRB is
output high when PWDNB is low.
Lock Output. Open-drain output with internal pullup to IOVDD.
LOCK high indicates PLLs are locked with correct serial-word
boundary alignment. LOCK low indicates PLLs are not locked, or
incorrect serial-word boundary alignment. LOCK is low when the
configuration link is active. LOCK is output high when PWDNB is
low.
12
LOCK
IOVDD
Digital
Active-Low, Power-Down Input with Internal Pulldown to EP.
Set PWDNB low to enter power-down mode to reduce power
consumption.
27
32
PWDNB
IOVDD
IOVDD
Digital
Digital
Mode-select Input with Internal Pulldown to EP. Set MS low to
select base mode. Set MS high to select bypass mode.
MS
Maxim Integrated
│ 19
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
Functional Diagrams
LFLTB
ERRB
LOCK
MAX96700
LMN0
PCLKOUT
DOUT[4:0]
CLKDIV
CDR/PLL
LINE
FAULT
LMN1
EYE-WIDTH
MONITOR
DOUT5/HIM
HIM
DOUT6/ADD0
ADD0
IN0+
IN0-
VIDEO
SYNC
DOUT7/ADD1
ADD1
14 X 14
CROSSBAR
SWITCH
DOUT8/ADD2
ADD2
CML RX
CML RX
DESCRAMBLE/
HVEN/CRC/
PARITY/
DOUT9/ADD3
ADD3
SERIAL TO
PARALLEL
ADAPTIVE
EQ
DOUT10/I2CSEL
I2CSEL
IN1+
IN1-
DECODE/DBL
DOUT11/CX/TP/DE
CX/TP
DOUT12/HS
DOUT13/VS
HIM
ADD[3:0]
I2CSEL
CX/TP
FCC
TX
REVERSE CONTROL
CHANNEL
CONTROL
UART/I2C
PWDNB
GPI
TX/
SCL
RX/
SDA
Maxim Integrated
│ 20
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
R /2
L
GMSL
DESERIALIZER
IN+
IN-
V
ROD
REVERSE
V
CMR
CONTROL-CHANNEL
TRANSMITTER
R /2
L
IN+
IN-
IN-
V
CMR
IN+
V
ROH
0.9 x V
ROH
0.1 x V
ROH
(IN+) - (IN-)
0.1 x V
ROL
ROL
t
R
0.9 x V
V
ROL
t
F
Figure 1. Reverse Control-Channel Output Parameters
Maxim Integrated
│ 21
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
R /2
L
IN+
IN-
VIS(P)
0.22µF
49.9Ω
IN_
V
ID(P)
R /2
L
_
V
IN+
+
_
C
IN
C
IN
+
-
VIN_
+
_
V
CIN
IN-
V | V - V
ID(P) = IN+ IN-
|
V
(V + V )/2
CMR = IN+
IN-
Figure 2. Test Circuit for Differential Input Measurement
Figure 3. Test Circuit for Single-Ended Input Measurement
ꢊꢍꢎꢅ
ꢏꢒꢍꢓꢑΩꢈ
ꢏꢍꢐꢐꢑΩꢈ
ꢏꢒꢍꢓꢑΩꢈ
ꢏꢍꢐꢐꢑΩꢈ
GMSL
DESERIALIꢆER
LMNꢌ
LMNꢊ
LMNꢌ
GMSL
DESERIALIꢆER
OUTꢀUT
LOGIC
ꢁINꢂꢃ
TꢇISTED ꢀAIR
INꢂ
INꢄ
ꢏꢐꢍꢐꢑΩꢈ
ꢏꢐꢍꢐꢑΩꢈ
CONNECTORS
LFLTB
REFERENCE
ꢅOLTAGE
ꢊꢍꢎꢅ
GENERATOR
ꢏꢒꢍꢓꢑΩꢈ
ꢏꢍꢐꢐꢑΩ*
LMNꢊ
LMNꢌ
GMSL
DESERIALIꢆER
OUTꢀUT
LOGIC
ꢁINꢄꢃ
COAX
INꢂ
INꢄ
ꢏꢐꢍꢐꢑΩꢈ
ꢏꢐꢍꢐΩꢈ
CONNECTORS
ꢈꢉꢊꢋ
TOLERANCE
Figure 4. Line Fault
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
PCLKOUT
DOUT_
NOTE: PCLKOUT PROGRAMMED FOR RISING LATCH EDGE.
Figure 5. Worst-Case Pattern Output
START
CONDITION
BIT 7
STOP
CONDITION
(P)
BIT 6
MSB
BIT 0
(R/W)
ACKNOWLEDGE
(A)
PROTOCOL
(A6)
(S)
(A7)
t
t
LOW
t
SU;STA
HIGH
1/f
SCL
V
V
x 0.7
x 0.3
IOVDD
IOVDD
SCL
SDA
t
SP
t
t
f
BUF
t
r
V
x 0.7
x 0.3
IOVDD
V
IOVDD
t
t
t
t
t
SU;STO
HD;STA
t
HD;DAT
VD;DAT
VD;ACK
SU;DAT
2
Figure 6. I C Timing Parameters
C
L
SINGLE-ENDED OUTPUT LOAD
0.8 x V
I0VDD
0.2 x V
I0VDD
t
t
F
R
Figure 7. Output Rise-and-Fall Times
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
SERIAL-WORD LENGTH
SERIAL WORD N
SERIAL WORD N+1
SERIAL WORD N+2
IN+/-
FIRST BIT
LAST BIT
DOUT_
PARALLEL WORD N-1
PARALLEL WORD N
PARALLEL WORD N-2
PCLKOUT
t
SD
NOTE: PCLKOUT PROGRAMMED FOR RISING LATCHING EDGE.
Figure 8. Deserializer Delay
V
IH_MIN
DESERIALIZER
GPI
V
IL_MAX
t
GPIO
t
GPIO
V
OH_MIN
SERIALIZER
GPO
V
OL_MAX
Figure 9. GPI-to-GPO Delay
IN+/-
IN+ - IN-
V
PWDN
IH1
t
LOCK
t
PU
LOCK
V
OH
LOCK
V
OH
PWDN MUST BE HIGH
Figure 10. Lock Time
Figure 11. Power-Up Delay
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
MAX96700
DOUT_
5kΩ
C
L
V
IOVDD
RS/SDA
UART/I2C
Figure 12. Active Output to High-Impedance Time, High Impedance to Active-Output Time Test Circuit
RX/SDA
DISABLE
PACKET
ENABLE
PACKET
0.1 x VIOVDD
0.9 x VIOVDD
DOUT_
tOAZ
tOAZ
Figure 13. Active Output to High-Impedance Time, High Impedance to Active-Output Time
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
By default, video-link mode requires a valid PCLK for
operation. Set the AUTO_CLINK bit = 1 (if supported),
and SEREN = 1 in the serializer to automatically switch
between the video link and the configuration link when-
ever PCLK is not present.
Detailed Description
The MAX96700 deserializer is a compact device with
features especially suited for automotive camera
applications. The device operates at a variety of output
widths and word rates up to a total serial-data rate up
to 1.75Gbps. High-bandwidth mode offers a 116MHz
parallel clock rate with 12 bits of video data + 2 bits of
sync (HS/VS) data. An embedded 9.6kbps to 1Mbps
control channel programs the serializer, deserializer, and
Single and Double Modes of Operation
Single and double modes of operation configure the
available 1.74Gbps bandwidth into a variety of widths and
word rates. Single-mode operation is compatible with all
GMSL devices, and serializes one parallel word for each
serial word. Double-mode operation serializes two half-
width parallel words for each serial word, resulting in a 2x
increase in parallel word-rate range (compared to single
mode). Set DBL = 0 for single-mode operation and DBL =
1 for double-mode operation.
2
any attached UART or I C peripherals.
To promote safety applications, the device features
CRC protection of video and control data. In addition,
control-channel retransmission and high-immunity modes
reduce the effects of bit errors corrupting communica-
tion. Automatic equalization, along with a PRBS tester
and an embedded eye-width monitor, allow for in-system
optimization of the link.
HS/VS Encoding
By default, GMSL assigns a video bit slot to HSYNC,
VSYNC, and DE (if used). With HS/VS encoding, the
device instead encodes special packets to sync signals
to free up additional video bit slots. HS/VS encoding is
on by default when the device is in high-bandwidth mode.
(HIBW = 1). DE is encoded only when HIBW = 1 and
DE_EN = 1. Set HVEN = 1 to turn on HS/VS encoding
when HIBW = 0 (DE, if enabled, uses up a video bit).
HS/VS encoding requires that HSYNC, VSYNC, and DE
(if used) remain high during the active video, and low
during the blanking period. Use HS/VS inversion when
using reverse-polarity sync signals.
This device operates over the -40°C to +115°C automotive
temperature range.
Serial-Link Signaling and Data Format
The serializer scrambles the input parallel data and
combines this with the forward control data. The data is
then encoded for transmission and output as a single
bitstream at several times the input word rate (depending
on bus width). The deserializer receives the serial data and
recovers the clock signal. The data is then deserialized,
decoded, and descrambled into parallel output data and
forward control data.
Error Detection
Operating Modes
The serial link's 8b/10b encoding/decoding, and 1-bit
parity detect bit errors that occur on the serial link. An
optional 6-bit CRC check is available at the expense of 6
video bits (when HIBW = 0). To activate 6-bit CRC mode,
set PXL_CRC = 1 in the remote-side device first, and then
in the local-side device. When using 6-bit CRC mode, the
available internal bus width is reduced by 6 bits in single-
input mode (DBL = 0) and 3 bits in double-input mode
(DBL = 1). Note that the input bus width may already have
been reduced due to pin availability of the serializer or
deserializer; thus, the reduction of bandwidth from CRC
may not be visible (see Table 3).
The GMSL devices are configurable to operate in many
modes, depending on the application. These modes allow
for a more efficient use of serial bandwidth. Most of these
settings are set during system design and are configured
using the external configuration pins, or through register
bits.
Video/Configuration Link
In normal operation, the serializer runs in video-link mode
(SEREN = 1), with video data and control data sent
across the serial link. Set SEREN = 0 in the serializer to
turn off serialization. The serializer powers up in video-link
mode and requires a valid PCLK for operation.
An additional 32-bit video line CRC is available by
setting LINE_CRC_EN = 1. When enabled, the serializer
calculates the 32-bit CRC of the video line and sends this
information during the blanking period. The deserializer
compares the received CRC with the video line data. The
deserializer's LINE_CRC_ERR bit latches when a CRC
error is detected. LINE_CRC_ERR clears when read.
The configuration link is available to set up the serializer,
deserializer, and peripherals when PCLK is not available.
Set SEREN = 0 and CLINK = 1 in the serializer to enable
the configuration link (SEREN = 1 forces the serializer into
video-link mode). Once PCLK has been established, turn
on the video link (SEREN = 1).
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
half if used. The remaining bits can be used for video bits
minus any sync bits if HV encoding is not used.
Bus Widths
The serial link has multiple bus-width settings that
determine the parallel bus width and the resulting parallel
word rate. The serial link operates to a maximum serial
bit rate of 1.74Gbps. The BWS bit determines if each
serial packet is 30 or 40 bits long, which translates to a
maximum serial packet rate; thus, a maximum parallel
word rate of 58MHz or 43.5MHz when BWS = 0 or 1,
respectively. Decoding translates the 30- or 40-bit serial
packets into 24, 27, or 32 parallel bits. One bit is used for
parity, while a second is reserved for the control channel.
An additional 6 bits is used during optional 6-bit CRC. In
addition, double mode splits the remaining word size in
Note: The following modes list the internal bus widths.
The number of available input and output pins may limit
the actual bus width available.
24-Bit Mode (Figure 14)
When BWS = 0 and HIBW = 0, the 30-bit serial packet
corresponds with three 8b/10b symbols, representing
24 bits (24-bit mode). After parity and control channel,
this leaves 16/22 bits of video data if CRC is/is not used
(single mode), or 8/11 bits of video data if CRC is/is not
used (double mode).
24-BIT
MODE
22 BITS
2 BITS
SERIAL
DATA
D0
D1
D15
D16
D17
D18
D19
D20
D21
FCC
PCB
NO PXL_CRC
PXL_CRC ON
PACKET PARITY-
CHECK BIT
6
22 VIDEO
BITS
16 VIDEO
BITS
PXL_CRC
BITS
FORWARD CONTROL-
CHANNEL BIT
RX/
SDA
TX/
SCL
D0
D1
D21
D0
D1
D15
D16
D17
D18
D19
D20
D21
UART/I2C
DBL = 0
DBL = 1
DBL = 1
DBL = 0
11 x 2
VIDEO
BITS*
8 x 2
VIDEO
BITS*
22 VIDEO
BITS*
PXL_CRC
16 VIDEO
BITS*
D11
D0
D12
D21
D10
D0
D1
D21
D8
D0
D9
D15
D1
D0
D1
D15
NO PXL_CRC, DBL = 0
58MHz MAX
D1
D7
NO PXL_CRC, DBL = 1
116MHz MAX
PXL_CRC ON, DBL = 0
58MHz MAX
PXL_CRC ON, DBL = 1
116MHz MAX
*INTERNAL BITS. INPUT/OUTPUT PIN AVAILABILITY MAY LIMIT THE EXTERNAL BUS WIDTH.
Figure 14. 24-Bit Mode Serial-Data Format
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
27-Bit High-Bandwidth Mode (Figure 15)
When BWS = 0 and HIBW = 1 (high-bandwidth mode) the 30-bit serial packet represents three 9b/10b symbols represent-
ing 27 bits. After parity and control channel, this leaves 19/25 bits of video data if CRC is/is not used (single mode), or
9/12 bits of video data if CRC is/is not used (double mode).
27-BIT
MODE
25 BITS
D17
2 BITS
SERIAL
DATA
D0
D1
D15
D16
D18
D19
D20
D21
D22
D23
D24
FCC
PCB
NO PXL_CRC
PXL_CRC ON
PACKET PARITY-
CHECK BIT
6
25 VIDEO
BITS
19 VIDEO
BITS
PXL_CRC
BITS
FORWARD CONTROL-
CHANNEL BIT
RX/
SDA
TX/
SCL
D0
D1
D24
D0
D1
D15
D16
D17
D18
D22
D23
D24
UART/I2C
DBL = 0
DBL = 1
DBL = 1
DBL = 0
12 x 2
VIDEO
BITS*
9 x 2
VIDEO
BITS*
25 VIDEO
BITS*
PXL_CRC
19 VIDEO
BITS*
D12
D0
D13
D23
D11
D24
D0
D1
D24
D9
D0
D10
D17
D18
D1
D0
D1
D18
NO PXL_CRC, DBL = 0
58MHz MAX
D1
D8
NO PXL_CRC, DBL = 1
116MHz MAX
PXL_CRC ON, DBL = 0
58MHz MAX
PXL_CRC ON, DBL = 1
116MHz MAX
*INTERNAL BITS. INPUT/OUTPUT PIN AVAILABILITY MAY LIMIT THE EXTERNAL BUS WIDTH.
Figure 15. 27-Bit High-Bandwidth Mode Serial-Data Format
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
32-Bit Mode (Figure 16)
When BWS = 1 the 40-bit serial packet corresponds with four 8b/10b symbols, representing 32 bits (32-bit mode). After
parity and control channel, this leaves 24/30 bits of video data if CRC is/is not used (single mode), or 12/15 bits of video
data if CRC is/is not used (double mode).
32-BIT
MODE
30 BITS
2 BITS
SERIAL
DATA
D0
D1
D23
D24
D25
D26
D27
D28
D29
FCC
PCB
NO PXL_CRC
PXL_CRC ON
PACKET
PARITY-
CHECK BIT
6
30 VIDEO
BITS
24 VIDEO
BITS
PXL_CRC
BITS
FORWARD CONTROL-
CHANNEL BIT
RX/
SDA
TX/
SCL
D0
D2
D29
D0
D2
D23
D24
D25
D26
D27
D28
D29
UART/I2C
DBL = 0
DBL = 1
DBL = 1
DBL = 0
15 x 2
VIDEO
BITS*
12 x 2
VIDEO
BITS*
30 VIDEO
BITS*
PXL_CRC
24 VIDEO
BITS*
D15
D0
D16
D29
D14
D0
D1
D29
D12
D0
D13
D23
D1
D0
D1
D23
NO PXL_CRC, DBL = 0
43.5MHz MAX
D1
D11
NO PXL_CRC, DBL = 1
87MHz MAX
PXL_CRC ON, DBL = 0
43.5MHz MAX
PXL_CRC ON, DBL = 1
87MHz MAX
*INTERNAL BITS. INPUT/OUTPUT PIN AVAILABILITY MAY LIMIT THE EXTERNAL BUS WIDTH.
Figure 16. 32-Bit Mode Serial-Data Format
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
2
I C Interface
Control Channel and Register Programming
The control channel sends I C or UART information across
the serial link for control of the serializer, deserializer, and
any attached peripherals. The control channel is multi-
plexed onto the serial link and is available with or without
the video channel.
2
2
The serial link connects the serializer and deserializer I C
interfaces together through the control channel. When an
2
I C master sends a command to one side of the link (local
side) the control channel forwards this information to and
from the other side of the link (remote side), allowing a
single microcontroller to configure the serializer,
deserializer, and peripherals. The microcontroller can be
located on the serializer side (display applications) and the
deserializerside(cameraapplications).Dual-microcontroller
operations are supported as long as a software-arbitration
method is used. The serial link assumes that only one
microcontroller is talking at any given time.
Forward Control Channel
Control data sent from the serializer to the deserializer is
sent on the forward control channel. The data is encoded
as one of the serial bits in the forward high-speed link.
After deserialization, the forward control-channel data is
extracted from the serial link. The forward control-channel
bandwidth exceeds the maximum external control data
rate, and all data sent on the forward control channel
appears on the remote side after transmission delay of a
few bit times.
Remote-End Operation
2
When an I C master initiates communication on the local
slave device (the serializer/deserializer directly connected
to the master), the remote-side device acts as a master
device that sends data forwarded from the local-side
device, and forwards any data received from peripher-
als attached to the remote-side device. This remote-side
master device operates according to the timing settings in
Reverse Control Channel
Control data sent from the deserializer to the serializer is
sent on the reverse control channel. The data is encoded
as a series of 1μs pulses, with a maximum raw data rate of
1Mbps. High-immunity mode is available to increase the
robustness of the reverse control channel at a reduced
raw bit rate of 500kbps (Table 1). In high-immunity mode,
set HPFTUNE = 00 in the deserializer when the serial bit
rate is larger than 1Gbps. Setting the REV_FAST bit =
2
the I C Master setting register. Set the master settings to
match the timing settings used by the external μC.
Clock-Stretch Timing
2
The I C interface uses clock stretching to allow time for
2
data to be forwarded across the serial link. The master
microcontroller, along with any attached peripherals, must
accept clock stretching of the GMSL devices.
1 increases this rate back to 1Mbps. In I C mode, when
the input data rate (after encoding) exceeds the reverse
data rate, the input clock is held through clock stretching
to slow the external clock to match the internal bit rate.
2
Packet-Based I C
UART Interface
A packet-based control channel is available for enhanced
error handling of the control channel. This control-channel
method handles simultaneous GPI/GPO and I C trans-
The UART interface, compatible with all GMSL devices,
sends commands from device to device through several
UART packets. Set I2CSEL = 0 to set the device to use
the UART protocol.
2
mission, along with error detection and retransmission.
Table 1. Reverse Control-Channel Modes
2
REVERSE CONTROL-
CHANNEL MODE
MAX UART/I C BIT RATE
(kbps)
HIM PIN SETTING
REVFAST BIT
Legacy reverse control-
channel mode (compatible with
all GMSL devices)
Low
X
0
1
1000
500
High-immunity mode
Fast high-immunity mode
(requires HIBW = 0, serial-data
rate > 1.25Gbps)
High
1000
X = Don’t care.
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
Packet Protocol Summary
Eye-Width Monitor
The packet-based control channel uses a synchronous,
symbol-based system to send data across the control
channel. Data to be sent across the control channel is split
into symbols and stored in a transmit queue and then sent
The horizontal eye diagram opening is measured using
the eye-width monitor. By default this measurement is
done after link is established and also with 1 second
intervals when link is running. Eye width below a
programmed threshold flags the ERRB output pin. A very
low eye width restarts equalizer adaptation.
2
across the link. If both GPI and I C data need to be sent
2
(e.g., when GPI transitions during an I C transmission) the
symbols from both commands are combined in the queue.
If the transmit queue is empty, idle packets are sent across
the link to maintain control-channel lock. Received I C
packets are output as determined by the microcontroller
SCL rate (local device), or the programmed master bit rate
(remote device). The device holds SCL low (clock stretch)
until data has been received from the remote-side device.
Spread-Spectrum Tracking
The deserializer can track a spread input clock, eliminating
the need for multiple spread clocks.
2
Cable-Type Configuration and Input Mux
The driver inputs are programmable for two kinds of
cable: 100Ω twisted pair and 50Ω coax (contact the
factory for devices compatible with 75Ω cables). In
coax mode, connect IN0+ to OUT+ of the serializer.
Connect IN1+ to OUT+ of the second serializer. Control-
channel data is sent to the serializer selected with the
GMSL_IN_SEL bit. Leave all unused IN_ pins
unconnected, or connect them to ground through 50Ω and
a capacitor for increased power-supply rejection. If OUT- is
Control-Channel Error Detection and
Packet Retransmission
When the packet-based control channel is used, all pack-
ets are checked for errors through CRC. Using 1, 5, or 8
bits, CRC detects 1, 3, or 4 random bit errors in a packet.
The transmitter retransmits packets whenever an error is
detected. The transmitter sets a flag if a number of retries
exceeds eight. The receiver filters out packets with errors.
not used, connect OUT- to V
through a 50Ω resistor
DD
(Figure 17). When there are μCs at the serializer, and at
each deserializer, only one μC can communicate at a time.
Disable forward and reverse channel links according to the
communicating deserializer connection to prevent conten-
GPO/GPI Control
GPO on the serializer follows GPI transitions on the
deserializer. This GPO/GPI function can be used to
transmit signals such as a frame sync in a surround-view
camera system (see the Providing a Frame Sync (Camera
Applications) section).
2
2
tion in I C-to-I C mode.
Adaptive Line Equalizer
GMSL
DESERIALIZER
GM
SERIALIZER
The deserializer includes an adaptive line equalizer to
compensate for higher cable attenuation at higher frequen-
cies. The cable equalizer has 12 levels of compensation
to handle up to 30m coax and 15m STP cable lengths.
At initial lock, the adaptive equalizer selects the optimum
compensation level. The device can be programmed to
re-adapt periodically, manually, or triggered from the eye-
width monitor to compensate for any significant changes in
the transmission environment.
OUT+
OUT-
IN+
IN-
AVDD
OPTIONAL COMPONENTS
FOR INCREASED
POWER-SUPPLY REJECTION
50Ω
Figure 17. Coax Connection
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
DATA
CROSSBAR_
4
D0
D1
:
XBI0
XBI1
:
DOUT0
DOUT1
:
:
TO OUTPUT PINS
D12
D13
XBI12
XBI13
DOUT12
DOUT13
XBI0
XBI1
:
:
XBI12
XBI13
0
DOUT_
1
14 SWITCHES
Figure 18. Crosspoint-Switch Dataflow
Sleep Mode
Crosspoint Switch
To reduce power consumption further, the devices can
be put into sleep mode. In this mode, all registers keep
their programmed values, and all functions in the device
are powered down except for the wake-up detectors on
The crosspoint switch routes data between the parallel
input/output and the SerDes (Figure 18). The anything-to-
anything routing assures the mapping between the video
source and destination.
2
the local I C/UART interface, and the serial link. Any
Shutdown/Sleep Modes
Several sleep and shutdown modes are available when
full operation is not needed.
activity seen by the wake-up detectors temporarily turns
on the control-channel interface. During this time, a micro-
controller can command the device to exit sleep mode.
See the Entering/Exiting Sleep Mode section.
Configuration Link
Power-Down Mode
When the high-speed video link is not needed, or unavail-
able, a configuration link can be used in its place. In
configuration-link mode, the parallel-digital input/output
is disabled, the LOCK pin remains low, and the serial link
internally generates its own clock, to allow full operation
The lowest power-consumption mode is power-down
mode. In this mode, all functions are powered down, and
all register values are lost.
Link-Startup Procedure
2
of the control channel (UART/I C and GPIO).
Table 2 lists the startup procedure for image-sensing
applications. The control channel is available after the
video link or the configuration link is established. If the
deserializer powers up after the serializer, the control
channel becomes unavailable until 2ms after power-up.
Serialization Disable
When the serial link is not needed, such as when down-
stream devices are powered off, the user can disable
serialization. In this mode, all forward communication is
shut down. The user can reenable serialization either
locally or through the reverse channel.
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
Table 2. Link-Startup Procedure
NO.
ΜC
SERIALIZER
DESERIALIZER
—
μC connected to deserializer.
Set all configuration inputs.
Set all configuration inputs.
Powers up and loads default
settings. Establishes video link
when valid PCLK available.
Powers up and loads default
settings. Locks to video-link
signal if available.
1
Powers up. Wait t
.
PU
(If no PCLK) Programs CLINKEN, SEREN, and/or
AUTOCLINK bits. Wait 5ms after each command.
1a
Establishes configuration link.
Locks to config link if available.
(If not locked) Sets any additional configuration bits
that are mismatched between serializer and
deserializer (e.g BWS, CX/TP). Wait 5ms for lock
after each command.
Configuration changed.
Reestablishes configuration/
video link if needed.
Configuration changed. Locks to
configuration/video link.
1b
Sets Register 0x07 configuration bits in the
Configuration changed.
2
3
serializer (DBL, BWS, HIBW, PXL_CRC, etc.). Wait Reestablishes config/video link
Loss of lock may occur.
2ms.
if needed
Sets Register 0x07 configuration bits in the
deserializer (DBL, BWS, HIBW, EDC, etc.). Wait
5ms for lock to re-establish.
Configuration changed. Locks to
configuration/video link.
—
Writes rest of serializer/deserializer configuration
bits.
4
5
Configuration changed.
Configuration changed.
Forwards commands from μC to Forwards commands to camera/
serializer.
Writes camera/peripheral configuration bits.
peripherals.
If in configuration link: When PCLK is available, set
SEREN = 1. Wait 5ms for lock.
5a
Enables video link.
Locks to video link.
SLEEP = 1, VIDEO LINK OR CONFIG
LINK NOT LOCKED AFTER 8ms
CONFIG LINK
OPERATING
SIGNAL
DETECTED
CONFIG LINK
UNLOCKED
WAKE UP
SIGNAL
POWER ON
IDLE
SERIAL PORT
SLEEP
LOCKING
CONFIG LINK
LOCKED
PROGRAM
REGISTERS
0 --> SLEEP
VIDEO LINK
LOCKED
VIDEO LINK
UNLOCKED
SERIAL LINK ACTIVITY STOPS OR 8ms ELAPSES
AFTER µC SETS SLEEP = 1
PWDNB = HIGH,
POWER ON
GPI CHANGES FROM
LOW TO HIGH OR
PRBSEN = 0
PRBSEN = 1
POWER-
DOWN
OR
SEND GPI TO
GMSL
SERIALIZER
HIGH TO LOW
PWDNB = LOW OR
POWER OFF
VIDEO LINK
OPERATING
VIDEO LINK
PRBS TEST
ALL STATES
POWER OFF
0 -- > SLEEP
Figure 19. State Diagram
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
Register Map
OFFSET
NAME
seraddr[7:0]
MSB
LSB
0x00
SERADDR[6:0]
DESADDR[6:0]
RSVD
CFG-
BLOCK
0x01
desaddr[7:0]
0x02
0x03
0x04
invpinh[7:0]
INVPINH[5:0]
INVPINL[7:0]
LOCKED OUTENB PRBSEN SLEEP INTTYPE[1:0]
SRNG[1:0]
invpinl[7:0]
main config[7:0]
REVCCENFWDCCEN
EQTUNE[3:0]
I2C-
HVTR_
MODE
0x05
eqtune[7:0]
DCS
EN_EQ
METHOD
MAX_RT_ I2C_RT_
GPI_
COMP_EN
GPI_RT_
0x06
0x07
0x08
hvsrc[7:0]
HIGHIMM
HV_SRC[2:0]
EN
EN
EN
config[7:0]
pktcc_en[7:0]
DBL
DRS
BWS
ES
HIBW
HVEN
CXTP
PXL_CRC
LFLT_EN_ LFLT_EN_
PKTCC_
CC_CRC_
LENGTH[1:0]
RSVD
GPI_EN DISSTAG ERR_RST
POS
NEG
EN
0x09
0x0A
0x0B
0x0C
i2csrc A[7:0]
i2cdst A[7:0]
i2csrc B[7:0]
i2cdst B[7:0]
I2C_SRC_A[6:0]
I2C_DST_A[6:0]
I2C_SRC_B[6:0]
I2C_DST_B[6:0]
RSVD
RSVD
RSVD
I2C_LOC_
ACK
0x0D
0x0E
0x0F
i2cconfig[7:0]
det_thr[7:0]
I2C_SLV_SH[1:0]
I2C_MST_BT[2:0]
I2C_SLV_TO[1:0]
DET_THR[7:0]
GMSL_IN_ EN_DE_ EN_HS_ EN_VS_
PRBS_
TYPE
filt_track[7:0]
DE_EN HTRACK VTRACK
SEL
FILT
FILT
FILT
RCEG_
BOUND
0x10
0x11
rceg[7:0]
RCEG_TYPE[1:0]
RCEG_ERR_NUM[3:0]
RCEG_EN
RCEG_LO_BST_
RCEG_LO_BST_
LEN[1:0]
rceg2[7:0]
RCEG_ERR_RATE[3:0]
PRB[1:0]
UNDER-
BST_DET_
EN
RCEG_
MAX_RT_
CC_CRC_
ERR_EN
LINE_
DIS_
0x12
0x13
0x14
line_crc[7:0]
ewm[7:0]
aeq[7:0]
LINE_CRC_LOC[1:0]
ERR_
CRC_EN RWAKE ERR_EN
PER_EN
EWM_
PER_
MODE TRG_REQ
EWM_
MAN_
EWM_EN
AEQ_EN
EWM_MIN_THR[4:0]
AEQ_
PER_
AEQ_
MAN_
EWM_PER_THR[4:0]
MODE TRG_REQ
0x15
0x16
det_err[7:0]
DET_ERR[7:0]
PRBS_ERR[7:0]
prbs_err[7:0]
MAX_RT_
0x17
lf[7:0]
RSVD
PRBS_OK GPI_IN
LF_NEG[1:0]
LF_POS[1:0]
ERR
0x18
0x19
0x1A
rsvd_18[7:0]
RSVD[7:0]
cc_crc_errcnt[7:0]
rceg_err_cnt[7:0]
CC_CRC_ERRCNT[7:0]
RCEG_ERR_CNT[7:0]
Maxim Integrated
│ 34
www.maximintegrated.com
MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
OFFSET
NAME
MSB
RSVD
RSVD
LSB
LINE_
CRC_ERR
EOM_EYE_WIDTH[5:0]
0x1B
0x1C
i2csel[7:0]
RSVD
RSVD
RSVD
RSVD
RSVD
I2CSEL
RSVD
RSVD
ewm_eye_width[7:0]
aeq_bst[7:0]
UNDER-
BOOST_
DET
0x1D
RSVD
RSVD
RSVD
RSVD
AEQ_BST[3:0]
REVISION[3:0]
0x1E
0x1F
0x20
0x21
0x22
0x23
id[7:0]
ID[7:0]
RSVD HDCPCAP
CRCVALUE_0_[7:0]
revision[7:0]
crcvalue 0[7:0]
crcvalue 1[7:0]
crcvalue 2[7:0]
crcvalue 3[7:0]
CRCVALUE_1_[7:0]
CRCVALUE_2_[7:0]
CRCVALUE_3_[7:0]
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x96
0x97
0x98
0x99
0x9A
0x9B
0x9C
crossbar 0[7:0]
crossbar 2[7:0]
crossbar 4[7:0]
crossbar 6[7:0]
crossbar 8[7:0]
crossbar 10[7:0]
crossbar 12[7:0]
rsvd_96[7:0]
CROSSBAR_N_0[3:0]
CROSSBAR_N_2[3:0]
CROSSBAR_N_4[3:0]
CROSSBAR_N_6[3:0]
CROSSBAR_N_8[3:0]
CROSSBAR_N_10[3:0]
CROSSBAR_N_12[3:0]
CROSSBAR_N+1_0[3:0]
CROSSBAR_N+1_2[3:0]
CROSSBAR_N+1_4[3:0]
CROSSBAR_N+1_6[3:0]
CROSSBAR_N+1_8[3:0]
CROSSBAR_N+1_10[3:0]
CROSSBAR_N+1_12[3:0]
RSVD[1:0]
REV_FAST RSVD
RSVD[1:0]
RSVD
RSVD[5:0]
RSVD[5:0]
RSVD
RSVD
RSVD
rev_fast[7:0]
rsvd_98[7:0]
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
rsvd_99[7:0]
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
rsvd_9a[7:0]
RSVD[1:0]
RSVD[2:0]
rsvd_9b[7:0]
RSVD[1:0]
RSVD[1:0]
RSVD[2:0]
RSVD[1:0]
rsvd_9c[7:0]
RSVD
RSVD
RSVD[3:0]
SOFT_
PD
0x9D
rsvd_9d[7:0]
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
0x9E
0x9F
0xA0
0xA1
0xA2
0xA3
0xA4
0xA5
0xA6
rsvd_9e[7:0]
rsvd_9f[7:0]
rsvd_a0[7:0]
rsvd_a1[7:0]
rsvd_a2[7:0]
rsvd_a3[7:0]
rsvd_a4[7:0]
rsvd_a5[7:0]
rsvd_a6[7:0]
RSVD
RSVD
RSVD
RSVD[1:0]
RSVD RSVD
RSVD[2:0]
RSVD
RSVD
RSVD
RSVD
RSVD
HPFTUNE[1:0]
RSVD
RSVD[1:0]
RSVD[3:0]
RSVD[2:0]
RSVD[4:0]
RSVD[7:0]
RSVD[3:0]
RSVD[3:0]
RSVD
RSVD[1:0]
RSVD[1:0]
RSVD[2:0]
RSVD
RSVD
RSVD
RSVD[1:0]
RSVD[3:0]
RSVD[1:0]
RSVD[1:0]
RSVD
RSVD
RSVD
Maxim Integrated
│ 35
www.maximintegrated.com
MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
OFFSET
NAME
rsvd_c9[7:0]
rsvd_ca[7:0]
MSB
LSB
0xC9
0xCA
RSVD[7:0]
RSVD[1:0]
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
REM_
RSVD
CC_
RSVD
CC_
0xCB
cc_locked[7:0]
RSVD
WBLOCK_ RSVD
LOST
WBLOCK CCLOCK
0xCC
0xCD
rsvd_cc[7:0]
rsvd_cd[7:0]
RSVD
RSVD
RSVD[6:0]
RSVD[6:0]
0xFD
0xFE
0xFF
rsvd_fd[7:0]
rsvd_fe[7:0]
rsvd_ff[7:0]
RSVD[7:0]
RSVD[3:0]
RSVD[3:0]
RSVD[3:0]
RSVD
RSVD
RSVD
RSVD
Maxim Integrated
│ 36
www.maximintegrated.com
MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
seraddr (0x00)
BIT
7
6
5
4
3
2
1
0
RSVD
0b
Field
SERADDR[6:0]
1000000b
Reset
Access Type
Write, Read
Write, Read
BITFIELD
SERADDR
RSVD
BITS
DESCRIPTION
DECODE
2
0000000: I C write/read address is 0x00, 0x01
0000001: I C write/read address is 0x02, 0x03
XXXXXXX: I C write/read address is XXXXXXX0,
2
2
7:1
0
Serializer Address: Serializer device address
Reserved: Do not change from default value
XXXXXXX1
2
1111111: I C write/read address is 0xFE, 0xFF
0: Reserved
desaddr (0x01)
BIT
7
6
5
4
3
2
1
0
Field
DESADDR[6:0]
XXXXXXXb
Write, Read
CFGBLOCK
0b
Reset
Access Type
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
2
0000000: I C write/read address is 0x00, 0x01
2
Deserializer Address: Deserializer device address 0000001: I C write/read address is 0x02, 0x03
2
DESADDR
7:1
(initial value depends on ADD3, ADD2, ADD1, and XXXXXXX: I C write/read address is XXXXXXX0,
ADD0 pin settings latched at power-up)
XXXXXXX1
1111111: I C write/read address is 0xFE, 0xFF
2
Configuration Block. When 1, make all registers
read only
0: Set all write/read registers as writable
1: Set all registers as read only
CFGBLOCK
0
invpinh (0x02)
BIT
7
6
5
4
3
2
1
0
Field
INVPINH[5:0]
000000b
SRNG[1:0]
11b
Reset
Access Type
Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
XXXXX0: Do not invert D8
XXXXX1: Invert D8
XXXX0X: Do not invert D9
XXXX1X: Invert D9
XXX0XX: Invert D10
Invert Output Pins High: Invert output pins
D8–D13
XXX1XX: Do not invert D10
XX0XXX: Do not invert D11
XX1XXX: Invert D11
INVPINH
7:2
X0XXXX: Do not invert D12
X1XXXX: Invert D12
0XXXXX: Do not invert D13
1XXXXX: Invert D13
00: 0.5 to 1Gbps
SRNG
1:0
Serial Data-Rate Range
01: 1 to 1.74Gbps
1X: Autodetect serial range
Maxim Integrated
│ 37
www.maximintegrated.com
MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
invpinl (0x03)
BIT
7
6
5
4
3
2
1
0
Field
INVPINL[7:0]
00000000b
Write, Read
Reset
Access Type
BITFIELD
BITS
DESCRIPTION
DECODE
XXXXXXX0: Do not invert D0
XXXXXXX1: Invert D0
XXXXXX0X: Do not invert D1
XXXXXX1X: Invert D1
XXXXX0XX: Do not invert D2
XXXXX1XX: Invert D2
XXXX0XXX: Do not invert D3
XXXX1XXX: Invert D3
XXX0XXXX: Do not invert D4
XXX1XXXX: Invert D4
Invert Output Pins Low: Invert output pins
D0–D7
INVPINL
7:0
XX0XXXXX: Do not invert D5
XX1XXXXX: Invert D5
X0XXXXXX: Do not invert D6
X1XXXXXX: Invert D6
0XXXXXXX: Do not invert D7
1XXXXXXX: Invert D7
main config (0x04)
BIT
Field
7
6
OUTENB
0b
5
PRBSEN
0b
4
3
2
1
REVCCEN
0b
0
FWDCCEN
0b
LOCKED
Xb
SLEEP
0b
INTTYPE[1:0]
Reset
01b
Access Type
Read Only
Write, Read Write, Read Write, Read
Write, Read
Write, Read Write, Read
DECODE
BITFIELD
BITS
DESCRIPTION
0: Video link not locked
1: Video link locked
LOCKED
7
6
5
4
LOCK Output: LOCK output pin level
Outputs Enable Bar: Disable outputs
PRBS Test Enable
0: Enable DOUT_outputs
1: Disable DOUT_ outputs
OUTENB
PRBSEN
SLEEP
0: Set device for normal operation
1: Enable PRBS test
0: Set device for normal operation
1: Put device into sleep mode
Sleep Mode: Activate sleep mode
2
00: UART-to-I C conversion
01: UART
Interface Type: Local control-channel interface
when I2CSEL = 0
INTTYPE
3:2
1X: Disable local control channel
Reverse Control-Channel Enable: Enable
reverse control channel from deserializer
0: Disable reverse control-channel receiver
1: Enable reverser control-channel receiver
REVCCEN
FWDCCEN
1
0
Forward Control-Channel Enable: Enable
forward control channel to deserializer
0: Disable forward control-channel transmitter
1: Enable forward control-channel transmitter
Maxim Integrated
│ 38
www.maximintegrated.com
MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
eqtune (0x05)
BIT
7
6
5
4
EN_EQ
1b
3
2
1
0
I2C-
METHOD
HVTR_
MODE
Field
DCS
0b
EQTUNE[3:0]
Reset
0b
1b
1001b
Access Type Write, Read Write, Read Write, Read Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
2
0: Send the register address during UART-to-I C
conversion
2
I C Method: Skip register address when
I2CMETHOD
7
2
converting UART to I C
1: Do not send the register address during
2
UART-to-I C conversion
Driver Current Selection: Driver current selec- 0: Set device for normal operation
tion for CMOS outputs 1: Increase CMOS driver current
HV Tracking Mode: HV tracking allows continu- 0: Use partial periodic HV tracking
ous HSYNC format 1: Use partial and full periodic HV tracking
Enable Equalizer: Enable equalizer for manual 0: Disable equalization
DCS
6
5
4
HVTR_MODE
EN_EQ
and adaptive modes
1: Enable equalization
0000: 1.6dB manual EQ setting
0001: 2.1dB manual EQ setting
0010: 2.8dB manual EQ setting
0011: 3.5dB manual EQ setting
0100: 4.3dB manual EQ setting
0101: 5.2dB manual EQ setting
0110: 6.3dB manual EQ setting
0111: 7.3dB manual EQ setting
1000: 8.5dB manual EQ setting
1001: 9.7dB manual EQ setting
1010: 11dB manual EQ setting
1011: 12.2dB manual EQ setting
11XX: Do Not Use
Equalizer Tune: Equalizer boost level at
750MHz (effective when Adaptive EQ is turned
off)
EQTUNE
3:0
Maxim Integrated
│ 39
www.maximintegrated.com
MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
hvsrc (0x06)
BIT
7
6
5
I2C_RT_EN
1b
4
3
GPI_RT_EN
1b
2
1
0
MAX_RT_
EN
GPI_
COMP_EN
Field
RSVD
Xb
HV_SRC[2:0]
Reset
1b
0b
110b
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read
Write, Read
BITS
DESCRIPTION
DECODE
High-Immunity Mode: Default value
depends on the state of the HIM input
0: Use legacy reverse-channel mode
1: Use high-immunity mode
HIGHIMM
Maximum Retransmission Limit
Enable
0: Disable maximum retransmission limit
1: Enable maximum retransmission limit
6
5
4
3
2
0: Disable I C retransmission
2
I C Retransmission Enable
2
1: Enable I C retransmission
GPI Compensation Enable: GPI skew 0: Disable GPI skew compensation
compensation enable
1: Enable GPI skew compensation
0: Disable GPI retransmission
1: Enable GPI retransmission
GPI Retransmission Enable
000: Use D18/D19 for HS/VS (use this setting when the serializer is a
3.125Gbps device or if HIBW mode is used; otherwise, this setting is for use
with the MAX9273 when DBL = 0 or HVEN = 1)
001: Use D14/D15 for HS/VS (for use with the MAX9271/MAX96705 when
DBL = 0 or HVEN = 1)
010: Use D12/D13 for HS/VS (for use with the MAX96707 when DBL = 0 or
HVEN = 1)
HS/VS Source Selection: HS/VS bit
2:0
selection
011: Use D0/D1 for HS/VS (for use with the MAX9271/MAX9273/MAX96705/
MAX96707 when DBL = 1 and HVEN = 0)
10X: Do Not Use
110: Automatically determine the source of HSYNC/VSYNC (for use with the
MAX96707)
111: Automatically determine the source of HSYNC/VSYNC (for use with the
MAX96705)
Maxim Integrated
│ 40
www.maximintegrated.com
MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
config (0x07)
BIT
7
6
5
4
3
2
1
0
PXL_CRC
0b
Field
DBL
1b
DRS
0b
BWS
0b
ES
0b
HIBW
0b
HVEN
1b
CXTP
Xb
Reset
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD
BITS
DESCRIPTION
Double-Output Mode
DECODE
0: Use single-rate output
1: Use double-rate output (2x word rate at 1/2x
width)
DBL
7
0: Use normal data-rate output
1: Use 1/2 rate data output (for use with low data
rates)
DRS
BWS
6
5
Data-Rate Select
0: Set bus width for 22-/24-bit bus, 24-/27-bit mode
(depending on HIBW setting)
Bus-Width Select
1: Set bus width for 30-bit bus (32-bit mode)
0: Set output data valid on rising edge of
PCLKOUT
1: Set output data valid on falling edge of
PCLKOUT
ES
4
Edge Select
0: Disable high-bandwidth mode
1: Enable high-bandwidth mode (when BWS = 0)
HIBW
HVEN
3
2
High-Bandwidth Mode
HS/VS Encoding Enable
0: Disable HS/VS encoding
1: Enable HS/VS encoding
0: Use differential-output mode (for use with
twisted-pair cable)
1: Use single-ended output mode (for use with
coax cable)
CXTP
1
0
Coax/TP Select
Pixel CRC Enable: Pixel error-detection type (this 0: Use 1-bit parity (compatible with all devices)
is controllable by pin when LCCEN = 0) 1: Use 6-bit CRC
PXL_CRC
Maxim Integrated
│ 41
www.maximintegrated.com
MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
pktcc_en (0x08)
BIT
7
6
5
GPI_EN
1b
4
DISSTAG
0b
3
2
1
0
CC_CRC_
LENGTH[1:0]
Field
LFLT_EN_POS LFLT_EN_NEG
ERR_RST PKTCC_EN
0b 0b
Reset
1b
Xb
01b
Access Type
Write, Read
Write, Read
Write, Read Write, Read Write, Read Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
0: Disable line-fault detector LMN0
1: Enable line-fault detector LMN0
Line-Fault Detector Enable Positive Line:
Enable line-fault detector LMN0
LFLT_EN_POS
7
Line-Fault Detector Enable Negative Line:
Enable line-fault detector LMN1; disabled by
default in coax mode and enabled by default in
twisted-pair mode
0: Disable line-fault detector LMN1
1: Enable line-fault detector LMN1
LFLT_EN_NEG
6
GPI-to-GPO Enable: Enable GPI-to-GPO
signal transmission to serializer
0: Disable GPI-to-GPO transmission
1: Enable GPI-to-GPO transmission
GPI_EN
5
4
Disable Staggering: Disable staggering of
outputs
0: Enable staggering of DOUT_outputs
1: Disable staggering of DOUT_outputs
DISSTAG
0: Disable automatic reset of DETERR_
Error Reset: When set to 1, automatically reset register
ERR_RST
3
2
DET_ERR 1μs after ERROR pin is asserted
1: Enable automatic reset of DETERR_
register
0: Disable packet-based control-channel mode
1: Enable packet-based control-channel mode
PKTCC_EN
Packet-Based Control-Channel Mode Enable
00: 1-bit CRC
01: 5-bit CRC
10: 8-bit CRC
11: Do Not Use
CC_CRC_LENGTH
1:0
Control-Channel CRC Length
i2csrc (0x09, 0x0B)
BIT
Field
7
6
5
4
I2C_SRC[6:0]
0b
3
2
1
0
RSVD
0b
Reset
Access Type
Write, Read
Write, Read
BITFIELD
I2C_SRC
RSVD
BITS
7:1
0
DESCRIPTION
DECODE
2
0000000: I C write/read address is 0x00, 0x01
0000001: I C write/read address is 0x02, 0x03
XXXXXXX: I C write/read address is
XXXXXXX0, XXXXXXX1
2
2
2
I C Address Translator Source: I C address
translator source A
2
2
1111111: I C write/read address is 0xFE, 0xFF
Reserved: Do not change from default value
0: Reserved
Maxim Integrated
│ 42
www.maximintegrated.com
MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
i2cdst (0x0A, 0x0C)
BIT
Field
7
6
5
4
I2C_DST[6:0]
0b
3
2
1
0
RSVD
0b
Reset
Access Type
Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
2
0000000: I C write/read address is 0x00, 0x01
2
0000001: I C write/read address is 0x02, 0x03
2
2
I C address translator destination: I C address
translator destination A
2
I2C_DST
7:1
XXXXXXX: I C write/read address is
XXXXXXX0, XXXXXXX1
2
1111111: I C write/read address is 0xFE, 0xFF
RSVD
0
Reserved: Do not change from default value
0: Reserved
i2cconfig (0x0D)
BIT
7
6
5
4
3
I2C_MST_BT[2:0]
101b
2
1
0
Field
I2C_LOC_ACK
0b
I2C_SLV_SH[1:0]
01b
I2C_SLV_TO[1:0]
10b
Reset
Access Type
Write, Read
Write, Read
Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
0: Disable local acknowledge when forward
channel is not available
1: Enable local acknowledge when forward
channel is not available
2
2
I C-to-I C Slave Local Acknowledge: When
I2C_LOC_ACK
7
forward channel is not available
00: (352, 117)ns
01: (469, 234)ns
10: (938, 352)ns
11: (1406, 469)ns
2
2
I C-to-I C Slave Setup and Hold Time Setting:
I2C_SLV_SH
I2C_MST_BT
I2C_SLV_TO
6:5
Setup, hold (typ)
000: (6.61, 8.47, 9.92)kbps bit rate
001: (22.1, 28.3, 33.2)kbps bit rate
010: (66.1, 84.7, 99.2)kbps bit rate
011: (82, 105, 123)kbps bit rate
100: (136, 173, 203)kbps bit rate
101: (265, 339, 397))kbps bit rate
110: (417, 533, 625)kbps bit rate
111: (654, 837, 980)kbps bit rate
2
2
4:2
1:0
I C-to-I C Master Bit Rate Setting: Min, typ, max.
00: 64μs timeout
01: 256μs timeout
10: 1024μs timeout
2
2
I C-to-I C Slave Remote-Side
Timeout Setting: Typ
2
11: I C timeout disabled
Maxim Integrated
│ 43
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
det_thr (0x0E)
BIT
7
6
5
4
3
2
1
0
Field
DET_THR[7:0]
Reset
00000000b
Write, Read
Access Type
BITFIELD
BITS
DESCRIPTION
DECODE
00000000: Value is 0
00000001: Value is 1, XXXXXXXX
11111111: Value is 255
Detected Errors Threshold: Threshold for de-
tected errors
DET_THR
7:0
filt_track (0x0F)
BIT
7
6
5
4
3
DE_EN
0b
2
HTRACK
1b
1
VTRACK
1b
0
GMSL_IN_
SEL
EN_DE_
FILT
EN_HS_
FILT
EN_VS_
FILT
PRBS_
TYPE
Field
Reset
0b
0b
0b
0b
1b
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD
BITS
DESCRIPTION
Select GMSL Input
DECODE
0: Select IN0+, IN0-
1: Select IN1+, IN1-
GMSL_IN_SEL
7
Enable DE Glitch Filtering: Enable glitch filtering
on DOUT11
0: Disable glitch filtering on DOUT11
1: Enable glitch filtering on DOUT11
EN_DE_FILT
EN_HS_FILT
EN_VS_FILT
DE_EN
6
5
4
3
2
1
0
Enable HS Glitch Filtering: Enable glitch filtering
on DOUT12
0: Disable glitch filtering on DOUT12
1: Enable glitch filtering on DOUT12
Enable VS Glitch Filtering: Enable glitch filtering
on DOUT13
0: Disable glitch filtering on DOUT13
1: Enable glitch filtering on DOUT13
DE Processing Enable: Enable processing sepa- 0: Disable processing HS and DE signals
rate HS and DE signals
1: Enable processing HS and DE signals
0: Disable HS tracking
1: Enable HS tracking
HTRACK
HS Tracking Enable
0: Disable VS tracking
1: Enable VS tracking
VTRACK
VS Tracking Enable
PRBS Type Select: PRBS type select (in HIBW
mode, set PRBS_TYPE = 0)
0: GMSL default style PRBS test
1: MAX9272 style PRBS
PRBS_TYPE
Maxim Integrated
│ 44
www.maximintegrated.com
MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
rceg (0x10)
BIT
7
6
5
4
3
2
1
0
RCEG_
BOUND
Field
RCEG_TYPE[1:0]
RCEG_ERR_NUM[3:0]
RCEG_EN
Reset
00b
0b
0001b
0b
Access Type
Write, Read
Write, Read
Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
00: Random errors
01: Short burst
1X: Long burst
RCEG_TYPE
7:6
5
Reverse-Channel Generated Error Type
Reverse-Channel Generated Error Bound-
ary:
Effective when RCEG_TYPE_ = 0X)
0: Errors are unbounded to symbols
1: Errors are bounded to symbols
RCEG_BOUND
0000: Value is 0.
0001: Value is 1
XXXX
Number of RCEG Errors Generated: Num-
ber of errors generated with each request
Effective when RCEG_TYPE_ = 0X)
RCEG_ERR_NUM
RCEG_EN
4:1
0
1111: Value is 15
0: Disable reverse-channel error generator
1: Enable reverse-channel error generator
Enable Reverse-Channel Error Generator
rceg2 (0x11)
BIT
7
6
5
4
3
2
1
0
Field
RCEG_ERR_RATE[3:0]
1111b
RCEG_LO_BST_PRB[1:0] RCEG_LO_BST_LEN[1:0]
Reset
00b
00b
Access Type
Write, Read
Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
0000: Rate is 2^-3
0001: Rate is 2^-4
0010: Rate is 2^-5
XXXX: Rate is 2^-(3 + value)
1110: Rate is 2^-17
Error-Generation Rate: Error-generation
rate in terms of bit time = 2^(RCEG_ERR_
RATE+3).
RCEG_ERR_RATE
7:4
Effective when RCEG_TYPE = 0X)
1111: Rate is 2^-18
00: 1/1024
01: 1/128
10: 1/32
11: 1/8
Long-Burst Error Probability: Effective
when
RCEG_TYPE = 10)
RCEG_LO_BST_PRB
3:2
1:0
00: continuous
Long-Burst Error Length: Long-burst error
length in terms of bit time
Effective when RCEG_TYPE = 10)
01: 128 (~150us)
10: 8192 (~9.83ms)
11: 1048576 (~1.26s)
RCEG_LO_BST_LEN
Maxim Integrated
│ 45
www.maximintegrated.com
MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
line_crc (0x12)
BIT
7
6
5
4
3
2
1
0
UNDER-
BST_DET_
EN
RCEG_
ERR_PER_
EN
CC_CRC_
ERR_EN
LINE_CRC_
EN
DIS_
RWAKE
MAX_RT_
ERR_EN
Field
LINE_CRC_LOC[1:0]
Reset
0b
1b
01b
0b
0b
1b
0b
Access Type Write, Read Write, Read
Write, Read
Write, Read Write, Read Write, Read Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
0: Disable underboost detection driving
Underboost-Detection Enable: Allow under- ERROR pin
UNDERBST_DET_EN
7
boost detection driving ERRORB pin
1: Enable underboost detection driving
ERROR pin
Control-Channel CRC ERR Enable: Enable
reporting of (CC_CRC_ERR_CNT -> 0) on the
ERRB pin
0: Disable reporting of errors on ERRB
1: Enable reporting of errors on ERRB
CC_CRC_ERR_EN
LINE_CRC_LOC
6
00: [1..4]
01: [5..8]
10: [9..12]
11: [13..16]
5:4
Video-Line CRC Insertion Location
0: Disable video-line CRC
1: Enable video-line CRC
LINE_CRC_EN
DIS_RWAKE
3
2
Video-Line CRC Enable
Disable Remote Wake-up
0: Enable remote wake-up
1: Disable remote wake-up
0: Disable maximum retransmission error on
the ERROR pin
1: Enable maximum retransmission error on
the ERROR pin
Enable Reflection of Maximum Retransmis-
sion Error: Enable reflection of maximum
retransmission error on the ERRORB pin
MAX_RT_ERR_EN
1
0
Periodic Error-Generation Enable: Effective 0: Disable periodic-error generator
when RCEG_TYPE = 0X) 1: Enable periodic-error generator
RCEG_ERR_PER_EN
Maxim Integrated
│ 46
www.maximintegrated.com
MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
ewm (0x13)
BIT
7
EWM_EN
1b
6
5
4
3
2
1
0
EWM_
MAN_TRG_
REQ
EWM_PER_
Field
EWM_MIN_THR[4:0]
MODE
Reset
1b
0b
01101b
Write 1 to
Set, Read
Access Type Write, Read Write, Read
Write, Read
BITFIELD
EWM_EN
BITS
DESCRIPTION
DECODE
0: Disable eye-width monitor
1: Enable eye-width monitor
7
Eye-Width Monitor Enable
0: Set eye-width monitor to use nonperi-
odic mode
1: Set eye-width monitor to use periodic
mode
EWM_PER_MODE
6
Eye-Width Monitor Periodic Mode Select
Eye-Width Manual Trigger Request: Rising
0: Do not trigger eye-width monitor.
EWM_MAN_TRG_REQ
5
edge of this register triggers eye-width monitor 1: Write 1 to this bit to manually trigger the
when not in periodic mode
eye-width monitor
00000: Eye-width threshold is disabled
XXXXX: (EWM_MIN_THR/64)% open eye
flags ERROR pin
Eye-Width Minimum Threshold: Eye-width
minimum threshold for flagging ERRORB pin
EWM_MIN_THR
4:0
aeq (0x14)
BIT
Field
Reset
7
AEQ_EN
1b
6
5
4
3
2
1
0
AEQ_PER_ AEQ_MAN_
MODE
EWM_PER_THR[4:0]
00000b
TRG_REQ
0b
0b
Write 1 to
Set, Read
Access Type Write, Read Write, Read
Write, Read
BITFIELD
AEQ_EN
BITS
DESCRIPTION
Adaptive Equalization Enable: Enable adap- 0: Disable AEQ
DECODE
7
tive equalization
1: Enable AEQ
Adaptive Equalization Periodic Mode
Select
0: Set AEQ to use nonperiodic mode
1: Set AEQ to use periodic mode
AEQ_PER_MODE
6
5
Adaptive Equalization Manual Fine-Tune
Request: Rising edge of this register triggers
AEQ fine tuning when not in periodic mode
0: Do not trigger AEQ fine tuning
1: Write 1 to this bit to manually trigger the
AEQ fine tuning
AEQ_MAN_TRG_REQ
00000: Eye-opening threshold is disabled
10000: 50% open-eye triggers fine-tune
operation
Eye-Width Trigger Threshold: Eye-width
threshold to trigger a fine tune operation
EWM_PER_THR
4:0
OTHER: Do Not Use
Maxim Integrated
│ 47
www.maximintegrated.com
MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
det_err (0x15)
BIT
7
6
5
4
3
2
1
0
0
0
Field
DET_ERR[7:0]
Reset
XXXXXXXXb
Read Only
Access Type
BITFIELD
BITS
DESCRIPTION
DECODE
00000000: Value is 0
00000001: Value is 1
XXXXXXXX
DET_ERR
7:0
Detected Error Counter
11111111: Value is 255.
prbs_err (0x16)
BIT
7
6
5
4
3
2
1
Field
PRBS_ERR[7:0]
XXXXXXXXb
Read Only
Reset
Access Type
BITFIELD
BITS
DESCRIPTION
DECODE
00000000: Value is 0
00000001: Value is 1
XXXXXXXX
PRBS_ERR
7:0
PRBS Error Counter
11111111: Value is 255
lf (0x17)
BIT
7
6
5
4
3
2
1
MAX_RT_
ERR
Field
RSVD
Xb
PRBS_OK
Xb
GPI_IN
Xb
LF_NEG[1:0]
LF_POS[1:0]
XXb
Reset
Xb
XXb
Read Clears
All
Access Type
Read Only
Read Only
Read Only
Read Only
Read Only
BITFIELD
BITS
DESCRIPTION
Reserved: Do not change from default value
DECODE
RSVD
7
X: Reserved
Maximum Retransmission Error Bit: Goes high if
packet control channel hits maximum retransmission
limit (8 retries); cleared when read
0: No control-channel retransmission error
1: Control-channel retransmission maximum
limit reached
MAX_RT_ERR
6
PRBS OK: MAX9271/MAX9273-compatible PRBS
0: No MAX9271/MAX9273-compatible PRBS
test for link is terminated normally; check PRBS_ERR test completed
register for the PRBS success; for other SerDes read 1: MAX9271/MAX9273-compatible PRBS test
PRBS_OK
GPI_IN
5
4
PRBS_ERR registers
completed normally
0: GPI is input low
1: GPI is input high
GPI Pin Level
00: Short to battery detected
01: Short to ground detected
10: No faults detected
Line Fault: Line-fault status of the indicated input
LF_POS -> LMN0
LF_NEG -> LMN1
LF_NEG
3:2
11: Open cable detected
00: Short to battery detected
01: Short to ground detected
10: No faults detected
Line Fault: Line-fault status of the indicated input
LF_POS -> LMN0
LF_NEG -> LMN1
LF_POS
1:0
11: Open cable detected
Maxim Integrated
│ 48
www.maximintegrated.com
MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
rsvd_18 (0x18)
BIT
7
6
5
4
3
2
1
0
Field
RSVD[7:0]
XXXXXXXXb
Read Only
Reset
Access Type
BITFIELD
BITS
7:0
DESCRIPTION
DECODE
RSVD
Reserved: Do not change from default value
XXXXXXXX: Reserved
cc_crc_errcnt (0x19)
BIT
Field
7
6
5
4
3
2
1
0
CC_CRC_ERRCNT[7:0]
XXXXXXXXb
Reset
Access Type
Read Only
BITFIELD
BITS
DESCRIPTION
DECODE
00000000: Value is 0
00000001: Value is 1
XXXXXXXX
Packet-Based Control-Channel CRC Error
Counter
CC_CRC_ERRCNT
7:0
11111111: Value is 255
rceg_err_cnt (0x1A)
BIT
Field
7
6
5
4
3
2
1
0
RCEG_ERR_CNT[7:0]
XXXXXXXXb
Reset
Access Type
Read Only
BITFIELD
BITS
DESCRIPTION
DECODE
00000000: Value is 0
00000001: Value is 1.
XXXXXXXX
RCEG_ERR_CNT
7:0
Control-Channel Number of Generated Errors
11111111: Value is 255
Maxim Integrated
│ 49
www.maximintegrated.com
MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
i2csel (0x1B)
BIT
7
6
5
4
3
2
1
RSVD
Xb
0
RSVD
Xb
LINE_CRC_
ERR
Field
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
I2CSEL
Xb
Reset
Xb
Read Clears
All
Access Type Write, Read Write, Read Write, Read Write, Read
Read Only
Read Only
Read Only
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
7
6
5
4
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
RSVD
RSVD
RSVD
0: Reserved
0: Reserved
0: Reserved
0: Low-I2CSEL pin detected (UART)
1: High-I2CSEL pin detected (I2C)
I2CSEL
3
I2CSEL Pin Level: Detected I2CSEL pin level
CRC-Error Bit: Goes high if received video line
has CRC mismatch and latched; cleared to 0
when read
LINE_CRC_
ERR
0: No line CRC error detected
1: Line CRC error detected
2
RSVD
RSVD
1
0
Reserved: Do not change from default value
Reserved: Do not change from default value
X: Reserved
X: Reserved
ewm_eye_width (0x1C)
BIT
Field
Reset
7
6
5
4
3
2
1
0
RSVD
0b
RSVD
0b
EOM_EYE_WIDTH[5:0]
XXXXXXb
Access Type Write, Read Write, Read
Read Only
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
7
6
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
0: Reserved
RSVD
000000: Width is 0%
000001: Width is 1/63 x 100%
111111: Width is 63/63 x 100%
Measured Eye Opening: Opening width =
EOM_EYE_WIDTH / 63 * 100%
EOM_EYE_WIDTH
5:0
Maxim Integrated
│ 50
www.maximintegrated.com
MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
aeq_bst (0x1D)
BIT
7
6
5
4
3
2
1
0
UNDER-
BOOST_
DET
Field
RSVD
0b
RSVD
0b
RSVD
0b
AEQ_BST[3:0]
Reset
Xb
XXXXb
Access Type Write, Read Write, Read Write, Read
Read Only
Read Only
BITFIELD
BITS
DESCRIPTION
DECODE
RSVD
RSVD
RSVD
7
6
5
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
0: Reserved
0: Reserved
Underboost Detected: '1' indicates that an
underboost is detected when the AEQ is at the
maximum setting
0: Normal operation
1: Underboost (at maximum AEQ gain)
detected
UNDERBOOST_DET
4
0000: 1.6dB EQ setting
0001: 2.1dB EQ setting
0010: 2.8dB EQ setting
0011: 3.5dB EQ setting
0100: 4.3dB EQ setting
0101: 5.2dB EQ setting
0110: 6.3dB EQ setting
0111: 7.3dB EQ setting
1000: 8.5dB EQ setting
1001: 9.7dB EQ setting
1010: 11dB EQ setting
1011: 12.2dB EQ setting
11XX: Reserved
Adaptive Equalizer Boost Value: Selected
adaptive equalizer value; settings correspond to
gain at 750MHz
AEQ_BST
3:0
id (0x1E)
BIT
7
6
5
4
3
2
1
0
Field
ID[7:0]
Reset
XXXXXXXXb
Read Only
Access Type
BITFIELD
BITS
DESCRIPTION
DECODE
Device ID: 8-bit value depends on the GMSL
device attached
ID
7:0
01001010: MAX96700
Maxim Integrated
│ 51
www.maximintegrated.com
MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
revision (0x1F)
BIT
Field
7
6
5
4
3
2
1
0
RSVD
0b
RSVD
0b
RSVD
0b
HDCPCAP
Xb
REVISION[3:0]
Reset
XXXXb
Access Type Write, Read Write, Read Write, Read
Read Only
Read Only
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
7
6
5
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
0: Reserved
0: Reserved
RSVD
RSVD
0: Device does not have HDCP
1: Device is HDCP capable
HDCPCAP
4
HDCP Capability: '1' = HDCP capable
0000: Value is 0
0001: Value is 1
1111: Value is 15
REVISION
3:0
Device Revision
crcvalue (0x20 to 0x23)
BIT
Field
7
6
5
4
3
2
1
0
CRCVALUE[7:0]
XXXXXXXXb
Read Only
Reset
Access Type
BITFIELD
BITS
DESCRIPTION
DECODE
CRC Value: CRC output for latest line;
CRC_VALUE_3 to CRC_VALUE_0 represents
CRC[31:0].
00000000: Value is 0
00000001: Value is 1
11111111: Value is 255
CRCVALUE
7:0
crossbar (0x65 to 0x6B)
BIT
Field
7
6
5
4
3
2
1
0
CROSSBAR_N[3:0]
XXXXb
CROSSBAR_N+1[3:0]
XXXXb
Reset
Access Type
Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
Crossbar Setting: CROSSBAR selects the internal
signal to connect to the output pin, DOUT_.
Register crossbar_(N) contains settings for two
outputs, with CROSSBAR_(N) at D[7:4] and
CROSSBAR_(N+1) at D[3:0]. Default settings for
CROSSBAR(N) connects internal signal D(N) to its
respective DOUT(N) pin.
0000: Connect D0 to output
0001: Connect D1 to output
:: :
1101: Connect D13 to output
1110: Force output low
1111: Force output high
CROSSBAR_N
7:4
Crossbar Setting: CROSSBAR selects the internal
signal to connect to the output pin, DOUT_.
Register crossbar_(N) contains settings for two
outputs, with CROSSBAR_(N) at D[7:4] and
CROSSBAR_(N+1) at D[3:0]. Default settings for
CROSSBAR(N) connects internal signal D(N) to its
respective DOUT(N) pin.
0000: Connect D0 to output
0001: Connect D1 to output
:: :
1101: Connect D13 to output
1110: Force output low
1111: Force output high
CROSSBAR_N+1
3:0
Maxim Integrated
│ 52
www.maximintegrated.com
MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
rsvd_96 (0x96)
BIT
7
6
5
4
3
2
1
0
Field
RSVD[1:0]
01b
RSVD[1:0]
01b
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
1b
Reset
Access Type
Write, Read
Write, Read
Write, Read Write, Read Write, Read Write, Read
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
01: Reserved
7:6
5:4
3
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
RSVD
01: Reserved
RSVD
0: Reserved
RSVD
2
0: Reserved
RSVD
1
0: Reserved
RSVD
0
1: Reserved
rev_fast (0x97)
BIT
7
6
5
4
3
2
1
0
Field
REV_FAST
0b
RSVD
0b
RSVD[5:0]
100010b
Reset
Access Type Write, Read Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
REV_
FAST
0: Disable reverse-channel fast mode
1: Enable reverse-channel fast mode
7
Reverse-Channel Fast Mode
RSVD
RSVD
6
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
5:0
100010: Reserved
rsvd_98 (0x98)
BIT
Field
7
6
5
4
3
2
1
0
RSVD
1b
RSVD
0b
RSVD[5:0]
011010b
Reset
Access Type Write, Read Write, Read
Write, Read
BITFIELD
RSVD
BITS
7
DESCRIPTION
DECODE
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
1: Reserved
0: Reserved
RSVD
6
RSVD
5:0
011010: Reserved
Maxim Integrated
│ 53
www.maximintegrated.com
MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
rsvd_99 (0x99)
BIT
Field
7
6
5
4
3
2
1
0
RSVD
0b
RSVD
1b
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
Reset
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
BITS
DESCRIPTION
DECODE
7
6
5
4
3
2
1
0
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
1: Reserved
0: Reserved
0: Reserved
0: Reserved
0: Reserved
0: Reserved
0: Reserved
rsvd_9a (0x9A)
BIT
Field
7
6
5
4
3
2
1
0
RSVD
0b
RSVD
0b
RSVD
0b
RSVD[1:0]
10b
RSVD[2:0]
010b
Reset
Access Type Write, Read Write, Read
Write, Read
Write, Read
DECODE
Write, Read
BITFIELD
RSVD
BITS
7
DESCRIPTION
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
RSVD
6
0: Reserved
10: Reserved
010: Reserved
0: Reserved
RSVD
5:4
3:1
0
RSVD
RSVD
Maxim Integrated
│ 54
www.maximintegrated.com
MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
rsvd_9b (0x9B)
BIT
Field
7
6
5
4
3
2
1
0
0
0
RSVD
0b
RSVD[1:0]
01b
RSVD[2:0]
001b
RSVD[1:0]
10b
Reset
Access Type Write, Read
Write, Read
Write, Read
Write, Read
BITFIELD
RSVD
BITS
7
DESCRIPTION
DECODE
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
RSVD
6:5
4:2
1:0
01: Reserved
001: Reserved
10: Reserved
RSVD
RSVD
rsvd_9c (0x9C)
BIT
Field
7
6
5
4
RSVD
1b
3
2
1
RSVD
0b
RSVD[1:0]
10b
RSVD[3:0]
Reset
0100b
Access Type Write, Read
Write, Read
Write, Read
Write, Read
BITFIELD
RSVD
BITS
7
DESCRIPTION
DECODE
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
10: Reserved
1: Reserved
RSVD
6:5
4
RSVD
RSVD
3:0
0100: Reserved
rsvd_9d (0x9D)
BIT
Field
7
6
5
4
3
SOFT_PD
0b
2
1
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
1b
RSVD
01b
RSVD
0b
RSVD
0b
Reset
Write 1 to
Set, Read
Access Type Write, Read Write, Read Write, Read Write, Read
Write, Read Write, Read Write, Read
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
7
6
5
4
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
RSVD
0: Reserved
1: Reserved
01: Reserved
RSVD
RSVD
0: Normal operation
1: Reset the device
SOFT_PD
3
Reserved: Do not change from default value
RSVD
RSVD
RSVD
2
1
0
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
0: Reserved
0: Reserved
Maxim Integrated
│ 55
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
rsvd_9e (0x9E)
BIT
Field
7
6
5
4
3
2
1
0
RSVD
1b
RSVD[1:0]
10b
RSVD[2:0]
010b
RSVD
0b
RSVD
0b
Reset
Access Type Write, Read
Write, Read
Write, Read
Write, Read Write, Read
DECODE
BITFIELD
RSVD
BITS
7
DESCRIPTION
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
1: Reserved
RSVD
6:5
4:2
1
10: Reserved
010: Reserved
0: Reserved
0: Reserved
RSVD
RSVD
RSVD
0
rsvd_9f (0x9F)
BIT
Field
7
6
5
4
3
2
1
0
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
HPFTUNE[1:0]
01b
Reset
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read
Write, Read
Write, Read
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
7
6
5
4
3
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
0: Reserved
0: Reserved
0: Reserved
0: Reserved
RSVD
RSVD
RSVD
RSVD
00: 7.5MHz cutoff frequency
01: 3.75MHz cutoff frequency
10: 2.5MHz cutoff frequency
11: 1.87MHz cutoff frequency
HPFTUNE
2:1
Equalizer High-Pass Filter Cutoff Frequency
RSVD
0
Reserved: Do not change from default value
0: Reserved
rsvd_a0 (0xA0)
BIT
Field
7
6
5
4
3
2
1
0
RSVD
1b
RSVD
0b
RSVD[1:0]
10b
RSVD[3:0]
1110b
Reset
Access Type Write, Read Write, Read
Write, Read
Write, Read
BITFIELD
RSVD
BITS
7
DESCRIPTION
DECODE
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
1: Reserved
0: Reserved
10: Reserved
RSVD
6
RSVD
5:4
3:0
RSVD
1110: Reserved
Maxim Integrated
│ 56
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
rsvd_a1(0xA1)
BIT
7
6
5
4
3
2
1
0
Field
RSVD[2:0]
010b
RSVD[4:0]
00100b
Reset
Access Type
Write, Read
Write, Read
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
7:5
4:0
Reserved: Do not change from default value
Reserved: Do not change from default value
010: Reserved
RSVD
00100: Reserved
rsvd_a2 (0xA2)
BIT
7
6
5
4
3
2
1
0
Field
RSVD[7:0]
00100000b
Write, Read
Reset
Access Type
BITFIELD
BITS
7:0
DESCRIPTION
DECODE
00100000: Reserved
RSVD
Reserved: Do not change from default value
rsvd_a3 (0xA3)
BIT
7
6
5
4
3
2
1
0
Field
RSVD[3:0]
0110b
RSVD[3:0]
Reset
1011b
Access Type
Write, Read
Write, Read
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
7:4
3:0
Reserved: Do not change from default value
Reserved: Do not change from default value
0110: Reserved
1011: Reserved
RSVD
rsvd_a4 (0xA4)
BIT
7
6
5
4
3
2
1
0
Field
RSVD[2:0]
101b
RSVD
1b
RSVD
0b
RSVD
1b
RSVD[1:0]
01b
Reset
Access Type
Write, Read
Write, Read Write, Read Write, Read
Write, Read
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
7:5
4
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
101: Reserved
1: Reserved
0: Reserved
1: Reserved
01: Reserved
RSVD
RSVD
3
RSVD
2
RSVD
1:0
Maxim Integrated
│ 57
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
rsvd_a5 (0xA5)
BIT
7
6
5
4
3
2
1
0
Field
RSVD[3:0]
1100b
RSVD[1:0]
11b
RSVD[1:0]
01b
Reset
Access Type
Write, Read
Write, Read
Write, Read
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
7:4
3:2
1:0
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
1100: Reserved
11: Reserved
01: Reserved
RSVD
RSVD
rsvd_a6 (0xA6)
BIT
Field
7
6
5
4
3
2
1
0
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
RSVD[1:0]
00b
RSVD[1:0]
01b
Reset
Access Type Write, Read Write, Read Write, Read Write, Read
Write, Read
Write, Read
BITFIELD
RSVD
BITS
7
DESCRIPTION
DECODE
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
0: Reserved
0: Reserved
0: Reserved
00: Reserved
01: Reserved
RSVD
6
RSVD
5
RSVD
4
RSVD
3:2
1:0
RSVD
rsvd_c9 (0xC9)
BIT
7
6
5
4
3
2
1
0
Field
RSVD[7:0]
XXXXXXXXb
Read Only
Reset
Access Type
BITFIELD
BITS
7:0
DESCRIPTION
DECODE
RSVD
Reserved: Do not change from default value
XXXXXXXX: Reserved
Maxim Integrated
│ 58
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
rsvd_ca (0xCA)
BIT
Field
7
6
RSVD
Xb
5
RSVD
Xb
4
3
2
RSVD
Xb
1
RSVD
Xb
0
RSVD
Xb
RSVD
0b
RSVD[1:0]
XXb
Reset
Access Type Write, Read
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
BITFIELD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
BITS
DESCRIPTION
DECODE
7
6
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
X: Reserved
X: Reserved
XX: Reserved
X: Reserved
X: Reserved
X: Reserved
5
4:3
2
1
0
cc_locked (0xCB)
BIT
7
6
5
4
3
2
1
0
CC_
WBLOCK_
LOST
CC_
WBLOCK
REM_
CCLOCK
Field
RSVD
RSVD
RSVD
RSVD
RSVD
Reset
Xb
Xb
Xb
Xb
Xb
Xb
Xb
0b
Access Type
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Write, Read
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
7
6
5
4
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
X: Reserved
RSVD
X: Reserved
X: Reserved
X: Reserved
RSVD
RSVD
CC_
WBLOCK
Control-Channel Word Boundary Locked: '1'
indicates locked.
0: Control-channel word boundary not locked.
1: Control-channel word boundary locked.
3
2
REM_
CCLOCK
Remote-Side CC Locked: '1' indicates remote
side CC locked.
0: Remote-side control channel not locked.
1: Remote-side control channel locked.
CC_
WBLOCK_
LOST
Word-Boundary Lock Lost: This bit is set to 1
when reverse control-channel word boundary loses
lock. It is cleared when read.
0: Normal operation
1: Control-channel word boundary lost lock.
1
0
RSVD
Reserved: Do not change from default value
0: Reserved
Maxim Integrated
│ 59
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
rsvd_cc (0xCC)
BIT
Field
7
6
5
4
3
2
1
0
RSVD
0b
RSVD[6:0]
XXXXXXXb
Read Only
Reset
Access Type Write, Read
BITFIELD
RSVD
BITS
7
DESCRIPTION
DECODE
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
XXXXXXX: Reserved
RSVD
6:0
rsvd_cd (0xCD)
BIT
Field
7
6
5
4
3
2
1
0
RSVD
0b
RSVD[6:0]
XXXXXXXb
Read Only
Reset
Access Type Write, Read
BITFIELD
RSVD
BITS
7
DESCRIPTION
DECODE
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
XXXXXXX: Reserved
RSVD
6:0
rsvd_fd (0xFD)
BIT
7
6
5
4
3
2
1
0
Field
RSVD[7:0]
0b
Reset
Access Type
Write, Read
BITFIELD
BITS
7:0
DESCRIPTION
DECODE
RSVD
Reserved: Do not change from default value
0: Reserved
rsvd_fe (0xFE)
BIT
7
6
5
4
3
2
1
0
Field
RSVD[3:0]
0b
RSVD[3:0]
Reset
0b
Access Type
Write, Read
Write, Read
BITFIELD
RSVD
BITS
7:4
DESCRIPTION
DECODE
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
0: Reserved
RSVD
3:0
Maxim Integrated
│ 60
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
rsvd_ff (0xFF)
BIT
Field
7
6
5
4
3
2
1
0
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
RSVD[3:0]
XXXXb
Reset
Access Type Write, Read Write, Read Write, Read Write, Read
Read Only
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
7
6
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
0: Reserved
0: Reserved
0: Reserved
RSVD
RSVD
5
RSVD
4
RSVD
3:0
XXXX: Reserved
Maxim Integrated
│ 61
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
Bus Data Rates
Applications Information
The bus data rate depends on the settings BWS and
DBL. Table 4 lists the available PCLK rates available for
different bus-width settings. For lower PCLK rates, set
DBL = 0 (if DBL = 1 in both the serializer and deserializer).
Parallel Interface
The CMOS parallel-interface data width is programmable
and depends on the application. Using a larger width
(BWS = 1) results in a lower-pixel clock rate, while a
smaller width (BWS = 0) allows a higher-pixel clock rate.
Crossbar Switch
By default, the crossbar switch connects the serializer
input pins DIN_ and HS/VS (when HV encoding is used)
to the corresponding deserializer output pins DOUT_ and
HS/VS when DBL of the serializer and deserializer match.
When there is a DBL mismatch use Tables 5 - 7 to map the
serial bits to the crossbar inputs. Reprogram the crossbar
switch when changing the output pin assignments.
Bus Data Width
The bus data width depends on the selected modes. The
available bus width is less when using error detection or
when in double mode (DBL = 1). Table 3 shows the avail-
able bit widths and default mapping for various modes.
Table 3. Output-Data Width Selection
Crossbar Switch Programming
REGISTER BIT SETTINGS
Each output pin can be assigned any of the 14 DOUT
signals. Multiple outputs can share the same input. To force
an output low, and ignore the input, set CROSSBAR_ bit
= 1110. To force an output high set CROSSBAR_ = 1111.
OUTPUT MAPPING
PXL_
CRC
DBL BWS HIBW
HVEN
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
—
—
—
—
1
1
1
0
DOUT11:0, HS, VS
DOUT11:0
1
Recommended Crossbar Switch Programming
Procedure
0
1
DOUT11:0*, HS, VS
DOUT13:0*
The following procedure programs the crossbar switch to
reassign input/output pin locations:
0
0
1
—
—
1
DOUT8:0, HS, VS
DOUT11:0, HS, VS
DOUT7:0, HS, VS
DOUT7:0
1) For the crossbar output equivalent of DOUT0 (XBO0)
select which pin to map (e.g., DOUT4 -> XBI4).
1
0
0
1
2) Set the crossbar bits (CROSSBAR0) to the desired
selected mapped input (e.g., CROSSBAR0 = 0100).
0
1
0
0
0
1
DOUT10:0, HS, VS
DOUT10:0
3) Repeat for the other crossbar outputs.
0
0
0
—
—
—
—
1
1
1
DOUT11:0*, HS, VS
DOUT13:0*
Table 4. Data-Rate Selection Table
1
0
DRS DBL BWS HIBW
PCLK RANGE (MHZ)
25 to 87
0
1
DOUT11:0*, HS, VS
DOUT13:0*
0
0
1
1
1
0
0
0
0
0
1
0
0
1
0
0
1
0
0
0
1
0
0
1
0
0
0
0
33.3 to 116
73.3 to 116
12.5 to 43.5
16.7 to 58
—
1
—
1
DOUT11:0*, HS, VS
DOUT11:0*, HS, VS
DOUT13:0*
0
0
0
0
1
0
0
0
0
1
DOUT11:0*, HS, VS
DOUT13:0*
0
36.7 to 58
0
0
0
1*
1*
6.25 to 12.5
8.33 to 16.7
*The bit width is limited by the number of available outputs.
*Use DRS = 1 with legacy devices only (MAX92XX).
Maxim Integrated
│ 62
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
Table 5. Output Map (DBL = 0 or DBL = 1, First Word)
BIT SETTING
OUTPUT BITS (FIRST WORD)
A9 A10 A11 A12 A13
DB HV BW HB CR DE SC* A0
A1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
A3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
A4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
A5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
A6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
A7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
Z
7
7
7
7
7
7
7
7
A8
8
8
8
8
8
8
8
8
8
Z
8
8
8
8
Z
Z
8
8
8
8
8
8
8
8
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
X
X
X
X
X
X
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
X
X
X
X
X
X
X
X
0
1
0
1
0
0
1
1
0
0
0
1
0
0
1
1
0
1
X
1
1
0
0
1
X
X
X
X
0
1
0
1
1
1
0
X
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
9
9
9
9
9
9
9
9
9
Z
9
9
9
9
Z
Z
9
9
9
9
9
9
Z
Z
10
10
10
10
10
10
10
10
10
Z
11
13
11
13
11
11
11
D
14
14
12
H
15
15
13
V
2
1
2
H
V
1,2
0
H
V
H
V
0
H
V
3
Z
Z
Z
3
Z
Z
Z
3
10
10
10
Z
11
11
Z
12
Z
13
Z
3
1,2
1,2
1,2
1,2
1
HL
HL
HL
HL
HL
HL
HL
HL
HL
HL
HL
HL
VL
VL
VL
VL
VL
VL
VL
VL
VL
VL
VL
VL
10
Z
Z
Z
7
10
10
10
10
10
10
Z
13
11
11
11
11
DL
Z
2
1,2
1,2
0
0
0
0
Z
DL
Maxim Integrated
│ 63
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
Table 6. Output Map (DBL = 1, Second Word)
BIT SETTING
OUTPUT BITS (SECOND WORD)
DB HV BW HB CR DE SC* B0
B1
12
9
B2
13
10
17
14
13
13
10
10
17
17
17
14
14
14
11
11
B3
14
11
18
15
14
14
11
11
18
18
18
15
15
15
12
12
B4
15
12
19
16
15
15
12
12
19
19
19
16
16
16
13
13
B5
16
13
20
17
16
16
13
13
20
20
20
17
17
17
14
14
B6
17
14
21
18
17
17
14
14
21
21
21
18
18
18
15
15
B7
18
15
22
19
18
18
15
Z
B8
19
Z
B9 B10 B11 B12 B13
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
0
1
0
0
1
1
0
0
0
1
0
0
1
1
X
X
X
X
0
1
0
1
1
1
0
X
0
1
0
1
3
3
11
8
20
Z
21
Z
Z
Z
Z
Z
Z
Z
3
15
12
11
11
8
16
13
12
12
9
23
20
19
19
Z
24
21
20
20
Z
25
22
21
Z
26
23
Z
27
Z
28
Z
3
1,2
1,2
1,2
1,2
1
HH VH
HH VH
HH VH
HH VH
HH VH
HH VH
HH VH
HH VH
HH VH
21
Z
Z
8
9
Z
Z
Z
15
28
26
26
23
26
15
15
15
12
12
12
9
16
16
16
13
13
13
10
10
22
22
22
19
19
19
16
16
23
23
23
20
20
20
17
17
24
24
24
21
24
24
Z
25
25
25
22
25
25
Z
2
1,2
1,2
0
0
DH HH VH
HH VH
DH HH VH
0
Z
0
9
Z
Z
Table 7. Legend
BIT SETTINGS
MAPPED SYNC OUTPUTS
DB
HV
BW
HB
CR
DE
SC*
X
Double mode bit DBL
H/V Encoding bit HVEN
BWS bit
H
HSYNC ( when DBL = 0)
VSYNC ( when DBL = 0)
DE ( when DBL = 0)
V
D
HIBW bit
HH
VH
DH
HL
VL
DL
#
HSYNC (high word, DBL = 1)
VSYNC (high word, DBL = 1)
DE (high word, DBL = 1)
HSYNC (low word, DBL = 1)
VSYNC (low word, DBL = 1)
DE (low word, DBL = 1)
Serial Bits
PXL_CRC bit
DEEN
HV_SRC (dec)
1 or 0
BIT COLOR
Sync Bits
Output on first word
Output on second word
Zero
Z
Zero
*HV_SRC is automatically set by default. MAX96705 mode automatically sets HV_SRC to 0, 1, or 3 according to the other bit set-
tings above. MAX96707 mode automatically sets HV_SRC to 0, 2, or 3 according to the other bit settings above.
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14-Bit GMSL Deserializer
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Cascaded/Parallel Devices
Control-Channel Interfaces
GMSL supports cascaded and parallel devices con-
2
I C
2
nected through I C. When cascading or using parallel
2
Set I2CSEL = 1 to configure the control channel for I C-
2
links, all I C commands are forwarded to all links. Each
2
to-I C mode. In this mode, the control channel forwards
link attempts to hold the control channel until it receives
an acknowledge/non-acknowledge from the remote side
device. It is important to keep the control channel active
between links in order to prevent timeout. If a link is
unused, keep the control channel clear by turning on the
2
I C commands from the microcontroller side to the other
2
side of the GMSL link. The remote device acts as an I C
master to the other peripherals connected to the remote
side device. I C-to-I C mode uses clock stretching to hold
the microcontroller until the data and the acknowledge/
no-acknowledge have been sent across the link.
2
2
2
configuration link, disconnecting the I C lines, or power-
ing down the unused device.
2
I C Bit Rate
Dual μC Control
2
The I C interface accepts bit rates from 9.6kbps to
1Mbps. The local I C rate is set by the microcontroller.
The remote I C rate is set by the remote device. By
default the control channel is set up for a 400kbps-to-I C
bit rate. Program the I2C_MSTBT and SLV_SH bits (reg-
ister 0x0D) to match the desired microcontroller I C rate.
Most systems use a single microcontroller; however, µCs
can reside on each side simultaneously and trade off run-
ning the control channel. Contention occurs if both µCs
attempt to use the control channel at the same time. It is
up to the user to prevent this contention by implementing
a higher-level protocol. In addition, the control channel
2
2
2
2
2
Software Programming of the Device Addresses
does not provide arbitration between I C masters on both
sides of the link. An acknowledge frame is not generated
when communication fails due to contention. If communi-
cation across the serial link is not required, the µCs can
disable the forward and reverse control channel using
the FWDCCEN and REVCCEN bits (0x04, D[1:0]) in the
serializer/deserializer. Communication across the serial
link is stopped and contention between µCs cannot occur.
The serializer and deserializer have programmable device
addresses. This allows multiple GMSL devices, along with
I C peripherals, to coexist on the same control channel.
2
The serializer device address is in register 0x00 of each
device, while the deserializer device address is in register
0x01 of each device. To change a device address, first
write to the device whose address changes (register 0x00
of the serializer for serializer device address change, or
register 0x01 of the deserializer for deserializer device
address change). Then write the same address into the
corresponding register on the other device (register 0x00
of the deserializer for serializer device address change,
or register 0x01 of the serializer for deserializer device
address change).
2
Packet-Based Control-Channel I C
2
Packet-based control-channel I C is not enabled by
2
default. To enable packet-based I C, set PKTCC_EN =
1 in the deserializer and wait 2ms. During this time, the
deserializer automatically enables packet-based control
channel in the serializer.
The internal bit rate used by the packet control channel
2
I C Address Translation
2
does not depend on the I C bit rate used by the host µC.
2
The device supports I C address translation for up to
The raw forward control channel bit rate is the same as
two device addresses. Use address translation to assign
unique device addresses to peripherals with limited
I C addresses. Source addresses (address to translate
from) are stored in registers 0x09 and 0x0B. Destination
addresses (address to translate to) are stored in registers
0x0A and 0x0C.
PCLK (e.g., 10Mbps when f
is 10MHz). The raw
PCLK
reverse-channel bit rate is 850kbps typically (425kbps
when HIM = 1). The packet length is 9 bits + the CRC bit
length, and affects the overall symbol rate. A larger CRC
bit length lowers the overall symbol rate.
2
The latency of GPI/GPO transitions depend on the packet
2
length. The latency of an I C transmission across the
Configuration Blocking
control channel depends on both the incoming/outgoing
SCL rate and the control-channel symbol rate. Sending a
single byte from serializer to deserializer has an additional
delay of 4 SCL bit times + 1.5 symbols. Sending a single
byte from deserializer to serializer has an additional delay
of 5 SCL bit times + 1.5 Symbols.
The device can block changes to its registers. Set
CFGBLOCK to make all registers read only. Once set, the
registers remain blocked until the supplies are removed or
until PWDNB is low.
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14-Bit GMSL Deserializer
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UART
UART Timing
Set I2CSEL = 0 to configure the control channel for UART
or UART to I C. In this mode, the control channel for-
wards UART commands from the microcontroller side to
In base mode, the UART idles high (through a pullup
resistor). Each GMSL-UART byte consists of a START
bit, 8 data bits, an even-parity bit and a stop bit (Figure
20). Keep the idle time between bytes of the same UART
packet to less than 4 bit times. The GMSL-UART protocol
is listed in Figure 21. A write packet consists of a SYNC
byte (Figure 22). Device address byte, Starting register
address byte, number of bytes to write, and the data
bytes. The slave device responds with an acknowledge
byte (Figure 23) if the write was successful. A Read pack-
et consists of a SYNC byte, Device address byte, Starting
register address byte, and number of bytes to read. The
slave device responds with an acknowledge byte and the
read data bytes.
2
the other side of the GMSL link. When INTTYPE = 00, the
2
remote device acts as an I C master to the other periph-
2
erals connected to the remote side device. UART-to-I C
mode does not support devices that use clock stretching.
Base Mode
In base mode, UART packets control the serializer, dese-
rializer and attached peripherals.
1 UART FRAME
START
D0
D1
D2
D3
D4
D5
D6
D7
PARITY*
STOP
FRAME 1
FRAME 2
FRAME 3
STOP
START
STOP
START
*BASE MODE USES EVEN PARITY
Figure 20. GMSL-UART Data Format for Base Mode
WRITE DATA FORMAT
DEV ADDR + R/W REG ADDR NUMBER OF BYTES BYTE 1
SYNC
SYNC
BYTE N
ACK
MASTER READS FROM SLAVE
MASTER WRITES TO SLAVE
READ DATA FORMAT
DEV ADDR + R/W REG ADDR NUMBER OF BYTES
MASTER WRITES TO SLAVE
ACK
BYTE 1
BYTE N
MASTER READS FROM SLAVE
Figure 21. GMSL-UART Protocol for Base Mode
D0
1
D1
0
D2
0
D3
1
D4
1
D5
1
D6
1
D7
0
D0
1
D1
1
D2
0
D3
0
D4
0
D5
0
D6
1
D7
1
START
PARITY STOP
START
PARITY STOP
Figure 23. ACK Byte (0xC3)
Figure 22. SYNC Byte (0x79)
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2
There are two possible methods the devices use to
UART-to-I C Conversion
2
convert UART to I C. In the first method, I2CMETHOD =
When using the UART control channel, the remote-side
2
0. The register address is sent with the I C communica-
2
device can communicate to I C peripherals through
tion (Figure 24). For devices that do not use a register
address (such as the MAX7324) set I2CMETHOD = 1
and send a dummy byte in place of the register address
(Figure 25). In this method, the remote device omits send-
ing the register address.
2
UART-to-I C conversion. Set the INTTYPE bits in the
2
remote side device to "00" to activate UART-to-I C
conversion. The converted I C bit rate is the same as
the incoming UART bit rate. I C peripherals must not use
clock stretching in order to be compatible with UART-
2
2
2
to-I C conversion.
2
UART-TO-I C CONVERSION OF WRITE PACKET (I2CMETHOD = 0)
SERIALIZER/DESERIALIZER
11
µC
11
11
11
11
11
11
SYNC FRAME
DEVICE ID + WR
REGISTER ADDRESS NUMBER OF BYTES
DATA 0
DATA N
ACK FRAME
SERIALIZER/DESERIALIZER
PERIPHERAL
1
7
1
1
8
1
8
1
8
1
1
S
DEV ID
W
A
REG ADDR
A
DATA 0
A
DATA N
A
P
2
UART-TO-I C CONVERSION OF READ PACKET (I2CMETHOD = 0)
SERIALIZER/DESERIALIZER
11
µC
11
11
11
11
ACK FRAME
11
DATA 0
11
DATA N
SYNC FRAME
DEVICE ID + RD
REGISTER ADDRESS NUMBER OF BYTES
SERIALIZER/DESERIALIZER
PERIPHERAL
1
7
1
1
8
1
1
7
1
1
8
1
8
1
1
S
DEV ID
W
A
REG ADDR
A
S
DEV ID
R
A
DATA 0
A
DATA N
A
P
S: START
P: STOP
A: ACKNOWLEDGE
: MASTER TO SLAVE
: SLAVE TO MASTER
2
Figure 24. Format Conversion Between GMSL UART and I C with Register Address (I2CMETHOD = 0)
2
UART-TO-I C CONVERSION OF WRITE PACKET (I2CMETHOD = 1)
µC
SERIALIZER/DESERIALIZER
11
SYNC FRAME
11
11
11
11
DATA 0
11
DATA N
11
ACK FRAME
DEVICE ID + WR
REGISTER ADDRESS NUMBER OF BYTES
SERIALIZER/DESERIALIZER
PERIPHERAL
1
7
1
1
8
1
8
1
1
S
DEV ID
W
A
DATA 0
A
DATA N
A
P
2
UART-TO-I C CONVERSION OF READ PACKET (I2CMETHOD = 1)
µC
SERIALIZER/DESERIALIZER
11
11
11
11
11
11
DATA 0
11
DATA N
SYNC FRAME
DEVICE ID + RD
REGISTER ADDRESS NUMBER OF BYTES
ACK FRAME
SERIALIZER/DESERIALIZER
PERIPHERAL
1
7
1
1
8
1
8
1
1
S
DEV ID
R
A
DATA 0
A
DATA N
A
P
MASTER TO SLAVE
SLAVE TO MASTER
S: START
P: STOP A: ACKNOWLEDGE
2
Figure 25. Format Conversion Between GMSL UART and I C without Register Address (I2CMETHOD = 1)
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14-Bit GMSL Deserializer
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Table 8. Default-Device Address
D7
D6
D5
D4
D3
D2
D1
D0
1
ADD3
ADD2
1
ADD1
ADD0
0
R/W
Note: ADD[3:0] pin settings latched at power-up.
UART Bypass Mode
Table 9. Cable-Equalizer Boost Levels
In UART bypass mode, the control channel acts as a
full-duplex 9.6kbps to 1Mbps link that forwards UART
commands across the serial link without responding to
the packets themselves. Set MS high on the GMSL device
connected to the μC to enter bypass mode (wait 1ms
after setting bypass mode if the μC is connected on the
deserializer side). Bypass uses bit rates from 9.6kbps to
1Mbps. Do not send a logic-low value longer than 100μs
when using the GPI/GPO functionality.
BOOST SETTING
TYPICAL BOOST GAIN AT
(MANUAL AND ADAPTIVE
750MHZ (DB)
EQ)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1.6
2.1
2.8
3.5
4.3
5.2
6.3
7.3
8.5
Device Address
The SerDes have a 7-bit-long slave address stored in
registers 0x00 and 0x01. The bit following a 7-bit slave
address is the R/W bit, which is low for a write command
and high for a read command. External inputs determine
the default slave address as shown in Table 8. After start-
up, a microcontroller can reprogram the slave address as
needed.
9.7
1001
Power-up default for
Manual EQ*
1010
1011
11.0
12.2
Cable Equalizer
By default, the cable equalizer is enabled and set to
Adaptive mode. Set AEQ_EN = 0 to switch to manual EQ
mode. EQTUNE determines the boost level in manual EQ
mode (see Table 9). Set EN_EQ = 0 to disable all equal-
ization (manual or automatic).
*Automatic EQ is enabled by default.
measurement (above the threshold) to clear.
Additional conditions that set ERRB (disabled by default)
include:
The auto-equalization level is determined during serial-
link locking. Set AEQ_MAN_TRG_REQ = 1 to re-trigger
auto equalization. Set AEQ_PER_MODE = 1 to set up
periodic AEQ.
● Insufficient boost at maximum boost setting
(set UNDERBST_DET_EN = 1). Retrigger the
equalization calibration to clear.
ERRB Output
● Control-channel CRC errors (set CC_CRC_ERR_EN
= 1 to enable). Read CC_CRC_ERRCNT to clear.
Requires packet control channel (PKTCC = 1).
The deserializer has an open-drain ERRB output. This
output asserts low whenever any of the following condi-
tions occur:
● Video line CRC errors (turn on video-line CRC to
● The number of detected errors exceeds the error
thresholds during normal operation. Read DET_ERR,
set auto-error reset, or re-lock the link to clear.
enable). Read LINE_CRC_ERR to clear.
Auto-Error Reset
The default method to reset errors is to read the respec-
tive error counter registers in the deserializer. Auto-error
reset clears the error counters DET_ERR ~1μs after
ERR goes low. Auto-error reset is disabled on power-up.
● Exceeding the maximum number control channel
retries. Read MAX_RT_ERR to clear.
● Measured eye width falls below a programmable
threshold (40% by default). Re-trigger an eye-width
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14-Bit GMSL Deserializer
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Enable auto-error reset through ERR_RST. Auto-error
reset does not run when the device is in PRBS test mode.
R
1.5kΩ
D
1MΩ
Board Layout
CHARGE-CURRENT- DISCHARGE
Power-Supply Circuits and Bypassing
LIMIT RESISTOR
RESISTANCE
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
The deserializer uses an AVDD and DVDD of 1.7V to
1.9V. All inputs and outputs, except for the serial input,
derive power from an IOVDD of 1.7V to 3.6V that scales
with IOVDD. Proper voltage-supply bypassing is essential
for high-frequency circuit stability.
C
S
STORAGE
CAPACITOR
100pF
SOURCE
High-Frequency Signals
Figure 26. Human Body Model ESD Test Circuit
Separate the LVCMOS logic signals and CML/coax high-
speed signals to prevent crosstalk. Use a four-layer PCB
with separate layers for power, ground, CML/coax, and
LVCMOS logic signals. Layout STP PCB traces close to
each other for a 100Ω differential characteristic imped-
ance. The trace dimensions depend on the type of trace
used (microstrip or stripline). Note that two 50Ω PCB
traces do not have 100Ω differential impedance when
brought close together—the impedance goes down when
the traces are brought closer. Use a 50Ω trace for the
single-ended output when driving coax. Route the PCB
traces for differential CML in parallel to maintain the dif-
ferential characteristic impedance. Avoid vias. Keep PCB
traces that make up a differential pair equal in length to
avoid skew within the differential pair.
R
D
330Ω
CHARGE-CURRENT- DISCHARGE
LIMIT RESISTOR
RESISTANCE
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
S
STORAGE
CAPACITOR
150pF
SOURCE
Figure 27. IEC 61000-4-2 Contact Discharge ESD Test Circuit
ESD Protection
R
D
ESD tolerance is rated for Human Body Model, IEC
61000-4-2, and ISO 10605. The ISO 10605 and IEC
61000-4-2 standards specify ESD tolerance for electronic
systems. The serial outputs are rated for ISO 10605 ESD
protection and IEC 61000-4-2 ESD protection. All pins
are tested for the Human Body Model. The Human Body
Model discharge components are CS = 100pF and RD =
1.5kΩ (Figure 26). The IEC 61000-4-2 discharge compo-
nents are CS = 150pF and RD = 330Ω (Figure 27). The
ISO 10605 discharge components are CS = 330pF and
RD = 2kΩ (Figure 28).
2kΩ
CHARGE-CURRENT- DISCHARGE
LIMIT RESISTOR
RESISTANCE
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
S
STORAGE
CAPACITOR
330pF
SOURCE
Figure 28. ISO 10605 Contact Discharge ESD Test Circuit
Compatibility with Other GMSL Devices
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14-Bit GMSL Deserializer
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Table 10. Feature Compatibility
DESERIALIZER FEATURE
GMSL SERIALIZER
HSYNC/VSYNC encoding
If feature not supported in the serializer, turn off in the deserializer.
If feature not supported in the serializer, use UART-to-I2C or UART-to-UART.
If feature not supported in the serializer, use Legacy control channel.
If feature not supported in the serializer, turn off in the deserializer.
2
2
I C-to-I C
Packet control channel
CRC error detection
If feature not supported in the serializer, data is output as a single word at half the input
frequency. Use Crossbar switch to correct input mapping.
Double input
Coax
If feature not supported in the serializer, connect unused serial input through 200nF
and 50Ω in series to AVDD, and set the reverse control-channel amplitude to 100mV.
2
2
I S encoding
If supported in the serializer, disable I S in the serializer
High-bandwidth mode
High-immunity mode
If feature not supported in the serializer, turn off in the deserializer.
If feature not supported in the serializer, turn off in the deserializer.
2
The device is designed to pair with the MAX96705−
MAX96711 family of devices, but interoperates with any
GMSL device. See Table 10 for operating limitations.
time becomes too slow. GMSL supports I C/UART rates
2
2
up to 1Mbps (UART-to-I C mode) and 400kbps (I C-to-
2
I C mode).
AC-Coupling Capacitors
Device Configuration and Component Selection
Internal Input Pulldowns
The control and configuration inputs include a pulldown
resistor to GND. External pulldown resistors are not needed.
Voltage droop and the digital sum variation (DSV) of trans-
mitted symbols cause signal transitions to start from dif-
ferent voltage levels. Because the transition time is fixed,
starting the signal transition from different voltage levels
causes timing jitter. The time constant for an AC-coupled
link needs to be chosen to reduce droop and jitter to an
acceptable level. The RC network for an AC-coupled link
consists of the CML/coax receiver termination resistor
Multifunction Inputs
The device has several inputs/outputs that function both
as a parallel input/output and as a configuration pin. On
power-up, or when reverting from a power-down state,
the pins act as configuration inputs. After latching the
input state, the configuration inputs become parallel digi-
tal input/outputs. Connect a configuration input through
a 30kΩ resistor to IOVDD to set a high level. Leave the
configuration input open to set a low level.
(R ), the CML/coax driver termination resistor (R ),
TR
TD
and the series AC-coupling capacitors (C). The RC time
constant for four equal-value series capacitors is (C x
(R
+ R ))/4. R
and R
are required to match the
TD
TR
TD
TR
transmission line impedance (usually 100Ω differential,
50Ω single-ended). This leaves the capacitor selection to
change the system time constant. Use 0.22μF or larger
high-frequency surface-mount ceramic capacitors, with
sufficient voltage rating to withstand a short to battery, to
pass the lower-speed reverse control-channel signal. Use
capacitors with a case size less than 3.2mm x 1.6mm to
have lower parasitic effects to the high-speed signal.
2
I C/UART Pullup Resistors
2
The I C and UART open-drain lines require a pullup
resistor to provide a logic-high level. There are tradeoffs
between power dissipation and speed, and a compromise
may be required when choosing pullup resistor values.
Every device connected to the bus introduces some
2
capacitance even when the device is not in operation. I C
Cables and Connectors
specifies 300ns rise times (30% to 70%) for fast mode,
Interconnect for CML typically has a differential imped-
ance of 100Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities. Coax cables typically have a characteristic
impedance of 50Ω (contact the factory for 75Ω operation).
which is defined for data rates up to 400kbps. See the
2
2
I C specifications in the I C/UART Port Timing section in
the AC Electrical Characteristics table for details. To meet
the fast-mode rise-time requirement, choose the pullup
resistors so that rise time t = 0.85 x R
x C
<
R
PULLUP
BUS
300ns. The waveforms are not recognized if the transition
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14-Bit GMSL Deserializer
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Table 11. Suggested Connectors and Cables for GMSL
VENDOR
CONNECTOR
59S2AX-400A5-Y
D4S10A-40ML5-Z
GT11L-2S
CABLE
TYPE
Coax
STP
Rosenberger
Dacar 302
Dacar 535-2
Rosenberger
Nissei
F-2WME AWG28
A-BW-Lxxxxx
STP
JAE
MX38-FF
STP
Table 11 lists the suggested cables and connectors used
in the GMSL link.
μC can implement a routine to distinguish between inter-
rupts from loss-of-sync and normal interrupts. Reverse
control-channel communication does not require an active
forward link to operate and accurately tracks the LOCK
status of the GMSL link. LOCK asserts for video link only
and not for the configuration link.
PRBS
The serializer includes a PRBS pattern generator that
works with bit-error verification in the deserializer. To
run the PRBS test, set PRBSEN = 1 (0x04, D5) in the
deserializer, then in the serializer. To exit the PRBS
test, set PRBSEN = 0 (0x04, D5) in the serializer. The
deserializerautomaticallyendsPRBScheckingandsetsthe
PRBS_OK bit high. Note that during PRBS mode, the
remote control channel is not available except to exit
PRBS mode if I2C_LOC_ACK=1; otherwise, the remote
control channel is not available at all.
Providing a Frame Sync (Camera Applications)
The GPI and GPO provide a simple solution for camera
applications that require a frame sync signal from the
ECU (e.g., surround-view systems). Connect the ECU
frame sync signal to the GPI input and connect the GPO
output to the camera-frame sync input. GPI/GPO have a
typical delay of 275μs in legacy mode and 21μs in packet
mode (with 5-bit CRC). Skew between multiple GPI/GPO
channels is 115μs (max) in legacy mode and 21μs (max)
in packet mode. If a lower-skew signal is required in
legacy mode, connect the camera’s frame-sync input to
To run the PRBS with a 3Gbps SerDes, or when HIBW
= 1, first set the PRBS_TYPE bit = 0 in the MAX967XX.
Then set PRBSEN = 1 (0x04, D5) in the serializer, then in
the deserializer. To exit the PRBS test, set PRBSEN = 0
(0x04, D5) in the deserializer, then in the serializer.
2
one of the serializer’s GPIOs and use an I C broadcast
write command to change the GPIO output state. This has
During PRBS test, ERRB function changes to reflect
PRBS errors only. ERRB goes low when any PRBS errors
occur. ERRB goes high when the PRBS error counter is
reset when PRBS_ERR is read. Normal ERRB function
resumes when exiting the PRBS test.
a maximum skew of 1.5µs, independent from the used
I C bit rate. In packet-based control-channel mode, set
GPI_COMP_EN = 1 in both the serializer and the dese-
rializer to turn on GPI/GPO compensation. This reduces
the device-to-device skew to 0.35μs.
2
GPI/GPO
Entering/Exiting Sleep Mode
GPO on the serializer follows GPI transitions on the
deserializer. By default, the GPI-to-GPO delay is 0.35ms
(max). Keep the time between GPI transitions to a
minimum 0.35ms. GPI_IN the deserializer stores the GPI
input state. GPO is low after power-up. The µC can set
GPO by writing to the SET_GPO register bit. Do not send
a logic-low value on the deserializer RX/SDA input (UART
mode) longer than 100µs in either base or bypass mode
to ensure proper GPO/GPI functionality.
The procedure for entering and exiting sleep mode
depends on the location of the microcontroller, and the
type of control-channel interface used. If wake-up from a
remote-side (serializer-side) microcontroller is not needed
or desired, set the DIS_RWAKE bit = 1 to shut down
remote wake-up for further power savings.
Legacy Control Channel
When μC is on the deserializer side, first put the serializer
to sleep, or disable serialization. Next, set SLEEP = 1 in
deserializer. The device sleeps after 8ms. To wake up the
device, send an arbitrary control-channel command to the
deserializer (the device will not send an acknowledge),
wait for 5ms for the chip to power up and then set SLEEP
= 0 to make the wake-up permanent.
Fast Detection of Loss-of-Lock
A measure of link quality is the recovery time from loss
of synchronization. The host can be quickly notified of
loss-of-lock by connecting the deserializer’s LOCK output
to the GPI input (when PKTCC_EN = 0). If other sources
use the GPI input, such as a touch-screen controller, the
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
When µC is on the serializer side, set SLEEP = 1 in dese-
rializer. Next, disable serialization. The device sleeps after
8ms. To wake up the deserializer, reenable serialization.
The deserializer wakes up and clears its SLEEP bit when
it locks to the serializer.
deserializer, send an arbitrary control-channel command
to deserializer (the device will not send an acknowledge),
wait for 5ms for the chip to power up, then set SLEEP = 0
to make the wake-up permanent.
When µC is on the serializer side, Set SLEEP = 1 in
deserializer. Next, disable serialization in the serializer.
The device sleeps after 8ms. To wake up the deserializer,
reenable serialization. The deserializer wakes up and
clear its SLEEP bit when it locks to the serializer.
Packet-Based Control Channel
When µC is on the deserializer side, first put the serializer
to sleep, or disable serialization. Next, set SLEEP = 1 in
deserializer. The device sleeps after 8ms. To wake up the
Typical Application Circuit
PCLKOUT
DOUT[11:0]
DOUT12/HS
PCLK
DIN[11:0]
PCLK
DIN[11:0]
PCLKIN
DIN[11:0]
HS
VS
DIN14/HS
DIN15/VS
HS
VS
DOUT13/VS
CAMERA
MAX96701
MAX96700
GPU
45.3kΩ
4.99kΩ
SDA
SCL
RX/SDA
49.9Ω
LMN0
TX/SCL/DBL
RX/SDA
TX/SCL
SDA
SCL
OUT-
I2C
OUT+
IN+
IN-
GPI
FSYNC
49.9kΩ
LOCK
LOCK
LCCEN
49.9Ω
CONF0
CONF1
ERRB
LFLTB
ERR
LFLT
MS/HVEN
I2CSEL = 1, CX/TP = 1
ECU
NOTE: NOT ALL PULLUP/PULLDOWN RESISTORS ARE SHOWN. SEE PIN DESCRIPTION FOR DETAILS.
CAMERA APPLICATION
Ordering Information
PART NUMBER
MAX96700GTJ/V+
MAX96700GTJ/V+T
TEMP RANGE PIN-PACKAGE
-40°C to +115°C 32 TQFN-EP*
-40°C to +115°C 32 TQFN-EP*
/V denotes an automotive qualified product.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
T = Tape and reel.
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MAX96700
14-Bit GMSL Deserializer
with Coax or STP Cable Input
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
6/17
Initial release
—
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2017 Maxim Integrated Products, Inc.
│ 73
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