MAX9671CTH+T [MAXIM]
Audio/Video Switch, BICMOS, PQCC44,;
| 型号： | MAX9671CTH+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Audio/Video Switch, BICMOS, PQCC44, 信息通信管理 |
| 文件： | 总44页 (文件大小：824K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4653; Rev 2; 12/10
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
0/MAX9671
General Description
Features
The MAX9670/MAX9671 dual SCART matrices route
audio and video signals between a set-top box
decoder chip and two external SCART connectors
under I2C control. Operating from a 3.3V supply and a
12V supply, the MAX9670/MAX9671 consume 66mW
during quiescent operation and 300mW during average
operation when driving typical signals into typical
loads. Video input detection, video load detection, and
a 2.8mW standby mode facilitate the design of intelli-
gent, low-power set-top boxes.
o 66mW Quiescent Power Consumption
o 2.8mW Standby Mode Consumption
o Programmable Audio Gain Control of -62dB to
0dB (TV Audio Outputs)
o Clickless, Popless, DirectDrive Audio
o Video Input and Video Load Detection
o Video Reconstruction Filter with 10MHz Passband
and 52dB Attenuation at 27MHz
The MAX9670/MAX9671 audio section contains a
buffered crosspoint to route audio inputs to audio out-
puts and programmable volume control from -62dB to
0dB in 2dB steps. The DirectDrive® output amplifiers
o 3.3V and 12V Supply Voltages
create a 2V
full-scale audio signal biased around
RMS
Ordering Information
ground, eliminating the need for bulky output capaci-
tors and reducing click-and-pop noise. The zero-cross
detection circuitry also further reduces clicks and pops
by enabling audio sources to switch only during a zero-
crossing. The MAX9671 offers TV left and right audio
inputs.
TV R+L
AUDIO
INPUTS
PIN-
PACKAGE
PART
TEMP RANGE
MAX9670CTL+
MAX9671CTH+
0°C to +70°C 40 TQFN-EP*
0°C to +70°C 44 TQFN-EP*
No
Yes
The MAX9670/MAX9671 video section contains a
buffered crosspoint to route video inputs to video out-
puts. The standard-definition video signals from the set-
top box decoder chip are lowpass filtered to remove
out-of-band artifacts.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
System Block Diagram
The MAX9670/MAX9671 also support slow-switching
and fast-switching signals. An interrupt signal from the
MAX9670/MAX9671 informs the microcontroller when
the system status has changed.
V
V
V
VID
AUD
12
12V
3.3V
3.3V
STB CHIP
MAX9670/MAX9671
Applications
RGB, Y/C, CVBS
CVBS
2
I C
2
Set-Top Boxes
TVs
I C INTERFACE
L/R AUDIO
(MAX9671 ONLY)
REGISTERS AND
ACTIVITY
INTERRUPT
OUTPUT
µC
MONITOR
TV
SCART
L/R AUDIO
(MAX9670 ONLY)
DVD Players
SLOW SWITCHING
FAST SWITCHING
RGB, Y/C, CVBS
VIDEO FILTERS AND
CROSSPOINT
VIDEO
ENCODER
Y/C, CVBS
SINGLE-ENDED R/L
STEREO AUDIO
AUDIO CROSSPOINT
WITH DIRECTDRIVE
OUTPUTS, VOLUME
CONTROL
STEREO
AUDIO
DAC
RGB, Y/C, CVBS
L/R AUDIO
VCR
SCART
SLOW SWITCHING
FAST SWITCHING
SLOW SWITCHING
FAST SWITCHING
Typical Application Circuit appears at end of data sheet.
CHARGE PUMP
EP
GNDVID
DirectDrive is a registered trademark of Maxim Integrated
Products, Inc.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
ABSOLUTE MAXIMUM RATINGS
V
V
V
to GNDVID........................................................-0.3V to +4V
Audio Outputs to V
TV_SS, VCR_SS to V , EP......................................Continuous
Continuous Power Dissipation (T = +70°C)
A
, EP.....................................Continuous
VID
AUD
12
to EP.................................................................-0.3V to +14V
12
to EP ...............................................................-0.3V to +4V
AUD
EP to GNDVID .......................................................-0.1V to +0.1V
All Video Inputs, VCRIN_FS to GNDVID...................-0.3V to +4V
40-Pin TQFN-EP (derate 26.3mW/°C above +70°C)...2105.3mW
44-Pin TQFN-EP (derate 26.3mW/°C above +70°C)...2222.2mW
All Audio Inputs to EP .......................................-1V to (V + 1V)
EP
SDA, SCL, DEV_ADDR, INT to GNDVID ..................-0.3V to +4V
Junction-to-Case Thermal Resistance (θ ) (Note 1)
JC
40/44-pin TQFN-EP .........................................................1°C/W
TV_SS, VCR_SS to EP .................................-0.3V to (V + 0.3V)
Current
All Video/Audio Inputs ................................................... 20mA
C1P, C1N, CPVSS ......................................................... 50mA
Output Short-Circuit Current Duration
Junction-to-Ambient Thermal Resistance (θ ) (Note 1)
12
JA
40/44-pin TQFN-EP .......................................................27°C/W
Operating Temperature Range...............................0°C to +70°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Video and Fast-Switching Outputs to V
,
VID
GNDVID.................................................................Continuous
Note 1: Package thermal resistance were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
0/MAX9671
ELECTRICAL CHARACTERISTICS
(V = 12V, V
= V
= 3.3V, V
= V = 0V, no load, T = 0°C to +70°C, unless otherwise noted. Typical values are at
GNDVID
EP
12
VID
AUD
A
T = +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Inferred from video PSRR test at 3V and
3.6V
Video Supply Voltage Range
Audio Supply Voltage Range
V
3
3.3
3.6
V
VID
Inferred from audio PSRR test at 3V and
3.6V
V
3
3.3
12
16
3.6
12.6
30
V
V
AUD
V
Supply Voltage Range
V
Inferred from slow-switching levels
11.4
12
12
Normal operation; all video output
amplifiers are enabled and muted (Note 3)
mA
V
Quiescent Supply Current
I
VID_Q
VID
Standby mode, slow switch inputs low
Shutdown
1500
35
µA
Normal operation (Note 3)
Shutdown
3.2
6
mA
µA
V
V
Quiescent Supply Current
I
AUD_Q
AUD
35
Slow-switching output
0.3
100
10
set to low-level
Normal operation
(Note 3)
µA
µA
Quiescent Supply Current
I
12_Q
12
Slow-switching output
set to medium-level
475
Shutdown, T = +25°C
A
VIDEO CHARACTERISTICS
DC-COUPLED INPUT
V
V
V
= 3V
1.15
1.3
R = 75Ω to
GNDVID or 150Ω
VID
VID
VID
L
Input Voltage Range
V
= 3.135V
= 3.3V
1.15
2
V
P-P
IN
to V /2; inferred
VID
from gain test
Input Current
I
V
= 0.3V, T = +25°C
1
µA
IN
IN
A
Input Resistance
R
300
kΩ
IN
2
_______________________________________________________________________________________
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
0/MAX9671
ELECTRICAL CHARACTERISTICS (continued)
(V = 12V, V
= V
= 3.3V, V
= V = 0V, no load, T = 0°C to +70°C, unless otherwise noted. Typical values are at
GNDVID
EP
12
VID
AUD
A
T = +25°C.) (Note 2)
A
PARAMETER
AC-COUPLED INPUT
Sync-Tip Clamp Level
SYMBOL
CONDITIONS
MIN
TYP
MAX
+6
2
UNITS
mV
V
Sync-tip clamp
Sync-tip clamp; percentage reduction in
sync pulse (0.3V ); guaranteed by input
-13
-4
CLP
Sync Crush
%
P-P
clamping current measurement, T = +25°C
A
Input Clamping Current
Sync-tip clamp, V = 0.3V, T = +25°C
1
2
µA
IN
A
Maximum Input Source
Resistance
Input sync-tip circuit must be stable even if
the source resistance is as high as 300Ω
300
0.6
Ω
Bias circuit
0.57
0.63
Input Voltage
V
0.3 x
0.36 x
V
VID
High-impedance input circuit
V
VID
Bias circuit
10
Input Resistance
kΩ
V/V
High-impedance input circuit
222
DC CHARACTERISTICS
DC Voltage Gain
A
Guaranteed by output voltage swing
1.95
-2
2
2.05
+2
V
Guaranteed by output voltage swing of
TV_R/C_OUT, TV_G_OUT, and TV_B_OUT;
first input signal set is VCR_R/C_IN,
VCR_G_IN, and VCR_B_IN; second signal
set is ENC_R/C_IN, ENC_G_IN, and
ENC_B_IN
DC Gain Mismatch Among R, G,
and B Outputs
%
V
Sync-tip clamp (V = V
IN
)
0.1
1.3
0.30
1.5
0.51
1.78
CLP
Output Level
Bias circuit
Sync-tip clamp, measured at output,
= 3V, V = V to (V +1.15V),
V
2.3
2.3
2.3
2.3
VID
IN
CLP
CLP
R = 150Ω to V /2, R = 75Ω to GNDVID
L
VID
L
Measured at output, V
= 3.135V, V
=
VID
IN
V
V
to (V
+ 1.15V), R = 150Ω to
2.243
2.358
CLP
CLP L
/2, R = 75Ω to GNDVID
VID
L
Output Voltage Swing
V
P-P
Bias circuit, measured at output, V
= 3V,
VID
V
= (V
- 0.575V) to (V
+ 0.575V),
IN
BIAS
BIAS
R = 150Ω to V /2, R = 75Ω to GNDVID
L
VID
L
Measured at output, V
= 3.135V,
VID
V
= (V
- 0.575V) to (V
+ 0.575V),
2.243
2.358
170
IN
BIAS
BIAS
R = 150Ω to V /2, R = 75Ω to GNDVID
L
VID
L
Output Short-Circuit Current
Output Resistance
100
0.5
mA
Ω
R
OUT
Output Leakage Current
Power-Supply Rejection Ratio
Output disabled (load detection not active)
3V ≤ V ≤ 3.6V
µA
dB
35
VID
_______________________________________________________________________________________
3
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
ELECTRICAL CHARACTERISTICS (continued)
(V = 12V, V
= V
= 3.3V, V
= V = 0V, no load, T = 0°C to +70°C, unless otherwise noted. Typical values are at
GNDVID
EP
12
VID
AUD
A
T = +25°C.) (Note 2)
A
PARAMETER
AC CHARACTERISTICS
Filter Passband Flatness
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
dB
V
= 2V , f = 100kHz to 5.5MHz
P-P
-1
3
OUT
OUT
f = 9.5MHz
V
= 2V
,
P-P
Filter Attenuation
dB
attenuation is
referred to 100kHz
f = 27MHz
f = 54MHz
40
55
Slew Rate
V
V
= 2V , no filter in video path
60
V/µs
ns
OUT
OUT
P-P
Settling Time
Differential Gain
Differential Phase
= 2V , settle to 0.1% (Note 4)
400
0.15
0.5
P-P
DG
DP
5-step modulated staircase, f = 4.43MHz
5-step modulated staircase, f = 4.43MHz
%
Degrees
2T = 200ns, bar time is 18µs, the beginning
2.5% and the ending 2.5% of the bar time is
ignored
2T Pulse-to-Bar K Rating
2T Pulse Response
2T Bar Response
0.3
0.2
0.2
K%
K%
K%
0/MAX9671
2T = 200ns
2T = 200ns, bar time is 18µs, the beginning
2.5% and the ending 2.5% of the bar time is
ignored
Nonlinearity
Group Delay Distortion
5-step staircase
100kHz ≤ f ≤ 5MHz, outputs are 2V
0.1
11
%
ns
P-P
Glitch Impulse Caused by
Charge-Pump Switching
Measured at outputs
100
pV-s
Peak Signal to RMS Noise
100kHz ≤ f ≤ 5MHz
70
47
2
dB
dB
Ω
Power-Supply Rejection Ratio
Output Impedance
f = 100kHz, 100mV
f = 5MHz
P-P
Video Crosstalk
f = 4.43MHz
-80
dB
VCR SCART inputs to encoder inputs,
full-power mode with VCR being looped
through to TV, f = 4.43MHz
Reverse Isolation
92
4.4
4
dB
Enable VCR_R/C_OUT pulldown through
Pulldown Resistance
7.5
Ω
2
I C interface
AUDIO CHARACTERISTICS
Voltage Gain
V
V
= -0.707V to +0.707V
= -0.707V to +0.707V
3.95
-1.5
4.05
+1.5
V/V
%
IN
IN
Gain Mismatch
Flatness
f = 20Hz to 20kHz, 0.25V
input
0.006
230
dB
RMS
0.25V
input, frequency where output is
RMS
Frequency Bandwidth
Capacitive Drive
kHz
pF
-3dB referenced to 1kHz
No sustained oscillations; 75Ω series
resistor on output
300
4
_______________________________________________________________________________________
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
0/MAX9671
ELECTRICAL CHARACTERISTICS (continued)
(V = 12V, V
= V
= 3.3V, V
= V = 0V, no load, T = 0°C to +70°C, unless otherwise noted. Typical values are at
GNDVID
EP
12
VID
AUD
A
T = +25°C.) (Note 2)
A
PARAMETER
Input Resistance
SYMBOL
CONDITIONS
MIN
TYP
MAX
500
+4
UNITS
MΩ
V
= -0.707V to +0.707V
10
IN
IN
Input Bias Current
Input Signal Amplitude
Output DC Level
V
= 0, T = +25°C
nA
A
f = 1kHz, THD < 1%
0.5
V
RMS
No input signal, V grounded
IN
-4
mV
dB
dB
%
DC
75
100
90
Power-Supply Rejection Ratio
f = 1kHz
Signal-to-Noise Ratio
f = 1kHz, 0.25V
input, 20Hz to 20kHz
96
RMS
R = 3.33kΩ, f = 1kHz, 0.25V
input
RMS
0.002
0.001
0.4
L
Total Harmonic Distortion Plus
Noise
R = 3.33kΩ, f = 1kHz, 0.5V
input
RMS
L
Output Impedance
f = 1kHz
Ω
Programmable gain to TV SCART volume
control from -62dB to 0
Volume Control Attenuation Step
2
0
dB
Volume Control Minimum
Attenuation
dB
dB
Volume Control Maximum
Attenuation
62
Mute Suppression
f = 1kHz, 0.25V
f = 1kHz, 0.25V
input
input
110
100
dB
dB
RMS
Audio Crosstalk
RMS
VIDEO-TO-AUDIO INTERACTION
Video input: f = 15kHz, 1V
Audio input: f = 15kHz, 0.5V
signal
P-P
Crosstalk
92
dB
signal
RMS
CHARGE PUMP
Switching Frequency
FAST SWITCHING
Input Low
570
kHz
0.4
V
V
Input High Level
Input Current
1
T
= +25°C
= 0.5mA
10
µA
V
A
Output Low Voltage
I
0.1
OL
V
-
VID
0.1
Output High Voltage
I
= 0.5mA
V
OH
Output Resistance
Rise Time
7
Ω
143Ω to GNDVID
143Ω to GNDVID
12
10
ns
ns
Fall Time
SLOW SWITCHING
Input Low Voltage
Input Medium Voltage
Input High Voltage
2
7
V
V
V
4.5
9.5
_______________________________________________________________________________________
5
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
ELECTRICAL CHARACTERISTICS (continued)
(V = 12V, V
= V
= 3.3V, V
= V = 0V, no load, T = 0°C to +70°C, unless otherwise noted. Typical values are at
GNDVID
EP
12
VID
AUD
A
T = +25°C.) (Note 2)
A
PARAMETER
Input Current
SYMBOL
CONDITIONS
MIN
TYP
MAX
100
1.5
UNITS
70
µA
V
Output Low Voltage
Output Medium Voltage
Output High Voltage
DIGITAL INTERFACE
10kΩ to EP, 11.4V ≤ V ≤ 12.6V
12
10kΩ to EP, 11.4V ≤ V ≤ 12.6V
5
6.5
V
12
10kΩ to EP, 11.4V ≤ V ≤ 12.6V
10
V
12
0.7 x
Input High Voltage
Input Low Voltage
Input Hysteresis
V
V
V
V
IH
V
VID
0.3 x
V
IL
V
VID
0.06 x
V
HYS
V
VID
0/MAX9671
Input Leakage Current
Input Capacitance
I
, I
IH IL
T
A
= +25°C
-1
+1
µA
pF
6
0.1V
0.1V
< SDA < 3.3V,
< SCL < 3.3V
VID
VID
Input Current
I/O pins of fast-mode devices must not
obstruct the SDA and SCL lines if V+ is
-10
+10
µA
switched off, T = +25°C
A
Output Low Voltage SDA
Serial-Clock Frequency
V
I
= 6mA
0.4
V
OL
SINK
f
0
400
kHz
SCL
Bus Free Time Between a STOP
and a START Condition
t
1.3
µs
µs
BUF
Hold Time, (Repeated) START
Condition
t
t
0.6
HD, STA
Low Period of the SCL Clock
High Period of the SCL Clock
t
1.3
0.6
µs
µs
LOW
t
HIGH
Setup Time for a Repeated
START Condition
0.6
µs
SU, STA
Data Hold Time
Data Setup Time
t
t
(Note 5)
0
0.9
µs
ns
HD, DAT
HD, DAT
100
I
≤ 6mA, C = total capacitance of one
B
SINK
Fall Time of SDA Transmitting
t
bus line in pF, t and t measured between
100
ns
F
R
F
0.3V
and 0.7V
VID
VID
Setup Time for STOP Condition
Pulse Width of Spike Suppressed
t
0.6
0
µs
ns
SU, STO
Input filters on the SDA and SCL inputs
suppress noise spikes less than 50ns
t
50
SP
6
_______________________________________________________________________________________
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
0/MAX9671
ELECTRICAL CHARACTERISTICS (continued)
(V = 12V, V
= V
= 3.3V, V
= V = 0V, no load, T = 0°C to +70°C, unless otherwise noted. Typical values are at
GNDVID
EP
12
VID
AUD
A
T = +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OTHER DIGITAL I/O
0.3 x
DEV_ADDR Low Level
V
V
V
VID
0.7 x
DEV_ADDR High Level
V
VID
DEV_ADDR Input Current
T
= +25°C
= 0.5mA
-1
+1
0.1
10
µA
V
A
Interrupt Output Low Voltage
I
OL
Interrupt Output Leakage Current
INT high impedance, T = +25°C
µA
A
Note 2: All devices are 100% production tested at T = +25°C. Specifications over temperature limits are guaranteed by design.
A
Note 3: Normal operation mode is full power with input video and load detection active.
Note 4: The settling time is measured from the 50% of the input swing to the 0.1% of the final value of the output.
Note 5: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V of the SCL signal) to bridge
IL
the undefined region of SCL’s falling edge.
Typical Operating Characteristics
(V
= V
= 3.3V, V = 12V, V
= V = 0V, video load is 150Ω to GNDVID, audio load is 10kΩ to EP, T = +25°C, unless
GNDVID
EP
VID
AUD
12
A
otherwise noted.)
SMALL-SIGNAL GAIN
vs. FREQUENCY
SMALL-SIGNAL GAIN FLATNESS
vs. FREQUENCY
LARGE-SIGNAL GAIN
vs. FREQUENCY
2
1
10
0
10
0
V
= 100mV
V
= 100mV
OUT P-P
OUT
P-P
V
= 2V
OUT P-P
0
-10
-20
-30
-40
-50
-60
-10
-20
-30
-40
-50
-60
-1
-2
-3
-4
-5
-6
-7
-8
NO FILTER
NO FILTER
NO FILTER
FILTER
FILTER
FILTER
1M
10M
FREQUENCY (Hz)
100M
100k
1M
10M
FREQUENCY (Hz)
100M
1G
100k
1M
10M
FREQUENCY (Hz)
100M
1G
_______________________________________________________________________________________
7
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
Typical Operating Characteristics (continued)
(V
= V
= 3.3V, V = 12V, V
= V = 0V, video load is 150Ω to GNDVID, audio load is 10kΩ to EP, T = +25°C, unless
GNDVID
EP
VID
AUD
12
A
otherwise noted.)
LARGE-SIGNAL GAIN FLATNESS
VIDEO CROSSTALK
vs. FREQUENCY
GROUP DELAY
vs. FREQUENCY
vs. FREQUENCY
0
-20
-40
-60
-80
2
1
140
120
100
80
V
= 100mV
P-P
OUT
V
OUT
= 2V
P-P
NO FILTER
0
-1
-2
-3
-4
-5
-6
-7
-8
FILTER
ALL HOSTILE
60
FILTER
40
-100
-120
20
NO FILTER
0
100k
1M
10M
100M
1M
10M
100M
100k
1M
10M
100M
0/MAX9671
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
VIDEO POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
VIDEO VOLTAGE GAIN
vs. TEMPERATURE
VIDEO OUTPUT VOLTAGE
vs. INPUT VOLTAGE
2.04
2.03
2.02
2.01
2.00
1.99
1.98
1.97
1.96
0
-5
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
-10
-15
-20
-25
-30
-35
-40
-45
-50
FILTER
NO FILTER
0
25
50
75
100k
1M
10M
100M
0
0.4
0.8
1.2
1.6
TEMPERATURE (°C)
FREQUENCY (Hz)
INPUT VOLTAGE (V)
2T WITH FILTER
DIFFERENTIAL GAIN AND PHASE
DIFFERENTIAL GAIN AND PHASE
MAX9670 toc12
0.3
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
0.2
0.1
0
-0.1
-0.2
-0.3
VIDEO INPUT
200mV/div
0
1
2
3
4
5
0
1
2
3
4
5
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
VIDEO OUTPUT
500mV/div
0
1
2
3
4
5
80ns/div
0
1
2
3
4
5
8
_______________________________________________________________________________________
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
0/MAX9671
Typical Operating Characteristics (continued)
(V
= V
= 3.3V, V = 12V, V
= V = 0V, video load is 150Ω to GNDVID, audio load is 10kΩ to EP, T = +25°C, unless
GNDVID
EP
VID
AUD
12
A
otherwise noted.)
2T NO FILTER
12.5T WITH FILTER
MAX9670 toc13
MAX9670 toc14
VIDEO INPUT
200mV/div
VIDEO INPUT
200mV/div
VIDEO OUTPUT
500mV/div
VIDEO OUTPUT
500mV/div
80ns/div
1µs/div
12.5T NO FILTER
NTC7 WITH FILTER
MAX9670 toc15
MAX9670 toc16
VIDEO INPUT
200mV/div
VIDEO INPUT
500mV/div
VIDEO OUTPUT
500mV/div
VIDEO OUTPUT
1V/div
1µs/div
10µs/div
NTC7 NO FILTER
FIELD SQUARE WAVE
MAX9670 toc17
MAX9670 toc18
VIDEO INPUT
500mV/div
VIDEO INPUT
500mV/div
VIDEO OUTPUT
1V/div
VIDEO OUTPUT
1V/div
10µs/div
2ms/div
_______________________________________________________________________________________
9
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
Typical Operating Characteristics (continued)
(V
= V
= 3.3V, V = 12V, V
= V = 0V, video load is 150Ω to GNDVID, audio load is 10kΩ to EP, T = +25°C, unless
GNDVID EP
A
VID
AUD
12
otherwise noted.)
VIDEO INPUT SYNC-TIP CLAMP VOLTAGE
vs. TEMPERATURE
VIDEO INPUT BIAS VOLTAGE
vs. TEMPERATURE
2
1
620
615
610
605
600
595
590
585
580
0
-1
-2
-3
-4
-5
-6
0
25
50
75
0
25
50
75
0/MAX9671
TEMPERATURE (°C)
TEMPERATURE (°C)
VIDEO INPUT SYNC-TIP CLAMP CURRENT
vs. TEMPERATURE
VIDEO INPUT SYNC-TIP CLAMP CURRENT
vs. INPUT VOLTAGE
8
7
6
5
4
3
2
1
0
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0
25
50
75
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5
INPUT VOLTAGE (V)
TEMPERATURE (°C)
VIDEO OUTPUT BIAS VOLTAGE
vs. TEMPERATURE
AUDIO LARGE-SIGNAL GAIN
vs. FREQUENCY
1.50
1.49
1.48
1.47
1.46
1.45
1.44
1.43
1.42
10
5
0
-5
-10
-15
-20
0
25
50
75
10
100
1k
10k
100k
1M
TEMPERATURE (°C)
FREQUENCY (Hz)
10 ______________________________________________________________________________________
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
0/MAX9671
Typical Operating Characteristics (continued)
(V
= V
= 3.3V, V = 12V, V
= V = 0V, video load is 150Ω to GNDVID, audio load is 10kΩ to EP, T = +25°C, unless
GNDVID
EP
VID
AUD
12
A
otherwise noted.)
AUDIO CROSSTALK
vs. FREQUENCY
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
0
-20
-40
-60
-80
0.1
0.01
V
= 0.25V
RMS
IN
TVIN TO
TVOUT
TVIN TO
VCROUT
0.001
0.0001
-100
-120
10
100
1k
10k
100k
10
100
1k
FREQUENCY (Hz)
10k
100k
FREQUENCY (Hz)
V
AUD
POWER-SUPPLY REJECTION RATIO
(INPUT REFERRED) vs. FREQUENCY
V
QUIESCENT SUPPLY CURRENT
vs. TEMPERATURE
VID
0
-20
30
25
20
15
10
5
V
= 3.3V + 100mV
P-P
AUD
-40
-60
-80
-100
-120
0
0
25
50
75
10
100
1k
FREQUENCY (Hz)
10k
100k
TEMPERATURE (°C)
V
QUIESCENT SUPPLY CURRENT
vs. TEMPERATURE
V
QUIESCENT SUPPLY CURRENT
vs. TEMPERATURE
AUD
12
800
700
600
500
400
300
200
100
0
5
4
3
2
1
0
0
25
50
75
0
25
50
75
TEMPERATURE (°C)
TEMPERATURE (°C)
______________________________________________________________________________________ 11
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
Pin Description
PIN
NAME
FUNCTION
MAX9670
MAX9671
1
2
3
1
2
3
SDA
SCL
Bidirectional I2C Data I/O. Output is open drain and tolerates up to 3.6V.
I2C Clock Input
DEV_ADDR
Device Address Set Input. Connect to GNDVID, V , SDA or SCL. See Table 3.
VID
Interrupt Output. This is an open-drain output that pulls down to GNDVID to
indicate a change in the VCR slow switching or fast switching input, the activity
status of the composite video inputs, or the load status of the composite video
outputs.
4
4
INT
Audio Supply. Connect to a 3.3V supply. Bypass with a 10µF aluminum
electrolytic capacitor and a 0.47µF ceramic capacitor to EP.
5
6
7
5
6
7
V
AUD
Charge-Pump Flying Capacitor Positive Terminal. Connect a 0.47µF capacitor
from C1P to C1N.
C1P
C1N
Charge-Pump Flying Capacitor Negative Terminal. Connect a 0.47µF capacitor
from C1P to C1N.
0/MAX9671
8
8
CPVSS
ENC_INL
ENC_INR
TV_INL
Charge-Pump Negative Power Supply. Bypass with a 1µF ceramic capacitor to EP.
Encoder Left-Channel Audio Input
9
9
10
—
—
11
12
13
14
15
16
17
10
11
12
13
14
15
16
17
18
19
Encoder Right-Channel Audio Input
TV SCART Left-Channel Audio Input
TV_INR
TV SCART Right-Channel Audio Input
VCR_INL
VCR_INR
TV_OUTL
VCR_OUTL
VCR_OUTR
TV_OUTR
TV_SS
VCR SCART Left-Channel Audio Input
VCR SCART Right-Channel Audio Input
TV SCART Left-Channel Audio Output
VCR SCART Left-Channel Audio Output
VCR SCART Right-Channel Audio Output
TV SCART Right-Channel Audio Output
TV SCART Bidirectional Slow-Switch Signal
+12V Supply for the Slow Switching Circuit. Bypass with a 10µF + 0.47µF ceramic
capacitor to EP.
18
20
V
12
19
20
—
21
22
VCR_SS
TVOUT_FS
N.C.
VCR SCART Bidirectional Slow-Switch Signal
TV SCART Fast-Switching Logic Output
No Connection. Leave unconnected.
VCR SCART Fast-Switching Logic Input
Encoder Blue Video Input
23, 44
24
21
22
23
24
25
26
27
VCRIN_FS
ENC_B_IN
ENC_G_IN
VCR_B_IN
VCR_G_IN
TV_B_OUT
TV_G_OUT
25
26
Encoder Green Video Input
27
VCR SCART Blue Video Input
28
VCR SCART Green Video Input
TV SCART Blue Video Output
29
30
TV SCART Green Video Output
12 ______________________________________________________________________________________
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
0/MAX9671
Pin Description (continued)
PIN
NAME
FUNCTION
MAX9670
MAX9671
28
29
31
32
GNDVID
Video Ground
VCR_R/C_IN
VCR SCART Red/Chroma Video Input
Video and Digital Supply. Connect to a 3.3V supply. Bypass with parallel 1µF and
0.1µF ceramic capacitors to GNDVID. V
I C interface.
also serves as a digital supply for the
30
33
V
VID
VID
2
31
32
33
34
35
36
37
38
39
40
34
35
36
37
38
39
40
41
42
43
ENC_C_IN
ENC_R/C_IN
TV_R/C_OUT
VCR_R/C_OUT
Encoder Chroma Video Input
Encoder Red/Chroma Video Input
TV SCART Red/Chroma Video Output
VCR SCART Red/Chroma Video Output
VCR_Y/CVBS_OUT VCR SCART Luma/Composite Video Output
TV_Y/CVBS_OUT TV SCART Luma/Composite Video Output
VCR_Y/CVBS_IN VCR SCART Luma/Composite Video Input
TV_Y/CVBS_IN
ENC_Y_IN
TV SCART Luma/Composite Video Input
Encoder Luma Video Input
ENC_Y/CVBS_IN Encoder Luma/Composite Video Input
Exposed Pad. The exposed pad is the internal ground for the audio amplifiers and
charge pump. A low-impedance connection between ground and EP is required
for proper isolation.
—
—
EP
ation of lower power set-top boxes, televisions, and
Detailed Description
DVD players. Unlike competing SCART ICs, the audio
and video circuits of the MAX9670/MAX9671 operate
entirely from 3.3V rather than from 5V and 12V. Only the
slow-switch circuit of the MAX9670/MAX9671 requires a
12V supply. The MAX9670/MAX9671 also have circuits
that detect activity on the CVBS inputs, loads on the
CVBS outputs, and the level of the slow-switch signals.
The INT signal informs the microcontroller if there are
any changes so that the microcontroller can intelli-
gently decide whether to power up or power down
the equipment.
The MAX9670/MAX9671 represents Maxim’s third gen-
eration of SCART audio/video (A/V) switches. Under I2C
control, these devices route audio, video, and control
information between the set-top box decoder chip and
two SCART connectors. The audio signals are left audio
and right audio. The video signals are composite video
with blanking and sync (CVBS) and component video
(red, green, blue). S-video (Y/C) can be transported
across the SCART interface if CVBS is reassigned to
luma (Y) and red is reassigned to chroma (C). Support
for S-video is optional. The slow-switch signal and the
fast-switch signal carry control information. The slow-
switch signal is a 12V, three-level signal that indicates
whether the picture aspect ratio is 4:3 or 16:9 or causes
the television to use an internal A/V source such as an
antenna. The fast-switch signal indicates whether the
television should display CVBS or RGB signals.
In addition, the MAX9670/MAX9671 have DirectDrive
audio circuitry to eliminate click-and-pop noise. With
DirectDrive, the DC bias of the audio line outputs is
always at ground, no matter whether the MAX9670/
MAX9671 are being powered up or powered down.
Conventional audio line output drivers that operate from a
single supply require series AC-coupling capacitors.
During power-up, the DC bias on the AC-coupling capac-
itor moves from ground to a positive voltage, and during
power-down, the opposite occurs. The changing DC bias
usually causes an audible transient.
CVBS, left audio, and right audio are full duplex. All the
other signals are half duplex. Therefore, one device on
the link must be designated as the transmitter, and the
other device must be designated as the receiver.
The low power consumption and the advanced monitor-
ing functions of the MAX9670/MAX9671 enable the cre-
______________________________________________________________________________________ 13
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
ZCD
MUTE
ENC_INL
VCR_INL
*TV_INL
VOLUME
CONTROL
0dB TO -62dB
x4
TV_OUTL
TV_OUTR
MUTE
(0.5V
FULL-SCALE INPUT)
RMS
(2V
RMS
FULL-SCALE OUTPUT)
x4
MUTE
VOLUME
CONTROL
0dB TO -62dB
MUTE
x4
VCR_OUTL
VCR_OUTR
0/MAX9671
MUTE
MUTE
ENC_INR
(2V
RMS
FULL-SCALE OUTPUT)
x4
VCR_INR
*TV_INR
SCL
SDA
REGISTER
CONTROL
DEV_ADDR
V
AUD
C1P
EP
CHARGE
PUMP
C1N
CPVSS
MAX9670/MAX9671
*MAX9671 ONLY.
Figure 1. MAX9670/MAX9671 Audio Section Functional Diagram
nonblocking audio crosspoint with TV as the third input
source.
Audio Section
The MAX9670 audio circuit is essentially a stereo,
2-by-2, nonblocking, audio crosspoint with output dri-
vers. The encoder (stereo audio DAC) and the VCR are
the two input sources, and the two outputs go to the TV
SCART connector and the VCR SCART connector. See
Figure 1. The MAX9671 audio circuit is similar to that of
the MAX9670 except that it is a stereo, 3-by-2,
The integrated charge pump inverts the +3.3V supply
to create a -3.3V supply. The audio circuit operates
from bipolar supplies so the audio signal is always
biased to ground.
14 ______________________________________________________________________________________
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
0/MAX9671
Audio Outputs
The MAX9670/MAX9671 audio output amplifiers feature
Maxim’s DirectDrive architecture, thereby eliminating
the need for output-coupling capacitors required by
V
DD
/2
conventional single-supply audio line drivers. An inter-
nal charge pump inverts the positive supply (V ),
AUD
V
V
DD
DD
creating a negative supply (CPVSS). The audio output
amplifiers operate from these bipolar supplies with their
outputs biased about audio ground (Figure 2). The ben-
efit of this audio ground bias is that the amplifier out-
puts do not have a DC component. The DC-blocking
capacitors required with conventional audio line drivers
are unnecessary, conserving board space, reducing
system cost, and improving frequency response.
GND
CONVENTIONAL DRIVER-BIASING SCHEME
Conventional single-supply audio line drivers have their
outputs biased about a nominal DC voltage (typically
half the supply) for maximum dynamic range. Large
coupling capacitors are needed to block this DC bias.
Clicks and pops are created when the coupling capaci-
tors are charged during power-up and discharged dur-
ing power-down.
+V
DD
V
OUT
2V
GND
DD
The MAX9670/MAX9671 features a low-noise charge
pump that requires only two small ceramic capacitors.
The 580kHz switching frequency is well beyond the
audio range and does not interfere with audio signals.
The switch drivers feature a controlled switching speed
that minimizes noise generated by turn-on and turn-off
transients.
-V
DD
DirectDrive BIASING SCHEME
Figure 2. Conventional Driver Output Waveform vs. MAX9670/
MAX9671 Output Waveform.
The SCART standard specifies 2V
as the full-scale
RMS
Clickless Switching
The TV audio channel incorporates a zero-crossing
detect (ZCD) circuit that minimizes click noise due to
abrupt signal level changes that occur when switching
between audio signals at an arbitrary moment.
for audio signals. As the audio circuits process
0.5V full-scale audio signals internal to the
RMS
MAX9670/MAX9671, the gain-of-4 output amplifiers
restore the audio signals to a full-scale of 2V
.
RMS
To select which audio input source is routed to the TV
SCART connector, write to bits 1 and 0 of the TV Audio
Control register (01h). To select which audio input
source is routed to the VCR SCART connector, write to
bits 3 and 2 of the TV Audio Control register (01h). The
power-on default is for the TV and VCR audio outputs to
be muted (the inputs of the output amplifiers are con-
nected to audio ground). See Tables 10 and 13.
To implement the zero-crossing function when switch-
ing audio signals, set the ZCD bit high (Audio Control
register 00h, bit 6). Then set the mute bit high (Audio
Control register 00h, bit 0). Next, wait for a sufficient
period of time for the audio signal to cross zero. This
period is a function of the audio signal path’s low-fre-
quency 3dB corner (f
). Thus, if f
= 20Hz, the
L3dB
L3dB
time period to wait for a zero-crossing detect is 1/20Hz
or 50ms.
Volume Control
Volume control is programmable from -62dB to 0dB in
2dB steps through I2C interface. The block consists of
a resistive ladder network to generate 31 2dB volume
control steps, a unity gain buffer to isolate the input
from the resistive ladder, switches (MPLx and MNLx)
that select 1 of 32 nodes on the resistive ladder, and
logic to decode the the I2C volume control value. See
Table 12.
After the wait period, select a new audio source for the
TV audio channel by writing to bits 1 and 0 of TV Audio
Control register (01h). Finally, clear mute (Audio Control
register, 00h, bit 0), but leave ZCD (Audio Control reg-
ister 00h, bit 6) high. The MAX9670/MAX9671 switches
the signal out of mute at the next zero crossing. See
Tables 12 and 13.
______________________________________________________________________________________ 15
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
ACTIVITY DETECT
ACTIVITY DETECT
MAX9670/MAX9671
ACTIVITY DETECT
ACTIVITY DETECT
TV_Y/CVBS_IN
VCR_Y/CVBS_IN
ENC_Y/CVBS_IN
ENC_Y_IN
CLAMP
CLAMP
CLAMP
CLAMP
LOAD SENSE
A
= 2V/V
TV_Y/CVBS_OUT
V
LPF
LPF
MUTE
LOAD SENSE
A
A
= 2V/V
= 2V/V
VCR_Y/CVBS_OUT
TV_R/C_OUT
V
V
VCR_R/C_IN
ENC_R/C_IN
ENC_C_IN
CLAMP/BIAS
CLAMP/BIAS
CLAMP/BIAS
LPF
LPF
0/MAX9671
MUTE
A
= 2V/V
VCR_R/C_OUT
V
VCR_G_IN
ENC_G_IN
CLAMP
CLAMP
A
A
= 2V/V
= 2V/V
TV_G_OUT
TV_B_OUT
V
V
LPF
LPF
MUTE
MUTE
VCR_B_IN
ENC_B_IN
CLAMP
CLAMP
V
VID
A
A
= 1V/V
= 1V/V
TVOUT_FS
TV_SS
V
V
GNDVID
VCRIN_FS
0.7V
V
12
+6V
EP
2
TO I C
x1
V
12
A
= 1V/V
VCR_SS
V
+6V
EP
2
TO I C
x1
Figure 3. MAX9670/MAX9671 Video Section Function Diagram
the VCR SCART connector. It also routes slow-switch
and fast-switch control information. See Figure 3.
Video Section
The video circuit routes different video formats between
the set-top box decoder, the TV SCART connector, and
16 ______________________________________________________________________________________
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
0/MAX9671
Video Inputs
Whether the incoming video signal is AC-coupled or
DC-coupled into the MAX9670/MAX9671 depends
upon the origin, format, and voltage range of the video
signal. Table 1 below shows the recommended con-
nections. Always AC-couple an external video signal
through a 0.1µF capacitor because its voltage is not
well defined (see the Typical Application Circuit). For
example, the video transmitter circuit might have a dif-
ferent ground than the video receiver, thereby level
shifting the DC bias. 60Hz power line hum might cause
the video signal to change DC bias slowly.
In high-impedance mode, the inputs to the MAX9670/
MAX9671 do not distort the video signal in case the out-
puts of the video DAC are also connected to another
video circuit such as a high-definition video filter amplifi-
er. See the SCART Set-Top Box with Analog HD Outputs
section. The inputs in high-impedance mode are biased
at V /3, which is sufficiently above ground so that the
VID
ESD diodes never forward biases as the video signal
changes. The input resistance is 222kΩ, which presents
negligible loading on the video current DAC.
Video Reconstruction Filter
The video DAC outputs of the set-top box decoder chip
need to be lowpass-filtered to reject the out-of-band
noise. The MAX9670/MAX9671 integrate sixth-order,
Butterworth filters. The filter passband ( 1dB) is typical-
ly 5.5MHz, and the attenuation at 27MHz is 52dB. The
filters are suited for standard-definition video.
Internal video signals that are between 0 and 1V can be
DC-coupled. Most video DACs generate video signals
between 0 and 1V because the video DAC sources cur-
rent into a ground-referenced resistor. For the minority
of video DACs that generate video signals between
2.3V and 3.3V because the video DAC sinks current
from a V -referenced resistor, AC-couple the video
VID
signal to the MAX9670/MAX9671.
Video Outputs
The video output amplifiers can both source and sink
load current, allowing output loads to be DC- or AC-
coupled. The amplifier output stage needs around
300mV of headroom from either supply rail. For video
signals with a sync pulse, the sync tip is typically at
300mV, as shown in Figure 4. For a chroma signal, the
blank level is typically at 1.5V, as shown in Figure 5.
The MAX9670/MAX9671 restore the DC level of incom-
ing, AC-coupled video signals with either transparent
sync-tip clamps or bias circuits. When using an AC-
coupled input, the transparent sync-tip clamp automati-
cally clamps the input signal minimum to ground,
preventing it from going lower. A small current of 1µA
pulls down on the input to prevent an AC-coupled sig-
nal from drifting outside the input range of the part. Use
sync-tip clamps with CVBS, RGB, and luma signals.
If the supply voltage is greater than 3.135V (5% below
a 3.3V supply), each amplifier can drive two DC-cou-
pled video loads to ground. If the supply is less than
3.135V, each amplifier can drive only one DC-coupled
or AC-coupled video load.
The transparent sync-tip clamp is transparent when the
incoming video signal is DC-coupled and at or above
ground. Under such conditions, the clamp never acti-
vates. Therefore, the outputs of video DACs that gener-
ate signals between 0 and 1V can be directly
connected to the MAX9670/MAX9671 inputs.
The SCART standard allows for video signals to have a
superimposed DC component within 0 and 2V.
Therefore, most video signals are DC-coupled at the
output. In the unlikely event that the video signal needs
to be AC-coupled, the coupling capacitors should be
220µF or greater to keep the highpass filter formed by
the 37.5Ω equivalent resistance of the video transmis-
sion line to a corner frequency of 4.8Hz or below to keep
it well below the 25Hz frame rate of the PAL standard.
The bias circuit accepts AC-coupled chroma, which is
a subcarrier with the color information modulated onto
it. The bias voltage of the bias circuits is around
600mV.
ENC_R/C_IN and VCR_R/C_IN can receive either a red
video signal or a chroma video signal. Set the input con-
figuration by writing to bits 7 and 3 of the VCR Video
Input Control register (08h). See Tables 10 and 16.
The CVBS outputs have load sense circuits. If enabled,
each load sense circuit checks for a load eight times
per second by connecting an internal 15kΩ pullup
resistor to the output for 1ms. If the output is pulled up,
no load is present. If the output stays low, a load is con-
nected. Read bits 1 and 3 of the Video Activity Status
register (0Fh) to determine load status. See Table 21.
The MAX9670/MAX9671 also have video input detec-
tion. When activated, activity detect circuits check if
sync is present on incoming CVBS and luma (Y) sig-
nals. If so, then there is a valid video signal. Read bits
0, 2, 4, and 5 of the Video Activity Status register (0Fh)
to determine the status of the CVBS and luma (Y)
inputs. See Table 21.
The selection of video sources that are sent to the TV
SCART connector are controlled by bits 0 to 4 of the TV
Video Input Control register (06h) while the selection of
______________________________________________________________________________________ 17
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
video sources that are sent to the VCR SCART connec-
tor are controlled by bits 0 to 2 of the VCR Video Input
Control register (08h). See Tables 10, 14, and 16. The
video outputs can be enabled or disabled by bits 2
through 7 of the Output Enable register (0Dh). See
Table 18.
the fast-switching signal is just used to switch between
CVBS and RGB signal sources.
Set the source of the fast-switching signal by writing to
bits 4 and 3 of the TV Video Output Control register
(07h). The fast-switching signal to the TV SCART con-
nector can be enabled or disabled by bit 1 of the Output
Enable register (0Dh). See Tables 10, 15, and 18.
Slow Switching
The MAX9670/MAX9671 support the IEC 933-1,
Amendment 1, three-level slow switching that selects
the aspect ratio for the display (TV). Under I2C control,
the MAX9670/MAX9671 set the slow-switching output
voltage level. Table 2 shows the valid input levels of the
slow-switching signal and the corresponding operating
modes of the display device.
I2C Serial Interface
The MAX9670/MAX9671 feature an I2C/SMBus™-com-
patible, 2-wire serial interface consisting of a serial-data
line (SDA) and a serial-clock line (SCL). SDA and SCL
facilitate communication between the MAX9670/
MAX9671 and the master at clock rates up to 400kHz.
Figure 6 shows the 2-wire interface timing diagram. The
master generates SCL and initiates data transfer on the
bus. A master device writes data to the MAX9670/
MAX9671 by transmitting a START (S) condition, the
proper slave address with the R/W bit set to 0, followed
by the register address and then the data word. Each
transmit sequence is framed by a START and a STOP
(P) condition. Each word transmitted to the
MAX9670/MAX9671 is 8 bits long and is followed by an
acknowledge clock pulse. A master reads from the
MAX9670/MAX9671 by transmitting the slave address
with the R/W bit set to 0, the register address of the reg-
ister to be read, a REPEATED START (Sr) condition, the
slave address with the R/W bit set to 1, followed by a
series of SCL pulses. The MAX9670/MAX9671 transmit
data on SDA in sync with the master-generated SCL
pulses. The master acknowledges receipt of each byte
of data. Each read sequence is framed by a START or
Two bidirectional ports are available for slow-switching
signals for the TV and VCR. The slow-switching input
status is continuously read and stored in the Status reg-
ister (0Eh). The slow-switching outputs can be set to a
logic level or high impedance by writing to the TV Video
Output Control register (07h) and the VCR Video Output
Control register (09h). When enabled, INT becomes
active low if the voltage level changes on TV_SS or
VCR_SS. See Tables 10, 15, 17, and 20.
0/MAX9671
Fast Switching
The fast-switching signal was originally used to switch
between CVBS and RGB signals on a pixel-by-pixel
basis so that on-screen display (OSD) information
could be inserted. Since modern set-top box decoder
chips have integrated OSD circuitry, there is no need to
create OSD information using the older technique. Now,
MAX9670 fig05
MAX9670 fig04
INPUT
200mV/div
INPUT
500mV/div
OUTPUT
500mV/div
OUTPUT
200mV/div
10µs/div
20µs/div
Figure 5. MAX9670/MAX9671 Video Output with Chroma (C)
Signal, Multiburst Video Test Signal Shown
Figure 4. MAX9670/MAX9671 Video Output with CVBS Signal,
Multiburst Video Test Signal Shown
18 ______________________________________________________________________________________
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
0/MAX9671
SDA
SCL
t
BUF
t
t
SU, STA
SU, DAT
t
t
SP
HD, STA
t
t
SU, STO
t
HD, DAT
LOW
t
HIGH
t
HD, STA
t
t
F
R
REPEATED
START CONDITION
STOP
CONDITION
START
CONDITION
START
CONDITION
Figure 6. I2C Serial-Interface Timing Diagram
REPEATED START condition, an acknowledge or a not
acknowledge, and a STOP condition. SDA operates as
both an input and an open-drain output. A pullup resis-
tor, typically greater than 500Ω, is required on the SDA
bus. SCL operates as only an input. A pullup resistor,
typically greater than 500Ω, is required on SCL if there
are multiple masters on the bus, or if the master in a
single-master system has an open-drain SCL output.
Series resistors in line with SDA and SCL are optional.
Series resistors protect the digital inputs of the
MAX9670/MAX9671 from high-voltage spikes on the
bus lines, and minimize crosstalk and undershoot of the
bus signals.
S
Sr
P
SCL
SDA
Figure 7. START, STOP, and REPEATED START Conditions
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the START and STOP
Conditions section). SDA and SCL idle high when the
I2C bus is not busy.
Early STOP Conditions
The MAX9670/MAX9671 recognize a STOP condition at
any point during data transmission except if the STOP
condition occurs in the same high pulse as a START
condition. For proper operation, do not send a STOP
condition during the same SCL high pulse as the
START condition.
START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START
condition. A START condition is a high-to-low transition
on SDA with SCL high. A STOP condition is a low-to-
high transition on SDA while SCL is high (Figure 7). A
START condition from the master signals the beginning
of a transmission to the MAX9670/MAX9671. The mas-
ter terminates transmission, and frees the bus, by issu-
ing a STOP condition. The bus remains active if a
REPEATED START condition is generated instead of a
STOP condition.
Slave Address
The slave address is defined as the 7 most significant
bits (MSBs) followed by the read/write (R/W) bit. Set the
R/W bit to 1 to configure the MAX9670/MAX9671 to
read mode. Set the R/W bit to 0 to configure the
MAX9670/MAX9671 to write mode. The slave address
is always the first byte of information sent to the
MAX9670/MAX9671 after a START or a REPEATED
START condition. The MAX9670/MAX9671 slave
address is configurable with DEV_ADDR. Table 3
shows the possible slave addresses for the
MAX9670/MAX9671.
______________________________________________________________________________________ 19
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX9670/MAX9671 use to handshake receipt of each
byte of data when in write mode (see Figure 8). The
MAX9670/MAX9671 pull down SDA during the entire
master-generated ninth clock pulse if the previous byte
is successfully received. Monitoring ACK allows for
detection of unsuccessful data transfers. An unsuc-
cessful data transfer occurs if a receiving device is
busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master may retry
communication. The master pulls down SDA during the
ninth clock cycle to acknowledge receipt of data when
the MAX9670/MAX9671 are in read mode. An acknowl-
edge is sent by the master after each read byte to allow
data transfer to continue. A not acknowledge is sent
when the master reads the final byte of data from the
MAX9670/MAX9671, followed by a STOP condition.
Write Data Format
A write to the MAX9670/MAX9671 consists of transmit-
ting a START condition, the slave address with the R/W
bit set to 0, one data byte to configure the internal reg-
ister address pointer, one or more data bytes, and a
STOP condition. Figure 9 illustrates the proper frame
format for writing one byte of data to the
MAX9670/MAX9671. Figure 10 illustrates the frame for-
mat for writing n bytes of data to the MAX9670/
MAX9671.
CLOCK PULSE FOR
ACKNOWLEDGMENT
START
The slave address with the R/W bit set to 0 indicates
that the master intends to write data to the MAX9670/
MAX9671. The MAX9670/MAX9671 acknowledge
receipt of the address byte during the master-generat-
ed ninth SCL pulse.
CONDITION
SCL
1
2
8
9
0/MAX9671
NOT ACKNOWLEDGE
The second byte transmitted from the master config-
ures the MAX9670/MAX9671’s internal register address
pointer. The pointer tells the MAX9670/MAX9671 where
to write the next byte of data. An acknowledge pulse is
sent by the MAX9670/MAX9671 upon receipt of the
address pointer data.
SDA
ACKNOWLEDGE
Figure 8. Acknowledge
ACKNOWLEDGE FROM MAX9670/MAX9671
B7 B6 B5 B4 B3 B2 B1 B0
ACKNOWLEDGE FROM MAX9670/MAX9671
ACKNOWLEDGE FROM MAX9670/MAX9671
REGISTER ADDRESS
A
P
S
SLAVE ADDRESS
0
A
A
DATA BYTE
1 BYTE
R/W
Figure 9. Writing a Byte of Data to the MAX9670/MAX9671
ACKNOWLEDGE FROM
MAX9670/MAX9671
ACKNOWLEDGE FROM
MAX9670/MAX9671
ACKNOWLEDGE FROM MAX9670/MAX9671
ACKNOWLEDGE FROM MAX9670/MAX9671
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
S
SLAVE ADDRESS
0
A
A
A
REGISTER ADDRESS
DATA BYTE 1
1 BYTE
DATA BYTE n
1 BYTE
A
P
R/W
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 10. Writing n Bytes of Data to the MAX9670/MAX9671
20 ______________________________________________________________________________________
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
0/MAX9671
NOT ACKNOWLEDGE FROM MASTER
ACKNOWLEDGE FROM
MAX9670/MAX9671
ACKNOWLEDGE FROM
MAX9670/MAX9671
ACKNOWLEDGE FROM
MAX9670/MAX9671
A
P
S
SLAVE ADDRESS
0
A
REGISTER ADDRESS
A
Sr
SLAVE ADDRESS
R/W
1
A
DATA BYTE
1 BYTE
R/W
REPEATED START
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 11. Reading One Indexed Byte of Data from the MAX9670/MAX9671
ACKNOWLEDGE FROM
MAX9670/MAX9671
ACKNOWLEDGE FROM
MAX9670/MAX9671
ACKNOWLEDGE FROM
MAX9670/MAX9671
NOT ACKNOWLEDGE FROM MASTER
A
P
S
SLAVE ADDRESS
0
A
REGISTER ADDRESS
A
Sr
SLAVE ADDRESS
1
A
DATA BYTE
1 BYTE
R/W
REPEATED START
R/W
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 12. Reading n Bytes of Indexed Data from the MAX9670/MAX9671
The third byte sent to the MAX9670/MAX9671 contains
the data that is written to the chosen register. An
acknowledge pulse from the MAX9670/MAX9671 sig-
nals receipt of the data byte. The address pointer
autoincrements to the next register address after each
received data byte. This autoincrement feature allows a
master to write to sequential register address locations
within one continuous frame. The master signals the
end of transmission by issuing a STOP condition.
addresses higher than 10h results in repeated reads
from a dummy register containing FFh data. The master
acknowledges receipt of each read byte during the
acknowledge clock pulse. The master must acknowl-
edge all correctly received bytes except the last byte.
The final byte must be followed by a not acknowledge
from the master and then a STOP condition. Figures 11
and 12 illustrate the frame format for reading data from
the MAX9670/MAX9671.
Read Data Format
The master presets the address pointer by first sending
the MAX9670/MAX9671’s slave address with the R/W
bit set to 0 followed by the register address after a
START condition. The MAX9670/MAX9671 acknowl-
edges receipt of its slave address and the register
address by pulling SDA low during the ninth SCL clock
pulse. A REPEATED START condition is then sent fol-
lowed by the slave address with the R/W bit set to 1.
The MAX9670/MAX9671 transmits the contents of the
specified register. Transmitted data is valid on the ris-
ing edge of the master-generated serial clock (SCL).
The address pointer autoincrements after each read
data byte. This autoincrement feature allows all regis-
ters to be read sequentially within one continuous
frame. A STOP condition can be issued after any num-
ber of read data bytes. If a STOP condition is issued
followed by another read operation, the first data byte
to be read is from the register address location set by
the previous transaction and not 00h and subsequent
reads autoincrement the address pointer until the next
STOP condition. Attempting to read from register
Interrupt Output
When interrupt is enabled in modes 1 and 2, INT, which
is an open-drain output, pulls low under the following
conditions: slow-switch signals change value, CVBS
input signals are detected or disappear, and CVBS out-
put loads are added or removed.
When interrupt is enabled in mode 3, INT pulls low only
when the slow-switch signal changes value.
Enable INT by writing a 1 into bit 4 of register 01h. See
Table 13.
The interrupt can be cleared by reading register 0Eh
and 0Fh.
Applications Information
Audio Inputs
The maximum full-scale audio signal that can be
applied to the audio inputs is 0.5V
biased at
RMS
ground. The recommended application circuit to atten-
uate and bias an incoming audio signal is shown in
Figure 13.
______________________________________________________________________________________ 21
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
considers this condition to be illegal and does not loop
through any signals.
STEREO
AUDIO
DACS
A finite state machine (Figure 14) controls the operation
MAX9670
1µF
of the MAX9670/MAX9671. State 0 is always the initial
state when the MAX9670/MAX9671 enter standby
mode. Table 4 shows the values of the I2C registers in
state 0. The state machine sets the other I2C registers
to the correct values to loop through the audio/video
signals in states 1 and 2 (see Tables 5 and 6). When
the MAX9670/MAX9671 leaves standby mode, the val-
ues in all of the I2C registers except register 10h are
preserved so that the operation is not disturbed. For
example, if in standby mode, the MAX9670 is looping
through the audio/video signals from VCR SCART to TV
SCART, and if the microcontroller changes the operat-
ing mode from standby mode to full-power mode, the
audio/video signals continue to be looped through dur-
ing and after the mode change. The user does not
experience any disruption in audio or video service.
6.65kΩ
6.65kΩ
ENC_INL
R1*
R1*
1µF
ENC_INR
*R1 VALUES
DAC = CS4334/5/8/9: R1 = 4.53kΩ, 1%
DAC = PCM1742: R1 = 5.57kΩ, 1%
Figure 13. Application circuit to connect audio source to audio
inputs. The 1µF capacitor connected to the ground-referenced
resistors biases the audio signal at ground. The resistors atten-
uate the audio signal.
0/MAX9671
The microcontroller can be turned off in standby mode
because the MAX9670/MAX9671 operate autonomous-
ly. Upon power-up, the default operating mode is
standby mode.
The audio path has a gain of 4V/V so that the full scale
of the audio output signal is 2V
. If less than 2V
,
RMS
RMS
full scale is desired at the audio outputs, and the full
scale of the audio input signal should be proportionate-
Full-Power Mode with Video Input Detection
and Video Load Detection
ly decreased below 0.5V
.
RMS
In this mode, the MAX9670/MAX9671 are fully on. If
interrupt is enabled, INT goes active low whenever the
slow-switch signal changes; a CVBS signal appears or
disappears; or a CVBS load appears or disappears.
The microcontroller can decide whether to change the
routing configuration or operating mode of the
MAX9670/MAX9671.
Operating Modes
The MAX9670/MAX9671 has four operating modes,
which can be set by writing to bits 6 and 7 of register
10h. See Table 19.
Shutdown
All circuitry is shutdown in the MAX9670/MAX9671
except for the I2C interface, which is designed with sta-
tic CMOS logic. Except for register 10h, which sets the
operating mode, the values in all of the other I2C regis-
ters are preserved while entering, during, and leaving
shutdown mode.
Full-Power Mode Without Video Input Detection
and Video Load Detection
This mode is similar to the above mode except that
video input detection and video load detection are not
active. If interrupt is enabled, INT goes active low only
when the slow-switch signal changes.
Standby Mode
In standby mode, the MAX9670/MAX9671 monitor the
slow-switch signals and decide whether to loop through
the audio/video signals. If the VCR slow switch input
has activity (6V or 12V at the input), the audio/video sig-
nals are looped through from the VCR SCART to the TV
SCART. If the TV slow-switch input has activity, the
audio/video signals are looped through from the TV
SCART to the VCR SCART. If neither the VCR slow-
switch input nor the TV slow switch input show activity,
i.e., both inputs are at ground, no signals are looped
through. If both the VCR slow-switch input and the TV
slow-switch input have activity, the MAX9670/MAX9671
Power Consumption
The quiescent power consumption and average power
consumption of the MAX9670/MAX9671 are very low
because of 3.3V operation and low-power circuit design.
Quiescent power consumption is defined when the
MAX9670/MAX9671 are operating without loads and
without any audio or video signals. Table 7 shows the
quiescent power consumption in all 4 operating modes.
Average power consumption is defined when the MAX9670/
MAX9671 drives typical signals into typical loads. Table 8
shows the average power consumption in full-power
mode and Table 9 shows the input and output conditions.
22 ______________________________________________________________________________________
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
0/MAX9671
TV_SS ACTIVE
TV_SS NOT ACTIVE
VCR_SS ACTIVE
VCR_SS NOT ACTIVE
STATE 0
SEARCH
AUDIO: INACTIVE
VIDEO: INACTIVE
SLOW SWITCH: LISTENING FOR ACTIVITY
FAST SWITCH: INACTIVE
TV_SS ACTIVE
VCR_SS NOT ACTIVE
TV_SS NOT ACTIVE
VCR_SS ACTIVE
TV_SS NOT ACTIVE
VCR_SS NOT ACTIVE
TV_SS NOT ACTIVE
VCR_SS NOT ACTIVE
TV_SS ACTIVE
VCR_SS NOT ACTIVE
TV_SS NOT ACTIVE
VCR_SS ACTIVE
STATE 1
TV-TO-VCR
STATE 2
VCR-TO-TV
AUDIO: TV TO VCR
VIDEO: TV TO VCR
SLOW SWITCH: TV TO VCR
FAST SWITCH: NOT APPLICABLE
AUDIO: VCR TO TV
VIDEO: VCR TO TV
SLOW SWITCH: VCR TO TV
FAST SWITCH: VCR TO TV
TV_SS ACTIVE
VCR_SS ACTIVE
TV_SS ACTIVE
VCR_SS ACTIVE
TV_SS NOT ACTIVE
VCR_SS ACTIVE
TV_SS ACTIVE
VCR_SS NOT ACTIVE
Figure 14. Standby mode finite state machine. TV_SS is active when either 6V or 12V are present. VCR_SS is active when either 6V
or 12V are present.
red signal. The pins that can carry both CVBS and luma
have Y/CVBS in their names, and the pins that can
carry red and chroma have R/C in their names.
S-Video
The MAX9670/MAX9671 support S-video from the set-
top box to the TV, set-top box to the VCR, and VCR to
the set-top box. S-video was not included in the original
SCART specifications but was added afterwards. As a
consequence, the luma (Y) signal of S-video shares the
same SCART pin as the CVBS signal. Likewise, the
chroma (C) signal shares the same SCART pin as the
Now, the Y/CVBS signals are full duplex while the R/C
signals are half duplex. Therefore, S-video is limited to
being half duplex. The MAX9670/MAX9671 have to
transmit a chroma signal and receive a chroma signal
______________________________________________________________________________________ 23
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
0.1µF
VCR_R/C_IN
75Ω
BIAS
BIAS
BIAS
TV_R/C_OUT
TV
SCART
A
= 2V/V
V
ENC_R/C_IN
ENC_C_IN
LPF
LPF
75Ω
VCR_R/C_OUT
VCR
SCART
A
= 2V/V
ON
V
MAX9670/MAX9671
0/MAX9671
Figure 15. Gain-of-2 amplifier on VCR_R/C_OUT outputs chroma signal to VCR SCART connector. Notice that the pulldown switch on
VCR_R/C_OUT is open.
0.1µF
VCR_R/C_IN
75Ω
75Ω
BIAS
BIAS
BIAS
TV_R/C_OUT
TV
SCART
A = 2V/V
V
ENC_R/C_IN
ENC_C_IN
LPF
LPF
VCR_R/C_OUT
VCR
SCART
A = 2V/V
V
MAX9670/MAX9671
OFF
Figure 16. VCR_R/C_IN receives chroma signal from VCR SCART connector. Notice that the pulldown switch on VCR_R/C_OUT is
closed and that the gain-of-2 amplifier is off. The chroma signal from VCR SCART is looped through to the TV SCART in the above
configuration.
on the same SCART pin, but not at the same time. The
75Ω resistor connected to VCR_R/C_OUT must act as a
back termination resistor when the MAX9670/MAX9671
is transmitting chroma signal and as an input termina-
tion resistor when it is receiving a chroma signal. Figure
15 shows how the MAX9670/MAX9671 transmits a
chroma signal to the VCR SCART connector while
Figure 16 shows how the MAX9670/MAX9671 receives
a chroma from the VCR SCART connector.
Write a 0 into bit 2 of register 09h to open the pulldown
switch at VCR_R/C_OUT. To close the pulldown switch,
write a 0 into bit 6 of register 0Dh to turn off the output
amplifier, and then write a 1 into bit 2 of register 09h.
See Tables 17 and 18.
24 ______________________________________________________________________________________
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
0/MAX9671
TV_OUTR
10kΩ
MAX9670/MAX9671
MONO AUDIO
10kΩ
TV
SCART
TV_OUTL
75Ω
TV_Y/CVBS_OUT
75Ω OR GREATER
75Ω OR GREATER
RF
MODULATOR
Figure 17. Application Circuit to Connect CVBS and Mono Audio from TV SCART to RF Modulator
To better protect the MAX9670/MAX9671 against
Interfacing to an RF Modulator
If the set-top box modulates CVBS and mono audio
onto an RF carrier (for example, channel 3), a simple
application circuit can provide the needed signals (see
Figure 17). 10kΩ resistor summer circuit between
TV_OUTR and TV_OUTL creates the mono audio sig-
nal. The resistor-divider to ground on TV_Y/CVBS_OUT
creates a video signal with normal amplitude. The
unique feature of the MAX9670/MAX9671 that facilitates
this application circuit is that the audio and video out-
put amplifiers of the MAX9670/MAX9671 can drive mul-
excess voltages during the cable discharge condition
or ESD events, add series resistors to all inputs and
outputs to the SCART connector if series resistors are
not already present in the application circuit. Also, add
external ESD protection diodes (for example, BAV99)
on all inputs and outputs to the SCART connector.
SCART Set-Top Box
with Analog HD Outputs
In set-top boxes with SCART connectors and cinch
connectors for high-definition YPbPr outputs, a triple-
video DAC usually outputs either standard-definition
RGB signals that are routed to the MAX9670/MAX9671
or high-definition YPbPr signals that are routed through
a high-definition filter amplifier like the MAX9653 (see
Figure 19). The set-top box devices have a limited num-
ber of video DACs, and hence, one bank of triple-video
DACs switches video format depending upon whether
standard-definition RGB or high-definition YPbPr sig-
nals are required.
tiple loads if V
3.135V.
and V
are both greater than
VID
AUD
Unconnected-Chassis Discharge
Protection and ESD
Some set-top boxes are not connected to earth ground.
As a result, the chassis can charge up to 500V. When a
SCART cable is connected to the SCART connector,
the charged chassis can discharge through a signal
pin. The equivalent circuit is a 2200pF capacitor
charged to 311V connected through less than 0.1Ω to a
signal pin. The MAX9670/MAX9671 are soldered on the
PCB when it experiences such a discharge. Therefore,
the current spike flows through both external and inter-
nal ESD protection devices and is absorbed by the
supply bypass capacitors, which have high capaci-
tance and low ESR.
When RGB signals are desired, the high-definition filter
amplifier should be turned off so that the RGB signals
do not appear on the YPbPr connectors. The
MAX9653/MAX9654 are well-suited for this application
because their video inputs are in high-impedance
mode when in shutdown.
______________________________________________________________________________________ 25
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
12V
3.3V
3.3V
0.1µF
0.1µF
0.1µF
V
AUD
V
V
VID
V
12
AUD
1µF
1µF
7.68kΩ
TV_INL
(MAX9671 ONLY)
CPVSS
V
AUD
2.55kΩ
7.68kΩ
+3.3 V
TV_INR
(MAX9671 ONLY)
STB CHIP
V
AUD
CPVSS
2.55kΩ
75Ω
SDA
SCL
TV_OUTR
TV_OUTL
MICRO-
CONTROLLER
V
AUD
75Ω
75Ω
CPVSS
INT
V
12
DEV_ADDR
CPVSS
TV_SS
V
VID
75Ω
75Ω
75Ω
75Ω
75Ω
TV
SCART
EP
TV_B_OUT
TV_G_OUT
TV_R/C_OUT
TVOUT_FS
VIDEO ENCODER
V
VID
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
ENC_Y/CVBS_IN
ENC_R/C_IN
GNDVID
V
VID
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
GNDVID
V
VID
0/MAX9671
GNDVID
ENC_G_IN
ENC_B_IN
ENC_Y_IN
ENC_C_IN
V
VID
GNDVID
TV_Y/CVBS_OUT
TV_Y/CVBS_IN
V
VID
0.1µF
75Ω
GNDVID
MAX9670
MAX9671
75Ω
AUD
GNDVID
V
GNDVID
75Ω
VCR_OUTR
V
AUD
1µF
1µF
7.68kΩ
CPVSS
VCR_INR
CPVSS
V
STEREO
AUDIO DACS
AUD
2.55kΩ
75Ω
1µF
6.65kΩ
VCR_OUTL
VCR_INL
ENC_INL
ENC_INR
V
AUD
7.68kΩ
CPVSS
R1*
CPVSS
V
12
2.55kΩ
75Ω
1µF
VCR
SCART
6.65kΩ
VCR_SS
V
VID
0.1µF
75Ω
EP
R1*
VCR_B_IN
75Ω
75Ω
GNDVID
V
VID
0.1µF
75Ω
75Ω
VCR_G_IN
GNDVID
V
VID
0.1µF
VCR_R/C_IN
VCR_R/C_OUT
VCRIN_FS
V
VID
GNDVID
V
*R1 VALUES
DAC = CS4334/5/8/9: R1 = 4.53kΩ 1%
DAC = PCM1742: R1 = 5.57kΩ 1%
VID
75Ω
GNDVID
V
VID
75Ω
75Ω
GNDVID
VCR_Y/CVBS_OUT
VCR_Y/CVBS_IN
V
VID
GNDVID
0.1µF
EP
C1P
C1N CPVSS
75Ω
75Ω
GNDVID
1µF
1µF
Figure 18. Application Circuit to Connect Series Resistors and External ESD Protection Diodes at MAX9670/MAX9671 Outputs
26 ______________________________________________________________________________________
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
0/MAX9671
MAX9670/MAX9671
MAX9670/MAX9671
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
ENC_R/C_IN TV_R/C_OUT
ENC_R/C_IN TV_R/C_OUT
SCART
SCART
CONNECTOR
ENC_G_IN
ENC_B_IN
TV_G_OUT
TV_B_OUT
ENC_G_IN
ENC_B_IN
TV_G_OUT
TV_B_OUT
CONNECTOR
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
SET-TOP BOX
CHIP
SET-TOP BOX
CHIP
INPUTS SET TO SYNC-TIP CLAMP
INPUTS SET TO HIGH IMPEDANCE
DAC
DAC
DAC
DAC
DAC
DAC
MAX9653
MAX9654
MAX9653
MAX9654
0.1µF
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
YOUT
YIN
YOUT
YIN
0.1µF
0.1µF
PBOUT
PBOUT
YPbPr OUTPUTS
PBIN
PBIN
YPbPr OUTPUTS
PRIN
PROUT
PRIN
PROUT
3.3V
SHDN
SHDN
OFF
ON
(A)
(B)
Figure 19. Triple DAC is connected to both a MAX9670/MAX9671 and a MAX9653/MAX9654 high-definition video-filter amplifier. (A)
The MAX9670/MAX9671 are transmitting standard-definition RGB signals while the MAX9653/MAX9654 are in shutdown mode. (B)
The MAX9670/MAX9671 are not transmitting RGB signals, but the MAX9653/MAX9654 are transmitting high-definition YPbPr signals.
Similarly, when YPbPr signals are desired, ENC_R/C_IN,
ENC_G_IN, and ENC_B_IN of the MAX9670/MAX9671
should be set to high-impedance mode by setting bit 4 in
register 08h to high if those video inputs are AC-coupled.
The high-impedance mode has higher priority whether
ENC_R/C_IN is in sync-tip clamp or bias circuit mode
(set by bit 3 in register 08h). If ENC_R/C_IN, ENC_G_IN,
and ENC_B_IN are DC-coupled, the inputs should be left
in sync-tip clamp mode. The RGB outputs of the
MAX9670/MAX9671 should be muted or shut down.
and stripes appear on the television screen, increase
the supply bypass capacitance. An additional, smaller
capacitor in parallel with the main bypass capacitor
can reduce digital supply noise because the smaller
capacitor has lower equivalent series resistance (ESR)
and equivalent series inductance (ESL).
Layout and Grounding
For optimal performance, use controlled-impedance
traces for video signal paths and place input termina-
tion resistors and output back-termination resistors
close to the MAX9670/MAX9671. Avoid routing video
traces parallel to high-speed data lines.
In either case, the inactive device should not distort the
video signals generated by the DACs.
Power-Supply Bypassing
The MAX9670/MAX9671 feature single 3.3V and 12V
supply operation and require no negative supply. The
The MAX9670/MAX9671 provide separate ground con-
nections for video and audio supplies. For best perfor-
mance, use separate ground planes for each of the
ground returns and connect all ground planes together
at a single point. See the MAX9670/MAX9671 evalua-
tion kit for a proven circuit board layout example.
12V supply V is for the SCART switching function. For
12
V
12
, place a 0.1µF bypass capacitor as close as possi-
ble. Connect all V
pins together to 3.3V and bypass
AUD
with a 10µF electrolytic capacitor in parallel with a
0.1µF ceramic capacitor to audio ground. Bypass each
VID
If the MAX9670/MAX9671 are mounted using flow sol-
dering or wave soldering, the ground via(s) for the EP
pad should have a finished hole size of at least 14mils
to insure adequate wicking of soldering onto the
exposed pad. If the MAX9670/MAX9671 are mounted
using solder mask technique, the via requirement does
not apply. In either case, a good connection between
the exposed pad and ground is required to minimize
noise from coupling onto the outputs.
V
to video ground with a 0.1µF ceramic capacitor.
Using a Digital Supply
The MAX9670/MAX9671 are designed to operate from
noisy digital supplies. The high PSRR (49dB at 100kHz)
allows the MAX9670/MAX9671 to reject the noise from
the digital power supplies (see the Typical Operating
Characteristics). If the digital power supply is very noisy
______________________________________________________________________________________ 27
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
Table 1. Recommended Coupling for Incoming Video Signals and Input Circuit
Configuration*
VIDEO ORIGIN
External
External
External
External
Internal
FORMAT
CVBS
RGB
Y
VOLTAGE RANGE
Unknown
Unknown
Unknown
Unknown
0 to 1V
COUPLING
AC
INPUT CIRCUIT CONFIGURATION
Transparent sync-tip clamp
Transparent sync-tip clamp
Transparent sync-tip clamp
Bias circuit
AC
AC
C
AC
CVBS
RGB
Y/C
DC
Transparent sync-tip clamp
Transparent sync-tip clamp
Transparent sync-tip clamp
Transparent sync-tip clamp
Transparent sync-tip clamp
Transparent sync-tip clamp
Transparent sync-tip clamp
Bias circuit
Internal
0 to 1V
DC
Internal
0 to 1V
DC
Internal
YPbPr
CVBS
RGB
Y
0 to 1V
DC
Internal
2.3V to 3.3V
2.3V to 3.3V
2.3V to 3.3V
2.3V to 3.3V
AC
Internal
AC
Internal
AC
0/MAX9671
Internal
C
AC
*Use a 0.1µF capacitor to AC-couple a video signal into the MAX9670/MAX9671.
Table 2. Slow-Switching Modes
SLOW-SWITCHING
SIGNAL VOLTAGE
(V)
MODE
Display device uses an internal
source such as a built-in tuner to
provide a video signal.
0 to 2
Display device uses a video signal
from the SCART connector and sets
the display to 16:9 aspect ratio.
4.5 to 7.0
9.5 to 12.6
Display device uses a signal from the
SCART connector and sets the
display to 4:3 aspect ratio.
28 ______________________________________________________________________________________
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
0/MAX9671
Table 3. Slave Address
WRITE ADDRESS
READ ADDRESS
DEV_ADDR
B7
B6
B5
B4
B3
B2
B1
B0
(hex)
94h
96h
98h
9Ah
(hex)
95h
97h
99h
9Bh
GNDVID
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
0
0
0
1
0
1
R/W
R/W
R/W
R/W
V
VID
SCL
SDA
2
2
Table 4. I C Register Values in State 0*
Table 5. I C Register Values in State 1*
REGISTER ADDRESS
VALUE (binary)
REGISTER ADDRESS
VALUE (binary)
(hexadecimal)
(hexadecimal)
00h
01h
06h
07h
08h
09h
0Dh
uuuu uuu0
uuuu 1011
uuuu uuuu
uuu0 0u10
uuuu u011
uuuu u0MM
1100 001u
00h
01h
06h
07h
08h
09h
0Dh
uuuu uuuu
uuuu 1111
uuuu uuuu
uuuu uu10
uuuu uuuu
uuuu u010
0000 000u
*u indicates that the bit is unchanged from its previous state.
*u indicates that the bit is unchanged from its previous state;
MM = Register 0Eh (bit 1, bit 0)
2
Table 6. I C Register Values in State 2*
REGISTER ADDRESS
VALUE (binary)
(hexadecimal)
00h
01h
06h
07h
08h
09h
0Dh
uuuu uuu0
uuuu 1101
uuu0 1010
uuu0 0uNN
uuuu uuuu
uuuu u110
0011 111u
*u indicates that the bit is unchanged from its previous state;
NN = Register 0Eh (bit 3, bit 2)
______________________________________________________________________________________ 29
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
Table 7. Quiescent Power Consumption
Table 8. Average Power Consumption
POWER CONSUMPTION
POWER CONSUMPTION
OPERATING MODE
(mW)
OPERATING MODE
(mW)
Shutdown
0.13
Full-power mode with input video
Standby mode with no video
activity (i.e., TV slow-switch and
VCR slow-switch inputs are at
ground). Standby mode is the
power-on default.
detection and video load
detection active.
300
300
2.83
Full-power mode without input
video detection and video load
detection active.
Full-power mode with input video
detection and video load
detection active.
66
65
Full-power mode without input
video detection and video load
detection active.
0/MAX9671
Table 9. Conditions for Average Power Consumption Measurement
PIN (MAX9670)
NAME
TYPE
Supply
Input
SIGNAL
LOAD
5
V
3.3V
N/A
AUD
9
ENC_INL
ENC_INR
VCR_INL
VCR_INR
TV_OUTL
VCR_OUTL
VCR_OUTR
TV_OUTR
TV_SS
0.25V
, 1kHz
N/A
RMS
RMS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Input
0.25V
, 1kHz
N/A
Input
None
None
N/A
Input
N/A
10kΩ to ground
10kΩ to ground
10kΩ to ground
10kΩ to ground
10kΩ to ground
N/A
Output
Output
Output
Output
Output
Supply
Input
1V
1V
1V
1V
, 1kHz
RMS
RMS
RMS
RMS
, 1kHz
, 1kHz
, 1kHz
12V
V
12V
0
12
VCR_SS
TVOUT_FS
VCRIN_FS
ENC_B_IN
ENC_G_IN
VCR_B_IN
VCR_G_IN
TV_B_OUT
TV_G_OUT
GNDVID
N/A
Output
Input
3.3V
0
150Ω to ground
N/A
Input
50% flat field
50% flat field
None
N/A
Input
N/A
Input
N/A
Input
None
N/A
Output
Output
Supply
Input
50% flat field
50% flat field
0
150Ω to ground
150Ω to ground
N/A
VCR_R/C_IN
None
N/A
V
Supply
3.3V
N/A
VID
30 ______________________________________________________________________________________
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
0/MAX9671
Table 9. Conditions for Average Power Consumption Measurement (continued)
PIN (MAX9670)
NAME
TYPE
Input
SIGNAL
None
LOAD
N/A
31
32
33
34
35
36
37
38
39
40
ENC_C_IN
ENC_R/C_IN
Input
50% flat field
50% flat field
50% flat field
50% flat field
50% flat field
None
N/A
TV_R/C_OUT
Output
Output
Output
Output
Input
150Ω to ground
150Ω to ground
150Ω to ground
150Ω to ground
N/A
VCR_R/C_OUT
VCR_Y/CVBS_OUT
TV_Y/CVBS_OUT
VCR_Y/CVBS_IN
TV_Y/CVBS_IN
ENC_Y_IN
Input
None
N/A
Input
None
N/A
ENC_Y/CVBS_IN
Input
50% flat field
N/A
Table 10. Data Format for Write Mode
REGISTER
ADDRESS (hex)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
TV volume control
BIT 2
BIT 1
BIT 0
TV audio
output mute
00h
Not used
TV ZCD
Interrupt
enable
01h
Not used
VCR audio selection
TV audio selection
02h
03h
04h
05h
06h
07h
Not used
Not used
Not used
Not used
Not used
Not used
TV G and B video switch
Set TV fast switching
ENC R/G/B
TV video switch
Not used
Set TV slow switching
VCR_R/C_IN
clamp
ENC_R/C_IN
clamp
high-
impedance
bias
08h
Not used
VCR video switch
VCR_R/C_OUT
ground
Set VCR slow
switching
09h
Not used
0Ah
0Bh
0Ch
Not used
Not used
Not used
VCR_Y/
CVBS_OUT
enable
VCR_R/
C_OUT
enable
TV_R/
C_OUT
enable
TV_Y/
CVBS_OUT
enable
TV_G_OUT TV_B_OUT
TVOUT_FS
enable
0Dh
10h
Not used
enable
enable
Operating mode
Not used
______________________________________________________________________________________ 31
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
Table 11. Data Format for Read Mode
REGISTER
ADDRESS (hex)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Power-on
reset
VCR slow-switch input
status
TV slow switch input
status
0Eh
Not used
Not used
ENC_Y/
CVBS_IN
input video
detection
ENC_Y_IN
input video
detection
VCR CVBS
VCR CVBS
TV CVBS
TV CVBS
input video
input video
0Fh
Not used
output load
output load
detection
detection
Table 12. Register 00h: Audio Control
BIT
DESCRIPTION
COMMENTS
7
6
5
4
3
2
1
0
0
1
Off
TV Audio Mute
On (power-on default)
0dB gain (power-on default)
-2dB gain
0/MAX9671
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
-4dB gain
-6dB gain
-8dB gain
-10dB gain
TV Volume Control
1
1
1
1
1
1
1
1
0
1
-60dB gain
-62dB gain
Off
0
1
TV Zero-Crossing Detector
On (power-on default)
Table 13. Register 01h: TV Audio
BIT
DESCRIPTION
COMMENTS
7
6
5
4
3
2
1
0
0
1
1
0
0
1
0
1
Encoder audio
VCR audio
Input Source for TV Audio
TV audio (MAX9671 only)
Mute (power-on default)
Encoder audio
0
0
1
1
0
1
0
1
VCR audio
Input Source for VCR Audio
Interrupt Enable
TV audio (MAX9671 only)
Mute (power-on default)
Disabled (power-on default)
Enabled
0
1
32 ______________________________________________________________________________________
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
0/MAX9671
Table 14. Register 06h: TV Video Input Control
BIT
DESCRIPTION
COMMENTS
TV_Y/CVBS_OUT
7
6
5
4
3
2
1
0
TV_R/C_OUT
ENC_R/C_IN
ENC_C_IN
VCR_R/C_IN
Mute
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
ENC_Y/CVBS_IN
ENC_Y_IN
VCR_Y/CVBS_IN
TV_Y/CVBS_IN
Not used
Input Sources for TV Video
Not used
Mute
Mute
Mute
Mute
Mute (power-on
default)
Mute (power-on
default)
1
1
1
TV_G_OUT
ENC_G_IN
VCR_G_IN
Mute
TV_B_OUT
ENC_B_IN
VCR_B_IN
Mute
0
0
1
0
1
0
Input Sources for TV_G_OUT and TV_B_OUT
Mute (power-on
default)
Mute (power-on
default)
1
1
Table 15. Register 07h: TV Video Output Control
BIT
DESCRIPTION
COMMENTS
7
6
5
4
3
2
1
0
0
0
Low (< 2V) internal source
Medium (4.5V to 7V); external SCART
source with 16:9 aspect ratio
0
1
1
1
0
1
Set TV Slow Switching
Set TV Fast Switching
High impedance (power-on default)
High (> 9.5V); external SCART source
with 4:3 aspect ratio
0
0
1
1
0
1
0
1
GNDVID (power-on default)
Not used
Same level as VCRIN_FS
V
VID
______________________________________________________________________________________ 33
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
Table 16. Register 08h: ENC and VCR Video Input/Output Control
BIT
DESCRIPTION
COMMENTS
VCR_Y/CVBS_OUT
7
6
5
4
3
2
1
0
VCR_R/C_OUT
ENC_R/C_IN
ENC_C_IN
VCR_R/C_IN
Mute
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
ENC_Y/CVBS_IN
ENC_Y_IN
VCR_Y/CVBS_IN
TV_Y/CVBS_IN
Not used
Input Sources for VCR Video
Not used
Mute
Mute
Mute
Mute
Mute (power-on
default)
Mute (power-on
default)
1
1
1
DC restore clamp active at input
(power-on default)
0
1
0/MAX9671
ENC_R/C_IN Clamp/Bias
Chrominance bias applied at input
High-impedance bias off
(power-on default)
0
1
ENC R/C, G, and B inputs high-impedance
bias (in HD application)
Biases the R/C, G, and B inputs to high
impedance (overwrites the ENC_R/C_IN
clamp and bias bit)
DC restore clamp active at input
(power-on default)
0
1
VCR_R/C_IN Clamp/Bias
Chrominance bias applied at input
34 ______________________________________________________________________________________
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
0/MAX9671
Table 17. Register 09h: VCR Video Output Control
BIT
DESCRIPTION
COMMENTS
7
6
5
4
3
2
1
0
0
0
Low (< 2V) internal source
Medium (4.5V to 7V); external SCART
source with 16:9 aspect ratio
0
1
1
1
0
1
Set VCR Slow Switching
High impedance (power-on default)
High (> 9.5V); external SCART source
with 4:3 aspect ratio
Normal operation; pulldown on
VCR_R/C_OUT is off (power-on
default)
0
1
VCR_R/C_OUT Ground
Ground; pulldown on VCR_R/C_OUT
is on; the output amplifier driving
VCR_R/C_OUT is off
Table 18. Register 0Dh: Output Enable
BIT
DESCRIPTION
COMMENTS
7
6
5
4
3
2
1
0
1
0
Off (power-on default)
TVOUT_FS Enable
On
0
1
Off (power-on default)
TV_Y/CVBS_OUT Enable
TV_B_OUT Enable
On
0
1
Off (power-on default)
On
0
1
Off (power-on default)
TV_G_OUT Enable
On
0
1
Off (power-on default)
TV_R/C_OUT Enable
VCR_R/C_OUT Enable
VCR_Y/CVBS_OUT Enable
On
0
1
Off (power-on default)
On
0
1
Off (power-on default)
On
______________________________________________________________________________________ 35
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
Table 19. Register 10h: Operating Modes
BIT
DESCRIPTION
COMMENTS
7
6
5
4
3
2
1
0
0
0
Shutdown
Standby mode (power-on default).
Input video detection circuits are
active. Audio circuitry is off unless
video is detected. Once slow switch
is detected, the signal paths between
the VCR and TV SCART are
0
1
connected.
Operating Mode
Full-power mode with input video
detection and video-load detection
active.
1
1
0
1
Full-power mode without input video
detection and video-load detection
active.
0/MAX9671
Table 20. Register 0Eh: Status
BIT
DESCRIPTION
COMMENTS
7
6
5
4
3
2
1
0
0
0
0 to 2V; internal source
4.5V to 7V; external source with 16:9
aspect ratio
0
1
1
1
0
1
TV Slow-Switching Input Status
Not used
9.5V to 12.6V; external source with
4:3 aspect ratio
0
0
1
1
0
1
0
1
0 to 2V; internal source
4.5V to 7V; external source with 16:9
aspect ratio
VCR Slow-Switching Input Status
Not used
9.5V to 12.6V; external source with
4:3 aspect ratio
V
is too low for digital logic to
VID
0
1
operate
Power-On Reset
V
is high enough for digital logic to
VID
operate
36 ______________________________________________________________________________________
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
0/MAX9671
Table 21. Register 0Fh: Video Activity Status
BIT
DESCRIPTION
TV CVBS Input Video Detection
TV CVBS Output Load
COMMENTS
No video detected.
7
6
5
4
3
2
1
0
0
1
Video detected.
0
1
No video detected.
Video detected.
0
1
No video detected.
Video detected.
VCR CVBS Input Video Detection
VCR CVBS Output Load
0
1
No load connected.
Load connected.
No video detected.
Video detected.
0
1
ENC_Y/CVBS_IN Input Video Detection
ENC_Y_IN Input Video Detection
0
1
No video detected.
Video detected.
______________________________________________________________________________________ 37
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
Typical Application Circuit
12V
3.3V
3.3V
0.1µF
0.1µF
0.1µF
V
V
VID
V
12
AUD
7.68kΩ
TV_INL
(MAX9671 ONLY)
+3.3 V
2.55kΩ
7.68kΩ
TV_INR
(MAX9671 ONLY)
STB CHIP
2.55kΩ
75Ω
SDA
SCL
TV_OUTR
TV_OUTL
MICRO-
CONTROLLER
INT
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
DEV_ADDR
TV_SS
TV_B_OUT
TV_G_OUT
TV_R/C_OUT
TVOUT_FS
TV
SCART
VIDEO ENCODER
0/MAX9671
ENC_Y/CVBS_IN
ENC_R/C_IN
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
ENC_G_IN
ENC_B_IN
ENC_Y_IN
ENC_C_IN
TV_Y/CVBS_OUT
TV_Y/CVBS_IN
0.1µF
75Ω
MAX9670
MAX9671
GNDVID
VCR_OUTR
75Ω
1µF
1µF
7.68kΩ
VCR_INR
2.55kΩ
VCR_OUTL
VCR_INL
STEREO
AUDIO DACS
75Ω
1µF
1µF
6.65kΩ
7.68kΩ
ENC_INL
ENC_INR
R1*
2.55kΩ
75Ω
VCR_SS
0.1µF
VCR
SCART
6.65kΩ
VCR_B_IN
75Ω
75Ω
75Ω
0.1µF
0.1µF
R1*
VCR_G_IN
VCR_R/C_IN
VCR_R/C_OUT
VCRIN_FS
75Ω
75Ω
VCR_Y/CVBS_OUT
VCR_Y/CVBS_IN
*R1 VALUES
0.1µF
DAC = CS4334/5/8/9: R1 = 4.53kΩ 1%
DAC = PCM1742: R1 = 5.57kΩ 1%
EP
C1P
C1N CPVSS
75Ω
1µF
1µF
38 ______________________________________________________________________________________
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
0/MAX9671
Pin Configurations
TOP VIEW
TOP VIEW
30 29 28 27 26 25 24 23 22 21
20
31
32
33
TVOUT_FS
19 VCR_SS
18
17 TV_SS
16
ENC_C_IN
ENC_R/C_IN
TV_R/C_OUT
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
18
17
16
15
14
13
12
ENC_C_IN
ENC_R/C_IN
TVOUT_FS
VCR_SS
V
12
TV_R/C_OUT
V
12
TV_SS
VCR_R/C_OUT
VCR_Y/CVBS_OUT
TV _Y/CVBS_OUT
VCR_Y/CVBS_IN
TV_Y/CVBS_IN
ENC_Y_IN
VCR_R/C_OUT 34
TV_OUTR
VCR_OUTR
VCR_OUTL
TV_OUTL
VCR_INR
VCR_INL
TV_INR
35
36
37
38
39
40
TV_OUTR
15 VCR_OUTR
14
VCR _Y/CVBS_OUT
TV_Y/CVBS_OUT
VCR_Y/CVBS_IN
TV_Y/CVBS_IN
ENC_Y_IN
MAX9670
MAX9671
VCR_OUTL
13 TV_OUTL
12
*EP
*EP
ENC_Y/CVBS_IN
N.C.
VCR_INR
11 VCR_INL
ENC_Y/CVBS_IN
1
2
3
4
5
6
7
8
9
10
44 TQFN
40 TQFN
*EP = EXPOSED PAD
*EP = EXPOSED PAD
Chip Information
PROCESS: BiCMOS
______________________________________________________________________________________ 39
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
PACKAGE TYPE
40 TQFN
PACKAGE CODE
T4066+3
OUTLINE NO.
21-0141
LAND PATTERN NO.
90-0054
44 TQFN
T4477+2
21-0144
90-0127
0/MAX9671
40 ______________________________________________________________________________________
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
0/MAX9671
Package Information (continued)
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
______________________________________________________________________________________ 41
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
Package Information (continued)
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
0/MAX9671
42 ______________________________________________________________________________________
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
0/MAX9671
Package Information (continued)
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
______________________________________________________________________________________ 43
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
7/09
Initial release
Added θ and θ information in the Absolute Maximum Ratings section,
adjusted Note references, updated power consumption Figures, and made
various corrections
—
JA
JC
1–8, 17, 20, 21, 22,
24–29, 33, 35, 36, 37
1
2
3/10
12/10
Updated Table 14
33
0/MAX9671
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
44 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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