MAX98357AETE+ [MAXIM]
Tiny, Low-Cost, PCM Class D Amplifier with Class AB Performance;
| 型号： | MAX98357AETE+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Tiny, Low-Cost, PCM Class D Amplifier with Class AB Performance PC |
| 文件： | 总38页 (文件大小：4771K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
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MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
General Description
Features
The MAX98357A/MAX98357B is an easy-to-use, low-cost,
digital pulse-code modulation (PCM) input Class D ampli-
fier that provides industry-leading Class AB audio perfor-
mance with Class D efficiency. The digital audio interface
automatically recognizes up to 35 different PCM and TDM
● Single-Supply Operation (2.5V to 5.5V)
● 3.2W Output Power into 4Ω at 5V
● 2.4mA Quiescent Current
● 92% Efficiency (R = 8Ω, P
= 1W)
OUT
Output Noise (A = 15dB)
V
L
2
● 22.8μV
clocking schemes which eliminates the need for I C pro-
RMS
gramming. Operation is further simplified by eliminating
the need for an external MCLK signal that is typically used
for PCM communication. Simply supply power, LRCLK,
BCLK, and digital audio to generate audio! Furthermore,
a novel pinout allows customers to use the cost-effective
WLP package with no need for expensive vias (refer
to Application Note 6643: Optimize Cost, Size, and
Performance with MAX98357 WLP for more information).
● Low 0.013% THD+N at 1kHz
● No MCLK Required
● Sample Rates of 8kHz to 96kHz
● Supports Left, Right, or (Left/2 + Right/2) Output
● Sophisticated Edge Rate Control Enables
Filterless Class D Outputs
● 77dB PSRR at 1kHz
The digital audio interface is highly flexible with the
● Low RF Susceptibility Rejects TDMA
2
MAX98357A supporting I S data and the MAX98357B
Noise from GSM Radios
supporting left-justified data. Both ICs support 8 channel
time division multiplexed (TDM) data. The digital audio
interface accepts specified sample rates between 8kHz
and 96kHz for all supported data formats. The ICs can
be configured to produce a left channel, right channel, or
(left/2 + right/2) output from the stereo input data. The ICs
● Extensive Click-and-Pop Reduction Circuitry
● Robust Short-Circuit and Thermal Protection
● Available in Space-Saving Packages:
1.345mm x 1.435mm WLP (0.4mm Pitch)
and 3mm x 3mm TQFN
2
operate using 16/24/32-bit data for I S and left-justified
● Solution Size with Single Bypass Capacitor is
modes as well as 16-bit or 32-bit data using TDM mode.
The ICs eliminate the need for the external MCLK signal
that is typically used for PCM communication. This reduc-
es EMI and possible board coupling issues in addition to
reducing the size and pin count of the ICs.
4.32mm2
Applications
● Single Li-ion Cell/5V Devices
● Smart Speakers
● Notebook Computers
● IoT Devices
● Gaming Devices (Audio and Haptics)
● Smartphones
The ICs also feature a very high wideband jitter toler-
ance (12ns typ) on BCLK and LRCLK to provide robust
operation.
Active emissions-limiting, edge-rate limiting, and over-
shoot control circuitry greatly reduce EMI. A filterless
spread-spectrum modulation scheme eliminates the need
for output filtering found in traditional Class D devices and
reduces the component count of the solution.
● Tablets
● Cameras
Simplified Block Diagram
The ICs are available in 9-pin WLP (1.345mm x 1.435mm
x 0.64mm) and 16-pin TQFN (3mm x 3mm x 0.75mm)
packages and are specified over the -40°C to +85°C tem-
perature range.
SHUTDOWN
AND
CHANNEL
SELECT
GAIN
CONTROL
MAX98357A
MAX98357B
Ordering Information appears at end of data sheet.
Functional Diagram appears at end of data sheet.
CLASS D
OUTPUT
STAGE
DIGITAL
AUDIO
INTERFACE
PCM
INPUT
DAC
19-6779; Rev 13; 7/19
MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Digital Audio Interface Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MCLK Elimination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
BCLK Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
BCLK Polarity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
LRCLK Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DAC Digital Filters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
S D_M O D E and Shutdown Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2
I S and Left Justified Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
TDM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Class D Speaker Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Ultra-Low EMI Filterless Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Speaker Current Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Gain Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Click-and-Pop Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Filterless Class D Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Power-Supply Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Layout and Grounding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
WLP Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Maxim Integrated
│ 2
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MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
LIST OF FIGURES
Figure 1. I2S Audio Interface Timing Diagram (MAX98357A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2. Left-Justified Audio Interface Timing Diagram (MAX98357B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. TDM Audio Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. SD_MODE Resistor Connected Using Open-Drain Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 5. SD_MODE Resistor Connected Using Push-Pull Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 6. Required startup sequence when using BCLK = 256kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 7. MAX98357A I2S Digital Audio Interface Timing, 16-Bit Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 8. MAX98357A I2S Digital Audio Interface Timing, 32-Bit Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 9. MAX98357B Left-Justified Digital Audio Interface Timing, 16-Bit Resolution. . . . . . . . . . . . . . . . . . . . . . . 22
Figure 10. MAX98357B Left-Justified Digital Audio Interface Timing, 32-Bit Resolution . . . . . . . . . . . . . . . . . . . . . . 23
Figure 11. MAX98357A TDM 16-Bit DAI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12. MAX98357A TDM 32-Bit DAI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 13. MAX98357B TDM 16-Bit DAI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 14. MAX98357B TDM 32-Bit DAI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 15. EMI with 12in of Speaker Cable and No Output Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 16. Left-Channel PCM Operation with 6dB Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 17. Left-Channel PCM Operation with 12dB Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 18. Right-Channel PCM Operation with 6dB Gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 19. (Left/2 + Right/2) PCM Operation with 6dB Gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 20. Stereo PCM Operation Using Two ICs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 21. Channel TDM Operation (Gain Fixed at 12dB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 22. WLP Pin Connect for set 12dB Gain Without Via. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 23. Example Layout Configured for Left-Channel Audio and Gain of 12dB. . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 24. MAX98357A/MAX98357B WLP Ball Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
LIST OF TABLES
Table 1. RMS Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 2. BCLK Polarity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 3. LRCLK Polarity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. Digital Filter Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. SD_MODE Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6. Examples of SD_MODE Pullup Resistor Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 7. TDM Mode Channel Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. Gain Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Maxim Integrated
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MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
Absolute Maximum Ratings
V
, LRCLK, BCLK, and DIN to GND....................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
A
DD
All Other Pins to GND.............................. -0.3V to (V
+ 0.3V)
WLP (derate 13.7mW/°C above +70°C)....................1096mW
TQFN (derate 20.8mW/°C above +70°C)..................1666mW
Junction Temperature......................................................+150°C
Operating Temperature Range........................... -40°C to +85°C
Storage Temperature Range............................ -65°C to +150°C
Soldering Temperature (reflow).......................................+260°C
Lead Temperature (soldering, 10s, TQFN) .....................+300°C
DD
Continuous Current In/Out of V /GND/OUT_..................±1.6A
DD
Continuous Input Current (all other pins).........................±20mA
Duration of OUT_ Short Circuit to GND or V …....Continuous
DD
Duration of OUTP Short to OUTN.............................Continuous
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
(Note 1)
Package Thermal Characteristics
WLP
TQFN
Junction-to-Ambient Thermal Resistance (θ ) ..........48°C/W
Junction-to-Ambient Thermal Resistance (θ ) ..........73°C/W
JA
JA
Junction-to-Case Thermal Resistance (θ )...............50°C/W
Junction-to-Case Thermal Resistance (θ ).................7°C/W
JC
JC
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(V
= 5V, V
= 0V, GAIN_SLOT = V . BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (Z
) connected between OUTP
DD
GND
SPK
DD
SPK
and OUTN, Z
= ∞, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX A
A
MIN
PARAMETER
Supply Voltage Range
Undervoltage Lockout
SYMBOL
CONDITIONS
MIN
2.5
TYP
MAX
5.5
UNITS
V
Guaranteed by PSSR test
V
V
DD
UVLO
1.5
1.8
2.75
2.4
2.3
T
T
= +25°C
3.35
2.85
2
A
Quiescent Current
I
mA
DD
= +25°C, V
= 3.7V
A
DD
Shutdown Current
Standby Current
I
SD_MODE = 0V, T = +25°C
0.6
µA
µA
SHDN
A
I
SD_MODE = 1.8V, no BCLK, T = +25°C
340
400
STNDBY
A
Turn-On Time
t
7
7.5
ms
ON
Output Offset Voltage
V
T
= +25°C, gain = 15dB
±0.3
-72
±2.5
mV
OS
CP
A
Peak voltage, T
=
Into shutdown
A
+25°C, A-weighted,
32 samples per
second (Note 3)
Click-and-Pop Level
K
dBV
dB
Out of shutdown
-66
V
= 2.5V to 5.5V, T = +25°C
60
75
77
DD
A
f = 217Hz,
Power-Supply Rejection Ratio
PSRR
200mV
P-P
ripple
ripple
T
= +25°C
A
(Notes 3, 4)
f = 10kHz,
200mV
60
P-P
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MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
Electrical Characteristics (continued)
(V
= 5V, V
= 0V, GAIN_SLOT = V . BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (Z
) connected between OUTP
DD
GND
SPK
DD
SPK
and OUTN, Z
= ∞, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
3.2
MAX
UNITS
Z
Z
Z
= 4Ω + 33µH
= 8Ω + 68µH
SPK
SPK
SPK
THD+N 10%,
gain = 12dB
1.8
= 8Ω + 68µH,
0.93
V
= 3.7V
DD
Output Power (Note 3)
P
W
OUT
Z
Z
Z
= 4Ω + 33µH
= 8Ω + 68µH
2.5
1.4
SPK
SPK
SPK
THD+N = 1%,
gain = 12dB
= 8Ω + 68µH,
0.77
0.02
V
= 3.7V
DD
f = 1kHz, P
= 1W, T = +25°C,
A
OUT
0.06
Z
= 4Ω + 33µH, WLP
SPK
Total Harmonic Distortion +
Noise
f = 1kHz, P
= 1W, T = +25°C,
OUT A
THD+N
DR
0.02
%
Z
= 4Ω + 33µH, TQFN
SPK
f = 1kHz, P
= 0.5W, T = +25°C,
A
OUT
0.013
103.5
Z
= 8Ω + 68µH
SPK
A-weighted, Z
= 8Ω + 33µH,
SPK
Dynamic Range
Output Noise
dB
V
= 3.40V, 24- or 32-bit data
RMS
V
A-weighted, 24- or 32-bit data (Note 4)
GAIN_SLOT = GND through 100kΩ
GAIN_SLOT = GND
22.8
15
12
9
µV
RMS
N
14.4
11.4
8.4
15.6
12.6
9.6
Gain (Relative to a 2.1dBV
Reference Level)
A
GAIN_SLOT = unconnected
dB
V
GAIN_SLOT = V
5.4
6
6.6
DD
DD
GAIN_SLOT = V
through 100kΩ
2.4
3
3.6
Current Limit
I
2.8
A
LIM
Z
= 8Ω + 68µH, THD+N = 10%,
SPK
Efficiency
ε
92
1
%
f = 1kHz, gain = 12dB
DAC Gain Error
%
Frequency Response
-0.2
+0.2
dB
Class D Switching Frequency
Spread-Spectrum Bandwidth
DAC DIGITAL FILTERS
f
300
±20
kHz
kHz
OSC
VOICE MODE IIR LOWPASS FILTER (LRCLK < 30kHz)
0.443
Ripple limit cutoff
-3dB cutoff
x f
S
Passband Cutoff
f
Hz
PLP
SLP
0.446
x f
S
0.464
Stopband Cutoff
f
Hz
dB
x f
S
Stopband Attenuation
f > f
75
SLP
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MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
Electrical Characteristics (continued)
(V
= 5V, V
= 0V, GAIN_SLOT = V . BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (Z
) connected between OUTP
DD
GND
SPK
DD
SPK
and OUTN, Z
= ∞, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
AUDIO MODE FIR LOWPASS FILTER (30kHz < LRCLK < 50kHz)
0.43
Ripple limit cutoff
x f
S
0.47
x f
Passband Cutoff
f
-3dB cutoff
Hz
PLP
SLP
S
0.5
x f
-6.02dB cutoff
S
0.58
Stopband Cutoff
f
Hz
dB
x f
S
Stopband Attenuation
f > f
60
SLP
AUDIO MODE FIR LOWPASS FILTER (LRCLK > 50kHz)
0.24
x f
Ripple limit cutoff
-3dB cutoff
S
Passband Cutoff
f
Hz
PLP
SLP
0.31
x f
S
0.477
x f
Stopband Cutoff
f
Hz
dB
S
Stopband Attenuation
DIGITAL AUDIO INTERFACE
LRCLK Range 1
f < f
60
SLP
f
f
f
f
7.6
8
16
8.4
16.8
50.4
100.8
S1
S2
S3
S4
LRCLK Range 2
15.2
30.4
83.8
kHz
Bits
LRCLK Range 3
48
LRCLK Range 4
96
2
I S/left justified mode
16/24/32
16/32
Resolution
TDM mode
BCLK Frequency Range
BCLK High Time
f
t
BCLK must be 32, 48, or 64X of LRCLK
0.2432
15
25.804
MHz
ns
BCLKH
BCLKH
BCLK Low Time
t
15
ns
BCLKL
Maximum Low Frequency
BCLK and LRCLK Jitter
RMS jitter below 40kHz
0.5
12
ns
V
Maximum High Frequency
BCLK and LRCLK Jitter
RMS jitter above 40kHz
Digital audio inputs
Input High Voltage
V
1.3
IH
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MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
Electrical Characteristics (continued)
(V
= 5V, V
= 0V, GAIN_SLOT = V . BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (Z
) connected between OUTP
DD
GND
SPK
DD
SPK
and OUTN, Z
= ∞, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX A
A
MIN
PARAMETER
Input Low Voltage
SYMBOL
CONDITIONS
Digital audio inputs
= 0V, V = 5.5V, T = +25°C
MIN
TYP
MAX
0.6
UNITS
V
V
IL
Input Leakage Current
Input Capacitance
I
, I
V
-1
+1
µA
pF
IH IL
IN
DD
A
C
3
IN
DIN to BCLK Setup Time
LRCLK to BCLK Setup Time
DIN to BCLK Hold Time
LRCLK to BCLK Hold Time
t
10
10
10
10
ns
SETUP
t
ns
SYNCSET
t
ns
HOLD
SYNCHOLD
t
ns
SD_MODE COMPARATOR TRIP POINTS
B0
B1
B2
0.08
0.65
1.245
92
0.16
0.77
1.4
0.355
0.825
1.5
See SD_MODE and shutdown operation
for details
V
SD_MODE Pulldown Resistor
R
100
108
kΩ
PD
GAIN COMPARATOR TRIP POINTS
0.65 x
0.85 x
A
A
A
A
A
= 3dB gain
= 6dB gain
= 9dB gain
= 12dB gain
= 15dB gain
V
V
V
V
V
V
V
DD
DD
0.9 x
V
DD
V
DD
V_GAIN_
SLOT
0.4 x
0.6 x
V
DD
V
V
DD
0.1 x
0
V
DD
0.15 x
0.35 x
V
DD
V
DD
Note 2: 100% production tested at T = +25°C. Specifications over temperature limits are guaranteed by design.
A
Note 3: Class D amplifier testing performed with a resistive load in series with an inductor to simulate an actual speaker load. For
R = 8Ω, L = 68µH. For R = 4Ω, L = 33µH.
L
L
L
L
Note 4: Digital silence used for input signal.
Note 5: Dynamic range measured using the EIAJ method. -60dBFS 1kHz output signal, A-weighted, and normalized to 0dBFS.
f = 20Hz to 20kHz.
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MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
tBCLK
tBCLKH
VIH
VIH
VIH
tBCLKL
BCLK (INPUT)
VIL
VIL
VIL
tSYNCHOLD
tSYNCSET
VIH
LRCLK (INPUT)
DIN (INPUT)
VIL
tSETUP tHOLD
VIHLEFT MSB
RIGHT MSB
VIL
2
Figure 1. I S Audio Interface Timing Diagram (MAX98357A)
tBCLK
tBCLKH
VIH
VIL
VIH
VIH
VIL
tBCLKL
BCLK (INPUT)
LRCLK (INPUT)
VIL
tSYNCHOLD
tSYNCSET
VIH
VIL
tSETUP tHOLD
VIH
DIN (INPUT)
LEFT MSB VIL
RIGHT MSB
Figure 2. Left-Justified Audio Interface Timing Diagram (MAX98357B)
tBCLK
tBCLK
tBCLKL tBCLKH
tBCLKL
tBCLKH
VIH
VIH
VIH
VIL
VIH
VIL
BCLK (INPUT)
BCLK (input)
VIL
VIL
tSYNCSET
tSYNCSET
tSYNCHOLD
tSYNCHOLD
VIH
VIH
VIL
LRCLK (input)
DIN (input)
LRCLK (INPUT)
DIN (INPUT)
VIL
tSETUP tHOLD
tSETUP tHOLD
VIH
VIH
MSB
MSB
VIL
VIL
MAX98357A
MAX98357B
Figure 3. TDM Audio Interface Timing Diagram
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MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
Typical Operating Characteristics
(V
= 5V, V
= 0V, GAIN_SLOT = GND (+12dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (Z
) connected between
SPK
DD
GND
OUTP and OUTN, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
A
MIN
MAX A
QUIESCENT CURRENT vs.
SUPPLY VOLTAGE
SHUTDOWN CURRENT vs. SUPPLY VOLTAGE
toc01
toc02
4.0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
VDDIO = 1.8V
VDDIO = 1.8V
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
Typical Operating Characteristics (continued)
(V
= 5V, V
= 0V, GAIN_SLOT = GND (+12dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (Z
) connected between
SPK
DD
GND
OUTP and OUTN, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
A
MIN
MAX A
OUTPUT POWER vs. LOAD RESISTANCE
OUTPUT POWER vs. LOAD RESISTANCE
OUTPUT POWER vs. LOAD RESISTANCE
toc15
toc16
toc17
2.5
2.0
1.5
1.0
0.5
0.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VDD = 3.7V
VDD = 4.2V
VDD = 5V
10% THD+N
1% THD+N
10% THD+N
1% THD+N
10% THD+N
1% THD+N
1
10
100
1
10
100
1
10
100
LOAD RESISTANCE
LOAD RESISTANCE
LOAD RESISTANCE
MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
Typical Operating Characteristics (continued)
(V
= 5V, V
= 0V, GAIN_SLOT = GND (+12dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (Z
) connected between
SPK
DD
GND
OUTP and OUTN, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
A
MIN
MAX A
NORMALIZED GAIN vs. FREQUENCY
toc20
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
1
10
100
1000
10000 100000
FREQUENCY (Hz)
MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
Typical Operating Characteristics (continued)
(V
= 5V, V
= 0V, GAIN_SLOT = GND (+12dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (Z
) connected between
SPK
DD
GND
OUTP and OUTN, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
A
MIN
MAX A
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
POWER-SUPPLY REJECTION RATIO
vs. SUPPLY VOLTAGE
TURN-ON RESPONSE
toc29
toc27
toc28
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
OUTPUT
1V/div
SD_MODE
1V/div
fS = 1kHz
10
100
1000 10000
FREQUENCY (Hz)
100000
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2ms/div
SUPPLY VOLTAGE (V)
TURN-OFF RESPONSE
(STANDBY MODE)
TURN-ON RESPONSE
(STANDBY MODE)
TURN-OFF RESPONSE
toc30a
toc30b
toc30
OUTPUT
1V/div
BCLK
2V/div
BCLK
2V/div
LRCLK
2V/div
LRCLK
2V/div
OUTPUT
1V/div
OUTPUT
1V/div
SD_MODE
1V/div
500µs/div
2ms/div
1ms/div
MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
Typical Operating Characteristics (continued)
(V
= 5V, V
= 0V, GAIN_SLOT = GND (+12dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (Z
) connected between
SPK
DD
GND
OUTP and OUTN, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
A
MIN
MAX A
MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
Typical Operating Characteristics (continued)
(V
= 5V, V
= 0V, GAIN_SLOT = GND (+12dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (Z
) connected between
SPK
DD
GND
OUTP and OUTN, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
A
MIN
MAX A
MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
Pin Configurations
TOP VIEW
BUMP SIDE DOWN
TOP VIEW
MAX98357A
MAX98357B
+
12
11
10
9
SD_MODE
V
OUTP
A3
DD
A1
A2
V
V
13
14
N.C.
8
7
6
5
DD
DIN
B1
GAIN_SLOT OUTN
LRCLK
DD
MAX98357A
MAX98357B
B2
B3
N.C.
N.C.
GND 15
16
BCLK
C1
GND
C2
LRCLK
C3
BCLK
+
1
2
3
4
WLP
TQFN
Pin Description
PIN
NAME
FUNCTION
Shutdown and Channel Select. Pull SD_MODE low to place the device in shutdown. In I S
WLP
TQFN
2
A1
4
SD_MODE or LJ mode, SD_MODE selects the data channel (Table 5). In TDM mode, SD_MODE and
GAIN_SLOT are both used for channel selection (Table 7).
A2
A3
B1
7, 8
9
V
Power-Supply Input
DD
OUTP
DIN
Positive Speaker Amplifier Output
Digital Input Signal
1
2
Gain and Channel Selection. In I S and LJ mode determines amplifier output gain (Table 8)
GAIN_
SLOT
B2
2
In TDM mode, used for channel selection with SD_MODE (Table 7). In TDM mode, gain is
fixed at 12dB.
B3
C1
C2
C3
10
16
OUTN
BCLK
GND
Negative Speaker Amplifier Output
Bit Clock Input
3, 11, 15
14
Ground
2
LRCLK
Frame Clock. Left/right clock for I S and LJ mode. Sync clock for TDM mode.
5, 6,
12, 13
—
—
N.C.
EP
No Connection
Exposed Pad. The exposed pad is not internally connected. Connect the exposed page to a
solid ground plane for thermal dissipation.
—
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MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
BCLK Jitter Tolerance
Detailed Description
The ICs feature a BCLK jitter tolerance of 0.5ns for RMS
jitter below 40kHz and 12ns for wideband RMS jitter while
maintaining a dynamic range greater than 98dB (Table 1).
The MAX98357A/MAX98357B are digital PCM input
Class D power amplifiers. The MAX98357A accepts stan-
2
dard I S data through DIN, BCLK, and LRCLK while the
MAX98357B accepts left-justified data through the same
inputs. Both versions also accept 16-bit or 32-bit TDM
data with up to eight slots. The digital audio interface
eliminates the need for an external MCLK signal that is
BCLK Polarity
2
When operating in I S/left-justified mode, incoming serial
data is always clocked-in on the rising edge of BCLK.
In TDM mode, the MAX98357A clocks-in serial data on
the rising edge of BCLK while the MAX98357B clocks in
serial data on the falling edge of BCLK (Table 2).
2
typically required for I S data transmission.
SD_MODE selects which data word is output by the
amplifier and is used to put the ICs into shutdown. These
LRCLK Polarity
2
devices offer five gain settings in I S/left-justified mode
LRCLK specifies whether left-channel data or right-
channel data is currently being read by the digital audio
interface. The MAX98357A indicates the left channel
word when LRCLK is low, and the MAX98357B indicates
the left channel word when LRCLK is high (Table 3).
and a fixed 12dB gain in TDM mode. Channel selection in
TDM mode is set with the combination of SD_MODE and
GAIN_SLOT (Table 7).
The MAX98357A/MAX98357B DAI includes a DC blocker
with a -3dB cutoff at 3.7Hz.
LRCLK ONLY supports 8kHz, 16kHz, 32kHz, 44.1kHz,
48kHz, 88.2kHz and 96kHz frequencies. LRCLK clocks
at 11.025kHz, 12kHz, 22.05kHz and 24kHz are NOT sup-
ported. Do not remove LRCLK while BCLK is present.
Removing LRCLK while BCLK is present can cause unex-
pected output behavior including a large DC output voltage.
The MAX98357A/MAX98357B feature low-quiescent cur-
rent, comprehensive click-and-pop suppression, and
excellent RF immunity. The ICs offer Class AB audio
performance with Class D efficiency in a minimal board-
space solution. The Class D amplifier features spread-
spectrum modulation with edge-rate and overshoot con-
trol circuitry that offers significant improvements in switch-
mode amplifier radiated emissions. The amplifier features
click-and-pop suppression that reduces audible transients
on startup and shutdown. The amplifier includes thermal-
overload and short-circuit protection.
Standby Mode
The ICs automatically enter standby mode when BCLK
is removed. If BCLK stops toggling, the ICs automatically
Table 1. RMS Jitter Tolerance
Digital Audio Interface Modes
FREQUENCY
< 40kHz
RMS JITTER TOLERANCE (ns)
The input stage of the digital audio interface is highly flexi-
ble, supporting 8kHz–96kHz sampling rates with 16/24/32-
0.5
12
40kHz–BCLK
2
bit resolution for I S/left justified data as well as up to a
8-slot, 16-bit or 32-bit time division multiplexed (TDM)
format. When LRCLK has a 50% duty cycle the data
format is determined by the part number selection
(MAX98357A/MAX98357B). When a frame sync pulse
is used for the LRCLK the data format is automatically
configured in TDM mode. The frame sync pulse indicates
the beginning of the first time slot.
Table 2. BCLK Polarity
MODE
PART NUMBER
BCLK POLARITY
Rising edge
2
I S
MAX98357A
MAX98357B
MAX98357A
MAX98357B
Left-justified
Rising edge
Rising edge
TDM
MCLK Elimination
Falling edge
The ICs eliminate the need for the external MCLK
signal that is typically used for PCM communication.
This reduces EMI and possible board coupling issues in
addition to reducing the size and pin-count of the ICs.
Table 3. LRCLK Polarity
PART NUMBER
MAX98357A
LRCLK POLARITY (LEFT CHANNEL)
Low
MAX98357B
High
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MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
enter standby mode. In standby mode, the Class D speak-
er is turned off and the outputs go into a high-impedance
state, ensuring that unwanted current is not transferred to
the load during this condition. Standby mode has reduced
power consumption from normal operation (340µA), but
does not reach as low as full shutdown (0.6µA). Standby
mode can be used to reduce power consumption when no
GPIO us available to pull SD_MODE low.
Drive SD_MODE high to select the left word of the stereo
input data. Drive SD_MODE high through a sufficiently
small resistor to select the right word of the stereo input
data. Drive SD_MODE high through a sufficiently large
resistor to select both the left and right words of the
stereo input data (left/2 + right/2). R
and R
LARGE
SMALL
are determined by the V
voltage (logic voltage from
DDIO
control interface) that is driving SD_MODE according to
the following two equations:
DAC Digital Filters
R
(kΩ) = 94.0 x V
- 100
- 100
SMALL
DDIO
The DAC features a digital lowpass filter that is auto-
matically configured for voice playback or music playback
based on the sample rate that is used. This filter elimi-
nates the effect of aliasing and any other high-frequency
noise that might otherwise be present. Table 4 shows the
digital filter settings that are automatically selected.
R
(kΩ) = 222.2 x V
DDIO
LARGE
When the devices are configured in left-channel mode
(SD_MODE is directly driven to logic-high by the con-
trol interface), take care to avoid violating the Absolute
Maximum Ratings limits for SD_MODE. Ensuring that
V
is always greater than V
is one way to prevent
DD
DDIO
SD_MODE and Shutdown Operation
SD_MODE from violating the Absolute Maximum Ratings
limits. If this is not possible in the application (e.g., if V
The ICs feature a low-power shutdown mode, drawing
less than 0.6µA (typ) of supply current. During shutdown,
all internal blocks are turned off, including setting the
output stage to a high-impedance state. Drive SD_MODE
low to put the ICs into shutdown.
DD
< 3.0V and V
= 3.3V), then it is necessary to add a
DDIO
small resistance (~2kΩ) in series with SD_MODE to limit
the current into the SD_MODE pin. This is not a concern
when using the right channel or (left/2 + right/2) modes.
The state of SD_MODE determines the audio channel
that is sent to the amplifier output (Table 5).
Figure 4 and Figure 5 show how to connect an external
resistor to SD_MODE when using an open-drain driver or
a push-pull driver.
Table 4. Digital Filter Settings
-3dB CUTOFF
FREQUENCY
RIPPLE LIMIT CUTOFF STOPBAND CUTOFF
FREQUENCY FREQUENCY
STOPBAND
ATTENUATION (dB)
LRCLK FREQUENCY
< 30kHz
f
0.446 x f
0.443 x f
0.464 x f
75
60
60
LRCLK
LRCLK
LRCLK
LRCLK
LRCLK
LRCLK
LRCLK
LRCLK
30kHz < f
< 50kHz
0.47 x f
0.31 x f
0.43 x f
0.24 x f
0.58 x f
0.477 x f
LRCLK
LRCLK
f
> 50kHz
LRCLK
LRCLK
Table 5. SD_MODE Control
SD_MODE STATUS
SELECTED CHANNEL
Left
High
Pullup through R
Pullup through R
Low
V
> B2 trip point
SD_MODE
B2 trip point > V
B1 trip point > V
> B1 trip point
> B0 trip point
Right
SMALL
LARGE
SD_MODE
SD_MODE
(Left/2 + right/2)
Shutdown
B0 trip point > V
SD_MODE
Table 6. Examples of SD_MODE Pullup Resistor Values
LOGIC VOLTAGE LEVEL (V
) (V)
R
(kΩ)
R
(kΩ)
DDIO
SMALL
LARGE
1.8
3.3
69.8
300
210.2
634
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MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
PROCESSOR
GPIO
V
DDIO
LEFT MODE
MAX98357A
MAX98357B
R
B2 (1.4V typ)
B1 (0.77V typ)
B0 (0.16V typ)
V
SD_MODE
RIGHT MODE
100kΩ
±8%
LEFT/2 + RIGHT/2
MODE
Figure 4. SD_MODE Resistor Connected Using Open-Drain Driver
PROCESSOR
MAX98357A
MAX98357B
V
DDIO
LEFT MODE
B2 (1.4V typ)
B1 (0.77V typ)
B0 (0.16V typ)
R
V
SD_MODE
GPIO
RIGHT MODE
100kΩ
±8%
LEFT/2 + RIGHT/2
MODE
Figure 5. SD_MODE Resistor Connected Using Push-Pull Driver
5) LRCLK must start no more than 1/2 LRCLK after
BCLK starts.
Startup
With the exception of BCLK = 256KHz, the only required
sequence for startup is that LRCLK must start within 1/2
LRCLK period of BCLK starting.
6) LRCLK must complete a full cycle; no partial LRCLK
cycles.
When using a mode with BCLK = 256kHz, there are addi-
tional requirements for the part to power-up properly:
7) Once started, BCLK and LRCLK must remain switch-
ing at 256kHz and 8kHz, respectively, and cannot
be interrupted during device operation. If BCLK and
LRCLK need to be stopped, SD_MODE must first be
set to 0V. Subsequent startups with BCLK = 256kHz
and LRCLK = 8kHz need to follow the sequence
described in steps 1-6.
1) BCLK and LRCLK cannot be applied before the part
is enabled.
2) BCLK and LRCLK must start from logic low and tran-
sition to logic high.
3) After V
is > 2.3V AND SD_MODE is high, there
DD
Figure 6 shows an example where V
maximum before SD_MODE is applied. In this example,
the 10μs wait time starts after SD_MODE is applied.
reaches UVLO
DD
must be a 10μs wait time before starting BCLK and
LRCLK.
4) LRCLK must start at least 1/2 BCLK after BCLK starts.
Maxim Integrated
│ 18
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MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
V
= UVLO
DD
MAXIMUM (2.3V)
> 10µs
SD_MODE
> 10µs
BCLK
½ LRCLK
LRCLK
t
½ BCLK < t < ½ LRCLK
Figure 6. Required startup sequence when using BCLK = 256kHz
2
R
and R
are dependent on the voltage level
LARGE
I S and Left Justified Mode
SMALL
of V
. See Table 6 for pullup resistor values.
2
DDIO
The MAX98357A follows standard I S timing by allowing
a delay of one BCLK cycle after the LRCLK transition
before the beginning of a new data word (Figure 7 and
Figure 8). The MAX98357B follows the left justified timing
specification by aligning the LRCLK transitions with the
beginning of a new data word (Figure 9 and Figure 10).
LRCLK ONLY supports 8kHz, 16kHz, 32kHz, 44.1kHz,
48kHz, 88.2kHz, and 96kHz frequencies. LRCLK clocks
at 11.025kHz, 12kHz, 22.05kHz and 24kHz are NOT
supported. Do not remove LRCLK while BLCK is pres-
ent. Removing LRCLK while BCLK is present can cause
unexpected output behavior, including a large DC output
voltage.
TDM Mode
TDM mode is automatically detected by monitoring the
short channel sync pulse on LRCLK. The frequency
detector circuit detects the bit depth. In TDM mode,
the MAX98357A/MAX98357B has a fixed gain of 12dB.
GAIN_SLOT and SD_MODE are used to select to which
of 8 channels of TDM data the parts respond. Table 7
shows the connections for GAIN_SLOT and SD_MODE
for channel selection. The MAX98357A data is valid on
the BCLK rising edge. The MAX98357B data is valid on
the BCLK falling edge.
Figure 11, Figure 12, Figure 13, and Figure 14 show TDM
operation, in which a frame-sync pulse is used for LRCLK.
In TDM mode, there must be 128 (16-bit mode) or 256
(32-bit mode) BCLK cycles per frame. In TDM mode, the
ICs only accept 16-bit or 32-bit formatted data and any of
the 8 TDM slots can be selected.
The digital audio interface output mode is chosen by the
voltage at SD_MODE. Table 5 shows how the available
modes are selected. Trip point B0–B2 are shown the
Electrical Characteristics in the SD_MODE Comparator
Trip Points section. Values for SD_MODE pullup resistors
Maxim Integrated
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MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
Table 7. TDM Mode Channel Selection
GAIN_SLOT
CHANNEL
BITS
N/A
SD_MODE
Low
X
Off
0
V
V
V
V
V
GND
16/32
16/32
16/32
16/32
16/32
16/32
16/32
16/32
DD
DD
DD
DD
DD
V
with 0Ω
1
DD
Float
2
V
with 100kΩ
3
DD
GND with 100kΩ
GND
4
V
V
V
through R
through R
through R
5
DD
DD
DD
LARGE
LARGE
LARGE
Float
6
V
7
DD
16 BITS/CHANNEL SD_MODE = VDD
LRCLK
RIGHT
LEFT
LEFT
BCLK
DIN
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14
D15
IGNORED
16 BITS/CHANNEL SD_MODE PULL UP THROUGH R
(70K)
SMALL
RIGHT
LRCLK
LEFT
LEFT
BCLK
DIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14
IGNORED
(300k)
16 BITS/CHANNEL SD_MODE PULL UP THROUGH R
LARGE
RIGHT
LRCLK
LEFT
LEFT
BCLK
DIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14
2
Figure 7. MAX98357A I S Digital Audio Interface Timing, 16-Bit Resolution
Maxim Integrated
│ 20
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MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
2
Figure 8. MAX98357A I S Digital Audio Interface Timing, 32-Bit Resolution
Maxim Integrated
│ 21
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MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
16 BITS/CHANNEL, SD_MODE = V
DD
LEFT
LRCLK
RIGHT
BCLK
D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14
D15 D14
DIN
IGNORED
16 BITS/CHANNEL, SD_MODE PULLUP THROUGH R
(70k)
SMALL
LEFT
LRCLK
RIGHT
BCLK
DIN
D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14
IGNORED
D15 D14
16 BITS/CHANNEL, SD_MODE PULLUP THROUGH R
(300k)
LARGE
LEFT
LRCLK
RIGHT
BCLK
D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14
LEFT AND RIGHT SUMMED
DIN
D15 D14
Figure 9. MAX98357B Left-Justified Digital Audio Interface Timing, 16-Bit Resolution
Maxim Integrated
│ 22
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MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
Figure 10. MAX98357B Left-Justified Digital Audio Interface Timing, 32-Bit Resolution
Maxim Integrated
│ 23
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MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
Figure 11. MAX98357A TDM 16-Bit DAI Timing
Maxim Integrated
│ 24
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MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
Figure 12. MAX98357A TDM 32-Bit DAI Timing
Maxim Integrated
│ 25
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MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
Figure 13. MAX98357B TDM 16-Bit DAI Timing
Maxim Integrated
│ 26
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MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
Figure 14. MAX98357B TDM 32-Bit DAI Timing
Maxim Integrated
│ 27
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MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
Gain Selection
Class D Speaker Amplifier
The ICs offer five programmable gain selections through a
single gain input (GAIN_SLOT) in I S/left justified mode.
The filterless Class D amplifier offers much higher effi-
ciency than Class AB amplifiers. The high efficiency of a
Class D amplifier is due to the switching operation of the
output stage transistors. Any power loss associated with
the Class D output stage is mostly due to the I R loss of the
MOSFET on-resistance and quiescent current overhead.
2
Gain is referenced to the full-scale output of the DAC,
which is 2.1dBV (Table 8). In TDM mode, the gain is auto-
matically set at a fixed 12dB. Assuming that the desired
output swing is not limited by the supply voltage rail, the
IC’s output level can be calculated based on the digital
input signal level and selected amplifier gain according to
the following equation:
2
Ultra-Low EMI Filterless Output Stage
Traditional Class D amplifiers require the use of external
LC filters, or shielding, to meet EN55022B electromagnet-
ic-interference (EMI) regulation standards. Maxim’s active
emissions-limiting edge-rate control circuitry and spread-
spectrum modulation reduces EMI emissions while main-
taining up to 92% efficiency.
Output signal level (dBV) = input signal level (dBFS) +
2.1dB + selected amplifier gain (dB)
where 0dBFS is referenced to 0dBV.
Click-and-Pop Suppression
Maxim’s spread-spectrum modulation mode flattens wide-
band spectral components while proprietary techniques
ensure that the cycle-to-cycle variation of the switching
period does not degrade audio reproduction or efficiency.
The ICs’ spread-spectrum modulator randomly varies the
switching frequency by ±20kHz around the center fre-
quency (300kHz). Above 10MHz, the wideband spectrum
looks like noise for EMI purposes (Figure 15).
The IC speaker amplifier features Maxim’s comprehen-
sive click-and-pop suppression. During startup, the click-
and-pop suppression circuitry reduces audible transient
sources internal to the device by ramping the input signal
from mute to 0dB. When entering shutdown, the differen-
tial speaker outputs simultaneously drop to GND.
The comprehensive click-and-pop suppression of the
MAX98357 is unaffected by power-up or power-down
sequencing. Applying the DAI clocks before or after the
transition of SD_MODE yields the same click-and-pop
performance. The MAX98357 does not have a volume
ramp-down response when entering shutdown. For opti-
mal click-and-pop performance, ramp down the digital
data on SDIN before powering down the MAX98357.
Speaker Current Limit
If the output current of the speaker amplifier exceeds the
current limit (2.8A typ), the IC disables the outputs for
approximately 100µs. At the end of the 100µs, the outputs
are re-enabled. If the fault condition still exists, the IC con-
tinues to disable and reenable the outputs until the fault
condition is removed.
Table 8. Gain Selection
90
70
50
30
10
-10
2
GAIN_SLOT
I S/LJ GAIN (dB)
Connect to GND through 100kΩ
15
±5% resistor
Connect to GND
Unconnected
12
9
Connect to V
6
DD
Connect to V
through 100kΩ
DD
3
±5% resistor
0
100 200 300 400 500 600 700 800 900 1000
FREQUENCY (MHz)
Figure 15. EMI with 12in of Speaker Cable and No Output
Filtering
Maxim Integrated
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MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
Applications Information
2.5V TO 5.5V
10µF
0.1µF
CODEC
V
GAIN_SLOT
B2
DD
SD_MODE
BCLK
A2
GPIO*
A1
C1
C3
B1
OUTP
OUTN
A3
BIT CLOCK
MAX98357A
MAX98357B
LRCLK
DIN
FRAME CLOCK
DATA OUT
B3
C2
GND
*RESPONDS TO LEFT CHANNEL WHEN GPIO IS HIGH.
THE MAX98357A/B ARE SHUT DOWN WHEN GPIO IS LOW.
Figure 16. Left-Channel PCM Operation with 6dB Gain
2.5V TO 5.5V
10µF
0.1µF
CODEC
V
GAIN_SLOT
B2
DD
SD_MODE
BCLK
A2
GPIO*
BIT CLOCK
A1
C1
C3
B1
OUTP
OUTN
A3
MAX98357A
MAX98357B
LRCLK
DIN
FRAME CLOCK
DATA OUT
B3
C2
GND
*RESPONDS TO LEFT CHANNEL WHEN GPIO IS HIGH.
THE MAX98357A/B ARE SHUT DOWN WHEN GPIO IS LOW.
Figure 17. Left-Channel PCM Operation with 12dB Gain
Maxim Integrated
│ 29
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MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
2.5V TO 5.5V
10µF
0.1µF
CODEC
R
SMALL
(69.8kΩ)ꢁꢁ
V
GAINꢀSLOT
B2
DD
SD_MODE
BCLK
A2
A1
C1
C3
B1
GPIOꢁ
BIT CLOCK
OUTP
OUTN
A3
B3
MAX98357A
MAX98357B
LRCLK
DIN
FRAME CLOCK
DATA OUT
C2
GND
ꢁRESPONDS TO RIGHT CHANNEL WHEN GPIO IS HIGH.
ꢁꢁ69.8kΩ ASSUMES V = 1.8V.
GPIO
THE MAX98357A/B ARE SHUT DOWN WHEN GPIO IS LOW.
Figure 18. Right-Channel PCM Operation with 6dB Gain
2.5V TO 5.5V
10µF
0.1µF
CODEC
R
LARGE
(300kΩ)ꢁꢁ
V
GAINꢀSLOT DD
B2
A2
SD_MODE
BCLK
A1
C1
C3
B1
GPIOꢁ
BIT CLOCK
OUTP
OUTN
A3
B3
MAX98357A
MAX98357B
LRCLK
DIN
FRAME CLOCK
DATA OUT
C2
GND
ꢁLEFT AND RIGHT CHANNELS SUMMED WHEN GPIO IS HIGH.
ꢁꢁ300kΩ ASSUMES V = 1.8V.
GPIO
THE MAX98357A/B ARE SHUT DOWN WHEN GPIO IS LOW.
Figure 19. (Left/2 + Right/2) PCM Operation with 6dB Gain
Maxim Integrated
│ 30
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MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
2.5V TO 5.5V
10µF
0.1µF
V
GAIN_SLOT
B2
DD
SD_MODE
BCLK
A2
A1
C1
C3
B1
OUTP
OUTN
A3
MAX98357A
MAX98357B
LRCLK
DIN
B3
C2
GND
CODEC
*RESPONDS TO CHANNEL 0 WHEN GPIO IS HIGH.
THE MAX98357A/B ARE SHUT DOWN WHEN GPIO IS LOW.
GPIO*
BIT CLOCK
2.5V TO 5.5V
FRAME CLOCK
DATA OUT
10µF
0.1µF
R
SMALL
V
GAIN_SLOT
B2
DD
(69.8kΩ)**
SD_MODE
BCLK
A2
A1
C1
C3
B1
OUTP
OUTN
A3
B3
MAX98357A
MAX98357B
LRCLK
DIN
C2
GND
*RESPONDS TO RIGHT CHANNEL WHEN GPIO IS HIGH.
**69.8kΩ ASSUMES V = 1.8V.
GPIO
THE MAX98357A/B ARE SHUT DOWN WHEN GPIO IS LOW.
Figure 20. Stereo PCM Operation Using Two ICs
Maxim Integrated
│ 31
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MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
2.5V TO 5.5V
10µF
0.1µF
V
GAIN_SLOT
B2
DD
SD_MODE
BCLK
A2
A1
C1
C3
B1
OUTP
OUTN
A3
B3
MAX98357A
MAX98357B
LRCLK
DIN
C2
GND
*RESPONDS TO CHANNEL 0 WHEN GPIO IS HIGH.
THE MAX98357A/B ARE SHUT DOWN WHEN GPIO IS LOW.
2.5V TO 5.5V
10µF
0.1µF
CODEC
V
GAIN_SLOT
B2
DD
SD_MODE
BCLK
A2
A1
C1
C3
B1
OUTP
OUTN
GPIO*
BIT CLOCK
A3
B3
MAX98357A
MAX98357B
LRCLK
DIN
FRAME CLOCK
DATA OUT
C2
GND
*RESPONDS TO CHANNEL 1 WHEN GPIO IS HIGH.
THE MAX98357A/B ARE SHUT DOWN WHEN GPIO IS LOW.
2.5V TO 5.5V
10µF
0.1µF
V
GAIN_SLOT
B2
DD
SD_MODE
BCLK
A2
A1
C1
C3
B1
OUTP
OUTN
A3
B3
MAX98357A
MAX98357B
LRCLK
DIN
C2
GND
*RESPONDS TO CHANNEL 2 WHEN GPIO IS HIGH.
THE MAX98357A/B ARE SHUT DOWN WHEN GPIO IS LOW.
2.5V TO 5.5V
100kΩ
10µF
0.1µF
V
GAIN_SLOT
B2
DD
SD_MODE
BCLK
A2
A1
C1
C3
B1
OUTP
OUTN
A3
B3
MAX98357A
MAX98357B
LRCLK
DIN
C2
GND
*RESPONDS TO CHANNEL 3 WHEN GPIO IS HIGH.
THE MAX98357A/B ARE SHUT DOWN WHEN GPIO IS LOW.
Figure 21. Channel TDM Operation (Gain Fixed at 12dB)
Maxim Integrated
│ 32
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MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
Functional Diagram
2.5V TO 5.5V
10µF
0.1µF
V
DD
GAIN_SLOT
A2
B2
MAX98357A
MAX98357B
LRCLK
C3
A3 OUTP
B3 OUTN
BCLK C1
DIN B1
DIGITAL
AUDIO
INTERFACE
CLASS D
OUTPUT
STAGE
INTERPOLATOR
DAC
SD_MODE
A1
C2
GND
Filterless Class D Operation
Layout and Grounding
Traditional Class D amplifiers require an output filter
to recover the audio signal from the amplifier’s output.
The filter adds cost, size, and decreases efficiency
and THD+N performance. The ICs’ filterless modulation
scheme does not require an output filter. The device relies
on the inherent inductance of the speaker coil and the
natural filtering of both the speaker and the human ear to
recover the audio component of the square-wave output.
Proper layout and grounding are essential for optimum
performance. Good grounding improves audio perfor-
mance and prevents switching noise from coupling into
the audio signal.
Use wide, low-resistance output traces. As load imped-
ance decreases, the current drawn from the device out-
puts increases. At higher current, the resistance of the
output traces decreases the power delivered to the load.
For example, if 2W is delivered from the speaker output to
a 4Ω load through 100mΩ of total speaker trace, 1.904W
is being delivered to the speaker. If power is delivered
through 10mΩ of total speaker trace, 1.951W is being
delivered to the speaker. Wide output, supply, and ground
traces also improve the power dissipation of the ICs.
Parasitic capacitance on the output traces cause higher
Because the switching frequency of the ICs is well beyond
the bandwidth of most speakers, voice coil movement due
to the switching frequency is very small. Use a speaker
with a series inductance > 10µH. Typical 8Ω speakers
exhibit series inductances in the 20µH to 100µH range.
Power-Supply Input
V
DD
, which ranges from 2.5V to 5.5V, powers the IC,
quiescent current by V
x 300kHz x C
.
DD
PARASITIC
including the speaker amplifier. Bypass V
with a 0.1µF
DD
For example, at V
= 5V and a total parasitic capaci-
DD
and 10µF capacitor to GND. Some applications might
require only the 10µF bypass capacitor, making it pos-
sible to operate with a single external component. Apply
additional bulk capacitance at the ICs if long input traces
tance of 100pF (50pF on each output trace), the increase
in quiescent current is 5 x 300kHz x 100pF = 150µA.
The ICs are inherently designed for excellent RF immu-
nity. For best performance, add ground fills around all
signal traces on top or bottom PCB planes.
between V
and the power source are used.
DD
Maxim Integrated
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MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
Gains of 6dB, 9dB, and 12dB are selectable without
using a via or routing out the center bump of the WLP.
This simplifies the layout and allows for inexpensive PCB
fabrication. Here is a layout example with the gain set to
12dB. The center bump is tied to the adjacent GND pin.
Refer to Application Note 6643: Optimize Cost, Size, and
Performance with MAX98357 WLP for more information.
In many applications, the only passive component required
would be a single capacitor which results in a tiny solution
size of 4.32mm .
2
WLP Applications Information
For the latest application details on WLP construction,
dimensions, tape carrier information, PCB techniques,
bump-pad layout, and recommended reflow temperature
profile, as well as the latest information on reliability test-
ing results, refer to the Application Note 1891: Wafer-
Level Packaging (WLP) and Its Applications. Figure 24
shows the dimensions of the WLP balls used on the ICs.
0.24mm
Figure 22. WLP Pin Connect for set 12dB Gain Without Via.
1.78mm
0.21mm
2.49mm
Figure 24. MAX98357A/MAX98357B WLP Ball Dimensions
Figure 23. Example Layout Configured for Left-Channel Audio
and Gain of 12dB.
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +105°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
16 TQFN
16 TQFN
9 WLP
TOP MARK
MAX98357AETE+
MAX98357AETE+T
MAX98357AEWL+T
MAX98357AGTE/V+
MAX98357BETE+
MAX98357BETE+T
MAX98357BEWL+T
—
—
+AKM
+AKV
—
16 TQFN
16 TQFN
16 TQFN
9 WLP
—
+AKN
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
/V denotes an automotive-qualified part.
Maxim Integrated
│ 34
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MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE TYPE
9 WLP
PACKAGE CODE
W91F1+1
OUTLINE NO.
21-0896
LAND PATTERN NO.
Refer to Application Note 1891
90-0031
16 TQFN
T1633+4
21-0136
0.05 S
maxim
TM
integrated
0.05
AB
Maxim Integrated
│ 35
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MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
Package Information (continued)
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Maxim Integrated
│ 36
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MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
Package Information (continued)
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Maxim Integrated
│ 37
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MAX98357A/
MAX98357B
Tiny, Low-Cost, PCM Class D Amplifier with
Class AB Performance
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
9/13
Initial release
—
Added two new TOCs, replaced TOC 29, updated Figures 1–3, and made various
corrections
1, 4–20,
29–32, 34
1
11/13
2
3
4
5
6
7
8
8/14
1/15
2/15
6/15
8/15
2/16
6/16
Added THD+N for TQFN package with typical spec
Updated spread-spectrum bandwidth spec
Added automotive-qualified part
5
5, 28
34
Updated TOCs 30a and 30b
12
Corrected package outline for WLP package
Removed future product designations
36
34
Removed future product designation on MAX98357AGTE/V+
34
Updated dynamic range and output noise specifications in Electrical Characteristics
table
9
7/17
8/17
5
4
10
Updated soldering temperature in the Absolute Maximum Ratings section
Updated General Description, Features, and Applications sections, changed Class D
Switching Frequency in Electrical Characteristics table and other sections, replaced
TOC 20, added DC blocker information to Detailed Description section, updated and
added figures to Layout and Grounding section
1, 5, 11, 16,
28, 33, 34
11
5/18
Updated Features section to match Electrical Characteristics table typical values.
Added Startup section and new Figure 6 for startup requirements when using
BCLK = 256kHz
12
13
4/19
7/19
1, 17–34
11, 12
Updated TOCs 05 and 12
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
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