MIC7400YFL [MICREL]
Configurable PMIC, Five-Channel Buck Regulator Plus One-Boost with HyperLight Load® and I2C Control;
| 型号： | MIC7400YFL |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | Configurable PMIC, Five-Channel Buck Regulator Plus One-Boost with HyperLight Load® and I2C Control 集成电源管理电路 |
| 文件： | 总68页 (文件大小：5888K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MIC7400
Configurable PMIC, Five-Channel Buck
Regulator Plus One-Boost with
HyperLight Load® and I2C Control
General Description
Features
The MIC7400 is
a
powerful, highly integrated,
• Input voltage: 2.4V to 5.5V
configurable, power-management IC (PMIC) featuring five
synchronous buck regulators, one boost regulator and
high-speed I2C interface with an internal EEPROM.
• Five independent synchronous bucks up to 3A
• One independent non-synchronous boost 200mA
• 200µA quiescent current (all regulators on)
• 93% peak buck efficiency, 85% typical efficiency at 1mA
• Dual power mode: stand-by and normal mode
• I²C interface up to 3.4MHz
The device offers two distinct modes of operation “stand-
by mode” and “normal mode” intended to provide an
energy optimized solution suitable for portable handheld,
and infotainment applications.
In normal mode, the programmable switching converters
can be configured to support a variety of features,
including start-up sequencing, timing, soft-start ramp,
output voltage levels, current limit levels and output
discharge for each channel.
• I²C on-the-fly EEPROM programmability, featuring:
− Buck and boost output voltage scaling
− Power-on-reset threshold and delay
− Power-up sequencing/sequencing delay
− Buck and boost current limit
− Buck and boost pull-down when disabled
− Individual ON, OFF, and standby modes
− Soft-start and global power-good masking
• 23µA buck typical quiescent current
In stand-by mode the PMIC can configured in a low power
state by either disabling an output or by changing the
output voltage to a lower level. Independent exit from
stand-by mode can be achieved either by I2C
communication or the external STBY pin.
The device has five synchronous buck regulators with
high-speed adaptive on-time control supporting even the
challenging ultra-fast transient requirement for Core
supplies. One boost regulator provides a flash-memory
programming supply that delivers up to 200mA of output
current. The boost is equipped with an output disconnect
switch that opens if a short-to-ground fault is detected.
• 70µA boost typical quiescent current
• 1.5% output accuracy over temperature/line/load
• 2.0MHz boost switching frequency
• 1.3MHz buck operation in continuous mode
• Ultra-fast buck transient response
• 15mm × 15mm × 1.25mm solution size
• Thermal-shutdown and current-limit protection
An internal EEPROM enables a single-chip solution across
many platforms by allowing the designer to customize the
PMIC for their design. Modifications can be made without
the need to re-approve a new PMIC, saving valuable
design resources and time.
• 36-pin 4.5mm × 4.5mm × 0.85mm FQFN package
(0.4mm pitch)
• −40°C to +125°C junction temperature range
Applications
All switchers provide light-load efficiency with HyperLight
Load® mode for buck and PFM mode for boost. An
additional benefit of this proprietary architecture is very-low
output ripple voltage throughout the entire load range with
the use of small output capacitors. The MIC7400 is
designed for use with a small inductors (down to 0.47µH
for buck, 1.5µH for boost), and an output capacitor as
small as 10µF for buck, enabling a total solution size of
15mm × 15mm and less than 1mm height.
• Client and enterprise solid state drives (SSD)
• Consumer and in-vehicle infotainment devices
• Multimedia devices
• Portable handheld devices
• Security camera
• Gaming machines
• Service provider gateways
The datasheet and other support documentation can be
found on Micrel’s website at: www.micrel.com.
HyperLight Load is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
Revision 2.0
March 3, 2015
Micrel, Inc.
MIC7400
Typical Application
Ordering Information
Lead
Finish
Part Number
Marking
Output Voltages
Features
Package(1)
7400
1.8V, 1.1V, 1.8V
STBY – Active Low
36-Pin
Pb-
Free
MIC7400YFL
YWWS
1.05V, 1.25V, 12V
Falling Edge (DEFAULT) 4.5mm × 4.5mm FQFN
X
X 7400
X YYWW
X
36-Pin
Configurable
Pb-
Free
MIC7400-XXXXYFL (2)
Configurable
4.5mm × 4.5mm FQFN
Notes:
1. GREEN, RoHS-compliant package. Lead finish is Matte Tin. Mold compound is Halogen Free.
2. Configurable options available upon request. Contact Marketing.
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MIC7400
Table of Contents
List of Figures.......................................................................................................................................................................... 5
List of Tables........................................................................................................................................................................... 6
Pin Configuration..................................................................................................................................................................... 7
Pin Description ........................................................................................................................................................................ 7
Absolute Maximum Ratings ..................................................................................................................................................10
Operating Ratings .................................................................................................................................................................10
Electrical Characteristics.......................................................................................................................................................10
Typical Characteristics..........................................................................................................................................................15
Functional Characteristics.....................................................................................................................................................17
MIC7400 Block Diagram .......................................................................................................................................................24
Functional Description...........................................................................................................................................................25
Programmable Buck Soft-Start Control.............................................................................................................................25
Buck Digital Voltage Control (DVC)...................................................................................................................................26
Programmable Boost Soft-Start Control............................................................................................................................27
Boost Digital Voltage Control (DVC) .................................................................................................................................28
Buck Current Limit.............................................................................................................................................................28
Boost Current Limit............................................................................................................................................................29
Global Power Good Pin.....................................................................................................................................................29
Standard Delay..................................................................................................................................................................29
Power-Up Sequencing.......................................................................................................................................................29
Programmable Power-on-Reset (POR) Delay ..................................................................................................................30
Power-Down Sequencing..................................................................................................................................................30
Stand-By Mode..................................................................................................................................................................31
Resistive Discharge...........................................................................................................................................................31
STBY Pin ...........................................................................................................................................................................31
Safe Start-Up into a Pre-Biased Output ............................................................................................................................32
Buck Regulator Power Dissipation ....................................................................................................................................32
Total Power Dissipation.....................................................................................................................................................32
Power Derating..................................................................................................................................................................33
Overtemperature Fault ......................................................................................................................................................33
Thermal Measurements.....................................................................................................................................................34
Timing Diagrams...................................................................................................................................................................35
Normal Power-Up Sequence for Outputs..........................................................................................................................35
Standby (STBY) Pin (Wake-Up)............................................................................................................................................36
Evaluation Board Schematic.................................................................................................................................................37
Bill of Materials......................................................................................................................................................................38
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MIC7400
Table of Contents (Continued)
PCB Layout Guidelines
General..............................................................................................................................................................................39
IC .......................................................................................................................................................................................39
Input Capacitor ..................................................................................................................................................................39
Inductor..............................................................................................................................................................................39
Output Capacitor ...............................................................................................................................................................39
Proper Termination of Unused Pins......................................................................................................................................40
PCB Layout Recommendations............................................................................................................................................41
Package Information and Recommended Landing Pattern..................................................................................................45
Appendix A............................................................................................................................................................................46
I2C Control Register...........................................................................................................................................................47
Serial Port Operation.........................................................................................................................................................47
External Host Interface ..................................................................................................................................................47
Special Host I2C Commands .........................................................................................................................................48
Special Keys ..................................................................................................................................................................48
Appendix B............................................................................................................................................................................49
Register Settings Descriptions ..........................................................................................................................................49
Power Good Register (00’h) ..........................................................................................................................................49
EEPROM-Ready Register (01’h)...................................................................................................................................50
Fault Registers (02’h).....................................................................................................................................................51
Standby Register (03’h).....................................................................................................................................................52
Enable/Disable Register (04’h)..........................................................................................................................................53
Regulator Output Voltage Setting NORMAL Mode (05’h − 09’h)......................................................................................54
Boost Regulator Output Voltage Setting NORMAL Mode (0A’h) ......................................................................................55
Regulator Voltage Setting STBY Mode (0B’h – 0F’h) .......................................................................................................56
Boost Regulator Output Voltage Setting STBY Mode (10’h).............................................................................................57
Sequence Register (11’h)..................................................................................................................................................58
Delay Register (17’h).........................................................................................................................................................61
Soft-Start Registers (18’h − 1A’h)......................................................................................................................................62
Current-Limit (Normal Mode) Registers (1B’h − 1D’h) ......................................................................................................63
Current-Limit (STBY Mode) Registers (1E − 20’h)............................................................................................................65
Power-on-Reset (POR) Threshold Voltage Setting Register (21’h and 22’h)...................................................................66
Pull-Down when Disabled Register (23’h).........................................................................................................................67
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MIC7400
List of Figures
Figure 1. Buck Soft-Start.....................................................................................................................................................25
Figure 2. Buck Soft-Start.....................................................................................................................................................26
Figure 3. Buck DVC Control Ramp.....................................................................................................................................26
Figure 4. Buck DVC Control Ramp.....................................................................................................................................27
Figure 5. Boost Soft-Start Ramp.........................................................................................................................................27
Figure 6. Boost Soft-Start....................................................................................................................................................27
Figure 7. Boost DVC Control Ramp....................................................................................................................................28
Figure 8. Standard Delay Time...........................................................................................................................................29
Figure 9. Hot Plug − VIN Rising ...........................................................................................................................................30
Figure 10. POR .....................................................................................................................................................................30
Figure 11. Hot Un-Plug − VIN Falling.....................................................................................................................................30
Figure 12. I2C Stand-By Mode ..............................................................................................................................................31
Figure 13. Output Pull-Down Resistance..............................................................................................................................31
Figure 14. STBY-to-NORMAL Transition (DEFAULT)..........................................................................................................32
Figure 15. Pre-Biased Output Voltage ..................................................................................................................................32
Figure 16. Power Dissipation ................................................................................................................................................33
Figure 17. Power Derating Curve..........................................................................................................................................33
Figure 18. Hot Plug Input Voltage Spike...............................................................................................................................34
Figure 19. MIC7400 Power-Up/Down...................................................................................................................................35
Figure 20. MIC7400 STBY Function (DEFAULT) .................................................................................................................36
Figure 21. Connections for Unused Pins ..............................................................................................................................40
Figure 22. Read/Write Protocol.............................................................................................................................................47
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MIC7400
List of Tables
Table 1. Buck Outputs Default Soft-Start Time (DEFAULT).................................................................................................26
Table 2. Boost Output Default Soft-Start Time .....................................................................................................................28
Table 3. Buck Current Limit Register Settings......................................................................................................................28
Table 4. Summarization of Unused Pin Connections ...........................................................................................................40
Table 5. Power Good Status Register ..................................................................................................................................49
Table 6. EEPROM Status Register.......................................................................................................................................50
Table 7. Overcurrent Status Fault Register ..........................................................................................................................51
Table 8. Standby Register.....................................................................................................................................................52
Table 9. Enable Register.......................................................................................................................................................53
Table 10. DVC Registers for OUT[1 − 5] ..............................................................................................................................54
Table 11. DVC Registers for OUT6.......................................................................................................................................55
Table 12. Standby Registers.................................................................................................................................................56
Table 13. Standby DVC Register for OUT6..........................................................................................................................57
Table 14. Sequence State 1 Register ...................................................................................................................................59
Table 15. Sequence State 2 Register...................................................................................................................................59
Table 16. Sequence State 3 Register ...................................................................................................................................59
Table 17. Sequence State 4 Register ...................................................................................................................................60
Table 18. Sequence State 5 Register ...................................................................................................................................60
Table 19. Sequence State 6 Register ...................................................................................................................................61
Table 20. Delay Register.......................................................................................................................................................61
Table 21. Soft-Start Register Speed Settings.......................................................................................................................62
Table 22. Soft-Start Register OUT1 and OUT2 ....................................................................................................................62
Table 23. Soft-Start Register OUT3 and OUT4 ....................................................................................................................62
Table 24. Soft-Start Register OUT5 and OUT6 ....................................................................................................................63
Table 25. Current-Limit Register IOUT1 and IOUT2 ...................................................................................................................63
Table 26. Current-Limit Register IOUT3 and IOUT4 ...................................................................................................................64
Table 27. Current-Limit Register IOUT 5 and IOUT6 ...................................................................................................................64
Table 28. Standby Current-Limit Register IOUT1 and IOUT2 .....................................................................................................65
Table 29. Standby Current-Limit Register IOUT3 and IOUT4 .....................................................................................................65
Table 30. Standby Current-Limit Register IOUT5 and IOUT6 .....................................................................................................66
Table 31. Rising and Falling Power-on-Reset Threshold Voltage Settings..........................................................................66
Table 32. Power-on-Reset Rising Threshold Voltage Setting Register (21’h)......................................................................67
Table 33. Power-on-Reset Falling Threshold Voltage Setting Register (22’h) .....................................................................67
Table 34. Pull-Down when Disabled Register.......................................................................................................................67
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March 3, 2015
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Micrel, Inc.
MIC7400
Pin Configuration
36-Pin 4.5mm × 4.5mm FQFN (FL)
(Top View)
Pin Description
Pin Number
Pin Name Description
Switch Pin 2 (Output): Inductor connection for the synchronous step-down regulator. Connect the
inductor between the output capacitor and the SW2 pin.
1
SW2
Power Supply Voltage 2 (Input): Input supply to the source of the internal high-side P-channel
MOSFET. An input capacitor between PVIN2 and the power ground PGND2 pin is required and to be
placed as close as possible to the IC.
2
3
PVIN2
Output Voltage Sense 2 (Input): This pin is used to sense the output voltage. Connect OUT2 as close
to the output capacitor as possible to sense output voltage. Also provides the path to discharge the
output through an internal 90Ω resistor when disabled. This pull-down feature is programmed through
the PULLD[x] register.
OUT2
Power Supply Voltage 3 (Input): Input supply to the source of the internal high-side P-channel
MOSFET. An input capacitor between PVIN3 and the power ground PGND3 pin is required and to be
placed as close as possible to the IC.
4
5
6
PVIN3
SW3
Switch Pin 3 (Output): Inductor connection for the synchronous step-down regulator. Connect the
inductor between the output capacitor and the SW3 pin.
Power Ground 3: The power ground for the synchronous buck converter power stage. The PGND pin
connects to the sources of the internal low-side N-Channel MOSFET, the negative terminals of input
capacitors, and the negative terminals of output capacitors.
PGND3
Output Voltage Sense 3 (Input): This pin is used to sense the output voltage. Connect OUT3 as close
to the output capacitor as possible to sense output voltage. Also provides the path to discharge the
output through an internal 90Ω resistor when disabled. This pull-down feature is programmed through
the PULLD[x] register.
7
8
OUT3
PVIN4
Power Supply Voltage 4 (Input): Input supply to the source of the internal high-side P-channel
MOSFET. An input capacitor between PVIN4 and the power ground PGND4 pin is required and to be
placed as close as possible to the IC.
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Pin Description (Continued)
Pin Number
Pin Name Description
Switch Pin 4 (Output): Inductor connection for the synchronous step-down regulator. Connect the
inductor between the output capacitor and the SW4 pin.
9
SW4
Power Ground 4: The power ground for the synchronous buck converter power stage. The PGND pin
connects to the source of the internal low-side N-Channel MOSFET, the negative terminals of input
capacitors, and the negative terminals of output capacitors.
10
11
PGND4
Output Voltage Sense 4 (Input): This pin is used to sense the output voltage. Connect the OUT4 as
close to the output capacitor as possible to sense output voltage. Also provides the path to discharge
the output through an internal 90Ω resistor when disabled. This pull-down feature is programmed
through the PULLD[x] register.
OUT4
Standby Reset (Input): Standby mode allows the total power consumption to be reduced by either
lowering a supply voltage or turning it off. The IC can be placed in standby mode while operating in
normal mode by a high-to-low transition (DEFAULT) on the STBY input. When this occurs, the
STBY_MODEB bit will be set to logic “0”. Either a low-to-high transition on the STBY pin or an I²C
write command to the STBY_MODEB bit sets all of the regulators to their normal mode default
settings. This pin can be driven with either a digital signal or open collector output. Do not let this pin
float. Connect to ground or VIN. A pull-down resistor of 100kΩ or less can also be used. There are
both a high-to-low (DEFAULT) and low-to-high normal to standby trigger options available.
12
13
STBY
SDA
High-Speed Mode 3.4MHz I²C Data (Input/Output): This is an open drain, bidirectional data pin. Data
is read on the rising edge of the SCL and data is clocked out on the falling edge of the SCL. External
pull-up resistors are required.
Analog Ground: Internal signal ground for all low power circuits. Connect to ground plane for best
operation.
14
15
AGND
SCL
High-Speed Mode 3.4MHz I²C Clock (Input): I²C serial clock line open drain input. External pull-up
resistors are required.
Power-on-Reset (Output): This is an open drain output that goes high after the POR delay time
elapses. The POR delay time starts as soon as the AVIN pin voltage rises above the upper threshold
set by the PORUP register. The POR output goes low without delay when AVIN falls below the lower
threshold set by the PORDN register.
16
17
POR
Output Voltage Sense 5 (Input): This pin is used to sense the output voltage. Connect OUT5 as close
to the output capacitor as possible to sense output voltage. Also provides the path to discharge the
output through an internal 90Ω resistor when disabled. This pull-down feature is programmed through
the PULLD[x] register.
OUT5
Power Ground 5: The power ground for the synchronous buck converter power stage. The PGND pin
connects to the source of the internal low-side N-Channel MOSFET, the negative terminals of input
capacitors, and the negative terminals of output capacitors.
18
19
20
PGND5
SW5
Switch Pin 5 (Output): Inductor connection for the synchronous step-down regulator. Connect the
inductor between the output capacitor and the SW5 pin.
Power Supply Voltage 5 (Input): Input supply to the source of the internal high-side P-channel
MOSFET. An input capacitor between PVIN5 and the power ground PGND5 pin is required and to be
placed as close as possible to the IC.
PVIN5
Output Voltage 6 Sense (Input): This pin is used to sense the output voltage. Connect OUT6 as close
to the output capacitor as possible to sense output voltage. Also provides the path to discharge the
output through an internal programmable current source when disabled. This pull-down feature is
programmed through the PULLD[x] register.
21
OUT6
Power Ground 6: The power ground for the boost converter power stage. The PGND pin connects to
the source of the internal low-side N-Channel MOSFET, the negative terminals of input capacitors,
and the negative terminals of output capacitors.
22
23
PGND6
SW6
Switch Pin 6 (Input): Inductor connection for the boost regulator. Connect the inductor between the
PVIN6O and SW6 pin.
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Pin Description (Continued)
Pin Number
Pin Name Description
Power Supply Voltage 6 (Output): This pin is the output of the power disconnect switch for the boost
regulator. When the boost regulator is on, an internal switch provides a current path for the boost
inductor. In shutdown, an internal P-channel MOSFET is turned off and disconnects the boost output
from the input supply. This feature eliminates current draw from the input supply during shutdown. An
input capacitor between PVIN6O and the power ground PGND6 pin is required and place as close as
possible to the IC.
24
PVIN6O
25
26
PVIN6
PVIN1
Power Supply Voltage 6 (Input): Input supply to the internal disconnect switch.
Power Supply Voltage 1 (Input): Input supply to the source of the internal high-side P-channel
MOSFET. An input capacitor between PVIN1 and the power ground PGND1 pin is required and to be
placed as close as possible to the IC.
Switch Pin 1 (Output): Inductor connection for the synchronous step-down regulator. Connect the
inductor between the output capacitor and the SW1 pin.
27
28
SW1
Power Ground 1: The power ground for the synchronous buck converter power stage. The PGND pin
connects to the source of the internal low-side N-Channel MOSFET, the negative terminals of input
capacitors, and the negative terminals of output capacitors.
PGND1
Output Voltage Sense 1(Input): This pin is used to sense the output voltage remotely. Connect OUT1
as close to output capacitor as possible to sense output voltage. This feature also provides the path to
discharge the output through an internal 90Ω resistor when disabled. The pull-down feature is
programmed through the PULLD[x] register.
29
30
31
OUT1
VSLT
AVIN
POR Selection Threshold (Input): A high on this pin sets the PORUP and PORDN registers to their
upper threshold limits and a low to their lower threshold limits. Do not leave floating.
Analog Voltage Supply (Input): The start-up sequence begins as soon as the AVIN pin voltage rises
above the IC’s UVLO upper threshold. The outputs do not turn off until AVIN pin voltage falls below
the lower threshold limit. A 2.2µF ceramic capacitor from the AVIN pin to AGND pin must be placed
next to the IC.
Analog Ground: Internal signal ground for all low power circuits. Connect directly to the layer 2 ground
plane. Layer 2 is the point where all the PGNDs and AGND are connected. Do not connect PGND
and AGND together on the top layer.
32
AGND
33
34
NC
NC
No Connect. Must be left floating.
No Connect. Must be left floating.
Global Power Good (Output): This is an open drain output that is pulled high when all the regulator
power good flags are high. If an output falls below the power good threshold or a thermal fault occurs,
the global power good flag is pulled low. There is a falling edge de-glitch time of 50µs to prevent false
triggering on output voltage transients. A power good mask feature programmed through the
PGOOD_MASK[x] registers can be used to ignore a power good fault. When masked an individual
power good fault will not cause the global power good output to de-assert. Do not connect the power
good pull-up resistor to a voltage higher than AVIN.
35
PG
Power Ground 2: The power ground for the synchronous buck converter power stage. The PGND pin
connects to the source of the internal low-side N-Channel MOSFET, the negative terminals of input
capacitors, and the negative terminals of output capacitors.
36
PGND2
ePad
EP
Exposed Pad: Must be connected to the GND plane for full output power to be realized.
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MIC7400
Operating Ratings(4)
Absolute Maximum Ratings(3)
Input Voltage (PVIN[1-6])..................................... 2.4V to 5.5V
Analog Input Voltage (AVIN) ............................. 2.4V to 5.5V
Buck Output Voltage Range (VOUT[1-5])............. 0.8V to 3.3V
Boost Output Voltage Range (VOUT6) ................... 7V to 14V
Power Good Voltage (VPG)...................................0V to AVIN
Power-On Reset Output (VPOR)............................0V to AVIN
POR Threshold Voltage (VVSLT) ...........................0V to AVIN
Standby Voltage (VSTBY).......................................0V to AVIN
I²C IO (VSDA, VSCL)................................................0V to AVIN
Junction Temperature (TJ)(5) ......................-40°C to +125°C
Junction Thermal Resistance
Supply Voltages (PVIN[1-6]).................................. -0.3V to 6V
Analog Supply Voltage (AVIN) ............................ -0.3V to 6V
Buck Output Voltages (VOUT[1-5])......................... -0.3V to 6V
Boost Output Voltage (VOUT6)........................... -0.3V to 20V
Buck Switch Voltages (VSW[1-5]). ......................... -0.3V to 6V
Boost Switch Voltage (VSW6). ........................... -0.3V to 20V
Power Good Voltage (VPG).............................. -0.3V to AVIN
Power-On Reset Output (VPOR).......................... -0.3V to 6V
POR Threshold Voltage (VVSLT) ......................... -0.3V to 6V
Standby Voltage (VSTBY)..................................... -0.3V to 6V
I²C IO (VSDA, VSCL) ........................................... -0.3V to AVIN
AGND to PGND[1-6] ....................................... -0.3V to 0.3V
Ambient Storage Temperature (Ts) ...........-40°C to +150°C
ESD HBM Rating(6) ........................................................2kV
ESD MM Rating............................................................200V
4.5mm × 4.5mm FQFN-36 (θJA) ........................30°C/W
Electrical Characteristics(7)
VIN = AVIN = PVIN(1-6) = 5.0V; VOUT1 = 1.8V; VOUT2 = 1.1V; VOUT3 = 1.8V; VOUT4 = 1.05V; VOUT5 = 1.25V; VOUT6 = 12V (refer to the
Evaluation Board Schematic for component values). TA = 25°C, unless otherwise noted. Bold values indicate −40°C ≤ TJ ≤ +125°C.
Parameter
Conditions
Min.
2.4
Typ.
Max.
Unit
Input Supply (VIN)
5.5
Input Voltage Range (AVIN, PVIN[1-6]
Operating Quiescent Current
)
V
VIN = 5.0V; IOUT = 0A
200
0.3
240
μA
(8, 9)
into AVIN
Operating Quiescent Current
VIN = 5.0V; IOUT = 0A
AVIN Rising
1
μA
(8)
into PVIN
2.15
1.2
2.35
Undervoltage Lockout Threshold
Undervoltage Lockout Hysteresis
Standby Input (STBY)
2.25
150
V
mV
Logic Level High
Logic Level Low
V
V
0.4
200
200
Bias Current into Pin
Bias Current out of Pin
Rising/Falling Edge Reset Deglitch
Notes:
VSTBY = VIN
VSTBY = 0V
nA
nA
μs
100
3. Absolute maximum ratings indicate limits beyond which damage to the component may occur.
4. The device is not guaranteed to function outside its operating rating.
5. The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(Max), the junction-to-ambient thermal resistance, θJA,
and the ambient temperature, TA. The maximum allowable power dissipation will result in excessive die temperature, and the regulator will go into
thermal shutdown.
6. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5kΩ in series with 100pF.
7. Specification for packaged product only.
8. Tested in a non-switching configuration.
9. When all outputs are configured to the minimum programmable voltage.
Revision 2.0
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Electrical Characteristics(7) (Continued)
VIN = AVIN = PVIN(1-6) = 5.0V; VOUT1 = 1.8V; VOUT2 = 1.1V; VOUT3 = 1.8V; VOUT4 = 1.05V; VOUT5 = 1.25V; VOUT6 = 12V (refer to the
Evaluation Board Schematic for component values). TA = 25°C, unless otherwise noted. Bold values indicate −40°C ≤ TJ ≤ +125°C.
Parameter
Conditions
Min.
1.2
Typ.
Max.
Unit
POR Threshold Input (VSLT)
Logic Level High
V
V
0.4
200
200
Logic Level Low
Bias Current Into Pin
Bias Current Out of Pin
Power-On-Reset (POR) Comparator
VVSLT = VIN
VVSLT = 0V
nA
nA
POR Upper Comparator Range
POR Lower Comparator Range
POR Upper Comparator Range
AVIN Rising, VVSLT = 0V
AVIN Falling, VVSLT = 0V
AVIN Rising, VVSLT = VIN
AVIN Falling, VVSLT = VIN
2.646
2.548
3.626
3.528
2.7
2.6
3.7
3.6
2.754
2.652
3.774
3.672
V
V
V
V
POR Lower Comparator Range
Power Reset Output (POR) and Timer
POR Delay
18
20
50
75
22
ms
μs
POR Deglitch Delay
AVIN Falling
POR Output Low Voltage
POR Leakage Current
IPOR = 10mA (sinking)
VPOR = 5.5V
400
200
mV
nA
Global Power Good Output (PG)
Buck Power Good Threshold Voltage
Buck Hysteresis(10)
VOUT[1-5] Rising
VOUT[1-5] Falling
VOUT[6] Rising
VOUT[6] Falling
IPG = 10mA (sinking)
VPG = 5.5V
87
87
91
4
95
95
%VOUT
%VOUT
%VOUT
mV
Boost Power Good Threshold Voltage
Boost Hysteresis(10)
91
380
75
Power Good Output Low Voltage
Power Good Leakage Current
Power Good De-Glitch Delay
Output Sequencing Delay(10)
Thermal Protection
400
200
mV
0.01
100
1
nA
VOUT[1-6] Falling
μs
0.96
1.04
ms
Thermal Shutdown
TJ Rising
160
20
°C
°C
Thermal Hysteresis
Note:
10. Guaranteed by design.
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MIC7400
Electrical Characteristics(7) (Continued)
VIN = AVIN = PVIN(1-6) = 5.0V; VOUT1 = 1.8V; VOUT2 = 1.1V; VOUT3 = 1.8V; VOUT4 = 1.05V; VOUT5 = 1.25V; VOUT6 = 12V (refer to the
Evaluation Board Schematic for component values). TA = 25°C, unless otherwise noted. Bold values indicate −40°C ≤ TJ ≤ +125°C.
Parameter
Conditions
Min.
Typ.
Max.
Unit
Synchronous Buck (VOUT1 - VOUT5
)
Buck Output Voltage Accuracy (OUT[1-5])
Typical Output Voltage 1 Accuracy(11)
Typical Output Voltage 2 Accuracy(11)
Typical Output Voltage 3 Accuracy(11)
Typical Output Voltage 4 Accuracy(11)
Includes Load, Line, and Reference
−1.5%
−1.5%
−1.5%
−1.5%
%
%
%
%
1.5%
1.5%
1.5%
1.5%
Includes Load, Line, and Reference
Includes Load, Line, and Reference
Includes Load, Line, and Reference
Includes Load, Line, and Reference
Typical Output Voltage 5 Accuracy(11)
Output Voltage 1 Accuracy(11)
Output Voltage 2 Accuracy(11)
Output Voltage 3 Accuracy(11)
Output Voltage 4 Accuracy(11)
−1.5%
−1%
−1%
−1%
−1%
−1%
%
%
%
%
%
1.5%
1%
1%
1%
1%
1%
Output Voltage 5 Accuracy(11)
Load Regulation
%
%
%
IOUT = 10mA to IOUT(MAX)
VIN = 3.3V to 5.0V
0.1
Line Regulation
0.05
Buck Soft-Start
Soft-Start (1-5) LSB(10, 12)
Buck Internal MOSFETs
High-Side On-Resistance
High-Side On-Resistance
Low-Side On-Resistance
Low-Side On-Resistance
Output Pull-Down Resistance
Buck Controller Timing
Fixed On-Time(13)
3.84
4
4.16
µs/step
VIN = 3.3V; ISW[1-5] = 200mA
VIN = 5.0V; ISW[1-5] = 200mA
VIN = 3.3V; ISW[1-5] = -200mA
VIN = 5.0V; ISW[1-5] = -200mA
VSW[1-5] = 0V
54
40
37
30
90
mΩ
mΩ
mΩ
mΩ
Ω
75
200
VIN = 3.3; VOUT = 1.0V; IOUT = 1.0A
220
80
ns
ns
Minimum OFF-Time
Note:
11. Not tested in a closed loop configuration.
12. The soft-start time is calculated using the following equation: tsoftstart = [(VOUT_PROGRAM – 0.15)/0.05 +1) × tRAMP
.
13. Buck frequency is calculated using the following equation fSW = (VOUT/VIN) × (1/tON).
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Micrel, Inc.
MIC7400
Electrical Characteristics(7) (Continued)
VIN = AVIN = PVIN(1-6) = 5.0V; VOUT1 = 1.8V; VOUT2 = 1.1V; VOUT3 = 1.8V; VOUT4 = 1.05V; VOUT5 = 1.25V; VOUT6 = 12V (refer to the
Evaluation Board Schematic for component values). TA = 25°C, unless otherwise noted. Bold values indicate −40°C ≤ TJ ≤ +125°C.
Parameter
Conditions
Min.
Typ.
Max.
Unit
Buck Current Limit (OUT1-OUT5)
Buck 1 Current Limit Threshold
Buck 2 Current Limit Threshold
Buck 3 Current Limit Threshold
Buck 4 Current Limit Threshold
Buck 5 Current Limit Threshold
Gross High-Side Current Limit [1-5]
Zero Cross Threshold
3.075
3.075
3.075
4.88
4.1
4.1
4.1
6.1
4.1
150
0
5.125
5.125
5.125
7.32
See Table 3 for IPROG Settings
See Table 3 for IPROG Settings
See Table 3 for IPROG Settings
See Table 3 for IPROG Settings
See Table 3 for IPROG Settings
With Respect to Buck [x] Current Limit
Zero crossing detector
A
A
A
A
3.075
5.125
A
%
mV
Boost (VOUT6
)
Boost Output Voltage (VOUT6
)
Typical Output Voltage Accuracy(11)
Output Voltage Accuracy(11)
Load Regulation
Includes Load, Line, and Reference
%
%
-1.5%
-1%
1.5%
1%
IOUT6 = 1.0mA to 200mA
0.2
0.2
%
Line Regulation
VIN = 2.4V to 5.5V; IOUT6 = 10mA
VIN = 3.3V; VOUT6 = 12V
%
VOUT6 Discharge Current
Boost Soft-Start Step Duration
Soft-Start 6 LSB(10, 12)
111
148
185
mA
3.84
4
4.16
µs/step
Boost Internal MOSFETs
Low-Side On-Resistance
Low-Side On-Resistance
Boost Disconnect MOSFETs
Disconnect Switch On-Resistance
Disconnect Switch Current Limit
Boost Switching Frequency
Switching Frequency (PWM Mode)
Minimum Duty Cycle
160
140
mΩ
mΩ
VIN = 3.3V; ISW1 = −100mA
VIN = 5.0V; ISW1 = −100mA
IPVIN6O = 100mA; VIN = 3.3V
90
5
mΩ
A
1.92
35
2
2.08
45
MHz
%
40
85
Maximum Duty Cycle
80
90
%
Boost Current Limit
NMOS Current-Limit Threshold
2.24
A
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Micrel, Inc.
MIC7400
Electrical Characteristics(7) (Continued)
VIN = AVIN = PVIN(1-6) = 5.0V; VOUT1 = 1.8V; VOUT2 = 1.1V; VOUT3 = 1.8V; VOUT4 = 1.05V; VOUT5 = 1.25V; VOUT6 = 12V (refer to the
Evaluation Board Schematic for component values). TA = 25°C, unless otherwise noted. Bold values indicate −40°C ≤ TJ ≤ +125°C.
Parameter
Conditions
Min.
Typ.
Max.
Unit
I²C Interface
I²C Interface (SCL, SDA)
Low Level Input Voltage
High Level Input Voltage
High Level Input Current
Low Level Input Current
SDA Pull-Down Resistance
SDA Logic 0 Output Voltage
CLK, DATA Pin Capacitance
I²C Interface Timing(10)
0.4
V
V
1.2
0.01
0.01
20
200
200
nA
nA
Ω
−200
−200
0.4
ISDA = 3mA
V
0.7
pF
100
400
3.4
Standard Mode
Fast Mode
High-Speed Mode(10)
kHz
SCL Clock Frequency
MHz
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MIC7400
Typical Characteristics
Buck Efficiency (LDCR = 0mΩ)
Buck Efficiency (LDCR = 0mΩ)
Boost Efficiency (12V)
vs. Output Current
vs. Output Current
vs. Output Current
100
90
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
80
70
0.8V
1.0V
1.2V
1.5V
1.8V
60
50
40
30
0.8V
1.0V
1.2V
1.5V
1.8V
L = 2.2µH
DCR = 116mΩ
VIN = 3.3V
L = 2.2µH
TA = 25°C
SAMSUNG
CIG22H2R2MNE
TA = 25°C
VIN = 5.0V
L = 2.2µH
TA = 25°C
3.3V
5.0V
2.5V
3.3V
3
0.0001
0.001
0.01
0.1
1
0.0001
0.001
0.01
0.1
1
3
0.0001
0.001
0.01
0.1 0.2
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Buck Efficiency (LDCR = 40mΩ)
Buck Efficiency (LDCR = 40mΩ)
Output Voltage
vs. Output Current
vs. Output Current
vs. Output Current
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
2.0%
1.5%
1.0%
0.5%
0.0%
-0.5%
-1.0%
-1.5%
-2.0%
VIN = 3.3V
VOUT4 = 1.05V
0.8V
1.0V
0.8V
1.2V
VIN = 5.0V
L = 1.0µH
DCR = 40mΩ
SAMSUNG
CIGW252010GM1R0MNE
TA = 25⁰C
VIN = 5.0V
1.0V
-40
1.5V
1.8V
2.5V
3.3V
L = 1.0µH
DCR = 40mΩ
SAMSUNG
CIGW252010GM1R0MNE
1.2V
25
1.5V
1.8V
85
TA = 25°C
125
0.0001
0.001
0.01
0.1
1
3
0.0001
0.001
0.01
0.1
1
0.0001
0.001
0.01
0.1
1
10
3
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Buck Efficiency (LDCR = 116mΩ)
Buck Efficiency (LDCR = 116mΩ)
Output Voltage
vs. Temperature
vs. Output Current
vs. Output Current
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
1.0%
0.5%
0.0%
-0.5%
-1.0%
0.8V
1.0V
1.2V
0.8V
VIN = 5.0V
1.5V
L = 2.2µH
VIN = 3.3VL = 2.2µH
DCR = 116mΩ
SAMSUNG
CIG22H2R2MNE
TA = 25°C
1.0V
1.2V
1.5V
1.8V
DCR = 116mΩ
SAMSUNG
CIG22H2R2MNE
TA = 25°C
1.8V
VIN = 3.3V
VOUT4 = 1.05V
IOUT4 = 2.5A
2.5V
3.3V
0.0001
0.001
0.01
0.1
1
0.0001
0.001
0.01
0.1
1
-50
-25
0
25
50
75
100 125
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
TEMPERATURE (°C)
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MIC7400
Typical Characteristics (Continued)
Buck Output Voltage Regulation
vs. Output Current
Buck Line Regulation
vs. Input Voltage
Buck Output Voltage (1.0V)
vs. Output Current
0.035%
0.030%
0.025%
0.020%
0.015%
0.010%
0.005%
0.000%
1.001
1.000
1.000
0.999
0.999
0.998
0.20%
0.15%
0.10%
0.05%
0.00%
-0.05%
-0.10%
-0.15%
-0.20%
IOUT = 1A
TA = 25°C
3.3V
5V
3.3V
TA = 25°C
5V
TA = 25°C
0.0001
0.001
0.01
0.1
1
0.0001
0.001
0.01
0.1
1
2
3
4
5
6
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
INPUT VOLTAGE (V)
Buck 2 Switching Frequency
vs. Input Voltage
VIN Operating Supply Current
vs. Input Voltage
Dropout Output Voltage
vs. Output Current
1.5
300
250
200
150
100
50
3.3
3.1
2.9
2.7
2.5
2.3
2.1
1.9
1.4
1.3
1.2
1.1
1.0
0.9
0.8
VIN = 3.3V
VOUT = 3.3V
L = 2.2µH
DCR = 116mΩ
SAMSUNG
CIG22H2R2MNE
TA = 25⁰C
IOUT = 0A SWITCHING
RPG = OPEN
RPOR = OPEN
TA = 25⁰C
VOUT2 = 1.1V
IOUT2 = 0.5A
TA = 25°C
0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
0.0
1.0
2.0
3.0
4.0
5.0
0
1
2
3
OUTPUT CURRENT (A)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Output Current Limit
vs. Output Voltage
Programmed Current Limit
vs. Measured Current Limit
Current-Limit Threshold
vs. Output Voltage
6
5
4
3
2
1
6
5
4
3
2
1
0
6
5
4
3
2
1
0
VIN = 5.0V
VOUT = 1.05V
5.1A
4.6A
4.1A
3.6A
3.1A
2.6A
2.1A
1.6A
1.1A
5.1A
4.6A
4.1A
3.6A
3.1A
2.6A
2.1A
1.6A
1.1A
0
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
1
2
3
4
5
6
OUTPUT VOLTAGE (V)
PROGRAMMED CURRENT LIMIT (A)
OUTPUT VOLTAGE (V)
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Functional Characteristics
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Functional Characteristics (Continued)
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MIC7400
Functional Characteristics (Continued)
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MIC7400
Functional Characteristics (Continued)
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MIC7400
Functional Characteristics (Continued)
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MIC7400
Functional Characteristics (Continued)
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MIC7400
Functional Characteristics (Continued)
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MIC7400
MIC7400 Block Diagram
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MIC7400
Functional Description
The MIC7400 has a current-mode boost regulator that
can deliver up to 200mA of output current and only
consumes 70µA of quiescent current. The 2.0MHz
switching frequency allows small chip inductors to be
used. Programmable overcurrent sensing protects the
boost from overloads and an output disconnect switch
opens to protect against a short-circuit condition. Soft-
start is also programmable and controls both the rising
and falling output.
The MIC7400 is one of the industry’s most-advanced
PMIC designed for solid state drives (SSD) on the market
today. It is a multi-channel solution which offers software
configurable soft-start, sequencing, and digital voltage
control (DVC) that minimizes PC board area. These
features usually require a pin for programming. However,
this approach makes the IC larger by increasing pin
count, and also increases BOM cost due to the external
components.
Programmable Buck Soft-Start Control
The following is a complete list of programmable
features:
The MIC7400 soft-start feature forces the output voltage
to rise gradually, which limits the inrush current during
start-up. A slower output rise time will draw a lower input
surge current. The soft-start time is based on the least
significant bit (LSB) of an internal DAC and the speed of
the ramp rate, as shown in Figure 1. This illustrates the
soft-start waveform for all five synchronous buck
converters. The initial step starts at 150mV and each
subsequent step is 50mV.
• Buck output voltage (0.8V – 3.3V/50mV steps)
• Boost output voltage (7.0V – 14V/ 200mV steps)
• Power-on-reset (2.25V – 4.25V/50mV steps)
• Power-on-reset delay (5ms – 160ms/5ms steps)
• Power-up sequencing (6 time slots)
• Power-up sequencing delay (0ms – 7ms/1ms steps)
• Soft-start (4µs – 1024µs per step)
• Buck current limit threshold
− (1.1A to 6.1A/0.5A steps)
• Boost current limit threshold
− (1.76A to 2.6A/0.12A steps)
• Boost pull-down (37mA to 148mA/37mA steps)
• Buck pull-down (90Ω)
• Buck standby output voltage programmable
• Boost standby output voltage programmable
• Global power good masking
These features give the system designer the flexibility to
customize the MIC7400 for their application. For
example, VOUT1 current limit can be programmed to 4.1A
and VOUT2 can be set to 1.1A. These outputs can be
programmed to come up at the same time or 2.0ms
apart. In addition, in power-saving standby mode, the
outputs can either be turned off or programmed to a
lower voltage. With this programmability the MIC7400
can be used in multiple platforms.
Figure 1. Buck Soft-Start
The output ramp rate (tRAMP) is set by the soft-start
registers. Each output ramp rate can be individually set
from 4µs to 1024µs, see Table 1 for details.
The MIC7400 buck regulators are adaptive on-time
synchronous step-down DC-to-DC regulators. They are
designed to operate over a wide input voltage range from
2.4V to 5.5V and provide a regulated output voltage at up
to 3.0A of output current. An adaptive on-time control
scheme is employed to obtain a constant switching
frequency and to simplify the control compensation. The
device includes an internal soft-start function which
reduces the power supply input surge current at start-up
by controlling the output voltage rise time.
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Micrel, Inc.
MIC7400
The soft-start time tSS can be calculated by Equation 1:
V
− 0.15V
50mV
OUT
Eq. 1
t
=
× t
RAMP
SS
Where:
SS = Output rise time
OUT = Output voltage
RAMP = Output dwell time
t
V
t
For example:
Figure 2. Buck Soft-Start
Buck Digital Voltage Control (DVC)
1.8V − 0.15V
t
t
=
× 8ms
SS
SS
The output voltage has a 6-bit control DAC that can be
programmed from 0.8V to 3.3V in 50mV increments. If
the output is programmed to a higher voltage, then the
output ramps up, as shown in Figure 3.
50mV
= 264ms
Where:
OUT = 1.8V
tRAMP = 8.0µs
V
Table 1. Buck Outputs Default Soft-Start Time (DEFAULT)
VOUT
(V)
tRAMP
(µs)
tSS
(µs)
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
1.8
1.1
8
8
8
8
8
264
152
264
144
176
1.8
1.05
1.25
Figure 3. Buck DVC Control Ramp
Figure 2 shows the output of Buck 1 ramping up cleanly,
starting from 0.15V to its final 1.1V value.
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MIC7400
The ramp time is determined by Equation 2:
After the T1 period, the DAC output ramp starts, T2. The
total soft-start time, tSS, is the sum of both periods. Figure
6 displays the actual boost soft-start waveform.
V
− V
OUT _ INIT
OUT
∆t =
× t
Eq. 2
RAMP
50mV
Where:
V
OUT_INIT = Initial output voltage
OUT = Final output voltage
V
tRAMP = Output dwell time
When the regulator is set in stand-by mode or
programmed to a lower voltage, then the output voltage
ramps down at a rate determined by the output ramp rate
(tRAMP), the output capacitance and the external load.
Small loads result in slow output voltage decay and
heavy loads cause the decay to be controlled by the DAC
ramp rate.
Figure 5. Boost Soft-Start Ramp
In Figure 4, VOUT1 is switched to stand-by mode with an
I²C command and then switched back to normal mode
either by an I²C command or a low-to-high transition of
the STBY pin. In this case, the rise and fall times are the
same due to a 1A load on VOUT1
.
Figure 6. Boost Soft-Start
Figure 4. Buck DVC Control Ramp
Programmable Boost Soft-Start Control
The boost soft-start time is divided into two parts as
shown in Figure 5. T1 is a fixed 367µs delay starting from
when the internal enable goes high. This delay gives
enough time for the disconnect switch to turn on and
bring the inductor voltage to VIN before the boost is turned
on. There is a 50µs delay which is controlled by the
parasitic capacitance (Cgd) of the disconnect switch
before the output starts to rise.
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tSS = T1+ T2
MIC7400
The ramp time can be computed using Equation 3:
(
VOUT −1.4V
)
T2 =
T2 =
× t
RAMP
Eq. 2
0.2V
V
− V
OUT _INIT
OUT
∆t =
× t
Eq. 3
RAMP
(
12V −1.4V
)
0.2V
×16ms
0.2V
Where:
OUT_INIT = Initial output voltage
Table 2. Boost Output Default Soft-Start Time
Where:
V
T1 = 367µs
T2 = 848µs
tSS = 367µs + 848µs = 1.215ms
VOUT = Output voltage
VOUT
(V)
tRAMP
(µs)
tSS
(ms)
tRAMP = Output dwell time = 16µs
VOUT6
12
16
1.215
Boost Digital Voltage Control (DVC)
Buck Current Limit
The boost output control works the same way as the
buck, except that the voltage steps are 200mV, see
Figure 7. When the boost is programmed to a lower
voltage the output ramps down at a rate determined by
the output ramp rate (tRAMP), the output capacitance and
the external load. During both the ramp up and down
time, the power good output is blanked and if the power
good mask bit is set to “1”.
The MIC7400 buck regulators have high-side current
limiting that can be varied by a 4-bit code. If the regulator
remains in current limit for more than seven consecutive
PWM cycles, the output is latched off, the over-current
status register bit is set to 1, the power-good status
register bit is set to 0 and the global power good (PG)
output pin is pulled low. An overcurrent fault on one
output will not disable the remaining outputs. Table 3
shows the current limit register settings verses output
current. The current limit register setting is set at twice
the maximum output current.
Table 3. Buck Current Limit Register Settings
IOUT(MAX)
IPROG
BINARY
HEX
0.5A
1.0A
1.5A
2.0A
2.5A
3.0A
1.1A
2.1A
3.1A
4.1A
5.1A
6.1A
1111
1101
1011
1001
0111
0101
F’h
D’h
B'h
9'h
7'h
5'h
The output can be turned back on by recycling the input
power or by software control. To clear the overcurrent
fault by software control, set the enable register bit to “0”
then clear the overcurrent fault by setting the fault
register bit to “0”. This will clear the over-current and
power good status registers. Now the output can be re-
enabled by setting the enable register bit to “1”.
Figure 7. Boost DVC Control Ramp
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MIC7400
During start-up sequencing if Output 1 is still shorted,
Outputs 2 through 4 will come up normally. Once an
overcurrent condition is sensed, then the fault register is
set to “1” and the start-up sequence will stop and no
further outputs will be enabled. See Figure 9 for default
start-up sequence.
Standard Delay
There is a programmable timer that is used to set the
standard delay time between each time slot. The timer
starts as soon as the previous time slot’s output power
good goes high. When the delay completes, the
regulators assigned to that time slot are enabled, see
Figure 8.
Boost Current Limit
The boost current limit features cycle-by-cycle protection.
The duty cycle is cut immediately once the current limit is
hit. When the boost current limit is hit for five consecutive
cycles, the FAULT signal is asserted and remains
asserted with the boost converter keeping on running
until the boost is powered off.
This protects the boost in normal overload conditions, but
not in a short-to-ground case. For a short circuit to
ground, the boost current limit will not be able to limit the
inductor current. This short-circuit condition is sensed by
the current in the disconnect switch. When the disconnect
switch current limit is hit for four consecutive master clock
cycles (2MHz), regardless if the boost is switching or not,
both the disconnect switch and boost are latched off
automatically and the FAULT signal is asserted.
The output can be turned back on by recycling the input
power or by software control. To clear the overcurrent
fault by software control, set the enable register bit to “0”
then clear the overcurrent fault by setting the fault
register bit to “0”.
Figure 8. Standard Delay Time
Power-Up Sequencing
When power is first applied to the MIC7400, all I²C
registers are loaded with their default values from the
EEPROM. There is about a 1.5ms delay before the first
regulator is enabled while the MIC7400 goes through the
initialization process. The DELAY register’s STDEL bits
set the delay between powering up each regulator at
initial power up.
Global Power Good Pin
The global power-good output indicates that all the
outputs are above the 91% limit after the power-up
sequence is completed. Once the power-up sequence is
complete, the global power good output stays high unless
an output falls below its power-good limit, a thermal fault
occurs, the input voltage drops below the lower UVLO
threshold or an output is turned OFF by setting the
enable register bit to “0” unless the PGOOD_MASK[x] bit
is set to “1” (Default).
The sequencing registers allow the outputs to come up in
any order. There are six time slots that an output can be
configured to power up in. Each time slot can be
programmed for up to six regulators to be turned on at
once or none at all.
A power-good mask bit can be used to control the global
power good output. The power-good mask feature is
programmed through the PGOOD_MASK[x] registers and
is used to ignore an individual power-good fault. When
masked, PGOOD_MASK[x] bit is set to “1”, an individual
power good fault will not cause the global power good
output to de-assert.
Figure 9 shows an example of this feature. VOUT4 is
enabled in time slot 1. After a 1ms delay, VOUT2 and VOUT3
are enable at the same time in time slot 2. The 1ms is the
standard delay for all of the outputs and can be
programmed from 0ms to 7ms in 1ms. Next, VOUT1 is
powered up in time slot 3 and VOUT5 in time slot 4. There
are no regulators programmed for time slot 5. Finally,
VOUT6 is powered up in time slot 6. The global power good
output, VPG, goes high as soon as the last output reaches
91% of its final value.
If all the PGOOD_MASK[x] bits are set to “1”, then the
power good output de-asserts as soon as the first output
starts to rise. The PGOOD_MASK[x] bit of the last output
must be set to “0” to have the PG output stay low until the
last output reaches 91% of its final value.
The global power-good output is an open-drain output. A
pull-up resistor can be connected to VIN or VOUT. Do not
connect the pull-up resistor to a voltage higher than AVIN.
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Figure 10. POR
Power-Down Sequencing
When power is removed from VIN, all the regulators try to
maintain the output voltage until the input voltage falls
below the UVLO limit of 2.35V as shown in Figure 11.
Figure 9. Hot Plug − VIN Rising
VSLT Pin
The power-on reset threshold toggles between two
different ranges by driving the VSLT pin high or low. The
lower range of 2.25V to 3.25V is selected when the VSLT
pin is tied to ground. The upper range, 3.25V to 4.25V, is
selected when the VSLT pin is tied to VIN.
Programmable Power-on-Reset (POR) Delay
The POR output pin provides the user with a way to let
the SOC know that the input power is failing. If the input
voltage falls below the power-on reset lower threshold
level, the POR output immediately goes low. The lower
threshold is set in the PORDN register and the upper
threshold uses PORUP register.
The low-to-high POR transition can be delayed from 5ms
to 160ms in 5ms increments. This feature can be used to
signal the SOC that the power supplies are stable. The
PORDEL register sets the delay of the POR pin. The
POR delay starts as soon as the AVIN pin voltage rises
above the power-on reset upper threshold limit. Figure 10
shows the POR operation.
Figure 11. Hot Un-Plug − VIN Falling
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MIC7400
Stand-By Mode
Resistive Discharge
In stand-by mode, efficiency can be improved by lowering
the output voltage to the standby mode value or turning
an output off completely. There are two registers used for
setting the output voltage, normal-mode register and
stand-by mode register. The default power-up voltages
are set in the normal-mode registers.
To ensure a known output condition in stand-by mode,
the output is actively discharged to ground if the output is
disabled. Setting the buck pull down register field
PULLD[1-5] = 1 connects a 90Ω pull down resistor from
OUT[x] to PGND[x] when the MIC7400 is disabled. If
PULLD[x] = 0 the output drifts to PGND at a rate
determined by the load current and the output
capacitance value. The boost has a programmable pull-
down current level from 37mA to 148mA. In Figure 13,
the top trace shows the normal pull down and the bottom
trace is with the 90Ω pull-down.
An I²C write command to the STBY_CTRL_REG register
or the STBY pin can be used to set the MIC7400 into
stand-by mode. Figure 12 shows an I²C write command
implementation. In stand-by mode, the output can be
programmed to a lower voltage or turned completely off.
When disabled, the output will be soft-discharged to zero
if the PULLD[1-6] register are set to 1. If PULLD[x] = 0
the output drifts to PGND at a rate determined by the
load current and output capacitance.
In stand-by, if an output is disabled, the global power
good output is not affected when the PGOOD_MASK[x]
is set to logic 1. If the PGOOD_MASK[x] is set to logic 0,
then the global power good flag is pulled low. In Figure
12, all the PGOOD_MASK[x] bits are set to logic 1.
Figure 13. Output Pull-Down Resistance
STBY Pin
A pin-selectable STBY input allows the MIC7400 to be
placed into standby or normal mode. In standby mode,
the individual regulator can be turned on or off or the
output voltage can be set to a different value. If the
regulators are turned off, standby mode cuts the
quiescent current by 23µA for each buck regulator and
70µA for the boost.
Figure 14 illustrates the STBY pin operation. A low-to-
high transition on the STBY pin switches the output from
standby mode to normal mode. There is a 100µs STBY
deglitch time to eliminate nuisance tripping then all the
regulators are enabled at the same time and ramp up
with their programmed ramp rates.
A high-to-low
transition on the STBY pin switches the output from
normal mode to standby mode.
Figure 12. I2C Stand-By Mode
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Figure 15. Pre-Biased Output Voltage
Buck Regulator Power Dissipation
The total power dissipation in
a
MIC7400 is a
combination of the five buck regulators and the boost
dissipation. The buck regulators (OUT1 to OUT5)
dissipation is approximately the switcher’s input power
minus the switcher’s output power and minus the power
loss in the inductor:
Figure 14. STBY-to-NORMAL Transition (DEFAULT)
PD_BUCK ≈ VIN × IIN – VOUT × IOUT – PL_LOSS
Eq. 4
Safe Start-Up into a Pre-Biased Output
The MIC7400 is designed for safe start-up into a pre-
biased output. This prevents large negative inductor
currents which can cause the output voltage to dip and
excessive output voltage oscillations. A zero crossing
comparator is used to detect a negative inductor current.
If a negative inductor current is detected, the low-side
synchronous MOSFET functions as a diode and is
immediately turned off.
While the boost power dissipation is estimated by
Equation 5:
PD_BOOST ≈ VIN × IIN – VOUT x IOUT – PL_LOSS – Vf ×
IOUT
Eq. 5
Although the maximum output current for a single buck
regulator can be as much as 3A, the MIC7400 will
thermal limit and will not support this high output current
on all outputs at the same time.
Figure 15 shows a 1V output pre-bias at 0.5V at start-up,
see VOUT4 trace. The inductor current, Trace IL4, is not
allowed to go negative by more than 0.5A before the low-
side switch is turned off. This feature prevents high
negative inductor current flow in a pre-bias condition
which can damage the IC.
Total Power Dissipation
The total power dissipation in the MIC7400 package is
equal to the sum of the power loss of each regulator:
PD_TOTAL ≈ SUM (PD_SWITCHERS
)
Eq. 6
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Once the total power dissipation is calculated, the IC
junction temperature can be estimated using Equation 7:
TJ(MAX) ≈ TA + PD_TOTAL × θJA
Eq. 7
Where:
J(MAX) = The maximum junction temperature
TA = The ambient temperature
T
θJA = The junction-to-ambient thermal resistance of the
package (30°C/W)
Figure 17. Power Derating Curve
Figure 16 shows the measured junction temperature
versus power dissipation of the MIC7400 evaluation
board. The actual junction temperature of the IC depends
upon many factors. The significant factors influencing the
die temperature rise are copper thickness in the PCB, the
surface area available for convection heat transfer, air
flow and power dissipation from other components,
including inductors, SOCs and processor ICs. It is good
engineering practice to measure all power components
temperature during the final design review using a
thermal couple or IR thermometer, see the “Thermal
Measurements” sub-section for details.
The maximum power dissipation of the package can be
calculated by Equation 8:
T
− T
A
J(MAX)
P
≈
Eq. 8
D(MAX)
θ
JA
Where:
J(MAX) = Maximum junction temperature (125°C)
TA = Ambient temperature
T
θJA = Junction-to-ambient thermal resistance of the
package (30°C/W).
Overtemperature Fault
An overtemperature fault is triggered when the IC
junction temperature reaches 160°C. When this occurs,
both the overtemperature fault flag is set to “1”, the global
power good output is pulled low and all the outputs are
turned off. During the fault condition the I²C interface
remains active and all registers values are maintained.
When the die temperature decreases by 20°C the
overtemperature fault bit can be cleared. To clear the
fault, either recycle power or write a logic “0” to the over
temperature fault register. Once the fault bit is cleared,
the outputs power up to their default values and are
sequenced according to the time slot settings.
Figure 16. Power Dissipation
Power Derating
The MIC7400 package has a 2W power dissipation limit.
To keep the IC junction temperature below a 125°C
design limit, the output power has to be limited above an
ambient temperature of 65°C. Figure 17 shows the power
dissipation derating curve.
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Input Voltage “Hot Plug”
Thermal Measurements
High-voltage spikes twice the input voltage can appear
on the MIC7401 PVIN pins if a battery pack is hot-
plugged to the input supply voltage connection as shown
in Figure 18 (Trace 1). These spikes are due to the
inductance of the wires to the battery and the very low
inductance and ESR of the ceramic input capacitors. This
problem can be solved by placing a 150µF POS capacitor
across the input terminals. Figure 18 (Trace 2) shows
that the high-voltage spike is greatly reduced to a value
below the maximum allowable input voltage rating.
Measuring the IC’s case temperature is recommended to
ensure it is within its operating limits. Although this might
seem like a very elementary task, it is easy to get
erroneous results. The most common mistake is to use
the standard thermal couple that comes with a thermal
meter. This thermal couple wire gauge is large (typically
22 gauge) and behaves like a heatsink, resulting in a
lower case measurement.
Two reliable methods of temperature measurement are a
smaller thermal couple wire or an infrared thermometer. If
a thermal couple wire is used, it must be constructed of
36 gauge wire or higher (smaller wire size) to minimize
the wire heat-sinking effect. In addition, the thermal
couple tip must be covered in either thermal grease or
thermal glue to make sure that the thermal couple
junction is making good contact with the case of the IC.
Omega brand thermal couple (5SC-TT-K-36-36) is
adequate for most applications.
Whenever possible, an infrared thermometer is
recommended. The measurement spot size of most
infrared thermometers is too large for an accurate
reading on a small form factor ICs. However, an IR
thermometer from Optris has a 1mm spot size, which
makes it a good choice for measuring the hottest point on
the case. An optional stand makes it easy to hold the
beam on the IC for long periods of time.
Figure 18. Hot Plug Input Voltage Spike
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Timing Diagrams
Normal Power-Up Sequence for Outputs
The STDEL register sets the delay between powering up
of each regulator at initial power-up (see power-up
sequencing in Figure 19). Once all the internal power
good registers PGOOD[1-6] are all “1”, then the global
PG pin goes high without delay if the PGOOD_MASK[6]
bit is set to “0”.
The PORDEL register sets the delay for the POR flag pin.
The POR delay time starts as soon as the AVIN pin
voltage rises above the system UVLO upper threshold
set by the PORUP register. The POR output goes low
without delay if AVIN falls below the lower UVLO
threshold set by the PORDN register.
Figure 19. MIC7400 Power-Up/Down
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MIC7400
Standby (STBY) Pin (Wake-Up)
An I²C write command to the STBY_CTRL_REG register
or the STBY pin can be used to set the MIC7400 into
stand-by mode. The standby (STBY) pin provides a
hardware-specific manner in which to wake-up from
stand-by mode and go into normal mode. Figure 20
shows the STBY pin operation. A low-to-high transition
on the STBY pin switches the output from stand-by mode
to normal mode.
There is a 100µs STBY deglitch time to eliminate
nuisance tripping, then all the regulators are enabled at
the same time and ramp up with their programmed ramp
rates.
Figure 20. MIC7400 STBY Function (DEFAULT)
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MIC7400
Evaluation Board Schematic
VIN
VIN
+
C15
150µF
R7
0Ω
PGND
PGND
R6
499kΩ
VIN
C1
2.2µF
R1
100kΩ
VSLT
PG
2
VSLT
26
VIN
PVIN2
PVIN1
VIN
C9
10µF
C2
10µF
L2
2.2µH
L1
2.2µH
VOUT2
1
3
27
29
28
VOUT1
SW2
SW1
OUT1
1.1V/0.5A
1.8V/0.8A
C10
22µF
C3
22µF
OUT2
PGND2
36
PGND
VIN
PGND1
PGND
VIN
MIC7400
4
PVIN3
25
PVIN6
C11
10µF
L3
D1
L6
2.2µH
PMEG4002
VOUT3
1.8V/0.5A
5
7
6
2.2µH
SW3
24
23
VOUT6
12V/0.2A
PVIN6O
SW6
C12
22µF
OUT3
PGND3
C6
10µF
C4
10µF
PGND
VIN
C5
22µF
22
21
20
PGND6
OUT6
PGND
8
PVIN4
C13
10µF
L4
1.0µH
PVIN5
VIN
VOUT4
1.05V/3.0A
9
11
10
SW4
C7
10µF
L5
2.2µH
C14
22µF
OUT4
PGND4
19
17
18
VOUT5
1.25V/1.0A
SW5
OUT5
PGND
C8
22µF
VIN
PGND5
PGND
VIN
R4
VIN
499kΩ
TP14
R8
NF
R5
2kΩ
R3
2kΩ
R2
100kΩ
4
3
SDA
CLK
VIN
2
1
NC
STAND-BY
STAND-BY
POR
GND
PG
VSLT
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Bill of Materials
Item
Part Number
Manufacturer Description
Qty.
C1
CL05A225KO5NQNC
Samsung(14)
Samsung
Samsung
Samsung
2.2µF/16V, Ceramic, X5R, 0402, 0.8mm, ±10%
1
C2, C7, C9, C11,
C13
CL10A106MO8NQNC
CL21A106KAYNNNE
CL10A226MQ8NUNE
10µF/16V, Ceramic, X5R, 0603, 0.8mm, ±20%
10µF/25V, Ceramic, X5R, 0805, 1.25mm, ±20%
22µF/6.3V, Ceramic, X5R, 0603, 0.8mm, ±20%
5
2
6
C4, C6
C3, C5, C8, C10,
C12, C14
C15
D1
EEF-CX0J151XR
PMEG4002EL
Panasonic
NXP(15)
150µF/6.3V, POS Capacitor, SP, ±20%
0.2A/40V, Schottky, SOD-882
1
1
Samsung
R1, R2
RC1005F104CS
100kΩ, Resistor, 0402, 1%
3
2
1
1
5
1
Samsung
Samsung
Samsung
R3, R5
RC1005F202CS
2.0kΩ, Resistor, 0402, 1%
R4, R6
RC1005F4993CS
RC1005J000CS
499kΩ, Resistor, 0402, 1%
R7
0.00Ω, Resistor, 0402, Jumper
L1, L2, L3, L5, L6
L4
CIG22H2R2MNE
CIGW252010GM1R0MNE
Samsung
Samsung
2.2µH, 1.6A Inductor, 116mΩ, 2520 × 1.2mm (max)
1.0µH, 3.3A Inductor, 40mΩ, 2520 × 1.0mm (max)
Five-Channel Buck Regulator Plus One Boost
with HyperLight Load® and I2C Control
U1
MIC7400YFL
Micrel(16)
1
Notes:
14. Samsung: www.samsung.com.
15. NXP: www.nxp.com.
16. Micrel, Inc.: www.micrel.com.
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PCB Layout Guidelines
Input Capacitor
Warning!!! To minimize EMI and output noise, follow
these layout recommendations.
• A 10µF X5R or X7R dielectrics ceramic capacitor is
recommended on each of the PVIN pins for bypassing.
PCB layout is critical to achieve reliable, stable, and
efficient performance. A ground plane is required to
control EMI and minimize the inductance in power, signal,
and return paths.
• Place the input capacitors on the same side of the
board and as close to the IC as possible.
• Keep both the PVIN pin and PGND connections short.
• If possible, place vias to the ground plane close to the
each input capacitor ground terminal, but not in the
way of the high di/dit current path.
The following guidelines should be followed to ensure
proper operation:
General
• Use either X7R or X5R dielectric input capacitors. Do
• Most of the heat removed from the IC is due to the
exposed pad (EP) on the bottom of the IC conducting
heat into the internal ground planes and the ground
plane on the bottom side of the board. Use at least 16
vias for the EP to ground plane connection.
not use Y5V or Z5U type capacitors.
• Do not replace the ceramic input capacitor with any
other type of capacitor. Any type of capacitor can be
placed in parallel with the input capacitor.
• In “Hot-Plug” applications, a Tantalum or Electrolytic
bypass capacitor must be used to limit the over-voltage
spike seen on the input supply with power is suddenly
applied.
• Do not connect the PGND and AGND traces together
on the top layer. The single point connection is made
on the layer 2 ground plane.
• Do not put a via directly in front of a high current pin,
SW, PGND, or PVIN. This will increase the trace
resistance and parasitic inductance.
Inductor
• Keep the inductor connection to the switch node (SW)
short.
• Do not place a via in between the input and output
capacitor ground connection. Put it to the inside of the
output capacitor and in the way of the high di/dt
current path.
• Do not route any digital lines underneath or close to
the inductor.
• To minimize noise, place a ground plane underneath
• Route all power traces on the top layer, as shown in
the inductor.
the example layout.
Output Capacitor
• Place the input capacitors first and put them as close
• Use a wide trace to connect the output capacitor
ground terminal to the input capacitor ground terminal.
In the example layout, all input and output capacitor
ground connections are place back-to-back.
as possible to the IC.
IC
• The 2.2µF ceramic capacitor, which is connected to the
AVIN pin, must be located right at the IC. The AVIN pin
is very noise sensitive and placement of the capacitor
is very critical. Use wide traces to connect to the AVIN
and AGND pins.
• The OUT[1-6] trace should be separate from the power
trace and connected as close as possible to the output
capacitor. Sensing a long high-current load trace can
degrade the DC load regulation.
• The analog ground pin (AGND) must be connected
directly to the ground planes. Do not route the SGND
pin to the PGND Pad on the top layer.
• Use fat traces to route the input and output power
lines.
• Use Layer 5 as an input voltage power plane.
• Layer 2 and the bottom layer (Layer 6) are ground
planes.
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Proper Termination of Unused Pins
Many designs will not require all six DC-to-DC output
voltages. In these cases, the unused pin must be
connected to either VIN or GND.
The schematic in Figure 21 shows where to tie the unused
pins and Table
4
summarizes the connections.
VIN
VIN
+
C15
150µF
R7
0Ω
PGND
PGND
R6
499kΩ
VIN
C1
R1
100kΩ
2.2µF
VSLT
PG
2
VSLT
26
29
VIN
PVIN2
PVIN1
VIN
C9
10µF
L2
OUT1
2.2µH
VOUT2
1.1V/0.5A
1
3
SW2
27
28
SW1
C10
22µF
OUT2
PGND2
36
PGND
VIN
PGND1
MIC7400
4
PVIN3
25
PVIN6
VIN
C11
10µF
L3
2.2µH
VOUT3
1.8V/0.5A
5
7
6
SW3
24
23
PVIN6O
SW6
C12
22µF
OUT3
PGND3
PGND
VIN
22
21
20
PGND6
OUT6
8
PVIN4
C13
10µF
L4
1.0µH
PVIN5
VIN
VOUT4
1.05V/2.5A
9
11
10
SW4
C7
L5
2.2µH
C14
22µF
10µF
OUT4
PGND4
19
17
18
VOUT5
SW5
OUT5
1.25V/1.0A
PGND
C8
22µF
VIN
PGND5
PGND
VIN
R4
100kΩ
VIN
TP14
R8
NF
R5
2kΩ
R3
2kΩ
4
3
SDA
CLK
VIN
2
1
NC
STAND-BY
STAND-BY
POR
GND
PG
VSLT
Figure 21. Connections for Unused Pins
Table 4. Summarization of Unused Pin Connections
Unused
VIN
PGND
Boost
Buck
POR
PVIN6, PGIN6O, VOUT6
PVIN[x], VOUT[x}
PGND6, SW6
PGND[6], SW[x]
POR
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MIC7400
PCB Layout Recommendations
Evaluation Board Top Layer − Power Component Placement
Evaluation Board Top Layer − Layer 1 (Power Routing Layer)
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MIC7400
PCB Layout Recommendations (Continued)
Evaluation Board Top Layer − Layer 1 (Power Routing Layer)
Evaluation Board Layer 2 (Ground Plane)
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PCB Layout Recommendations (Continued)
Evaluation Board Top Layer − Layer 3 (Signal Routing Layer)
Evaluation Board Layer 4 (Ground Plane)
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PCB Layout Recommendations (Continued)
Evaluation Board Layer − Layer 5 (VIN Plane)
Evaluation Board Bottom Later − Layer 6 (Ground Plane)
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MIC7400
Package Information(17) and Recommended Landing Pattern
36-Pin 4.5mm × 4.5mm FQFN (FL)
Note:
17. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com.
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Via Layout Design and Layout Constraints
0.48
16x, dia. 0.2
1.80
0.48
1.80
Via Layout Design
Notes:
Dimensions in millimeters (mm).
This package is designed to be soldered to a thermal pad on the board. Connect all ground planes together
Customers should contact their board fabrication site for recommended solder mask tolerance and via tenting recommendations for vias placed in the
thermal pad.
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Appendix A
I2C Control Register
The MIC7400 I²C Read/Write registers are detailed here. During normal operation, the configuration data can be saved
into non-volatile registers in EEPROM by addressing the chip and writing to SAVECONFIG key = 66’h. Saving CONFIG
data to EEPROM takes time so the external host should poll the MIC7400 and read the CONFIG bit[1] of EEPROM Ready
register 01’h to determine the end of programming.
All transactions start with a control byte sent from the I²C master device. The control byte begins with a START condition,
followed by a 7-bit slave address. The slave address is seven bits long followed by an eighth bit which is a data direction
bit (R/W), a “0” indicates a transmission (WRITE) and a “1” indicates a request for data (READ). A data transfer is always
terminated by a STOP condition that is generated by the master.
Serial Port Operation
External Host Interface
Bidirectional I2C port capable of Standard (up to 100kbits/s), Fast (up to 400kbits/s), Fast Plus (up to 1Mbit/s) and High
Speed (up to 3.4Mbit/s) as defined in the I2C-Bus Specification.
The MIC7400 acts as an I2C slave when addressed by the external host. The MIC7400 slave address uses a fixed 7-bit
code and is followed by an R/W bit which is part of the control word that is right after the start bit as shown in Figure 22 in
the Device Address column.
The MIC7400 can receive multiple data bytes after a single address byte and automatically increments its register pointer
to block fill internal volatile memory. Byte data is latched after individual bytes are received so multi-byte transfers could
be corrupted if interrupted mid-stream.
No system clock is required by the digital core for I2C access from the external host (only the host SCL clock is assumed).
In order to prevent spurious operation of the I2C, if a start bit is seen, then any partial communication is aborted and new
I2C data is allowed. Start bit is when SDA goes low when SCL is high. Stop bit is when SDA goes high when SCL is high.
Normal I2C exchange is shown in Figure 22.
Figure 22. Read/Write Protocol
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Special Host I2C Commands
The following commands are all 2 byte communications:
Byte1 = device address with write bit set, LSB = 0
Byte2 = special key
Special Keys
•
•
SAVECONFIG Key = 66’h. Saves the shadow register configuration data into EEPROM registers 03’h thru 23’h.
RESET Key = 6A’h. Reloads only NORMAL mode voltage and current limit settings then enables the regulator to
NORMAL mode with no soft-start, no sequencing, and no delays. Then clears the STANDBY register bit 6 in register
03’h.
•
•
•
RELOAD Key = 6B’h. Reloads all data from EEPROM into the shadow registers. No other actions are performed,
including soft-start, sequencing, and delay.
REBOOT Key = 6C’h. Turns all regulators OFF, reloads EEPROM data into shadow registers, then re-sequences the
regulators with the programmed soft-start and sequence delays.
SEQUENCE Key = 6D’h. Turns all regulators OFF, restarts the sequencer including soft-start and sequence delays.
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Appendix B
Register Settings Descriptions
Power Good Register (00’h)
This register indicates when the regulators 1 − 6 output voltage is above 91% of the target value. The MIC7400 deglitches
the input signal for 50µs in order to prevent false events. The global PG pin indicator is functional ‘AND’ of all the power
good indicators during sequencing. Once the power-up sequence is complete, the global power good output stays high
unless an output falls below its power-good limit, a thermal fault occurs, the input voltage drops below the lower UVLO
threshold or an output is turned OFF by setting the enable register bit to “0” if the PGOOD_MASK[x] bit is set to “0”.
Table 5. Power Good Status Register
Register Name
Address
Power Good Status Register
0x00’h
PGOOD1-6_REG
Field
bit
R/W
Default
Description
Power Good indicator for Regulator 1
PGOOD1
PGOOD2
PGOOD3
PGOOD4
PGOOD5
PGOOD6
0
R
0
0
0
0
0
0
0 = Buck Not Valid
Power Good indicator for Regulator 2
0 = Buck Not Valid 1 = Buck Valid
Power Good indicator for regulator 3
0 = Buck Not Valid 1 = Buck Valid
Power Good indicator for Regulator 4
0 = Buck Not Valid 1 = Buck Valid
Power Good indicator for Regulator 5
0 = Buck Not Valid 1 = Buck Valid
Power Good indicator for Regulator 6
0 = Boost Not Valid 1 = Boost Valid
1 = Buck Valid
1
2
3
4
5
R
R
R
R
R
Reserved
Reserved
6
7
R/W
R/W
0
0
Not Used
Not Used
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EEPROM-Ready Register (01’h)
This register indicates the status of EEPROM to external I²C host.
The READY bit = 1 when the Trim and Configuration data have been loaded into core from EEPROM after reset, reboot
or reload and the chip is ready for operation. [If the SAVE1 bit in register 04’h is read in as logic 1, the configuration
registers will not be loaded from the EEPROM memory and the READY bit will still get set indicating that any startup
procedure involving the EEPROM memory is complete.] The READY bit will be set to 1 after loading or attempting to load
Trim and Configuration data from EEPROM into volatile memory. The Trim data will always be loaded and if SAVE1 bit in
register 04’h is set to logic 0, Configuration data is also loaded. Regardless of the SAVE1 bit being set or not, after the
loading operation the READY bit is set to 1.
The CONFIG bit = 1 when the Configuration data have been saved to EEPROM after the SAVECONFIG Code is issued
from the Host. If CONFIG=1 before the SAVECONFIG code is issued, CONFIG will be cleared immediately and then will
be set to logic 1 again once all Configuration data is written to the EEPROM memory.
The CALIB bit = 1 when the Trim data have been saved to EEPROM after the SAVETRIM Code is issued from the Host.
If CALIB=1 before the SAVETRIM code is issued, CALIB will be cleared immediately and then will be set to logic 1 again
once all Trim data is written to the EEPROM memory.
The EEPREAD and EEPWRITE bits indicate if an EEPROM read or write fault has occurred. These bits should be read
and cleared prior to reloading data from the EEPROM memory.
Table 6. EEPROM Status Register
Register Name
Address
EEPROM Status Register
STATUS_REG
0x01’h
Field
bit
R/W
Default Description
Indicate ready for operation when the trim and configuration data has been loaded
READY
CONFIG
CALIB
0
R
0
0
0
0 = Data not loaded
1 = Chip Ready
Indicate Configuration saved to EEPROM
0 = Configuration not saved
1
2
R
R
1 = Configuration Saved
Indicate trim data have been saved to EEROM
0 = Trim not saved
Not Used
1 = Trim saved
Reserved
Reserved
Reserved
3
4
5
R/W
R/W
R/W
0
0
0
Not Used
Not Used
EEPROM Read
0 = No Fault
EEPROM Write
0 = No Fault
EEPREAD
EEPWRITE
6
7
R/W
R/W
0
0
1 = Fault
1 = Fault
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Fault Registers (02’h)
This register indicates the over-current flag for each regulator and one global overtemperature (OT). These register bits
are set by an over current condition and reset by writing a logic “0” to each bit by the I²C host.
If the fault condition persists, the bit will be set to logic “1” again immediately by the MIC7400 after it is written to logic “0”
by the host.
Table 7. Overcurrent Status Fault Register
Register Name
Address
Overcurrent Status Fault Register
FAULT_REG
0x02’h
Field
bit
R/W
Default Description
Regulator 1 Overcurrent
0 = No Fault
REG1OC
REG2OC
REG3OC
REG4OC
REG5OC
0
R/W
0
0
0
0
0
1 = Fault
1 = Fault
1 = Fault
1 = Fault
1 = Fault
1 = Fault
Regulator 2 Overcurrent
0 = No Fault
1
2
3
4
R/W
R/W
R/W
R/W
Regulator 3 Overcurrent
0 = No Fault
Regulator 4 Overcurrent
0 = No Fault
Regulator 5 Overcurrent
0 = No Fault
Regulator 6 Overcurrent
0 = No Fault
REG6OC
Reserved
OT
5
6
7
R/W
R/W
R/W
0
0
0
Reserved
Overtemperature
0 = No Fault
1 = Fault
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Standby Register (03’h)
This register controls standby mode operation. Global stand-by mode can either be enabled by I²C or by changing the
logic state of the STBY input pin. Global stand-by is controlled by the STBY_MODEB bit. When STBY_MODEB [6] = 1
then the regulators output voltages are set to their normal-mode output voltage settings, (05’h – 0A’h) registers. When
STBY_MODEB [6] = 0 then regulators output voltages are set to the standby-mode output voltage settings, (0B’h – 10’h)
registers. If STBY [1-6] register is set to logic “0”, then the output is shut off in standby mode.
The global power good flag is asserted when an output is disabled unless the power good mask bit (PGOOD_MASK[x]) is
set to 1.
Table 8. Standby Register
Register Name
Address
Standby Register
STBY_CTRL_REG
0x03’h
Field
bit
R/W
Default Description
Regulator 1 Standby Voltage Control
0 = OFF
STBY1
STBY2
STBY3
STBY4
STBY5
STBY6
0
1
2
3
4
5
R/W
1
1
1
1
1
1
1 = ON
1 = ON
1 = ON
1 = ON
1 = ON
1 = ON
Regulator 2 Standby Voltage Control
0 = OFF
R/W
R/W
R/W
R/W
R/W
Regulator 3 Standby Voltage Control
0 = OFF
Regulator 4 Standby Voltage Control
0 = OFF
Regulator 5 Standby Voltage Control
0 = OFF
Regulator 6 Standby Voltage Control
0 = OFF
Global Standby Control
0 = All regulators in Standby Mode
1 = All regulators in Normal Mode
Not Used
STBY_MODEB
Reserved
6
7
R/W
R/W
1
0
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Enable/Disable Register (04’h)
This register controls the enable/disable of each DC-to-DC regulators. When EN(n) bit transitions from “0” to “1”, then the
regulator(n) is enabled with soft-start unless the STBY_MODEB register bit in register 03’h is set to logic “0”.
The configuration save bit “SAVE1” should be cleared by customer before saving configuration data to EEPROM. This bit
is used during power up to indicate via the Status register (00’h) that configuration data has previously been stored.
Table 9. Enable Register
Register Name
Address
Enable Register
EN_REG
0x04’h
Field
bit
R/W
Default Description
Regulator 1 ON/OFF Control bit
0 = OFF
EN1
EN2
EN3
EN4
EN5
0
R/W
1
1
1
1
1
1 = ON
1 = ON
1 = ON
1 = ON
1 = ON
1 = ON
Regulator 2 ON/OFF Control bit
0 = OFF
1
2
3
4
R/W
R/W
R/W
R/W
Regulator 3 ON/OFF Control
0 = OFF
Regulator 4 ON/OFF Control
0 = OFF
Regulator 5 ON/OFF Control
0 = OFF
Regulator 6 ON/OFF Control
0 = OFF
EN6
5
6
R/W
R/W
1
0
Reserved
Not Used
Save Configuration
0 = Configuration Saved to EEPROM
1 = Not Configuration Saved to EEPROM
SAVE1
7
R/W
0
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Regulator Output Voltage Setting NORMAL Mode (05’h − 09’h)
One register for each regulator output (OUT1 – OUT5). Sets output voltage of regulator for NORMAL mode operation.
Table 10. DVC Registers for OUT[1 − 5]
Register Name
DVC Registers for OUT[1-5]
OUT1-5_REG
OUT1 = 0x05’h
OUT2 = 0x06’h
OUT3 = 0x07’h
OUT4 = 0x08’h
OUT5 = 0x09’h
Address
Field
bit
R/W
Default
Description
Output Voltage setting of OUT[1-5]
DVC from 3.3 V to 0.8V in -50mV steps
000000 = 3.30V
000001 = 3.25V
000010 = 3.20V
000011 = 3.15V
000100 = 3.10V
000101 = 3.05V
000110 = 3.00V
000111 = 2.95V
001000 = 2.90V
001001 = 2.85V
001010 = 2.80V
001011 = 2.75V
001100 = 2.70V
001101 = 2.65V
001110 = 2.60V
001111 = 2.55V
Not Used
010000 = 2.50V
010001 = 2.45V
010010 = 2.40V
010011 = 2.35V
010100 = 2.30V
010101 = 2.25V
010110 = 2.20V
010111 = 2.15V
011000 = 2.10V
011001 = 2.05V
011010 = 2.00V
011011 = 1.95V
011100 = 1.90V
011101 = 1.85V
011110 = 1.80V
011111 = 1.75V
100000 = 1.70V
100001 = 1.65V
100010 = 1.60V
100011 = 1.55V
100100 = 1.50V
100101 = 1.45V
100110 = 1.40V
100111 = 1.35V
101000 = 1.30V
101001 = 1.25V
101010 = 1.20V
101011 = 1.15V
101100 = 1.10V
101101 = 1.05V
101110 = 1.00V
101111 = 0.95V
110000 = 0.90V
110001 = 0.85V
110010 = 0.80V
110011 = 0.80V
110100 = 0.80V
110101 = 0.80V
110110 = 0.80V
110111 = 0.80V
111000 = 0.80V
111001 = 0.80V
111010 = 0.80V
111011 = 0.80V
111100 = 0.80V
111101 = 0.80V
111110 = 0.80V
111111 = 0.80V
OUT[1-5]
5:0
R/W
See Table 2
6
7
0
0
Not Used
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Boost Regulator Output Voltage Setting NORMAL Mode (0A’h)
Sets output voltage of the boost regulator (OUT6) in NORMAL mode operation.
Table 11. DVC Registers for OUT6
Register Name
Address
DVC Registers
OUT6_REG
0x0A’h
Field
bit
R/W
Default
Description
DVC from 14V to 7V in 200mV decrements
000000 = 14.0V
000001 = 13.8V
010000 = 10.8V
010001 = 10.6V
010010 = 10.4V
010011 = 10.2V
010100 = 10.0V
010101 = 9.8V
010110 = 9.6V
010111 = 9.4V
011000 = 9.2V
011001 = 9.0V
011010 = 8.8V
011011 = 8.6V
011100 = 8.4V
011101 = 8.2V
011110 = 8.0V
011111 = 7.8V
100000 = 7.6V
100001 = 7.4V
100010 = 7.2V
100011 = 7.0V
100100 = 7.0V
100101 = 7.0V
100110 = 7.0V
100111 = 7.0V
101000 = 7.0V
101001 = 7.0V
101010 = 7.0V
101011 = 7.0V
101100 = 7.0V
101101 = 7.0V
101110 = 7.0V
101111 = 7.0V
110000 = 7.0V
110001 = 7.0V
110010 = 7.0V
110011 = 7.0V
110100 = 7.0V
110101 = 7.0V
110110 = 7.0V
110111 = 7.0V
111000 = 7.0V
111001 = 7.0V
111010 = 7.0V
111011 = 7.0V
111100 = 7.0V
111101 = 7.0V
111110 = 7.0V
111111 = 7.0V
000010 = 13.6V
000011 = 13.4V
000100 = 13.2V
000101 = 13.0V
000110 = 12.8V
OUT6
5:0
R/W
See Table 2 000111 = 12.6V
001000 = 12.4V
001001 = 12.2V
001010 = 12.0V
001011 = 11.8V
001100 = 11.6V
001101 = 11.4V
001110 = 11.2V
001111 = 11.0V
6
7
0
0
Not Used
Not Used
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Regulator Voltage Setting STBY Mode (0B’h – 0F’h)
This register is used to sets the output voltage of regulators 1 − 5 in STBY mode operation.
Table 12. Standby Registers
Register Name
Standby DVC Registers
STBY_ OUT1-5_REG
OUT1 = 0x0B’h
OUT2 = 0x0C’h
OUT3 = 0x0D’h
OUT4 = 0x0E’h
OUT5 = 0x0F’h
Address
Field
bit
R/W
Default
Description
Output Voltage setting of OUT[1-5]
DVC from 3.3 V to 0.8V in -50mV steps
000000 = 3.30V
000001 = 3.25V
000010 = 3.20V
000011 = 3.15V
000100 = 3.10V
000101 = 3.05V
000110 = 3.00V
000111 = 2.95V
001000 = 2.90V
001001 = 2.85V
001010 = 2.80V
001011 = 2.75V
001100 = 2.70V
001101 = 2.65V
001110 = 2.60V
001111 = 2.55V
Not Used
010000 = 2.50V
010001 = 2.45V
010010 = 2.40V
010011 = 2.35V
010100 = 2.30V
010101 = 2.25V
010110 = 2.20V
010111 = 2.15V
011000 = 2.10V
011001 = 2.05V
011010 = 2.00V
011011 = 1.95V
011100 = 1.90V
011101 = 1.85V
011110 = 1.80V
011111 = 1.75V
100000 = 1.70V
100001 = 1.65V
100010 = 1.60V
100011 = 1.55V
100100 = 1.50V
100101 = 1.45V
100110 = 1.40V
100111 = 1.35V
101000 = 1.30V
101001 = 1.25V
101010 = 1.20V
101011 = 1.15V
101100 = 1.10V
101101 = 1.05V
101110 = 1.00V
101111 = 0.95V
110000 = 0.90V
110001 = 0.85V
110010 = 0.80V
110011 = 0.80V
110100 = 0.80V
110101 = 0.80V
110110 = 0.80V
110111 = 0.80V
111000 = 0.80V
111001 = 0.80V
111010 = 0.80V
111011 = 0.80V
111100 = 0.80V
111101 = 0.80V
111110 = 0.80V
111111 = 0.80V
SB_OUT[1-5]
5:0
R/W
See Table 2
6
7
0
0
Not Used
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Boost Regulator Output Voltage Setting STBY Mode (10’h)
Sets output voltage of the boost regulator (OUT6) for STBY mode operation.
Table 13. Standby DVC Register for OUT6
Register Name
Address
DVC Registers
STBY _OUT6_REG
0x10’h
Field
bit
R/W
Default
Description
DVC from 14V to 7V in 200mV decrements
000000 = 14.0V
000001 = 13.8V
010000 = 10.8V
010001 = 10.6V
010010 = 10.4V
010011 = 10.2V
010100 = 10.0V
010101 = 9.8V
010110 = 9.6V
010111 = 9.4V
011000 = 9.2V
011001 = 9.0V
011010 = 8.8V
011011 = 8.6V
011100 = 8.4V
011101 = 8.2V
011110 = 8.0V
011111 = 7.8V
100000 = 7.6V
100001 = 7.4V
100010 = 7.2V
100011 = 7.0V
100100 = 7.0V
100101 = 7.0V
100110 = 7.0V
100111 = 7.0V
101000 = 7.0V
101001 = 7.0V
101010 = 7.0V
101011 = 7.0V
101100 = 7.0V
101101 = 7.0V
101110 = 7.0V
101111 = 7.0V
110000 = 7.0V
110001 = 7.0V
110010 = 7.0V
110011 = 7.0V
110100 = 7.0V
110101 = 7.0V
110110 = 7.0V
110111 = 7.0V
111000 = 7.0V
111001 = 7.0V
111010 = 7.0V
111011 = 7.0V
111100 = 7.0V
111101 = 7.0V
111110 = 7.0V
111111 = 7.0V
000010 = 13.6V
000011 = 13.4V
000100 = 13.2V
000101 = 13.0V
000110 = 12.8V
SB_OUT6
5:0
R/W
See Table 2 000111 = 12.6V
001000 = 12.4V
001001 = 12.2V
001010 = 12.0V
001011 = 11.8V
001100 = 11.6V
001101 = 11.4V
001110 = 11.2V
001111 = 11.0V
6
7
0
0
Not Used
Not Used
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Sequence Register (11’h)
Each regulator can be assigned to start in any one of six sequencing slots (1 to 6). If starting in slot 1, the regulator starts
immediately. If starting in any other slot the regulator must wait for the PGOOD=1 flags of all regulators assigned to the
preceding slot and then wait for the specified delay time (register 17’h) i.e., all PGOODs in preceding state flag then the
delay timer is started and when delay completes the regulator is enabled.
Each regulator must delay its startup (after the appropriate preceding PGOOD flags) by the delay set in the Delay
Register (17’h), unless the regulator is assigned to sequence state 0.
If all default Enable bits = 0 the IC starts up, but no outputs are enabled.
Sequencing is only used during initial startup, and not used when outputs are enabled via I²C command. If outputs are
enabled via I²C then soft-start is still active but start-up delays (timed from preceding PGOODs) are not.
Table 14. Sequence State 1 Register
Register Name
Address
Sequence Register
SEQ1_REG
0x11’h
Field
bit
R/W
Default Description
REG1SQ1
REG2SQ1
REG3SQ1
REG4SQ1
REG5SQ1
REG6SQ1
0
R/W
0
0
0
1
0
0
0 = No Start
0 = No Start
0 = No Start
0 = No Start
0 = No Start
1 = Regulator 1 will Start in Sequence State 1
1 = Regulator 2 will Start in Sequence State 1
1 = Regulator 3 will Start in Sequence State 1
1 = Regulator 4 will Start in Sequence State 1
1 = Regulator 5 will Start in Sequence State 1
1 = Regulator 6 will Start in Sequence State 1
1
2
3
4
5
R/W
R/W
R/W
R/W
R/W
0 = No Start
Reserved
Reserved
6
7
R/W
R/W
0
0
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Table 15. Sequence State 2 Register
Register Name
Address
Sequence Register
SEQ2_REG
0x12’h
Field
bit
R/W
Default Description
REG1SQ2
REG2SQ2
REG3SQ2
REG4SQ2
REG5SQ2
REG6SQ2
0
R/W
0
1
1
0
0
0
0 = No Start
0 = No Start
0 = No Start
0 = No Start
0 = No Start
1 = Regulator 1 will Start in Sequence State 2
1 = Regulator 2 will Start in Sequence State 2
1 = Regulator 3 will Start in Sequence State 2
1 = Regulator 4 will Start in Sequence State 2
1 = Regulator 5 will Start in Sequence State 2
1 = Regulator 6 will Start in Sequence State 2
1
2
3
4
5
R/W
R/W
R/W
R/W
R/W
0 = No Start
Reserved
Reserved
6
7
R/W
R/W
0
0
Table 16. Sequence State 3 Register
Register Name
Address
Sequence Register
SEQ3_REG
0x13’h
Field
bit
R/W
Default Description
REG1SQ3
REG2SQ3
REG3SQ3
REG4SQ3
REG5SQ3
REG6SQ3
0
R/W
1
0 = No Start
1 = Regulator 1 will Start in Sequence State 3
1 = Regulator 2 will Start in Sequence State 3
1 = Regulator 3 will Start in Sequence State 3
1 = Regulator 4 will Start in Sequence State 3
1 = Regulator 5 will Start in Sequence State 3
1 = Regulator 6 will Start in Sequence State 3
1
2
3
4
5
R/W
R/W
R/W
R/W
R/W
0
0 = No Start
0
0 = No Start
0
0 = No Start
0
0 = No Start
0
0 = No Start
6
7
R/W
R/W
0
0
Reserved
Reserved
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Table 17. Sequence State 4 Register
Register Name
Address
Sequence Register
SEQ4_REG
0x14’h
Field
bit
R/W
Default Description
REG1SQ4
REG2SQ4
REG3SQ4
REG4SQ4
REG5SQ4
REG6SQ4
0
R/W
0
0
0
0
1
0
0 = No Start
0 = No Start
0 = No Start
0 = No Start
0 = No Start
1 = Regulator 1 will Start in Sequence State 4
1 = Regulator 2 will Start in Sequence State 4
1 = Regulator 3 will Start in Sequence State 4
1 = Regulator 4 will Start in Sequence State 4
1 = Regulator 5 will Start in Sequence State 4
1 = Regulator 6 will Start in Sequence State 4
1
2
3
4
5
R/W
R/W
R/W
R/W
R/W
0 = No Start
Reserved
Reserved
6
7
R/W
R/W
0
0
Table 18. Sequence State 5 Register
Register Name
Address
Sequence Register
SEQ5_REG
0x15’h
Field
bit
R/W
Default Description
REG1SQ5
REG2SQ5
REG3SQ5
REG4SQ5
REG5SQ5
REG6SQ5
0
R/W
0
0 = No Start
1 = Regulator 1 will Start in Sequence State 5
1 = Regulator 2 will Start in Sequence State 5
1 = Regulator 3 will Start in Sequence State 5
1 = Regulator 4 will Start in Sequence State 5
1 = Regulator 5 will Start in Sequence State 5
1 = Regulator 6 will Start in Sequence State 5
1
2
3
4
5
R/W
R/W
R/W
R/W
R/W
0
0 = No Start
0
0 = No Start
0
0 = No Start
0
0 = No Start
0
0 = No Start
6
7
R/W
R/W
0
0
Reserved
Reserved
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Table 19. Sequence State 6 Register
Register Name
Address
Sequence Register
SEQ6_REG
0x16’h
Field
bit
R/W
Default Description
REG1SQ6
REG2SQ6
REG3SQ6
REG4SQ6
REG5SQ6
REG6SQ6
0
R/W
0
0
0
0
0
1
0 = No Start
0 = No Start
0 = No Start
0 = No Start
0 = No Start
1 = Regulator 1 will Start in Sequence State 6
1 = Regulator 2 will Start in Sequence State 6
1 = Regulator 3 will Start in Sequence State 6
1 = Regulator 4 will Start in Sequence State 6
1 = Regulator 5 will Start in Sequence State 6
1 = Regulator 6 will Start in Sequence State 6
1
2
3
4
5
R/W
R/W
R/W
R/W
R/W
0 = No Start
Reserved
Reserved
6
7
R/W
R/W
0
0
Delay Register (17’h)
The STDEL register sets the delay between powering up of each regulator at initial power up (see Figure 19). Once all the
internal power good registers PGOOD[1-6] are all “1”, then the global PG pin goes high without delay.
The PORDEL register sets the delay for the POR flag pin. The POR delay time starts as soon as AVIN pin voltage rises
above the system UVLO upper threshold set by the PORUP register (21’h). The POR output goes low without delay if
AVIN falls below the lower UVLO threshold set by the PORDN register (22’h).
Table 20. Delay Register
Register Name
Address
Delay Register
DELAY_CNTL_REG
0x17’h
Field
bit
R/W
Default Description
Delay Time from 0ms to 7ms in 1ms increment
001
(1ms)
STDEL
2:0
R/W
000 = 0ms
001 = 1ms
010 = 2ms
011 = 3ms
100 = 4ms
101 = 5ms
110 = 6ms
111 = 7ms
Delay Time from 5ms to 160ms in 5ms increment
00000 = 5ms
00001 = 10ms
00010 = 15ms
00011 = 20ms
00100 = 25ms
00101 = 30ms
00110 = 35ms
00111 = 40ms
01000 = 45ms
01001 = 50ms
01010 = 55ms
01011 = 60ms
01100 = 65ms
01101 = 70ms
01110 = 75ms
01111 = 80ms
10000 = 85ms
10001 = 90ms
10010 = 95ms
10011 = 100ms
10100 = 105ms
10101 = 110ms
10110 = 115ms
10111 = 120ms
11000 = 125ms
11001 = 130ms
11010 = 135ms
11011 = 140ms
11100 = 145ms
11101 = 150ms
11110 = 155ms
11111 = 160ms
00011
(20ms)
PORDEL
7:3
R/W
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Soft-Start Registers (18’h − 1A’h)
When regulator(n) is turned on from either the Enable Register (04’h) in NORMAL mode or from the Standby Register
(03’h) in STANDBY mode, then the three REG(n)SS soft-start bits are used to control both the rising and falling ramp rate
of the outputs.
In NORMAL mode, the outputs are stepped from the current regulator voltage settings to a newly-programmed regulator
voltage setting or to the default value.
On power-up, the regulator voltage output is set to the lowest possible voltage setting which is 3F’h. The voltage regulator
will change by one step or increment at a time. The amount of time between each step is controlled by the soft-start
registers. Table 21 details the amount of time for each encoded soft-start value.
Table 21. Soft-Start Register Speed Settings
R/W
Default Description
Soft-Start Time from 4µs to 512µs
SS_SPEED = 0
SS_SPEED = 1
R/W
000
000
000 = 4µs
001 = 8µs
010 = 16µs
011 = 32µs
100 = 64µs
110 = 256µs
111 = 512µs
101 = 128µs
Soft-Start Time from 8µs to 1024µs
R/W
000 = 8µs
010 = 32µs
011 = 64µs
100 = 128µs
101 = 256µs
110 = 512µs
001 = 16µs
111 = 1024µs
Table 22. Soft-Start Register OUT1 and OUT2
Register Name
Address
Soft-Start Register for VOUT1 and VOUT2
SS1-2_REG
0x18’h
Field
bit
R/W
Default Description
OUT1 Soft-Start Time
001
REG1SS
REG2SS
2:0
R/W
(8µs)
See Table 19 for Soft-Start Settings
OUT2 Soft-Start Time
001
5:3
6
R/W
R/W
R/W
(8µs)
See Table 19 for Soft-Start Settings
Reserved
0
0
Set the speed of the clock to slow or fast for different clock division, see Table 19.
0 = Slow Speed 1 = Fast Speed
SS_SPEED
7
Table 23. Soft-Start Register OUT3 and OUT4
Register Name
Address
Soft-Start Register for VOUT3 and VOUT4
SS3-4_REG
0x19’h
Field
bit
R/W
Default Description
OUT3 Soft-Start Time
See Table 19 for Soft-Start Settings
OUT4 Soft-Start Time
See Table 19 for Soft-Start Settings
Reserved
001
REG3SS
REG4SS
2:0
R/W
(8µs)
001
5:3
R/W
(8µs)
6
7
R/W
R/W
0
0
Reserved
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Table 24. Soft-Start Register OUT5 and OUT6
Register Name
Address
Soft-Start Register for VOUT5 and VOUT6
SS5-6_REG
0x1A’h
Field
bit
R/W
Default Description
OUT5 Soft-Start Time
See Table 19 for Soft-Start Settings
OUT6 Soft-Start Time
See Table 19 for Soft-Start Settings
Reserved
001
REG5SS
REG6SS
2:0
R/W
(8µs)
010
5:3
R/W
(16µs)
6
7
R/W
R/W
0
0
Reserved
Current-Limit (Normal Mode) Registers (1B’h − 1D’h)
This register is use to set the current limit for each DC-to-DC regulator in normal mode operation.
Table 25. Current-Limit Register IOUT1 and IOUT2
Register Name
Address
Current-Limit Register for VOUT1 and VOUT2
ILIMIT_1-2_REG
0x1B’h
Field
bit
R/W
Default Description
Normal current-limit for regulator 1 from 8.6A to 1.1A in 0.5A decrements
0000 = 8.6A
0001 = 8.1A
0010 = 7.6A
0011 = 7.1A
0100 = 6.6A
0101 = 6.1A
0110 = 5.6A
0111 = 5.1A
1000 = 4.6A
1001 = 4.1A
1010 = 3.6A
1011 = 3.1A
1100 = 2.6 A
1101 = 2.1A
1110 = 1.6A
1111 = 1.1A
1001
REG1CL
REG2CL
3:0
7:4
R/W
(4.1A)
Normal current-limit for regulator 2 from 8.6A to 1.1A in 0.5A decrements
0000 = 8.6A
0001 = 8.1A
0010 = 7.6A
0011 = 7.1A
0100 = 6.6A
0101 = 6.1A
0110 = 5.6A
0111 = 5.1A
1000 = 4.6A
1001 = 4.1A
1010 = 3.6A
1011 = 3.1A
1100 = 2.6 A
1101 = 2.1A
1110 = 1.6A
1111 = 1.1A
1001
R/W
(4.1A)
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Table 26. Current-Limit Register IOUT3 and IOUT4
Register Name
Address
Current-Limit Register for VOUT3 and VOUT4
ILIMIT_3-4_REG
0x1C’h
Field
bit
R/W
Default Description
Normal current-limit for regulator 3 from 8.6A to 1.1A in 0.5A decrements
0000 = 8.6A
0001 = 8.1A
0010 = 7.6A
0011 = 7.1A
0100 = 6.6A
0101 = 6.1A
0110 = 5.6A
0111 = 5.1A
1000 = 4.6A
1001 = 4.1A
1010 = 3.6A
1011 = 3.1A
1100 = 2.6 A
1101 = 2.1A
1110 = 1.6A
1111 = 1.1A
1001
REG3CL
REG4CL
3:0
7:4
R/W
(4.1A)
Normal current-limit for regulator 4 from 8.6A to 1.1A in 0.5A decrements
0000 = 8.6A
0001 = 8.1A
0010 = 7.6A
0011 = 7.1A
0100 = 6.6A
0101 = 6.1A
0110 = 5.6A
0111 = 5.1A
1000 = 4.6A
1001 = 4.1A
1010 = 3.6A
1011 = 3.1A
1100 = 2.6 A
1101 = 2.1A
1110 = 1.6A
1111 = 1.1A
0101
R/W
(6.1A)
Table 27. Current-Limit Register IOUT 5 and IOUT6
Register Name
Address
Current-Limit Register for VOUT5 and VOUT6
ILIMIT_5-6_REG
0x1D’h
Field
bit
R/W
Default Description
Normal current-limit for regulator 5 from 8.6A to 1.1A in 0.5A decrements
0000 = 8.6A
0001 = 8.1A
0010 = 7.6A
0011 = 7.1A
0100 = 6.6A
0101 = 6.1A
0110 = 5.6A
0111 = 5.1A
1000 = 4.6A
1001 = 4.1A
1010 = 3.6A
1011 = 3.1A
1100 = 2.6 A
1101 = 2.1A
1110 = 1.6A
1111 = 1.1A
1001
REG5CL
REG6CL
3:0
R/W
(4.1A)
Current limit from 2.6A to 1.78A in 0.12A decrements
011
6:4
7
R/W
R/W
000 = 2.6A
010 = 2.36A
011 = 2.24A
100 = 2.12A
101 = 2.00A
110 = 1.88A
111 = 1.76A
(2.24A)
001 = 2.48A
0
0 = Current Limit On
1 = Current Limit Off
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Current-Limit (STBY Mode) Registers (1E − 20’h)
This register is used to set the current limit for each DC-to-DC regulator when in standby (STBY) mode operation.
Table 28. Standby Current-Limit Register IOUT1 and IOUT2
Register Name
Address
Standby Current-Limit Register for VOUT1 and VOUT2
STBY_ILIMIT_1-2_REG
0x1E’h
Field
bit
R/W
Default
Description
Standby current limit for regulator 1 from 8.6A to 1.1A in 0.5A decrements
0000 = 8.6A
0001 = 8.1A
0010 = 7.6A
0011 = 7.1A
0100 = 6.6A
0101 = 6.1A
0110 = 5.6A
0111 = 5.1A
1000 = 4.6A
1001 = 4.1A
1010 = 3.6A
1011 = 3.1A
1100 = 2.6 A
1101 = 2.1A
1110 = 1.6A
1111 = 1.1A
1001
SB1CL
SB2CL
3:0
R/W
(4.1A)
Standby current limit for regulator 2 from 8.6A to 1.1A in 0.5A decrements
0000 = 8.6A
0001 = 8.1A
0010 = 7.6A
0011 = 7.1A
0100 = 6.6A
0101 = 6.1A
0110 = 5.6A
0111 = 5.1A
1000 = 4.6A
1001 = 4.1A
1010 = 3.6A
1011 = 3.1A
1100 = 2.6 A
1101 = 2.1A
1110 = 1.6A
1111 = 1.1A
1001
7:4
R/W
(4.1A)
Table 29. Standby Current-Limit Register IOUT3 and IOUT4
Register Name
Address
Standby Current-Limit Register for VOUT3 and VOUT4
STBY_ILIMIT_3-4_REG
0x1F’h
Field
bit
R/W
Default
Description
Standby current limit for regulator 3 from 8.6A to 1.1A in 0.5A decrements
0000 = 8.6A
0001 = 8.1A
0010 = 7.6A
0011 = 7.1A
0100 = 6.6A
0101 = 6.1A
0110 = 5.6A
0111 = 5.1A
1000 = 4.6A
1001 = 4.1A
1010 = 3.6A
1011 = 3.1A
1100 = 2.6 A
1101 = 2.1A
1110 = 1.6A
1111 = 1.1A
1001
SB3CL
SB4CL
3:0
R/W
(4.1A)
Standby current limit for regulator 4 from 8.6A to 1.1A in 0.5A decrements
0000 = 8.6A
0001 = 8.1A
0010 = 7.6A
0011 = 7.1A
0100 = 6.6A
0101 = 6.1A
0110 = 5.6A
0111 = 5.1A
1000 = 4.6A
1001 = 4.1A
1010 = 3.6A
1011 = 3.1A
1100 = 2.6 A
1101 = 2.1A
1110 = 1.6A
1111 = 1.1A
0101
7:4
R/W
(6.1A)
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Table 30. Standby Current-Limit Register IOUT5 and IOUT6
Register Name
Address
Standby Current-Limit Register for VOUT5 and VOUT6
STBY_ILIMIT_5-6_REG
0x20’h
Field
bit
R/W
Default
Description
Standby current limit for regulator 5 from 8.6A to 1.1A in 0.5A decrements
0000 = 8.6A
0001 = 8.1A
0010 = 7.6A
0011 = 7.1A
0100 = 6.6A
0101 = 6.1A
0110 = 5.6A
0111 = 5.1A
1000 = 4.6A
1001 = 4.1A
1010 = 3.6A
1011 = 3.1A
1100 = 2.6 A
1101 = 2.1A
1110 = 1.6A
1111 = 1.1A
1001
SB5CL
SB6CL
3:0
R/W
(4.1A)
Current limit from 2.6A to 1.78A in 0.12A decrements
011
6:4
7
R/W
R/W
000 = 2.6A
010 = 2.36A
011 = 2.24A
100 = 2.12A
101 = 2.00A
110 = 1.88A
111 = 1.76A
(2.24A)
001 = 2.48A
0
0 = Current Limit On
1 = Current Limit Off
Power-on-Reset (POR) Threshold Voltage Setting Register (21’h and 22’h)
This register is used to set the rising and falling threshold of power-on-reset (POR) comparator. The POR threshold
voltage setting is based on the logic level of the VSLT pin in addition to the register bits. Refer to Table 20 for POR time
delay settings.
Table 31. Rising and Falling Power-on-Reset Threshold Voltage Settings
Rising and Falling Power-On-Reset Threshold Voltage Setting
bit
R/W
Default
Description
3.3V to 2.3V in 50mV decrements
00000 = 3.25V
00001 = 3.20V
00010 = 3.15V
00011 = 3.10V
00100 = 3.05V
00101 = 3.00V
00110 = 2.95V
00111 = 2.90V
01000 = 2.85V
01001 = 2.80V
01010 = 2.75V
01011 = 2.70V
01100 = 2.65V
01101 = 2.60V
01110 = 2.55V
01111 = 2.50V
10000 = 2.45V
10001 = 2.40V
10010 = 2.35V
10011 = 2.30V
10100 = 2.25V
10101 = 2.25V
10110 = 2.25V
10111 = 2.25V
11000 = 2.25V
11001 = 2.25V
11010 = 2.25V
11011 = 2.25V
11100 = 2.25V
11101 = 2.25V
11110 = 2.25V
11111 = 2.25V
VSCLT = 0
4:0
R/W
00000
4.3V to 3.3V in 50mV decrements
00000 = 4.25V
00001 = 4.20V
00010 = 4.15V
00011 = 4.10V
00100 = 4.05V
00101 = 4.00V
00110 = 3.95V
00111 = 3.90V
01000 = 3.85V
01001 = 3.80V
01010 = 3.75V
01011 = 3.70V
01100 = 3.65V
01101 = 3.60V
01110 = 3.55V
01111 = 3.50V
10000 = 3.45V
10001 = 3.40V
10010 = 3.35V
10011 = 3.30V
10100 = 3.25V
10101 = 3.25V
10110 = 3.25V
10111 = 3.25V
11000 = 3.25V
11001 = 3.25V
11010 = 3.25V
11011 = 3.25V
11100 = 3.25V
11101 = 3.25V
11110 = 3.25V
11111 = 3.25V
VSCLT = 1
4:0
R/W
00000
The three most significant bits [7:5] in registers 21’h and 22’h are used to mask the output voltage power-good flag after
the start-up sequenced is finished.
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Table 32. Power-on-Reset Rising Threshold Voltage Setting Register (21’h)
Register Name
Address
Power-on-Reset Falling Threshold
PORUO_REG
0x21’h
Field
bit
4:0
5
R/W
R/W
R/W
R/W
R/W
Default
Description
See Table 28
PORUP
01011 (2.7V)
PGOOD_MASK1
PGOOD_MASK2
PGOOD_MASK3
1
1
1
0 = Do not mask PGOOD1
1 = Mask PGOOD1
1 = Mask PGOOD2
1 = Mask PGOOD3
6
0 = Do not mask PGOOD2
0 = Do not mask PGOOD3
7
Table 33. Power-on-Reset Falling Threshold Voltage Setting Register (22’h)
Register Name
Address
Power-on-Reset Falling Threshold
PORDN_REG
0x22’h
Field
bit
4:0
5
R/W
R/W
R/W
R/W
R/W
Default
Description
See Table 28
PORDN
01101 (2.6V)
PGOOD_MASK4
PGOOD_MASK5
PGOOD_MASK6
1
1
1
0 = Do not mask PGOOD4
0 = Do not mask PGOOD5
0 = Do not mask PGOOD6
1 = Mask PGOOD4
1 = Mask PGOOD5
1 = Mask PGOOD6
6
7
Pull-Down when Disabled Register (23’h)
This register is used to set the preference of enabling/disabling a pull-down FET when the DC-to-DC regulators are
disabled. The pull-down value for buck regulators 1 − 5 is 90Ω. The pull-down current value for the boost regulator 6 is
programmable.
Table 34. Pull-Down when Disabled Register
Register Name
Address
Pull-Down when Disabled Register
PULLDN1-6_REG
0x23’h
Field
bit
R/W
Default Description
Enable/Disable the pull-down on Regulator 1 when power down
PULLD1
PULLD2
PULLD3
PULLD4
PULLD5
PULLD6C
PULLD6
0
1
R/W
0
0
0 = No Pull Down
Enable/Disable the pull-down on Regulator 2 when power down
0 = No Pull-Down 1 = Pull-Down
Enable/Disable the pull-down on Regulator 3 when power-down
0 = No Pull-Down 1 = Pull Down
Enable/Disable the pull-down on Regulator 4 when power down
0 = No Pull-Down 1 = Pull-Down
Enable/Disable the pull-down on Regulator 5 when power-down
1 = Pull-Down
R/W
R/W
R/W
R/W
R/W
R/W
2
0
3
0
4
0
0 = No Pull-Down
1 = Pull-Down
Sets Boost Pull-Down Current Level
6:5
7
00
0
00 = 148mA
Enable/Disable the pull-down on Regulator 6 when power-down
0 = No Pull-Down 1 = Pull-Down
01 = 111mA
10 = 74mA
11 = 37mA
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MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
Micrel, Inc. is a leading global manufacturer of IC solutions for the worldwide high-performance linear and power, LAN, and timing & communications
markets. The Company’s products include advanced mixed-signal, analog & power semiconductors; high-performance communication, clock
management, MEMs-based clock oscillators & crystal-less clock generators, Ethernet switches, and physical layer transceiver ICs. Company
customers include leading manufacturers of enterprise, consumer, industrial, mobile, telecommunications, automotive, and computer products.
Corporation headquarters and state-of-the-art wafer fabrication facilities are located in San Jose, CA, with regional sales and support offices and
advanced technology design centers situated throughout the Americas, Europe, and Asia. Additionally, the Company maintains an extensive network
of distributors and reps worldwide.
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this datasheet. This
information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry,
specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability
whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product
can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical
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