SY100S331JZTR [MICREL]
TRIPLE D FLIP-FLOP; 三重D触发器
| 型号： | SY100S331JZTR |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | TRIPLE D FLIP-FLOP |
| 文件： | 总8页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SY100S331
TRIPLE D
FLIP-FLOP
FEATURES
DESCRIPTION
The SY100S331 offers three D-type, edge-triggered
master/slave flip-flops with true and complement outputs,
designed for use in high-performance ECL systems. Each
flip-flop is controlled by a common clock (CPc), as well as
its own clock pulse (CPn). The resultant clock signal
controlling the flip-flop is the logical OR operation of these
two clock signals. Data enters the master when both CPc
and CPn are LOW and enters the slave on the rising edge
of either CPc or CPn (or both).
■ Max. toggle frequency of 800MHz
■ Differential outputs
■ IEE min. of –80mA
■ Industry standard 100K ECL levels
■ Extended supply voltage option:
VEE = –4.2V to –5.5V
■ Voltage and temperature compensation for improved
noise immunity
Additional control signals include Master Set (MS) and
Master Reset (MR) inputs. Each flip-flop also has its own
Direct Set (SDn) and Direct Clear (CDn) signals. The MR,
MS, SDn and DCn signals override the clock signals. The
inputs on this device have 75KΩ pull-down resistors.
■ Internal 75KΩ input pull-down resistors
■ 150% faster than Fairchild
■ 40% lower power than Fairchild
■ Function and pinout compatible with Fairchild F100K
■ Available in 24-pin CERPACK and 28-pin PLCC
packages
BLOCK DIAGRAM
PIN NAMES
Pin
CP0 – CP2
CPc
Function
Individual Clock Inputs
Common Clock Input
Data Inputs
CD
CP
2
CD
SD
CD
SD
CD
SD
C
Q
Q
2
2
CP
D
CP
2
2
2
1
D
D0 – D2
CD0 – CD2
SDn
SD
CD
Individual Direct Clear Inputs
Individual Direct Set Inputs
Master Reset Input
Master Set Input
Q
Q
1
1
CP
D
MR
CP
1
1
1
0
MS
D
Q0 – Q2
Q0 – Q2
VEES
Data Outputs
SD
CD
Complementary Data Outputs
VEE Substrate
Q
Q
0
0
CP
D
CP
0
0
0
VCCA
VCCO for ECL Outputs
D
SD
MS MR
Rev.: H
Amendment:/0
M9999-032206
hbwhelp@micrel.com or (408) 955-1690
1
Issue Date: March 2006
SY100S331
Micrel, Inc.
PACKAGE/ORDERING INFORMATION
Ordering Information
Package Operating
Package
Marking
Lead
Finish
11 10 9
8 7 6 5
Part Number
Type
F24-1
F24-1
J28-1
J28-1
J28-1
Range
MS
12
13
14
15
16
17
18
4
3
Q
Q
1
1
SY100S331FC
Commercial
Commercial
Commercial
Commercial
Commercial
SY100S331FC
SY100S331FC
SY100S331JC
SY100S331JC
Sn-Pb
Sn-Pb
CPC
SY100S331FCTR(1)
VEE
2
V
V
V
CCA
Top View
PLCC
J28-1
VEES
1
CC
SY100S331JC
Sn-Pb
MR
28
27
26
CC
SY100S331JCTR(1)
SY100S331JZ(2)
Sn-Pb
SD
1
1
Q
Q
2
2
D
SY100S331JZ with
Pb-Free bar-line indicator
Matte-Sn
19 20 21 22 23 24 25
SY100S331JZTR(1, 2)
J28-1
Commercial
SY100S331JZ with
Matte-Sn
Pb-Free bar-line indicator
Notes:
28-Pin PLCC (J28-1)
1. Tape and Reel.
2. Pb-Free package is recommended for new designs.
24 23 22 21 20 19
CP
1
1
1
2
3
4
5
6
18
17
16
15
14
13
SD
CD
CP
0
CD
0
Top View
Flatpack
F24-1
SD
2
2
0
CD
D
0
CP
2
Q
Q
0
0
D
2
7
8 9 10 11 12
24-Pin Cerpack (F24-1)
M9999-032206
hbwhelp@micrel.com or (408) 955-1690
2
SY100S331
Outputs
Micrel, Inc.
TRUTH TABLES
Synchronous Operation(1)
Asynchronous Operation(1)
Inputs
MS
Inputs
Outputs
MR
MS
MR
Dn
CPn
u
CPc
SDn
DCn
Qn
L
Dn
X
CPn
X
CPc
X
SDn
DCn
Qn (t+1)
L
L
L
L
L
L
L
L
L
L
H
L
L
H
H
H
L
H
u
L
L
H
X
X
X
L
L
u
L
L
X
X
X
H
U
H
L
u
L
H
NOTE:
1. H = High Voltage Level, L = Low Voltage Level, X = Don't Care, U =
Undefined, t = Time before CP Positive Transition, t+1 = Time after CP
Positive Transition, u = Low-to-High Transition
X
X
L
L
L
Qn (t)
Qn (t)
Qn (t)
H
X
X
L
X
H
L
NOTE:
1. H = High Voltage Level, L = Low Voltage Level, X = Don't Care, U =
Undefined, t = Time before CP Positive Transition, t+1 = Time after CP
Positive Transition, u = Low-to-High Transition
DC ELECTRICAL CHARACTERISTICS
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
Symbol
IIH
Parameter
Min.
—
Typ.
—
Max.
200
Unit
µA
Condition
Input HIGH Current, All Inputs
Power Supply Current
VIN = VIH (Max.)
Inputs Open
IEE
–80
–65
–35
mA
M9999-032206
hbwhelp@micrel.com or (408) 955-1690
3
SY100S331
Micrel, Inc.
AC ELECTRICAL CHARACTERISTICS
CERPACK
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
TA = 0°C
TA = +25°C
TA = +85°C
Symbol
Parameter
Toggle Frequency
Min.
Max.
—
Min.
800
300
Max.
—
Min.
800
300
Max.
—
Unit
MHz
ps
Condition
fmax
800
300
tPLH
tPHL
Propagation Delay
CPc to Output
800
800
800
tPLH
tPHL
Propagation Delay
CPn to Output
300
300
300
300
800
900
300
300
300
300
800
900
300
300
300
300
800
900
ps
ps
ps
ps
ps
tPLH
tPHL
Propagation Delay
CDn, SDn to Output
tPLH
tPHL
Propagation Delay
MS, MR to Output
1000
900
1000
900
1000
900
tTLH
tTHL
Transition Time
20% to 80%, 80% to 20%
tS
Set-up Time
Dn
400
500
800
—
—
—
400
500
800
—
—
—
400
500
800
—
—
—
CDn, SDn (Release Time)
MS, MR (Release Time)
tH
Hold Time Dn
300
800
—
—
300
800
—
—
300
800
—
—
ps
ps
tpw (H)
Pulse Width HIGH
CPn, CPc, DCn
SDn, MR, MS
PLCC
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
TA = 0°C TA = +25°C
TA = +85°C
Symbol
Parameter
Toggle Frequency
Min.
Max.
—
Min.
800
300
Max.
—
Min.
800
300
Max.
—
Unit
MHz
ps
Condition
fmax
800
300
tPLH
tPHL
Propagation Delay
CPc to Output
700
700
700
tPLH
tPHL
Propagation Delay
CPn to Output
300
300
300
300
700
800
900
900
300
300
300
300
700
800
900
900
300
300
300
300
700
800
900
900
ps
ps
ps
ps
ps
tPLH
tPHL
Propagation Delay
CDn, SDn to Output
tPLH
tPHL
Propagation Delay
MS, MR to Output
tTLH
tTHL
Transition Time
20% to 80%, 80% to 20%
tS
Set-up Time
Dn
400
500
800
—
—
—
400
500
800
—
—
—
400
500
800
—
—
—
CDn, SDn (Release Time)
MS, MR (Release Time)
tH
Hold Time Dn
300
800
—
—
300
800
—
—
300
800
—
—
ps
ps
tpw (H)
Pulse Width HIGH
CPn, CPc, DCn
SDn, MR, MS
M9999-032206
hbwhelp@micrel.com or (408) 955-1690
4
SY100S331
Micrel, Inc.
TIMING DIAGRAMS
DATA
0.7 ± 0.1 ns
0.7 ± 0.1 ns
–0.95V
80%
50%
20%
CLOCK
–1.69V
tpw (H)
1/fmax
t
t
PHL
PLH
tPLH
OUTPUT
OUTPUT
50%
t
PHL
t
THL
t
TLH
Propagation Delay (Clock) and Transition Times
Note:
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
0.7 ± 0.1 ns
0.7 ± 0.1 ns
+1.05V
80%
50%
20%
SDn, CDn
MS, MR
+0.31V
t
S
(RELEASE TIME)
t
pw (H)
CLOCK
50%
t
t
PHL
PLH
tPLH
OUTPUT
OUTPUT
50%
t
PHL
80%
50%
20%
Propagation Delay (Sets and Resets)
M9999-032206
hbwhelp@micrel.com or (408) 955-1690
5
SY100S331
Micrel, Inc.
TIMING DIAGRAMS
+1.05V
DATA
50%
+0.31V
+1.05V
t
h
t
S
CLOCK
50%
+0.31V
Data Setup and Hold Time
Notes:
ts is the minimum time before the transition of the clock that information must be present at the data input.
th is the minimum time after the transition of the clock that information must remain unchanged at the data input.
M9999-032206
hbwhelp@micrel.com or (408) 955-1690
6
SY100S331
Micrel, Inc.
24-PIN CERPACK (F24-1)
Rev. 03
M9999-032206
hbwhelp@micrel.com or (408) 955-1690
7
SY100S331
Micrel, Inc.
28-PIN PLCC (J28-1)
Rev. 03
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2006 Micrel, Incorporated.
M9999-032206
hbwhelp@micrel.com or (408) 955-1690
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