SY100S351JCTR [MICREL]
HEX D FLIP-FLOP; 六路D触发器
| 型号： | SY100S351JCTR |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | HEX D FLIP-FLOP |
| 文件： | 总7页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SY100S351
HEX D FLIP-FLOP
FEATURES
DESCRIPTION
■ Max. toggle frequency of 700MHz
■ Clock to Q max. of 1200ps
■ IEE min. of –98mA
The SY100S351 offers six D-type, edge-triggered,
master/slave flip-flops with differential outputs, and is
designed for use in high-performance ECL systems. The
flip-flops are controlled by the signal from the logical OR
operation on a pair of common clock signals (CPa, CPb).
Data enters the master when both CPa and CPb are LOW
and transfers to the slave when either CPa or CPb (or both)
go to a logic HIGH. The Master Reset (MR) input overrides
all other inputs and takes the Q outputs to a logic LOW. The
inputs on this device have 75KΩ pull-down resistors.
■ Industry standard 100K ECL levels
■ Extended supply voltage option:
VEE = –4.2V to –5.5V
■ Voltage and temperature compensation for improved
noise immunity
■ Internal 75KΩ input pull-down resistors
■ 50% faster than Fairchild 300K
PIN CONFIGURATIONS
■ Better than 20% lower power than Fairchild
■ Function and pinout compatible with Fairchild F100K
■ Available in 24-pin CERPACK and 28-pin PLCC
packages
11 10 9
8 7 6 5
D
D
2
3
12
13
14
15
16
17
18
4
3
Q
Q
2
2
VEE
2
V
V
V
CCA
Top View
PLCC
J28-1
V
EES
1
CC
MR
28
27
26
CC
BLOCK DIAGRAM
CP
a
b
Q
Q
3
3
CP
19 20 21 22 23 24 25
D
E
D
5
Q
Q
Q
Q
5
5
CP
CP
MR
b
a
R
R
R
R
R
R
24 23 22 21 20 19
18
1
D
D
4
5
D
D
1
0
D
E
D
D
D
D
D
4
3
2
1
0
Q
Q
Q
Q
4
4
2
3
4
5
6
17
16
15
14
13
Top View
Flatpack
F24-1
Q
Q
5
5
Q
Q
Q
Q
0
0
1
1
Q
4
D
E
Q
Q
Q
Q
3
3
Q
4
7
8
9 10 11 12
D
E
Q
Q
Q
Q
2
2
D
E
Q
Q
Q
Q
1
1
D
E
Q
Q
Q
Q
0
0
Rev.: G
Amendment:/0
Issue Date: July, 1999
1
SY100S351
Micrel
PIN NAMES
Pin
D0 — D5
CPa, CPb
MR
Function
Data Inputs
Common Clock Inputs
Asynchronous Master Reset Input
Data Outputs
Q0 — Q5
Q0 — Q5
VEES
Complementary Data Outputs
VEE Substrate
VCCA
VCCO for ECL Outputs
TRUTH TABLES
Asynchronous Operation(1)
Inputs
Synchronous Operation(1)
Inputs
Outputs
Qn (t+1)
L
Outputs
Dn
CPa
CPb
MR
Dn
L
CPa
u
CPb
L
MR
L
Qn (t+1)
X
X
X
H
L
H
H
L
u
L
L
NOTE:
1. H = High Voltage Level
L = Low Voltage Level
X = Don't Care
L
u
L
L
H
X
X
X
L
u
L
H
t = Time before CP Positive Transition
t+1 = Time after CP Positive Transition
u = LOW-to-HIGH Transition
H
u
u
L
Qn(t)
Qn(t)
Qn(t)
H
L
L
L
L
DC ELECTRICAL CHARACTERISTICS
VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND
Symbol
Parameter
Input HIGH Current
Min.
Typ.
Max.
Unit
Condition
IIH
µA
VIN = VIH (Max.)
MR
D0 – D5
CPa, CPb
—
—
—
—
—
—
270
200
300
IEE
Power Supply Current
–98
–71
–49
mA
Inputs Open
2
SY100S351
Micrel
AC ELECTRICAL CHARACTERISTICS
CERPACK
VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND
TA = 0°C
TA = +25°C
TA = +85°C
Symbol
Parameter
Toggle Frequency
Min.
Max.
—
Min.
700
—
Max.
—
Min.
700
—
Max.
—
Unit
MHz
ps
Condition
fMAX
700
—
tPLH
tPHL
Propagation Delay
CPa, CPb to Output
1200
1200
1200
tPLH
tPHL
Propagation Delay
MR to Output
—
1200
900
—
1200
900
—
1200
900
ps
ps
ps
tTLH
tTHL
Transition Time
20% to 80%, 80% to 20%
300
300
300
tS
Set-up Time
D0–D5
MR (Release Time)
500
1000
—
—
500
1000
—
—
500
1000
—
—
tH
Hold Time, D0–D5
550
—
—
550
—
—
550
—
—
ps
ps
tPW (H)
Pulse Width HIGH
CPa, CPb, MR
1000
1000
1000
PLCC
VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND
TA = 0°C TA = +25°C
TA = +85°C
Symbol
Parameter
Toggle Frequency
Min.
Max.
—
Min.
700
—
Max.
—
Min.
700
—
Max.
—
Unit
MHz
ps
Condition
fMAX
700
—
tPLH
tPHL
Propagation Delay
CPa, CPb to Output
1200
1200
1200
tPLH
tPHL
Propagation Delay
MR to Output
—
1200
900
—
1200
900
—
1200
900
ps
ps
ps
tTLH
tTHL
Transition Time
20% to 80%, 80% to 20%
300
300
300
tS
Set-up Time
D0–D5
MR (Release Time)
500
1000
—
—
500
1000
—
—
500
1000
—
—
tH
Hold Time, D0–D5
550
—
—
550
—
—
550
—
—
ps
ps
tPW (H)
Pulse Width HIGH
CPa, CPb, MR
1000
1000
1000
3
SY100S351
Micrel
TIMING DIAGRAMS
DATA
0.7 ± 0.1 ns
0.7 ± 0.1 ns
–0.95V
80%
CLOCK
50%
20%
–1.69V
1/fmax
tpw (H)
t
t
PHL
PLH
tPLH
OUTPUT
OUTPUT
50%
t
PHL
t
TLH
tTHL
Propagation Delay (Clock) and Transition Times
NOTE:
VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND
0.7 ± 0.1 ns
0.7 ± 0.1 ns
–0.95V
–1.69V
80%
50%
20%
MR
t
S
(RELEASE TIME)
50%
tpw (H)
CLOCK
t
t
PHL
PLH
tPLH
OUTPUT
OUTPUT
50%
t
PHL
80%
50%
20%
Propagation Delay (Resets)
4
SY100S351
Micrel
TIMING DIAGRAMS
–0.95V
DATA
50%
–1.69V
–0.95V
tH
tS
CLOCK
50%
–1.69V
Data Set-up and Hold Time
NOTES:
1. VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND
2. tS is the minimum time before the transition of the clock that information
must be present at the data input.
3. tH is the minimum time after the transition of the clock that information must
remain unchanged at the data input.
PRODUCT ORDERING CODE
Ordering
Code
Package
Type
Operating
Range
SY100S351FC
SY100S351JC
SY100S351JCTR
F24-1
J28-1
J28-1
Commercial
Commercial
Commercial
5
SY100S351
Micrel
24 LEAD CERPACK (F24-1)
Rev. 03
6
SY100S351
Micrel
28 LEAD PLCC (J28-1)
Rev. 03
MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
7
相关型号：
SY100S351JY
100S SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PQCC28
MICROCHIP
SY100S351JY-TR
100S SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PQCC28
MICROCHIP
SY100S351JZ
100S SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PQCC28
MICROCHIP
SY100S351JZ-TR
D Flip-Flop, 100S Series, 1-Func, Positive Edge Triggered, 6-Bit, Complementary Output, ECL, PQCC28, LEAD FREE, PLASTIC, LCC-28
MICROCHIP
©2020 ICPDF网 联系我们和版权申明