SY89429AZC [MICREL]
PROGRAMMABLE FREQUENCY SYNTHESIZER 25MHz to 400MHz; 可编程频率合成器的25MHz至400MHz
| 型号： | SY89429AZC |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | PROGRAMMABLE FREQUENCY SYNTHESIZER 25MHz to 400MHz |
| 文件： | 总9页 (文件大小：142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PROGRAMMABLE
FREQUENCY SYNTHESIZER
(25MHz to 400MHz)
ClockWorks™
SY89429A
DESCRIPTION
FEATURES
■ Improved jitter performance over SY89429
■ 25MHz to 400MHz differential PECL outputs
■ ±25ps peak-to-peak output jitter
■ Minimal frequency over-shoot
■ Synthesized architecture
The SY89429A is a general purpose, synthesized clock
source targeting applications that require both serial and
parallel interfaces. Its internal VCO will operate over a
range of frequencies from 400MHz to 800MHz. The
differential PECL output can be configured to be the VCO
frequency divided by 2, 4, 8 or 16. With the output configured
to divide the VCO frequency by 2, and with a 16MHz
external quartz crystal used to provide the reference
frequency, the output frequency can be specified in 1MHz
steps.
■ Serial 3 wire interface
■ Parallel interface for power-on
■ Internal quartz reference oscillator driven by quartz
crystal or PECL source
■ PECL output can operate with either +3.3V or +5V
VCC_OUT power supply
■ External loop filter optimizes performance/cost
■ Applications note (AN-06) for ease of design-ins
■ Available in PLCC and SOIC 28-pin packages
PIN CONFIGURATION
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
M[0]
P
_LOAD
CC1
V
M[1]
M[2]
3
XTAL
2
25 24 23 22 21 20 19
S_CLOCK
S_DATA
26
27
28
1
18
17
16
15
14
13
12
N[1]
N[0]
M[8]
M[7]
M[6]
M[5]
M[4]
4
XTAL
1
M[3]
5
M[4]
LOOP_REF
S_LOAD
PLCC
TOP VIEW
VCC_QUIET
LOOP _FILTER
LOOP_REF
XTAL1
6
M[5]
LOOP_FILTER
2
TOP VIEW
SOIC
Z28-1
7
M[6]
V
S
CC_QUIET
_LOAD
3
8
4
M[7]
5
6
7
8
9
10 11
9
M[8]
S
S
_DATA
10
11
12
13
14
N[0]
_CLOCK
N[1]
VCC_OUT
FOUT
GND (TTL)
TEST
APPLICATIONS
FOUT
GND
V
CC (TTL)
■ Workstations
■ Advanced communications
■ High end consumer
■ High-performance computing
■ RISC CPU clock
■ Graphics pixel clock
■ Test equipment
■ Other high-performance processor-based
applications
Rev.: H
Amendment: /0
Issue Date: October, 1998
1
ClockWorks™
SY89429A
Micrel
BLOCK DIAGRAM
+5.0V
PLL
F
REF
PHASE DETECTOR
÷ 8
10-25MHz
Fundamental
Crystal
VCO
PECL
or
PECL
Source
OSC
÷ M
÷ N
FOUT
TEST
400 – 800
MHz
INTERFACE
3 WIRE
INTERFACE
SERIAL
LOGIC
PARALLEL
CONFIG INFO
DETAILED BLOCK DIAGRAM
+5.0V
+5.0V
6, 21
2
3
1
LOOP_REF
LOOP_FILTER
V
CC_QUIET
V
CC1
FREF
PHASE DETECTOR
÷ 8
400-800
MHz
VCO
+5.0V
25
V
CC_OUT
10–25MHz
Fundamental
Crystal
T110
4
5
1
0
XTAL1
24
or
FOUT
23
9-BIT ÷ M
COUNTER
÷ N
(2,4,8,16)
OSC
PECL
Source
FOUT
XTAL2
L = LATCH
H = Transparent
7
FOUT ÷ 4 —
LATCH
LATCH
6
5
4
3
2
S_CLOCK ÷ M
—
28
7
S_LOAD
LOW —
FOUT —
÷ M —
LATCH
20
TEST
P_LOAD
0
1
0
1
FREF —
HIGH —
1
0
27
26
9-BIT SR
3-BIT SR
S_DATA
2-BIT SR
S_CLOCK
19,22
8 -> 16
17,18
9
2
N[1:0]
M[8:0]
NOTE:
Pin numbers reference PLCC pinout.
2
ClockWorks™
SY89429A
Micrel
PIN DESCRIPTIONS
INPUTS
OUTPUTS
XTAL1, XTAL2
FOUT, FOUT
These pins form an oscillator when connected to an external These differential positive-referenced ECL signals (PECL)
crystal. The crystal is series resonant. Alternatively, these are the output of the synthesizer.
pins can be driven with 100K PECL level by an external
TEST
source.
The function of this TTL output is determined by the serial
configuration bits T[2:0].
S_LOAD
This TTL pin loads the configuration latches with the contents
of the shift registers. The latches will be transparent when this POWER
signal is HIGH; thus, the register data must be stable on the
HIGH-to-LOW transition of S_LOAD for proper operation.
VCC1
Thisisthepositivesupplyforthechipandisnormallyconnected
to +5.0V.
S_DATA
This TTL pin is the input to the serial configuration shift
registers.
VCC_OUT
This is the positive reference for the PECL outputs, FOUT and
FOUT. It is constrained to be less than or equal to VCC1.
S_CLOCK
This TTL pin clocks the serial configuration shift registers. On
the rising edge of this signal, data from S_DATA is sampled.
VCC_QUIET
This is the positive supply for the PLL and should be as noise-
free as possible for low-jitter operation.
P_LOAD
This TTL pin loads the configuration latches with the contents
oftheparallelinputs. Thelatcheswillbetransparentwhenthis
signal is LOW; thus, the parallel data must be stable on the
LOW-to-HIGH transition of P_LOAD for proper operation.
GND
These pins are the negative supply for the chip and are
normally all connected to ground.
M[8:0]
OTHER
These TTL pins are used to configure the PLL loop divider.
They are sampled on the LOW-to-HIGH transition of P_LOAD.
LOOP_FILTER
M[8] is the MSB, M[0] is the LSB. The binary count on the M This is an analog I/O pin that provides the loop filter for the
pins equates to the divide-by value for the PLL.
PLL.
N[1:0]
LOOP_REF
This is an analog I/O pin that provides a reference voltage for
the PLL.
These TTL pins are used to configure the output divider
modulus. They are sampled on the LOW-to-HIGH transition
of P_LOAD.
N[1:0]
0 0
Output Division
2
4
0 1
1 0
8
1 1
16
3
ClockWorks™
SY89429A
Micrel
WITH 16MHZ INPUT
VCO Frequency
(MHz)
256
M8
128
M7
64
32
16
8
4
2
1
M Count
M6
M5
M4
M3
M2
M1
M0
400
402
404
406
•
200
201
202
203
•
0
0
0
0
•
1
1
1
1
•
1
1
1
1
•
0
0
0
0
•
0
0
0
0
•
1
1
1
1
•
0
0
0
0
•
0
0
1
1
•
0
1
0
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
794
796
798
800
397
398
399
400
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
1
0
0
1
1
0
1
0
1
0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VCC
Parameter
Power Supply Voltage
Value
Unit
–0.5 to +7.0
–0.5 to +7.0
V
V
VI
Input Voltage
Output Source
IOUT
Continuous
Surge
50
100
mA
Tstore
TA
Storage Temperature
Operating Temperature
–65 to +150
–0 to +75
°C
°C
NOTE:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at
conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions for extended periods may
affect device reliability.
FUNCTIONAL DESCRIPTION
The internal oscillator uses the external quartz crystal as the in 50Ω. The positive reference for the output driver is provided by
basis of its frequency reference. The output of the reference a dedicated power pin (VCC_OUT) to reduce noise and provide
oscillator is divided by eight before being sent to the phase application flexibility.
detector.Witha16MHzcrystal,thisprovidesareferencefrequency
of 2MHz.
The configuration logic has two sections: serial and parallel.
The parallel interface uses the values at the M[8:0] and N[1:0]
The VCO within the PLL operates over a range of 400– inputs to configure the internal counters. Normally upon system
800MHz. Its output is scaled by a divider that is configured by reset, the P_LOAD input is held LOW until sometime after
either the serial or parallel interfaces. The output of this loop power becomes valid. With S_LOAD held LOW, on the LOW-
divider is also applied to the phase detector.
to-HIGH transition of P_LOAD, the parallel inputs are captured.
The phase detector and loop filter force the VCO output The parallel interface has priority over the serial interface.
frequencytobeMtimesthereferencefrequencyby adjustingthe Internal pull-up resistors are provided on the M[8:0] and N[1:0]
VCO control voltage. Note that for some values of M (either too inputs to reduce component count.
high or too low) the PLL will not achieve loop lock. External loop
filter components are utilized to allow for optimal phase jitter register scheme. The register shifts once per rising edge of the
performance. S_CLOCK input. The serial input S_DATA must meet set-up and
The serial interface logic is implemented with a 14-bit shift
The output of the VCO is also passed through an output hold timing as specified in the AC parameters section of this data
divider before being sent to the PECL output driver. The output sheet. With P_LOAD held HIGH, the configuration latches will
divider is configured through either the serial or the parallel capture the value in the shift register on the HIGH-to-LOW edge
interfacesandcanprovideoneoffourdividerratios (2,4,8or16). of the S_LOAD input. See the programming section for more
This divider extends the performance of the part while providing information.
a 50% duty cycle.
The TEST output reflects various internal node values and is
The output driver is driven differentially from the output divider controlled by the T[2:0] bits in the serial data stream. See the
and is capable of driving a pair of transmission lines terminated programming section for more information.
4
ClockWorks™
SY89429A
Micrel
PROGRAMMING INTERFACE
Programming the device is accomplished by properly
The TEST output provides visibility for one of several
configuring the internal dividers to produce the desired internal nodes (as determined by the T[1:0] bits in the serial
frequency at the outputs. The output frequency can be configurationstream).Itisnotconfigurablethroughtheparallel
represented by this formula:
interface. Although it is possible to select the node that
represents FOUT, the TTL output may not be able to toggle
fastenoughforsomeofthehigheroutputfrequencies.TheT2,
T1, T0 configuration latches are preset to 000 when P_LOAD
M
N
FXTAL
FOUT = (
) x
8
Where FXTAL is the crystal frequency, M is the loop divider is low, so that the FOUT outputs are as jitter-free as possible.
modulus, and N is the output divider modulus. Note that it is The serial configuration port can be used to select one of the
possible to select values of M such that the PLL is unable to alternate functions for this pin.
achieve loop lock. To avoid this, always make sure that M is
selected to be 200 ≤ M ≤ 400 for a 16MHz input reference.
The Test register is loaded with the first three bits, the N
register with the next two and the M register with the final eight
M[8:0]and N[1:0]arenormallyspecifiedonceatpower-on, bits of the data stream on the S_DATA input. For each register
throughtheparallelinterface, andthenpossiblyagainthrough the most significant bit is loaded first (T2, N1 and M8).
theserialinterface. Thisapproachallowsthedesignertobring
When T[2:0] is set to 100 the SY89429A is placed in PLL
up the application at one frequency and then change or fine- bypass mode. In this mode the S_CLOCK input is fed directly
tune the clock, as the ability to control the serial interface into the M and N dividers. The N divider drives the FOUT
becomes available. To minimize transients in the frequency differential pair and the M counter drives the TEST output pin.
domain, the output should be varied in the smallest step size In this mode the S_CLOCK input could be used for low speed
possible.
board level functional test or debug. Bypassing the PLL and
driving FOUT directly gives the user more control on the test
clockssentthroughtheclocktree(SeedetailedBlockDiagram).
Because the S_CLOCK is a TTL level the input frequency is
limited to 250MHz or less. This means the fastest the FOUT
pin can be toggled via the S_CLOCK is 125MHz as the
minimum divide ratio of the N counter is 2. Note that the M
counteroutputontheTESToutputwillnotbea50%dutycycle
due to the way the divider is implemented.
T2 T1 T0
TEST
Data Out – Last Bit SR
HIGH
FOUT / FOUT
FVCO ÷ N
FVCO ÷ N
FVCO ÷ N
FVCO ÷ N
FVCO ÷ N
FVCO ÷ N
S_CLOCK ÷ N
FVCO ÷ N
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
FREF
M Counter Output
FOUT
LOW
S_CLOCK ÷ M
FOUT ÷ 4
S
_CLOCK
S
_DATA
_LOAD
T2 T1 T0 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0
Last
Bit
First
Bit
S
M[8:0]
N[1:0]
M,N
P
_LOAD
Input S_DATA to M0 then M1, then M2, etc., as indicated above.
5
ClockWorks™
SY89429A
Micrel
100H ECL DC ELECTRICAL CHARACTERISTICS
VCC1 = VCC_QUIET = VCC_TTL = +5.0V ±5%; VCC_OUT = +3.3V to +5.0V ±5%; TA = 0°C to +75°C
Symbol
VOH
Parameter
Output HIGH Voltage
Output LOW Voltage
Min.
Max.
Unit
V
Condition
VCC_OUT –1.075
VCC_OUT –1.860
VCC_OUT –0.830
VCC_OUT –1.570
50Ω to VCC_OUT –2V
50Ω to VCC_OUT –2V
VOL
V
TTL DC ELECTRICAL CHARACTERISTICS
VCC1 = VCC_QUIET = VCC_TTL = +5.0V ±5%; VCC_OUT = +3.3V to +5.0V ±5%; TA = 0°C to +75°C
TA = 0°C TA = +25°C TA = +75°C
Symbol
VIH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Input Clamp Voltage
Output HIGH Voltage
Output LOW Voltage
Output Short Circuit Current
Supply Current
Min.
Max.
—
Min.
2.0
—
Max.
Min.
2.0
—
Max.
Unit
Condition
—
2.0
—
—
—
—
—
—
—
0.8
50
—
0.8
50
V
V
VIL
0.8
—
IIH
50
—
—
µA
mA
V
VIN = 2.7V
VIN = 0.5V
IIN = –12mA
IOH = –2.0mA
IOL = 8mA
VOUT = 0V
—
IIL
–0.6
–1.2
2.5
—
–0.6
–1.2
2.5
0.5
—
–0.6
–1.2
2.5
0.5
VIK
—
—
VOH
VOL
IOS
—
—
V
0.5
—
—
V
–80 (Typ.)
–80 (Typ.)
225
–80 (Typ.)
— 225
mA
mA
ICC1
—
225
—
Typical % of ICC1
VCC1
91%
91%
91%
VCC_OUT
VCC_QUIET
VCC_TTL
4.5%
2.25%
2.25%
4.5%
2.25%
2.25%
4.5%
2.25%
2.25%
AC ELECTRICAL CHARACTERISTICS
VCC1 = VCC_QUIET = VCC_TTL = +5.0V ±5%; VCC_OUT = +3.3V to +5.0V ±5%; TA = 0°C to +75°C
TA = 0°C TA = +25°C TA = +75°C
Min. Max. Min. Max. Min. Max. Unit
Symbol
Parameter
Condition
fMAXI
Maximum Input Frequency(1)
S_CLOCK
Xtal Oscillator
—
10
10
25
—
10
10
25
—
10
10
25
MHz
Fundamental
Cyrstal
fMAXO
Maximum Output Frequency VCO (Internal)
FOUT
400
25
800
400
400
25
800
400
400
25
800 MHz
400
tLOCK
tjitter
tS
Maximum PLL Lock Time
—
—
20
10
±25
—
—
—
20
10
±25
—
—
—
20
10
±25
—
ms
ps
ns
Cycle-to-Cycle Jitter (Peak-toPeak)
Test output static
Setup Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
20
20
—
—
20
20
—
—
20
20
—
—
tH
Hold Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
20
20
20
—
—
—
20
20
20
—
—
—
20
20
20
—
—
—
ns
ns
tpw(MIN)
tDC
Minimum Pulse Width
FOUT Duty Cycle
S_LOAD
P_LOAD
50
50
—
—
50
50
—
—
50
50
—
—
45
55
45
55
45
55
%
tr
tf
Output Rise/Fall
20% to 80%
FOUT
300
800
300
800
300
800
ps
NOTE:
1. 10MHz is the maximum frequency to load the feedback divide registers. S_CLOCK can be switched at high frequencies when used as a test clock in
TEST_MODE 6.
6
ClockWorks™
SY89429A
Micrel
TIMING DIAGRAM
S_DATA
S_CLOCK
S_LOAD
t
HOLD
t
SET-UP
t
SET-UP
M[8:0]
N[1:0]
P_LOAD
t
HOLD
t
SET-UP
PRODUCT ORDERING CODE
Ordering
Code
Package
Type
Operating
Range
SY89429AJC
J28-1
J28-1
Z28-1
Z28-1
Commercial
Commercial
Commercial
Commercial
SY89429AJCTR
SY89429AZC
SY89429AZCTR
7
ClockWorks™
SY89429A
Micrel
28 LEAD SOIC .300" WIDE (Z28-1)
Rev. 02
8
ClockWorks™
SY89429A
Micrel
28 LEAD PLCC (J28-1)
Rev. 03
MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
9
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