SY89827LHYTR [MICREL]
3.3V 500MHz DUAL 1:10 HSTL FANOUT BUFFER/TRANSLATOR WITH 2:1 MUX INPUT; 3.3V 500MHz的双1:10 HSTL扇出缓冲器/翻译以2： 1多路复用器输入
| 型号： | SY89827LHYTR |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | 3.3V 500MHz DUAL 1:10 HSTL FANOUT BUFFER/TRANSLATOR WITH 2:1 MUX INPUT |
| 文件： | 总11页 (文件大小：165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
®
3.3V 500MHz DUAL 1:10 HSTL FANOUT
Precision Edge
SY89827L
BUFFER/TRANSLATOR WITH 2:1 MUX INPUT
FEATURES
■ Dual LVPECL or HSTL input, 10 differential 1.5V
®
HSTL compatible outputs
Precision Edge
■ Configurable as dual-channel 10 output or a single-
channel 20 output clock driver
DESCRIPTION
■ Guaranteed AC parameters over temperature and
voltage:
• > 500MHz f
• < 50ps within device skew
• < 1.5ns propagation delay
• < 700ps t / t time
The SY89827L is a High Performance Bus Clock Driver
with dual 1:10 or single 1:20 HSTL (High Speed
Transceiver Logic) output pairs. The part is designed for
use in low voltage (3.3V/1.8V) applications which require
a large number of outputs to drive precisely aligned, ultra
low skew signals to their destination. The input is
multiplexed from either HSTL or LVPECL (Low Voltage
Positive Emitter Coupled Logic) by the CLK_SEL pin.
The Output Enables (OE1 & OE2) are synchronous so
that the outputs will only be enabled/disabled when they
are already in the LOW state. This avoids any chance of
generating a runt clock pulse when the device is enabled/
disabled as can happen with an asynchronous control.
The SY89827L features extremely low skew
performance of <50ps over temperature and voltage –
performance previously unachievable in a standard
product having such a high number of outputs. The
SY89827L is available in a single space saving package,
enabling a lower overall cost solution. For applications
that require greater HSTL fanout capability, consider the
SY89824L.
MAX
r
f
■ Low jitter design
• < 1ps cycle-to-cycle jitter
RMS
• < 10ps total jitter
PP
■ 3.3V core supply, 1.8V output supply
■ Output enable function
■ Available in a 64-Pin EPAD-TQFP
APPLICATIONS
■ High-performance PCs
■ Workstations
■ Parallel processor-based systems
■ Other high-performance computing
■ Communications
TYPICAL APPLICATION CIRCUIT
10
Primary Clock Source
LVPECL_CLKA
Primary
Card
10
/LVPECL_CLKA
Redundant Backup
Clock Source
10
10
LVPECL_CLKB
Redundant
Card
/LVPECL_CLKB
SEL1
Primary/Backup Clock Select
(Switchover within 2.0ns)
System using SY89827L as a switchover circuit from a Primary Clock to a Redundant Backup Clock in a failsafe application.
LVPECL inputs only, shown in this application.
Precision Edge is a registered trademark of Micrel, Inc.
Rev.: E
Amendment: /0
M9999-011907
hbwhelp@micrel.com or (408) 955-1690
1
Issue Date: January 2007
Precision Edge®
SY89827L
Micrel, Inc.
PACKAGE/ORDERING INFORMATION
Ordering Information(1)
Package Operating
Package
Marking
Lead
Finish
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
Part Number
Type
H64-1
H64-1
H64-1
Range
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VCCO
Q7
/Q7
Q8
/Q8
SEL2
HSTL_CLKB
/HSTL_CLKB
1
2
3
SY89827LHI
Industrial
Industrial
Industrial
SY89827LHI
SY89827LHI
Sn-Pb
Sn-Pb
VCCI
HSTL_CLKA
/HSTL_CLKA
CLK_SEL1
4
5
6
7
SY89827LHITR(2)
SY89827LHY(3)
Q9
/Q9
SY89827LHY with
Pb-Free bar-line indicator Matte-Sn
Pb-Free
VCCO
VCCO
Q10
/Q10
Q11
/Q11
Q12
/Q12
VCCO
LVPECL_CLKA
/LVPECL_CLKA
GND
8
9
10
11
12
13
14
15
16
OE1
LVPECL_CLKB
/LVPECL_CLKB
CLK_SEL2
SY89827LHYTR(2, 3) H64-1
Industrial
SY89827LHY with Pb-Free
Pb-Free bar-line indicator Matte-Sn
OE2
SEL1
Notes:
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC electricals only.
2. Tape and Reel.
3. Pb-Free package recommended for new designs.
64-Pin TQFP (H64-1)
FUNCTIONAL BLOCK DIAGRAM
CLK_SEL1
SEL1
OE1
HSTL_CLKA
0
/HSTL_CLKA
10
10
0
1
Q0 – Q9
LVPECL_CLKA
1
/Q0 – /Q9
/LVPECL_CLKA
LEN
D
HSTL_CLKB
Q
0
/HSTL_CLKB
LVPECL_CLKB
1
/LVPECL_CLKB
0
1
10
10
Q10 – Q19
/Q10 – /Q19
CLK_SEL2
LEN
D
SEL2
Q
OE2
M9999-011907
hbwhelp@micrel.com or (408) 955-1690
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Precision Edge®
SY89827L
Micrel, Inc.
TRUTH TABLE
OE1(1) OE2(1) SEL1(1) SEL2(1) CLK_SEL1(1) CLK_SEL2(1)
Q0 – Q9
/Q0 – /Q9
Q10 – Q19
/Q10 – /Q19
1
1
1
1
0
0
0
0
0
1
X
X
HSTL_CLKA
/HSTL_CLKA
HSTL_CLKA
/HSTL_CLKA
LVPECL_CLKA /LVPECL_CLKA LVPECL_CLKA /LVPECL_CLKA
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
HSTL_CLKA
/HSTL_CLKA
HSTL_CLKB
LVPECL_CLKB /LVPECL_CLKB
HSTL_CLKB /HSTL_CLKB
LVPECL_CLKA /LVPECL_CLKA LVPECL_CLKB /LVPECL_CLKB
/HSTL_CLKB
HSTL_CLKA
/HSTL_CLKA
LVPECL_CLKA /LVPECL_CLKA
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
HSTL_CLKB
LVPECL_CLKB /LVPECL_CLKB
HSTL_CLKB /HSTL_CLKB
LVPECL_CLKB /LVPECL_CLKB LVPECL_CLKA /LVPECL_CLKA
HSTL_CLKB /HSTL_CLKB HSTL_CLKB /HSTL_CLKB
LVPECL_CLKB /LVPECL_CLKB LVPECL_CLKB /LVPECL_CLKB
/HSTL_CLKB
HSTL_CLKA
/HSTL_CLKA
HSTL_CLKA
/HSTL_CLKA
LVPECL_CLKA /LVPECL_CLKA
1
1
1
1
1
1
1
1
X
X
0
1
0
0
0
0
1
1
1
1
X
X
X
X
0
0
1
1
0
1
X
X
0
1
LOW
LOW
LOW
LOW
HIGH
HIGH
HIGH
HIGH
HSTL_CLKA
LVPECL_CLKA /LVPECL_CLKA
HSTL_CLKB /HSTL_CLKB
LVPECL_CLKB /LVPECL_CLKB
/HSTL_CLKA
X
X
1
1
1
1
0
0
0
0
0
0
1
1
X
X
X
X
0
1
X
X
0
1
HSTL_CLKA
/HSTL_CLKA
LOW
LOW
LOW
LOW
HIGH
HIGH
HIGH
HIGH
LVPECL_CLKA /LVPECL_CLKA
HSTL_CLKB /HSTL_CLKB
LVPECL_CLKB /LVPECL_CLKB
LOW HIGH
X
X
0
0
X
X
X
X
LOW
HIGH
Note 1. Input has internal pull-up Floating input = 1.
M9999-011907
hbwhelp@micrel.com or (408) 955-1690
3
Precision Edge®
SY89827L
Micrel, Inc.
PIN DESCRIPTIONS
Internal
P/U
Pin Number
Pin Name
I/O
Type
Pin Function
5, 6
HSTL_CLKA
/HSTL_CLKA
Input
HSTL
Differential clock input selected by CLK_SEL1, SEL1 and SEL2.
Can be left floating if not selected. Floating input, if selected
produces an indeterminate output. HSTL input signal requires
external termination 50Ω-to-GND.
2, 3
8, 9
HSTL_CLKB
/HSTL_CLKB
Input
HSTL
Differential clock input selected by CLK_SEL1, SEL1 and SEL2.
Can be left floating if not selected. Floating input, if selected
produces an indeterminate output. HSTL input signal requires
external termination 50Ω-to-GND.
LVPECL_CLKA Input LVPECL
/LVPECL_CLKA
75kΩ
Differential clock input selected by CLK_SEL1, SEL1 and SEL2.
pull-down Can be left floating. Floating input, if selected produces a LOW
at output. Requires external termination. See Figure 1.
12, 13
7
LVPECL_CLKB Input LVPECL
/LVPECL_CLKB
75kΩ
Differential clock input selected by CLK_SEL2, SEL1 and SEL2.
pull-down Requires external termination. See Figure 1.
CLK_SEL1
CLK_SEL2
SEL1
Input
Input
Input
Input
Input
Input
Power
LVTTL/
CMOS
11kΩ
Pull-up
Selects HSTL_CLKA input when LOW and LVPECL_CLKA
input when HIGH.
14
16
1
LVTTL/
CMOS
11kΩ
Pull-up
Selects HSTL_CLKB input when LOW and LVPECL_CLKB
input when HIGH.
LVTTL/
CMOS
11kΩ
Pull-up
Selects input source CLKA when LOW and CLKB
when HIGH for outputs Q0 – Q9 and /Q0 – /Q9.
SEL2
LVTTL/
CMOS
11kΩ
Pull-up
Selects input source CLKA when LOW and CLKB
when HIGH for outputs Q10 – Q19 and /Q10 – /Q19.
11
15
4
OE1
LVTTL/
CMOS
11kΩ
Pull-up
Enable input synchronized internally to prevent glitching of the
Q0 – Q9 and /Q0 – /Q9 outputs.
OE2
LVTTL/
CMOS
11kΩ
Pull-up
Enable input synchronized internally to prevent glitching of the
Q10 – Q19 and /Q10 – /Q19 outputs.
VCCI
Core VCC connected to 3.3V supply. Bypass with 0.1µF in
parallel with 0.01µF low ESR capacitors as close to VCC pins as
possible.
17, 32, 33,
40, 41, 48, 49, 64
VCCO
Power
Output buffer VCC connected to 1.8V nominal supply. All VCCO
pins should be connected together on the PCB. Bypass with
0.1µF in parallel with 0.01µF low ESR capacitors as close to
VCCO pins as possible.
10
GND
Power
Output
Ground.
63, 61, 59, 57, 55
53, 51, 47, 45, 43
Q0 – Q9
HSTL
HSTL
Differential clock outputs from CLKA when SEL1 = LOW and
from CLKB when SEL1 = HIGH. HSTL outputs (Q and /Q) must
be terminated with 50Ω-to-GND. Q outputs are static when
OE1 = LOW. Unused output pairs may be left floating.
62, 60, 58, 56, 54
52, 50, 46, 44, 42
/Q0 – /Q9
Output
Differential clock outputs (complement) from CLKA when SEL1 =
LOW and from CLKB when SEL1 = HIGH. HSTL outputs (Q and
/Q) must be terminated with 50Ω-to-GND. /Q outputs are static
HIGH when OE1 = LOW. Unused output pairs may be left
floating.
39, 37, 35, 31, 29
38, 36, 34, 30, 28
Q10 – Q19
27, 25, 23, 21, 19
Output
Output
HSTL
HSTL
Differential outputs from CLKA when SEL2 = LOW and from
CLKB when SEL2 = HIGH. HSTL outputs (Q and /Q) must be
terminated with 50Ω-to-GND. Q outputs are static LOW when
OE2 = LOW. Unused output pairs may be left floating.
/Q10 – /Q19
26, 24, 22, 20, 18
Differential outputs (complement) from CLKA when SEL2 = LOW
and from CLKB when SEL2 = HIGH. HSTL outputs (Q and /Q)
must be terminated with 50Ω-to-GND. /Q outputs are static HIGH
when OE2 = LOW. Unused output pairs may be left floating.
M9999-011907
hbwhelp@micrel.com or (408) 955-1690
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Precision Edge®
SY89827L
Micrel, Inc.
Absolute Maximum Ratings(Note 1)
Operating Ratings(Note 2)
Power Supply Voltage (V , V
) ..............–0.5 to +4.0V
Supply Voltage
CCI CCO
(V ) .................................................... +3.3V to +3.47V
Input Voltage (V ) ...........................................–0.5 to V
CCI
IN
CCI
(V
) ..................................................... +1.6V to +2.0V
CCO
Output Current (I
) ...............................................–50mA
OUT
Ambient Temperature (T ) ......................... –40°C to +85°C
A
Lead Temperature (T
, Soldering, 20sec.).......... 260°C
LEAD
Package Thermal Resistance
Storage Temperature (T ) ........................... –65 to +150°C
S
TQFP (θ
)
JA
ESD Rating, Note 3 .................................................... >1kV
Exposed pad soldered to GND, Note 4
Still-Air (multi-layer PCB).................................23°C/W
–200lfpm (multi-layer PCB) .............................18°C/W
–500lfpm (multi-layer PCB) .............................15°C/W
Exposed pad NOT soldered to GND (not recommended)
Still-Air (multi-layer PCB).................................44°C/W
–200lfpm (multi-layer PCB) .............................36°C/W
–500lfpm (multi-layer PCB) .............................30°C/W
TQFP (θ ) .........................................................4.4°C/W
JC
DC ELECTRICAL CHARACTERISTICS
Power Supply: TA = –40°C to +85°C
Symbol
VCCI
Parameter
VCC Core
VCC Output
ICC Core
Condition
Min
3.13
1.6
Typ
3.3
Max
3.47
2.0
Units
V
VCCO
ICCI
1.8
V
No Load
140
170
mA
HSTL Input/Output: VCCI = 3.3V ±5%, VCCO = 1.8V ±10%, TA = –40°C to +85°C
Symbol
VOH
VOL
VIH
Parameter
Condition
Note 5
Min
1.0
Typ
Max
1.2
Units
V
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Crossover Voltage
Input HIGH Current
Input LOW Current
Note 5
0.2
0.4
V
VX +0.1
–0.3
0.68
+20
1.6
V
VIL
VX –0.1
0.9
V
VX
V
IIH
–350
–500
µA
µA
IIL
Note 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratlng conditions
for extended periods may affect device reliability.
Note 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
Note 3. Devices are ESD sensitive. Handling precautions recommended.
Note 4. It is highly recommended to solder the exposed pad of the EPAD-TQFP package to a ground plane on the PCB for maximum thermal
efficiency.
Note 5. Outputs loaded with 50Ω-to-ground.
M9999-011907
hbwhelp@micrel.com or (408) 955-1690
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Precision Edge®
SY89827L
Micrel, Inc.
DC ELECTRICAL CHARACTERISTICS
LVPECL Input: VCCI = 3.3V ±5%, TA = –40°C to +85°C
Symbol
VIH
Parameter
Condition
Min
Typ
Max
Units
V
Input HIGH Voltage (Single-Ended)
Input LOW Voltage
VCCI –1.165
VCCI –1.945
300
VCCI –0.880
VCCI –1.625
VIL
V
VPP
VCMR
IIH
Minimum Input Swing (LVPECL_CLK)
Note 6
mV
V
Common Mode Range (LVPECL_CLK) Note 7
Input HIGH Current
GNDI +1.8
VCCI –0.4
150
µA
µA
IIL
Input LOW Current
0.5
Note 6. The V (min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay.
PP
Note 7.
V
is defined as the range within which the V level may vary, with the device still meeting the propagation delay specification. The
CMR IH
numbers in the table are referenced to V . The V level must be such that the peak-to-peak voltage is less than 1.0V and greater than or
CCI
IL
equal to V (min.). V
range varies 1:1 with V . V
(min) is fixed at GNDI +1.8V
CMR
PP
CMR
CCI
CMOS/LVTTL Inputs: VCCI = 3.3V ±5%, VCCO = 1.8V ±10%, TA = –40°C to +85°C
Symbol
VIH
Parameter
Condition
Min
Typ
Max
Units
V
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
2.0
VIL
0.8
V
IIH
+20
–250
–600
µA
µA
IIL
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Precision Edge®
SY89827L
Micrel, Inc.
(NOTE 1)
AC ELECTRICAL CHARACTERISTICS
VCCI = 3.3V ±5%, VCCO = 1.8V ±10%, TA = –40°C to +85°C, all outputs loaded, unless noted.
Symbol
fMAX
tPD
Parameter
Condition
Note 2
Min
500
1.0
Typ
Max
Units
MHz
ns
Maximum Toggle Frequency
Differential Propagation Delay
Minimum Input Swing, Note 4
Note 3
1.3
1.5
VPP
HSTL
PECL
200
150
mV
mV
tSW
Switchover Time
CLK_SEL-to-Q
SEL-to-Q
1.6
1.4
2.0
1.75
ns
ns
tJITTER
Cycle-to-Cycle
Note 8
Note 9
Note 5
Note 5
Note 6
<1
psRMS
psPP
ns
Total Jitter
<10
tS(OE)
tH(OE)
tskew
Output Enable Set-Up Time
Output Enable Hold Time
Within Device Skew
1.0
0.5
ns
0°C to +85°C
–40°C
25
35
50
75
ps
ps
Part-to-Part Skew
Note 7
400
700
ps
ps
tr, tf
Output Rise/Fall Times
(20% to 80%)
450
Note 1. Outputs loaded with 50Ω-t- ground.
Note 2. is defined as the maximum toggle frequency, measured with a 750mV LVPECL/HSTL input. HSTL output swing is > 400mV.
f
MAX
Note 3. Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the differential
output signals.
Note 4. The V (min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay.
PP
Note 5. OE set-up time is defined with respect to the rising edge of the clock. OE HIGH-to-LOW transition ensures outputs remain disabled during the next
clock cycle. OE LOW-to-HIGH transition enables normal operation of the next input clock.
Note 6. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the same
voltage and temperature. This parameters includes within bank skew and bank-to-bank skew.
Note 7. Thepart-to-partskewisdefinedastheabsoluteworstcasedifferencebetweenanytwodelaypathsonanytwodevicesoperatingatthesamevoltage
and temperature.
Note 8. Cycle-to-cycle jitter definition: The variation in period between adjacent cycles over a random sample of adjacent cycle pairs. T
=T –T
n n+1
JITTER_CC
where T is the time between rising edges of the output signal.
12
Note 9. Total jitter definition: with an ideal clock input, no more than one output edge in 10 output edges will deviate by more than the specified peak-
to-peak jitter value.
M9999-011907
hbwhelp@micrel.com or (408) 955-1690
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Precision Edge®
SY89827L
Micrel, Inc.
TYPICAL OPERATING CHARACTERISTICS
V
= 3.3V, V
= 1.8V, T = 25°C, unless otherwise stated.
CCI
CCO
A
Output Amplitude
vs. Frequency
800
700
600
500
400
300
200
100
0
0
200 400 600 800 1000
FREQUENCY (MHz)
Propagation Delay
vs. Input Amplitude
CLK_SEL Switchover Time
vs. Temperature
1400
1200
1000
800
600
400
200
0
1800
1600
1400
1200
1000
800
600
400
200
0
HSTL INPUT
PECL INPUT
0
200 400 600 800 1000
INPUT AMPLITUDE (mV)
-50 -25
0
25 50 75 100
TEMPERATURE (°C)
M9999-011907
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Precision Edge®
SY89827L
Micrel, Inc.
FUNCTIONAL CHARACTERISTICS
V
= 3.3V, V
= 1.8V, T = 25°C, unless otherwise stated.
CCI
CCO
A
100MHz Output
250MHz Output
/Q
/Q
Q
Q
TIME (500ps/div.)
TIME (2ns/div.)
500MHz Output
/Q
Q
TIME (500ps/div.)
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Precision Edge®
SY89827L
Micrel, Inc.
LVPECL/HSTL INPUTS
Figure 2. Simplified HSTL Input Stage
Figure 1. Simplified LVPECL Input Stage
HSTL OUTPUTS
QOUT
QOUT
1.6V
QOUT — /QOUT
800mV
/QOUT
/QOUT
Figure 3. Output Driver Signal Levels
(Single-Ended)
Figure 4. Output Driver Signal Levels
(Differential)
RELATED PRODUCT AND SUPPORT DOCUMENTATION
Part Number Function
Data Sheet Link
SY89809L
SY89824L
3.3V 1:9 High-Performance, Low-Voltage Bus Clock Driver
www.micrel.com/product-info/products/sy89809l.shtml
www.micrel.com/product-info/products/sy89824l.html
www.amkor.com/products/notes_papers/epad.pdf
www.micrel.com/product-info/products/solutions.shtml
www.micrel.com/product-info/products/mic3775.shtml
3.3V 1:22 High-Performance, Low-Voltage Bus Clock Driver
Exposed Pad Application Note
M-0317
HBW Solutions
MIC3775
750mA µCap Low-Voltage Low-Dropout Regulator
M9999-011907
hbwhelp@micrel.com or (408) 955-1690
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Precision Edge®
SY89827L
Micrel, Inc.
64-PIN EPAD-TQFP (DIE UP) (H64-1)
+0.05
–0.05
+0.002
–0.002
+0.05
–0.05
+0.012
–0.012
+0.03
+0.15
–0.03
–0.15
+0.012
–0.012
+0.006
–0.006
+0.05
–0.05
Rev. 02
+0.002
–0.002
Package
EP- Exposed Pad
Die
CompSide Island
Heat Dissipation
Heat Dissipation
VEE
Heavy Copper Plane
Heavy Copper Plane
VEE
PCB Thermal Consideration for 64-Pin EPAD-TQFP Package
(Always solder, or equivalent, the exposed pad to the PCB)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL + 1 (408) 944-0800 FAX + 1 (408) 944-0970 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2006 Micrel, Incorporated.
M9999-011907
hbwhelp@micrel.com or (408) 955-1690
11
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