25AA160I/SN [MICROCHIP]
2K X 8 SPI BUS SERIAL EEPROM, PDSO8, 0.150 INCH, PLASTIC, MS-012, SOIC-8;
| 型号： | 25AA160I/SN |
| 厂家： | 
MICROCHIP |
| 描述： | 2K X 8 SPI BUS SERIAL EEPROM, PDSO8, 0.150 INCH, PLASTIC, MS-012, SOIC-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总12页 (文件大小：89K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
25AA080/160
8K/16K 1.8V SPI Bus Serial EEPROM
FEATURES
PACKAGE TYPES
• 3 MHz Clock Rate
• SPI Modes 0,0 and 1,1.
PDIP
• Single supply with programming operation down
to 1.8V
• Low Power CMOS Technology
- Max Write Current: 5 mA
- Read Current: 1.0 mA
- Standby Current: 1 µA typical
• Organization
- 1024 x 8 for 25AA080
Vcc
CS
SO
1
2
3
4
8
7
6
5
HOLD
WP
Vss
SCK
SI
- 2048 x 8 for 25AA160
• 16 Byte Page
• Self-timed ERASE and WRITE Cycles
• Sequential Read
• Block Write Protection
SOIC
1
8
Vcc
CS
- Protect none, 1/4, 1/2, or all of Array
• Built-in Write Protection
- Power On/Off Data Protection Circuitry
- Write Latch
- Write Protect Pin
• High Reliability
- Endurance: 10M cycles (guaranteed)
- Data Retention: >200 years
- ESD protection: >4000 V
• 8-pin PDIP/SOIC Packages
• Temperature ranges supported
2
3
4
7
6
5
SO
WP
Vss
HOLD
SCK
SI
BLOCK DIAGRAM
- Commercial (C):
- Industrial (I):
0°C to +70°C
-40°C to +85°C
Status
Register
HV Generator
DESCRIPTION
The Microchip Technology Inc. 25AA080/160 are 8K
and 16K bit Serial Electrically Erasable PROMs. The
memory is accessed via a simple Serial Peripheral
Interface (SPI) compatible serial bus. The bus signals
required are a clock input (SCK) plus separate data in
(SI) and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing any
number of devices to share the same bus.
EEPROM
Array
Memory
Control
Logic
X
I/O Control
Logic
Dec
Page Latches
WP
SI
There are two other inputs that provide the end user
with additional flexibility. Communication to the device
can be paused via the hold pin (HOLD). While the
device is paused, transitions on its inputs will be
ignored, with the exception of chip select, allowing the
host to service higher priority interrupts. Also write
operations to the Status Register can be disabled via
the write protect pin (WP).
Y Decoder
SO
CS
SCK
HOLD
Sense Amp.
R/W Control
Vcc
Vss
SPI is a trademark of Motorola.
1996 Microchip Technology Inc.
Preliminary
DS21146D-page 1
25AA080/160
FIGURE 1-1: AC TEST CIRCUIT
1.0
ELECTRICAL
CHARACTERISTICS
Vcc
1.1
Maximum Ratings*
2.25 K
VCC ....................................................................... 7.0V
All inputs and outputs w.r.t. ......VSS-0.6V to VCC +1.0V
Storage temperature .............................-65˚C to 150˚C
Ambient temperature under bias...........-65˚C to 125˚C
Soldering temperature of leads (10 seconds) ...+300˚C
ESD protection on all pins...................................... 4kV
SO
1.8 K
100 pF
*Notice: Stresses above those listed under ‘Maximum ratings’
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at those or
any other conditions above those indicated in the operational
listings of this specification is not implied. Exposure to maxi-
mum rating conditions for extended period of time may affect
device reliability.
1.2
AC Test Conditions
AC Waveform:
VLO = 0.2V
VHI = Vcc - 0.2V
VHI = 4.0V
(Note 1)
(Note 2)
TABLE 1-1:
Name
PIN FUNCTION TABLE
Function
Timing Measurement Reference Level
Input
Output
Note 1: For VCC ≤ 4.0V
2: For VCC > 4.0V
0.5 VCC
0.5 VCC
CS
SO
Chip Select Input
Serial Data Output
Serial Data Input
Serial Clock Input
Write Protect Pin
Ground
SI
SCK
WP
VSS
VCC
HOLD
Supply Voltage
Hold Input
TABLE 1-2:
DC CHARACTERISTICS
Applicable over recommended operating ranges shown below unless otherwise noted.
VCC = +1.8V to 5.5V
Commercial (C): Tamb
Industrial (I): Tamb
=
=
0˚C to +70˚C
-40°C to +85°C
Parameter
Symbol
Min
Max
Units
Test Conditions
High level input voltage
VIH1
2.0
VCC+1
V
VCC 2.7V
≥
VIH2
VIL1
0.7 VCC
-0.3
VCC+1
0.8
V
V
VCC< 2.7V
Low level input voltage
VCC 2.7V
≥
VIL2
VOL
VOH
ILI
-0.3
—
0.3 VCC
0.4
V
V
VCC< 2.7V
Low level output voltage
High level output voltage
Input leakage current
Output leakage current
IOL=2.1 mA
VCC-0.5
-10
—
V
IOH=-400 µA
10
µA
µA
CS=VIH, VIN=VSS to VCC
ILO
-10
10
CS=VIH, V
=VSS to VCC
OUT
Internal Capacitance
(all inputs and outputs)
CINT
ICC WRITE
ICC READ
ICCS
—
7
pF
Tamb=25˚C, FCLK=3.0 MHz,
VCC=5.5V (Note)
Operating Current
—
—
5
3
mA
mA
VCC=5.5V
VCC=2.5V
—
—
1
500
mA
µA
VCC=5.5V; 3 MHz
VCC=2.5V; 2 MHz
Standby Current
—
—
5
2
µA
µA
CS=VCC=5.5V; Vin=0V or VCC
CS=VCC=2.5V; Vin=0V or VCC
Note:
This parameter is periodically sampled and not 100% tested.
DS21146D-page 2
Preliminary
1996 Microchip Technology Inc.
25AA080/160
FIGURE 1-2: SERIAL INPUT TIMING
tCSD
CS
tCLD
tR
tCSS
tF
tCSH
SCK
SI
tSU
tHD
MSB in
LSB in
high impedance
SO
FIGURE 1-3: SERIAL OUTPUT TIMING
CS
tCSH
tHI
tLO
SCK
tV
tDIS
tHO
MSB out
LSB out
SO
SI
don’t care
FIGURE 1-4: HOLD TIMING
CS
tHH
tHS
tHS
tHH
SCK
SO
tHZ
tHV
high impedance
don’t care
n
n+2
n+2
n+1
n
n-1
tSU
n
n+1
n
n-1
SI
HOLD
1996 Microchip Technology Inc.
Preliminary
DS21146D-page 3
25AA080/160
TABLE 1-3:
AC CHARACTERISTICS
Applicable over recommended operating ranges shown below unless otherwise noted.
VCC = +1.8V to 5.5V
Commercial (C): Tamb = 0˚C to +70˚C
Industrial (I):
Tamb = -40°C to +85°C
Symbol
Parameter
Min
Max
Units
Test Conditions
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
VCC=1.8V to 2.5V
fSCK Clock Frequency
—
—
—
3
2
1
MHz
MHz
MHz
tCSS CS Setup Time
tCSH CS Hold Time
tCSD CS Disable Time
100
250
500
—
—
—
ns
ns
ns
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
VCC=1.8V to 2.5V
100
250
500
—
—
—
ns
ns
ns
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
VCC=1.8V to 2.5V
250
500
500
—
—
—
ns
ns
ns
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
VCC=1.8V to 2.5V
tSU
tHD
Data Setup Time
Data Hold Time
30
50
50
—
—
—
ns
ns
ns
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
VCC=1.8V to 2.5V
50
100
100
—
—
—
ns
ns
ns
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
VCC=1.8V to 2.5V
tR
tF
CLK Rise Time
CLK Fall Time
Clock High Time
—
—
2
2
µs
µs
(Note 1)
(Note 1)
tHI
150
250
475
—
—
—
ns
ns
ns
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
VCC=1.8V to 2.5V
tLO
Clock Low Time
150
250
475
—
—
—
ns
ns
ns
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
VCC=1.8V to 2.5V
tCLD
tV
Clock Delay Time
50
—
ns
Output Valid from
Clock Low
—
—
—
150
250
475
ns
ns
ns
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
VCC=1.8V to 2.5V
tHO
tDIS
Output Hold Time
0
—
ns
Output Disable Time
—
—
—
200
250
500
ns
ns
ns
VCC=4.5V to 5.5V (Note 1)
VCC=2.5V to 4.5V (Note 1)
VCC=1.8V to 2.5V (Note 1)
tHS
tHH
tHZ
HOLD Setup Time
100
100
200
—
—
—
ns
ns
ns
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
VCC=1.8V to 2.5V
HOLD Hold Time
100
100
200
—
—
—
ns
ns
ns
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
VCC=1.8V to 2.5V
HOLD Low to Output High-Z
100
150
200
—
—
—
ns
ns
ns
VCC=4.5V to 5.5V (Note 1)
VCC=2.5V to 4.5V (Note 1)
VCC=1.8V to 2.5V (Note 1)
tHV
HOLD High to Output Valid
100
150
200
—
—
—
ns
ns
ns
VCC=4.5V to 5.5V (Note 1)
VCC=2.5V to 4.5V (Note 1)
VCC=1.8V to 2.5V (Note 1)
tWC
—
Internal Write Cycle Time
Endurance
—
5
ms
(Note 2)
10M
—
E/W
25°C, Vcc = 5.0V, Block Mode (Note 3)
Cycles
Note 1: This parameter is periodically sampled and not 100% tested.
2: twc begins on the rising edge of CS after a valid write sequence and ends when the internal self-timed write cycle is com-
plete.
3: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please
consult the Total Endurance Model which can be obtained on our BBS or website.
DS21146D-page 4
Preliminary
1996 Microchip Technology Inc.
25AA080/160
2.2
Read Status Register (RDSR)
2.0
PRINCIPLES OF OPERATION
The 25AA080/160 is an 1024/2048 byte EEPROM
designed to interface directly with the Serial Peripheral
Interface (SPI) port of many of today’s popular micro-
controller families, including Microchip’s midrange
PIC16CXX microcontrollers. It may also interface with
microcontrollers that do not have a built-in SPI port by
using discrete I/O lines programmed properly with soft-
ware.
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is format-
ted as follows:
7
6
5
4
3
2
1
0
WPEN
X
X
X
BP1
BP0
WEL
WIP
The 25AA080/160 contains an 8-bit instruction register.
The part is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. If the WPEN bit in
the status register is set, the WP pin must be held high
to allow writing to the non-volatile bits in the status reg-
ister.
The Write-In-Process (WIP) bit indicates whether the
25AA080/160 is busy with a write operation. When set
to a ‘1’ a write is in progress, when set to a ‘0’ no write
is in progress. This bit is read only.
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch. When set to a ‘1’ the latch
allows writes to the array and status register, when set
to a ‘0’ the latch prohibits writes to the array and status
register. The state of this bit can always be updated via
the WREN or WRDI commands regardless of the state
of write protection on the status register.This bit is read
only.
Table 2-1 contains a list of the possible instruction bytes
and format for device operation. All instructions,
addresses and data are transferred MSB first, LSB last.
Data is sampled on the first rising edge of SCK after CS
goes low. If the clock line is shared with other peripheral
devices on the SPI bus, the user can assert the HOLD
input and place the 25AA080/160 in ‘HOLD’ mode.
After releasing the HOLD pin, operation will resume
from the point when the HOLD was asserted.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write protected. These bits
are set by the user issuing the WRSR instruction.
These bits are non-volatile.
2.1
Write Enable (WREN) and Write
Disable (WRDI)
The Write Protect Enable (WPEN) bit is a non-volatile
bit that is available as an enable bit for the WP pin. The
Write Protect (WP) pin and the Write Protect Enable
(WPEN) bit in the status register control the program-
mable hardware write protect feature. Hardware write
protection is enabled when WP pin is low and the
WPEN bit is high. Hardware write protection is disabled
when either the WP pin is high or the WPEN bit is low.
When the chip is hardware write protected, only writes
to non-volatile bits in the status register are disabled.
See Table 2-2 for matrix of functionality on the WPEN
bit and Figure 2-1 for a flowchart of Table 2-2.
The 25AA080/160 contains a write enable latch. This
latch must be set before any write operation will be
completed internally. The WREN instruction will set the
latch, and the WRDI will reset the latch.The following is
a list of conditions under which the write enable latch
will be reset:
• Power-up
• WRDI instruction successfully executed
• WRSR instruction successfully executed
• WRITE instruction successfully executed
See Figure 3-5 for RDSR timing sequence.
1996 Microchip Technology Inc.
Preliminary
DS21146D-page 5
25AA080/160
TABLE 2-1:
INSTRUCTION SET
Instruction Name Instruction Format
Description
WREN
WRDI
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Set the write enable latch (enable write operations)
Reset the write enable latch (disable write operations)
Read status register
RDSR
WRSR
READ
WRITE
Write status register (write protect enable and block write protection bits)
Read data from memory array beginning at selected address
Write data to memory array beginning at selected address
TABLE 2-2:
WPEN
WRITE PROTECT FUNCTIONALITY MATRIX
WP
WEL
Protected Blocks
Unprotected Blocks
Status Register
0
0
1
1
X
X
X
0
1
0
1
0
1
Protected
Protected
Protected
Protected
Protected
Protected
Protected
Writable
Protected
Writable
Protected
Writable
Protected
Writable
X
Low
Low
High
High
Protected
Protected
Protected
Writable
FIGURE 2-1: WRITE TO STATUS REGISTER AND/OR ARRAY FLOWCHART
CS Returns High
Write
to Status
Reg?
No
No
No
No
Write
To other
Commands
to array?
Yes
Yes
WEL = 1?
Yes
WEL = 1?
Yes
Write to the
Unprotected Block
No
No
WP is low?
Yes
Do not write to
Array
WPEN = 1?
Yes
Write to
Status Register
Do not write to
Status Register
From other
Commands
Continue
DS21146D-page 6
Preliminary
1996 Microchip Technology Inc.
25AA080/160
transmitted, the CS must be brought high to set the
write enable latch. If the write operation is initiated
immediately after the WREN instruction without CS
being brought high, the data will not be written to the
array because the write enable latch will not have been
properly set.
2.3
Write Status Register (WRSR)
The WRSR instruction allows the user to select one of
four protection options for the array by writing to the
appropriate bits in the status register. The array is
divided up into four segments. The user has the ability
to write protect none, one, two, or all four of the seg-
ments of the array.The partitioning is controlled as illus-
trated in table below.
Once the write enable latch is set, the user may pro-
ceed by setting the CS low, issuing a write instruction,
followed by the 16-bit address, with the five (25AA080)
or six (25AA080) MSBs of the address being don’t care
bits, and then the data to be written. Up to 16 bytes of
data can be sent to the 25AA080/160 before a write
cycle is necessary. The only restriction is that all of the
bytes must reside in the same page. A page address
begins with XXXX XXXX XXXX 0000 and ends with
XXXX XXXX XXXX 1111. If the internal address
counter reaches XXXX XXXX XXXX 1111 and the
clock continues, the counter will roll back to the first
address of the page and overwrite any data in the page
that may have been written.
See Figure 3-6 for WRSR timing sequence.
TABLE 2-3:
ARRAY PROTECTION
Array Addresses
Write Protected
BP1
BP0
0
0
0
1
none
upper 1/4
300h-3FFh for 25AA080
600h-7FFh for 25AA160
1
1
0
1
upper 1/2
200h-3FFh for 25AA080
400h-7FFh for 25AA160
For the data to be actually written to the array, the CS
must be brought high after the least significant bit (D0)
th
of the n data byte has been clocked in. If CSis brought
all
high at any other time, the write operation will not be
completed. See Figure 3-3 and Figure 3-4 for more
detailed illustrations on the byte write sequence and the
page write sequence, respectively.
000h-3FFh for 25AA080
000h-7FFh for 25AA160
3.0
DEVICE OPERATION
While the write is in progress, the status register may
be read to check the status of the WPEN, WIP, WEL,
BP1, and BP0 bits. A read attempt of a memory array
location will not be possible during a write cycle. When
a write cycle is completed, the write enable latch is
reset.
3.1
Clock and Data Timing
Data input on the SI pin is latched on the rising edge of
SCK. Data is output on the SO pin after the falling edge
of SCK.
3.2
Read Sequence
3.4
Data Protection
The part is selected by pulling CS low. The 8-bit read
instruction is transmitted to the 25AA080/160 followed
by the 16-bit address, with the five (25AA160) or six
(25AA080) MSBs of the address being don’t care bits.
After the correct read instruction and address are sent,
the data stored in the memory at the selected address
is shifted out on the SO pin. The data stored in the
memory at the next address can be read sequentially
by continuing to provide clock pulses. The internal
address pointer is automatically incremented to the
next higher address after each byte of data is shifted
out. When the highest address is reached ($3FF for
25AA080, $7FF for 25AA160) the address counter rolls
over to address $000 allowing the read cycle to be con-
tinued indefinitely. The read operation is terminated by
setting CS high (see Figure 3-1).
The following protection has been implemented to pre-
vent inadvertent writes to the array:
• The write enable latch is reset on power-up.
• A write enable instruction must be issued to set
the write enable latch.
• After a successful byte write, page write, or status
register write, the write enable latch is reset.
• CS must be set high after the proper number of
clock cycles to start an internal write cycle.
• Access to the array during an internal write cycle
is ignored and programming is continued.
3.5
Power On State
The 25AA080/160 powers on in the following state:
• The device is in low power standby mode (CS=1).
• The write enable latch is reset.
• SO is in high impedance state.
3.3
Write Sequence
Prior to any attempt to write data to the 25AA080/160,
the write enable latch must be set by issuing the WREN
instruction (see Figure 3-2). This is done by setting CS
low and then clocking the proper instruction into the
25AA080/160. After all eight bits of the instruction are
• A low level on CS is required to enter active state.
1996 Microchip Technology Inc.
Preliminary
DS21146D-page 7
25AA080/160
FIGURE 3-1: READ SEQUENCE
CS
0
0
1
0
2
3
4
5
0
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
SCK
SI
instruction
16 bit address
1 15 14 13 12
0
0
0
1
2
1
0
data out
high impedance
7
6
5
4
3
2
1
0
SO
FIGURE 3-2: WRITE ENABLE SEQUENCE
CS
0
0
1
0
2
0
3
0
4
0
5
6
1
7
SCK
SI
1
0
high impedance
SO
FIGURE 3-3: WRITE SEQUENCE
CS
T
wc
0
0
1
0
2
3
4
5
0
6
1
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
data byte
SCK
SI
instruction
16 bit address
15 14 13 12
0
0
0
0
2
1
0
7
6
5
4
3
2
1
0
high impedance
SO
DS21146D-page 8
Preliminary
1996 Microchip Technology Inc.
25AA080/160
FIGURE 3-4: PAGE WRITE SEQUENCE
CS
0
0
1
0
2
3
4
5
0
6
7
8
9
10 11
21 22 23 24 25 26 27 28 29 30 31
data byte 1
SCK
SI
instruction
16 bit address
0
0
0
1
0 15 14 13 12
2
1
0
7
6
5
4
3
2
1
0
CS
32 33 34 35 36 37 38 39
data byte 2
41 42 43 44 45 46 47
data byte 3
40
7
SCK
SI
data byte n (16 max)
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
FIGURE 3-5: READ STATUS REGISTER SEQUENCE
CS
0
0
1
0
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
SI
instruction
0
0
0
1
0
1
data from status register
high impedance
7
6
5
4
3
2
1
0
SO
FIGURE 3-6: WRITE STATUS REGISTER SEQUENCE
CS
0
0
1
0
2
3
4
5
0
6
0
7
8
9
10 11 12 13 14 15
SCK
SI
instruction
data to status register
7
6
5
4
3
2
1
0
0
0
0
1
high impedance
SO
1996 Microchip Technology Inc.
Preliminary
DS21146D-page 9
25AA080/160
4.5
Write Protect (WP)
4.0
PIN DESCRIPTIONS
This pin is used in conjunction with the WPEN bit in the
status register to prohibit writes to the non-volatile bits
in the status register. When WP is low and WPEN is
high, writing to the non-volatile bits in the status register
is disabled. All other operations function normally.
When WP is high, all functions, including writes to the
non-volatile bits in the status register operate normally.
If the WPEN bit is set WP low during a status register
write sequence will disable writing to the status register.
If an internal write cycle has already begun, WP going
low will have no effect on the write.
4.1
Chip Select (CS)
A low level on this pin selects the device. A high level
deselects the device and forces it into standby mode.
However, a programming cycle which is already in
progress will be completed, regardless of the CS input
signal. If CS is brought high during a program cycle, the
device will go into standby mode as soon as the pro-
gramming cycle is complete. As soon as the device is
deselected, SO goes to the high impedance state,
allowing multiple parts to share the same SPI bus. A
low to high transition on CS after a valid write sequence
initiates an internal write cycle. After power-up, a low
level on CS is required prior to any sequence being ini-
tiated.
The WP pin function is blocked when the WPEN bit in
the status register is low. This allows the user to install
the 25AA080/160 in a system with WP pin grounded
and still be able to write to the status register. The WP
pin functions will be enabled when the WPEN bit is set
high.
4.2
Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses, and data. Data is
latched on the rising edge of the serial clock.
4.6
Hold (HOLD)
The HOLD pin is used to suspend transmission to the
25AA080/160 while in the middle of a serial sequence
without having to re-transmit the entire sequence over
at a later time. It should be held high any time this func-
tion is not being used. Once the device is selected and
a serial sequence is underway, the HOLD pin may be
pulled low to pause further serial communication with-
out resetting the serial sequence. The HOLD pin must
be brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high to
low transition. The 25AA080/160 must remain selected
during this sequence. The SI, SCK, and SO pins are in
a high impedance state during the time the part is
paused and transitions on these pins will be ignored.To
resume serial communication, HOLD must be brought
high while the SCK pin is low, otherwise serial commu-
nication will not resume.
It is possible for the SI pin and the SO pin to be tied
together. With SI and SO tied together, two way com-
munication of data can occur using only one microcon-
troller I/O line.
4.3
Serial Output (SO)
The SO pin is used to transfer data out of the 25AA080/
160. During a read cycle, data is shifted out on this pin
after the falling edge of the serial clock.
It is possible for the SI pin and the SO pin to be tied
together. With SI and SO tied together, two way com-
munication of data can occur using only one microcon-
troller I/O line.
4.4
Serial Clock (SCK)
The SCK is used to synchronize the communication
between a master and the 25AA080/160. Instructions,
addresses, or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
DS21146D-page 10
Preliminary
1996 Microchip Technology Inc.
25AA080/160
25AA080/160 Product Identification System
To order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed
sales offices.
25AA080/160
-
/P
Package:
P = Plastic DIP (300 mil body), 8 lead
SN = Plastic SOIC (150 mil body), 8 lead
Temperature
Range:
Blank = 0°C to +70°C
I = -40°C to +85°C
Device:
SPI Bus Serial EEPROM
25AA080/160
25AA080T/160T
SPI BUS EEPROM (Tape and Reel)
Sales and Support
Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office (see next page)
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.
1996 Microchip Technology Inc.
Preliminary
DS21146D-page 11
WORLDWIDE SALES & SERVICE
AMERICAS
Corporate Office
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Microchip Technology Inc.
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Tel: 81 45 471 6166 Fax: 81 45 471 6122
11/7/96
Los Angeles
Microchip Technology Inc.
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NewYork
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Toronto
Microchip Technology Inc.
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Tel: 905 405-6279 Fax: 905 405-6253
All rights reserved. 1996, Microchip Technology Incorporated, USA. 11/96
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No repre-
sentation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement
of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not autho-
rized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.The Microchip logo and
name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS21146D-page 12
Preliminary
1996 Microchip Technology Inc.
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