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HV5122PJ-G [MICROCHIP]

EL Driver, 32-Segment, CMOS, PQCC44, 0.653 X 0.653 INCH, 0.180 INCH HEIGHT, 0.05 INCH PITCH, GREEN, PLASTIC, MS-018AC, LCC-44;
HV5122PJ-G
型号： HV5122PJ-G
厂家： MICROCHIP    MICROCHIP
描述：

EL Driver, 32-Segment, CMOS, PQCC44, 0.653 X 0.653 INCH, 0.180 INCH HEIGHT, 0.05 INCH PITCH, GREEN, PLASTIC, MS-018AC, LCC-44

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HV5122  
Supertex inc.  
32-Channel Serial to Parallel Converter  
With Open Drain Outputs  
Features  
General Description  
► Processed with HVCMOS® technology  
The HV5122 is a low voltage serial to high voltage parallel converter  
with open drain outputs. This device has been designed for use as a  
driver for AC electroluminescent displays. They can also be used in  
any application requiring multiple output high voltage current sinking  
capabilities such as driving inkjet and electrostatic print heads,  
plasma panels, vacuum fluorescent, or large matrix LCD displays.  
► Output voltages to 225V using a ramped  
supply voltage  
► SINK current minimum 100mA  
► Shift register speed 8.0MHz  
► Strobe and enable inputs  
► CMOS compatible inputs  
This device consists of a 32-bit shift register and control logic to  
perform the Output Enable and all-on functions. Data is shifted  
through the shift register on the high to low transition of the clock.  
The HV5122 shifts in the counter-clockwise direction when viewed  
from the top of the package. A data output buffer is provided for  
cascading devices. This output reflects the current status of the last  
bit of the shift register. Operation of the shift register is not affected  
by the OE(Output Enable) or the STR(Strobe) inputs.  
► Forward and reverse shifting options  
► Hi-Rel processing available  
The HV5122 has been designed to be used in systems which either  
switch off the high voltage supply before changing the state of the  
high voltage outputs or which limit the current through each output.  
Functional Block Diagram  
STR  
OE  
HVOUT  
1
DATA  
INPUT  
HVOUT  
2
•
•
•
CLK  
28 Additional  
32 bit  
Static Shift  
Register  
Outputs  
•
•
•
HVOUT31  
HVOUT32  
Data Out  
Doc.# DSFP-HV5122  
B072213  
Supertex inc.  
www.supertex.com  
HV5122  
Pin Configuration  
Ordering Information  
6
1 44  
40  
Part Number  
HV5122DJ-G*  
HV5122PG-G  
Package  
Packing  
44-Lead Quad Cerpac 27/Tube  
44-Lead PQFP  
96/Tray  
HV5122PG-G M919 44-Lead PQFP  
500/Reel  
27/Tube  
500/Reel  
HV5122PJ-G  
44-Lead PLCC  
44-Lead PLCC  
HV5122PJ-G M903  
44-Lead Quad Cerpac Chip Carrier  
-G denotes a lead (Pb)-free / RoHS compliant package  
Hi-Rel processing available  
*
Absolute Maximum Ratings  
Parameter  
Value  
Supply voltage, VDD  
Supply voltage, VPP  
Logic input levels  
-0.5V to +15V  
-0.5V to +250V  
-0.5V to VDD +0.5V  
1.5A  
44  
1
44-Lead PQFP  
Ground current1  
6
1 44  
40  
Continuous total power dissipation2  
Plastic  
Ceramic  
1200W  
1500W  
Operating temperature range  
Plastic  
Ceramic  
-40OC to +85OC  
-55OC to +125OC  
Storage temperature range  
-65OC to +150OC  
44-Lead PLCC  
Absolute Maximum Ratings are those values beyond which damage to the  
device may occur. Functional operation under these conditions is not implied.  
Continuous operation of the device at the absolute rating level may affect  
device reliability. All voltages are referenced to device ground.  
Typical Thermal Resistance  
Package  
θja  
Notes:  
1. Duty cycle is limited by the total power dissipated in the package.  
2. For operation above 25°C ambient derate linearly to maximum  
operating temperature at 20mW/°C for plastic and at 15mW/°C for  
ceramic.  
44-Lead Quad Cerpac  
44-Lead PQFP  
44-Lead PLCC  
---  
51OC/W  
37OC/W  
Product Marking  
Top Marking  
Top Marking  
Top Marking  
YY = Year Sealed  
WW = Week Sealed  
L = Lot Number  
YYWW  
HV5122PG  
LLLLLLLLL  
YY = Year Sealed  
YYWW  
YYWW AAA  
HV5122PJ  
YY = Year Sealed  
WW = Week Sealed  
L = Lot Number  
C = Country of Origin*  
A = Assembler ID*  
*May be part of top marking  
HV5122DJ  
WW = Week Sealed  
L = Lot Number  
LLLLLLLLLL  
LLLLLLLLLL  
A = Assembler ID  
C = Country of Origin*  
Bottom Marking  
Bottom Marking  
C = Country of Origin*  
A = Assembler ID*  
Bottom Marking  
= “Green” Packaging  
*May be part of top marking  
CCCCCCCCCCC  
AAA  
CCCCCCCC  
AAA  
= “Green” Packaging  
CCCCCCCCCCC  
*May be part of top marking  
44-Lead PQFP  
44-Lead Quad Cerpac Chip Carrier  
44-Lead PLCC  
Packages may or may not include the following marks: Si or  
Doc.# DSFP-HV5122  
B072213  
Supertex inc.  
www.supertex.com  
2
HV5122  
Recommended Operating Conditions  
Sym  
Parameter  
Min  
10.8  
-0.3  
VDD -2.0  
0
Typ  
Max  
13.2  
225  
VDD  
Units  
V
VDD  
Logic voltage supply  
High voltage output  
High-level input voltage  
Low-level input voltage  
Clock frequency  
12  
-
HVOUT  
VIH  
V
-
V
VIL  
-
2.0  
V
fCLK  
-
-
8.0  
MHz  
Plastic  
-40  
-
+85  
+125  
TA  
Operating free-air temperature  
OC  
Ceramic  
-55  
-
Power-Up Sequence  
Power-up sequence should be the following:  
1. Connect ground  
2. Apply VDD  
3. Set all inputs to a known state  
Power-down sequence should be the reverse of the above.  
Electrical Characteristics (Over recommended operating conditions unless otherwise specified)  
DC Characteristics  
Sym  
Parameter  
Min  
Max  
15  
Units Conditions  
IDD  
VDD supply current  
-
mA  
µA  
µA  
µA  
µA  
V
fCLK = 8.0MHz, FDATA = 4.0MHz  
All VIN = 0V  
IDDQ  
IO(OFF)  
IIH  
Quiescent VDD supply current  
Off-state output current  
High level logic input current  
Low level logic input current  
High level output data out  
-
100  
10  
-
All outputs high, all SWS parallel  
VIH = 12V  
-
1.0  
-1.0  
-
IIL  
-
VIL = 0  
VOH  
VDD -1.0V  
IDOUT = -100µA  
HVOUT  
Data out  
-
-
-
15  
IHVOUT = +100mA  
IDOUT = +100µA  
VOL  
VOC  
Low level output voltage  
V
V
1.0  
-1.5  
HVOUT clamp voltage  
IOL = -100mA  
AC Characteristics (VDD = 12V, TA = 25°C)  
Sym  
fCLK  
tW  
Parameter  
Min  
-
Max  
8.0  
-
Units Conditions  
Clock frequency  
MHz ---  
Clock width, high or low  
62  
25  
10  
-
ns  
ns  
ns  
ns  
ns  
ns  
---  
tSU  
Data setup time before CLK falls  
Data hold time after CLK falls  
Turn-on time, HVOUT from strobe  
Data output delay after H to L CLK  
Data output delay after L to H CLK  
-
---  
tH  
-
---  
tON  
500  
100  
100  
RL = 2.0KΩ to 200V  
CL = 15pF  
CL = 15pF  
tDHL  
tDLH  
-
-
Doc.# DSFP-HV5122  
B072213  
Supertex inc.  
www.supertex.com  
3
HV5122  
Input and Output Equivalent Circuits  
VDD  
VDD  
HVOUT  
DATA  
OUT  
HVIN  
INPUT  
GND  
GND  
GND  
Logic Data Output  
Logic Inputs  
High Voltage Outputs  
Switching Waveforms  
12V  
DATA  
IN  
Data Valid 1  
0V  
tSU  
tH  
12V  
CLK  
50%  
50%  
50%  
0V  
tWH  
tWL  
DATA  
OUT  
50%  
tDHL  
DATA  
OUT  
tDLH  
STR  
50%  
tON  
HVOUT  
15V  
Function Table  
Inputs  
Outputs  
Shift Reg  
HV Outputs  
Function  
Data  
In  
Data  
Out  
CLK  
OE  
STR  
1
2...32  
1
2...32  
ON...ON  
All on  
All off  
X
X
X
L
L
H
H
H
●
●
●...●  
●...●  
●...●  
●...●  
ON  
OFF  
●
●
-
X
H OR L  
X
X
↓
OFF...OFF  
OFF...OFF  
●...●  
Load S/R  
L
H or L  
H or L  
OFF  
Output Enable  
H OR L  
H
ON or OFF  
●
Notes:  
H = high level, L = low level, X = irrelevant, ↓ = high-to-low transition  
● = dependent on previous stage’s state before the last CLK: High-to-low transition  
Doc.# DSFP-HV5122  
B072213  
Supertex inc.  
www.supertex.com  
4
HV5122  
44-Lead PQFP Pin description  
Pin  
Function  
HVOUT11  
HVOUT12  
HVOUT13  
HVOUT14  
HVOUT15  
HVOUT16  
HVOUT17  
HVOUT18  
HVOUT19  
HVOUT20  
HVOUT21  
HVOUT22  
HVOUT23  
HVOUT24  
HVOUT25  
HVOUT26  
HVOUT27  
HVOUT28  
HVOUT29  
HVOUT30  
HVOUT31  
HVOUT32  
DATA OUT  
Description  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
High voltage outputs.  
Data output for cascading to the data input of the next device.  
N/C  
No connect.  
Output enable input.  
28  
OE  
When OE is LOW, all HV outputs are forced into a LOW state, regardless of data in  
each channel. When OE is HIGH, all HV outputs reflect data latched.  
Data shift register clock. Input are shifted into the shift register on the positive edge of  
the clock.  
29  
CLK  
30  
31  
32  
GND  
VDD  
STR  
Logic and high voltage ground.  
Low voltage logic power rail.  
Strobe.  
Doc.# DSFP-HV5122  
B072213  
Supertex inc.  
www.supertex.com  
5
HV5122  
44-Lead PQFP Pin description (cont.)  
Pin  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
Function  
DATA IN  
N/C  
Description  
Serial data input. Data needs to be present before each rising edge of the clock.  
No connect.  
HVOUT  
HVOUT  
HVOUT  
HVOUT  
HVOUT  
HVOUT  
HVOUT  
HVOUT  
HVOUT  
1
2
3
4
5
6
7
8
9
High voltage outputs.  
HVOUT10  
44-Lead PLCC Pin description  
Pin  
1
Function  
HVOUT16  
HVOUT17  
HVOUT18  
HVOUT19  
HVOUT20  
HVOUT21  
HVOUT22  
HVOUT23  
HVOUT24  
HVOUT25  
HVOUT26  
HVOUT27  
HVOUT28  
HVOUT29  
HVOUT30  
HVOUT31  
HVOUT32  
Function  
2
3
4
5
6
7
8
9
High voltage outputs  
10  
11  
12  
13  
14  
15  
16  
17  
Doc.# DSFP-HV5122  
B072213  
Supertex inc.  
www.supertex.com  
6
HV5122  
44-Lead PLCC Pin description (cont.)  
Pin  
18  
19  
20  
21  
22  
Function  
Function  
DATA OUT  
Data output for cascading to the data input of the next device.  
N/C  
No connect.  
Output enable input.  
23  
OE  
When OE is LOW, all HV outputs are forced into a LOW state, regardless of data in  
each channel. When OE is HIGH, all HV outputs reflect data latched.  
Data shift register clock. Input are shifted into the shift register on the positive edge of  
the clock.  
24  
CLK  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
GND  
VDD  
Logic and high voltage ground.  
Low voltage logic power rail.  
STR  
Strobe.  
DATA IN  
N/C  
Serial data input. Data needs to be present before each rising edge of the clock.  
No connect.  
HVOUT1  
HVOUT  
HVOUT  
HVOUT  
HVOUT  
HVOUT  
HVOUT  
HVOUT  
HVOUT  
2
3
4
5
6
7
8
9
High voltage outputs.  
HVOUT10  
HVOUT11  
HVOUT12  
HVOUT13  
HVOUT14  
HVOUT15  
Doc.# DSFP-HV5122  
B072213  
Supertex inc.  
www.supertex.com  
7
HV5122  
44-Lead Quad Cerpac Package Outline (DJ)  
.650x.650in body, .190in height (max), .050in pitch  
.040 x 45O  
D
D1  
1
.035 x 45O  
6
44  
40  
.150 max  
Note 1  
(Index Area)  
.075 max  
E1  
E
0.25 max  
3 Places  
Top View  
Vertical Side View  
View B  
b1  
.025 MIN  
A
A2  
Seating  
Plane  
e
A1  
b
Horizontal Side View  
View B  
Note:  
1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or  
a printed indicator.  
Symbol  
A
A1  
A2  
b
b1  
D
D1  
E
E1  
e
MIN  
NOM  
MAX  
.155  
.172  
.190  
.090  
.100  
.120  
.017  
.019  
.021  
.026  
.029  
.032  
.685  
.690  
.695  
.630  
.650  
.665  
.685  
.690  
.695  
.630  
.650  
.665  
Dimension  
(inches)  
.060  
REF  
.050  
BSC  
JEDEC Registration MO-087, Variation AB, Issue B, August, 1991.  
Drawings not to scale.  
Supertex Doc. #: DSPD-44CERPACDJ, Version D090808.  
Doc.# DSFP-HV5122  
B072213  
Supertex inc.  
www.supertex.com  
8
HV5122  
44-Lead PQFP Package Outline (PG)  
10.00x10.00mm body, 2.35mm height (max), 0.80mm pitch  
D
D1  
E1  
E
Note 1  
(Index Area  
D1/4 x E1/4)  
44  
1
b
e
θ1  
Top View  
View B  
Gauge  
A2  
A1  
L2  
θ
Plane  
A
Seating  
Plane  
L
L1  
Seating  
Plane  
Side View  
View B  
Note:  
1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or  
a printed indicator.  
Symbol  
A
A1  
MIN 1.95* 0.00 1.95 0.30 13.65* 9.80* 13.65* 9.80*  
NOM 2.00 13.90 10.00 13.90 10.00  
MAX 2.35 0.25 2.10 0.45 14.15* 10.20* 14.15* 10.20*  
A2  
b
D
D1  
E
E1  
e
L
L1  
L2  
θ
0O  
0.73  
0.88  
1.03  
Dimension  
(mm)  
0.80  
BSC  
1.95 0.25  
REF BSC  
-
-
-
3.5O  
7O  
JEDEC Registration MO-112, Variation AA-2, Issue B, Sep.1995.  
* This dimension is not specified in the JEDEC drawing.  
Drawings not to scale.  
Supertex Doc. #: DSPD-44PQFPPG, Version C041309.  
Doc.# DSFP-HV5122  
B072213  
Supertex inc.  
www.supertex.com  
9
HV5122  
44-Lead PLCC Package Outline (PJ)  
.653x.653in body, .180in height (max), .050in pitch  
D
.048/.042  
D1  
x 45O  
.056/.042  
x 45O  
6
1
44  
40  
.150max  
Note 1  
(Index Area)  
.075max  
E
E1  
Note 2  
e
.020max  
(3 Places)  
Top View  
Vertical Side View  
View  
B
b1  
Base  
Plane  
A
.020min  
A2  
A1  
Seating  
Plane  
b
R
Horizontal Side View  
View B  
Notes:  
1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or  
a printed indicator.  
2. Actual shape of this feature may vary.  
Symbol  
A
A1  
A2  
.062  
-
b
.013  
-
b1  
.026  
-
D
D1  
E
E1  
e
R
MIN  
.165  
.172  
.180  
.090  
.105  
.120  
.685  
.690  
.695  
.650  
.653  
.656  
.685  
.690  
.695  
.650  
.653  
.656  
.025  
.035  
.045  
Dimension  
.050  
BSC  
NOM  
MAX  
(inches)  
.083  
.021  
.036†  
JEDEC Registration MS-018, Variation AC, Issue A, June, 1993.  
† This dimension differs from the JEDEC drawing.  
Drawings not to scale.  
Supertex Doc. #: DSPD-44PLCCPJ, Version F031111.  
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to:  
http://www.supertex.com/packaging.html.)  
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives  
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability  
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and  
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)  
©2013 Supertex inc.All rights reserved. Unauthorized use or reproduction is prohibited.  
Supertex inc.  
1235 Bordeaux Drive, Sunnyvale, CA 94089  
Tel: 408-222-8888  
www.supertex.com  
Doc.# DSFP-HV5122  
B072213  
10  

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