KSZ8081MNXCA [MICROCHIP]
10BASE-T/100BASE-TX Physical Layer Transceiver;
| 型号： | KSZ8081MNXCA |
| 厂家： | 
MICROCHIP |
| 描述： | 10BASE-T/100BASE-TX Physical Layer Transceiver |
| 文件： | 总66页 (文件大小：1770K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KSZ8081MNX/RNB
10BASE-T/100BASE-TX Physical Layer
Transceiver
Features
Applications
• Single-chip 10Base-T/100Base-TX IEEE 802.3
compliant Ethernet transceiver
• Game console
• IP phone
• IP set-top box
• IP TV
• MII interface support (KSZ8081MNX)
• RMII v1.2 Interface support with a 50 MHz refer-
ence clock output to MAC, and an option to input
a 50 MHz reference clock (KSZ8081RNB)
• LOM
• Printer
• Back-to-back mode support for a 100 Mbps
copper repeater
• MDC/MDIO management interface for PHY
register configuration
• Programmable interrupt output
• LED outputs for link, activity, and speed status
indication
• On-chip termination resistors for the differential
pairs
• Baseline wander correction
• HP Auto MDI/MDI-X to reliably detect and correct
straight-through and crossover cable connections
with disable and enable option
• Auto-negotiation to automatically select the
highest link-up speed (10/100 Mbps) and duplex
(half/full)
• Power-down and power-saving modes
• LinkMD TDR-based cable diagnostics to identify
faulty copper cabling
• Parametric NAND Tree support for fault detection
between chip I/Os and the board
• HBM ESD rating (6 kV)
• Loopback modes for diagnostics
• Single 3.3V power supply with VDD I/O options
for 1.8V, 2.5V, or 3.3V
• Built-in 1.2V regulator for core
• Available in 32-pin (5 mm × 5 mm) QFN package
2016 Microchip Technology Inc.
DS00002202A-page 1
KSZ8081MNX/RNB
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur-
rent devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the
revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are
using.
Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
DS00002202A-page 2
2016 Microchip Technology Inc.
KSZ8081MNX/RNB
Table of Contents
1.0 Introduction ..................................................................................................................................................................................... 4
2.0 Pin Description and Configuration ................................................................................................................................................... 5
3.0 Functional Description .................................................................................................................................................................. 15
4.0 Register Descriptions .................................................................................................................................................................... 34
5.0 Operational Characteristics ........................................................................................................................................................... 46
6.0 Electrical Characteristics ............................................................................................................................................................... 47
7.0 Timing Diagrams
49
8.0 Package Outline............................................................................................................................................................................. 60
Appendix A: Data Sheet Revision History ........................................................................................................................................... 61
The Microchip Web Site ...................................................................................................................................................................... 62
Customer Change Notification Service ............................................................................................................................................... 62
Customer Support ............................................................................................................................................................................... 62
Product Identification System ............................................................................................................................................................. 63
2016 Microchip Technology Inc.
DS00002202A-page 3
KSZ8081MNX/RNB
1.0
1.1
INTRODUCTION
General Description
The KSZ8081 is a single-supply 10BASE-T/100BASE-TX Ethernet physical-layer transceiver for transmission and
reception of data over standard CAT-5 unshielded twisted pair (UTP) cable.
The KSZ8081 is a highly-integrated PHY solution. It reduces board cost and simplifies board layout by using on-chip
termination resistors for the differential pairs and by integrating a low-noise regulator to supply the 1.2V core.
The KSZ8081MNX offers the Media Independent Interface (MII) and the KSZ8081RNB offers the Reduced Media Inde-
pendent Interface (RMII) for direct connection with MII/RMII-compliant Ethernet MAC processors and switches.
A 25 MHz crystal is used to generate all required clocks, including the 50 MHz RMII reference clock output for the
KSZ8081RNB.
The KSZ8081 provides diagnostic features to facilitate system bring-up and debugging in production testing and in prod-
uct deployment. Parametric NAND tree support enables fault detection between KSZ8081 I/Os and the board. LinkMD®
TDR-based cable diagnostics identify faulty copper cabling.
The KSZ8081MNX and KSZ8081RNB are available in 32-pin, lead-free QFN packages.
FIGURE 1-1:
FUNCTIONAL BLOCK DIAGRAM
MDC/MDIO
MANAGEMENT
MEDIA TYPES:
10BASE-T
100BASE-TX
KSZ8081MNX/
MII/RMII
RJ-45
CONNECTOR
10/100Mbps
MII/RMII MAC
KSZ8081RNB
50MHz
(KSZ8081RNB)
REF_CLK
XO
XI
25MHz
XTAL
22pF
22pF
DS00002202A-page 4
2016 Microchip Technology Inc.
KSZ8081MNX/RNB
2.0
PIN DESCRIPTION AND CONFIGURATION
FIGURE 2-1:
KSZ8081MNX 32-QFN PIN ASSIGNMENT (TOP VIEW)
32 31 30 29 28 27 26 25
1
2
24
23
GND
VDD_1.2
VDDA_3.3
RXM
TXD0
TXEN
3
4
5
22 TXC
21
PADDLE
INTRP/NAND_TREE#
RXER/ISO
GROUND
20
(ON BOTTOM OF CHIP)
RXP
TXM
RXC/B-CAST_OFF
6
7
8
19
18
17
TXP
XO
RXDV/CONFIG2
VDDIO
9
10 11 12 13 14 15 16
TABLE 2-1:
PIN DESCRIPTION — KSZ8081MNX
Buffer
Pin
Number
Name
Type
Description
(Note 2-1)
1
2
GND
GND
P
Ground
1.2V core VDD (power supplied by KSZ8081MNX). Decouple with
2.2 μF and 0.1 μF capacitors to ground.
VDD_1.2
3
4
5
6
7
VDDA_3.3
RXM
P
3.3V analog VDD.
I/O
I/O
I/O
I/O
Physical receive or transmit signal ( differential).
Physical receive or transmit signal (+ differential).
Physical transmit or receive signal ( differential).
Physical transmit or receive signal (+ differential).
RXP
TXM
TXP
2016 Microchip Technology Inc.
DS00002202A-page 5
KSZ8081MNX/RNB
TABLE 2-1:
PIN DESCRIPTION — KSZ8081MNX (CONTINUED)
Buffer
Type
(Note 2-1)
Pin
Number
Name
Description
Crystal feedback for 25 MHz crystal.
8
XO
O
This pin is a no connect if an oscillator or external clock source is
used.
9
XI
I
I
Crystal / Oscillator / External Clock Input. 25 MHz ±50 ppm.
Set PHY transmit output current. Connect a 6.49 kΩ resistor to
ground on this pin.
10
REXT
Management Interface (MII) Data I/O This pin has a weak pull-up, is
open-drain, and requires an external 1.0 kΩ pull-up resistor.
11
12
MDIO
MDC
Ipu/Opu
Ipu
Management Interface (MII) Clock Input. This clock pin is synchro-
nous to the MDIO data pin.
MII Mode: MII Receive Data Output[3].
Config Mode: The pull-up/pull-down value is latched as PHY-
ADDR[0] at the de-assertion of reset.
See the Strap-In Options – KSZ8081MNX section for details.
13
14
15
PHYAD0
PHYAD1
Ipu/O
Ipd/O
Ipd/O
MII Mode: MII Receive Data Output[2] (Note 2-2)
Config Mode: The pull-up/pull-down value is latched as PHY-
ADDR[1] at the de-assertion of reset.
See the section Strap-In Options – KSZ8081MNX for details.
MII Mode: MII Receive Data Output[1] (Note 2-2).
Config Mode: The pull-up/pull-down value is latched as PHY-
ADDR[2] at the de-assertion of reset.
RXD1/
PHYAD2
See the section Strap-In Options – KSZ8081MNX for details.
MII Mode: MII Receive Data Output[0] (Note 2-2).
Config Mode: The pull-up/pull-down value is latched as DUPLEX at
the de-assertion of reset.
RXD0/
DUPLEX
16
17
18
Ipu/O
P
See the section Strap-In Options – KSZ8081MNX for details.
VDDIO
3.3V, 2.5V, or 1.8V digital VDD.
MII Mode: MII Receive Data Valid Output.
Config Mode: The pull-up/pull-down value is latched as CONFIG2
at the de-assertion of reset.
RXDV/
CONFIG2
Ipd/O
See the section Strap-In Options – KSZ8081MNX for details.
MII Mode: MII Receive Clock Output.
RXC/
B-CAST_OFF
Config Mode: The pull-up/pull-down value is latched as B-
CAST_OFF at the de-assertion of reset.
See the section Strap-In Options – KSZ8081MNX for details.
19
20
Ipd/O
Ipd/O
MII mode: MII Receive Error Output.
Config Mode: The pull-up/pull-down value is latched as ISOLATE at
the de-assertion of reset.
RXER/
ISO
See the section Strap-In Options – KSZ8081MNX for details.
DS00002202A-page 6
2016 Microchip Technology Inc.
KSZ8081MNX/RNB
TABLE 2-1:
PIN DESCRIPTION — KSZ8081MNX (CONTINUED)
Buffer
Type
(Note 2-1)
Pin
Number
Name
Description
Interrupt Output: Programmable Interrupt Output.
This pin has a weak pull-up, is open-drain, and requires an external
1.0 kꢀ pull-up resistor.
Config Mode: The pull-up/pull-down value is latched as NAND
Tree# at the de-assertion of reset.
INTRP/
21
22
Ipu/Opu
Ipd/O
NAND_Tree#
See the section Strap-In Options – KSZ8081MNX for details.
MII Mode: MII Transmit Clock Output.
At the de-assertion of reset, this pin needs to latch in a pull-down
value for normal operation. If MAC side pulls this pin high, see
Register 16h, Bit [15] for solution. It is better having an external pull-
down resistor to avoid MAC side pulls this pin high.
TXC
23
24
25
26
27
TXEN
TXD0
TXD1
TXD2
TXD3
I
I
I
I
I
MII Mode: MII Transmit Enable input.
MII Mode: MII Transmit Data Input[0] (Note 2-4).
MII Mode: MII Transmit Data Input[1] (Note 2-4).
MII Mode: MII Transmit Data Input[2] (Note 2-4).
MII Mode: MII Transmit Data Input[3] (Note 2-4).
MII Mode: MII Collision Detect output.
COL/
Config Mode: The pull-up/pull-down value is latched as CONFIG0 at
the de-assertion of reset.
28
29
Ipd/O
Ipd/O
CONFIG0
See the section Strap-In Options – KSZ8081MNX for details.
MII mode: MII Carrier Sense output
CRS/
Config mode: The pull-up/pull-down value is latched as CONFIG1 at
the de-assertion of reset.
CONFIG1
See the section Strap-In Options – KSZ8081MNX for details.
LED Output: Programmable LED0 Output.
Config Mode: Latched as auto-negotiation enable (Register 0h, Bit
[12]) at the de-assertion of reset.
See the Strap-In Options – KSZ8081MNX section for details.
The LED0 pin is programmable using Register 1Fh bits [5:4], and is
defined as follows:
LED Mode = [00]
Link/Activity
No link
Pin State
High
LED Definition
OFF
LED0/
NWAYEN
30
Ipu/O
Link
Low
ON
Activity
Toggle
Blinking
LED Mode = [01]
Link
Pin State
High
LED Definition
No link
Link
OFF
ON
Low
LED Mode = [10], [11] Reserved
2016 Microchip Technology Inc.
DS00002202A-page 7
KSZ8081MNX/RNB
TABLE 2-1:
PIN DESCRIPTION — KSZ8081MNX (CONTINUED)
Buffer
Type
(Note 2-1)
Pin
Number
Name
Description
LED Output: Programmable LED1 Output.
Config Mode: Latched as Speed (Register 0h, Bit [13]) at the de-
assertion of reset.
See the Strap-In Options – KSZ8081MNX section for details.
The LED1 pin is programmable using Register 1Fh bits [5:4], and is
defined as follows:
:
LED Mode = [00]
Speed
Pin State
High
LED Definition
LED1/
SPEED
31
Ipu/O
10Base-T
100Base-TX
OFF
ON
Low
LED Mode = [01]
Activity
Pin State
High
LED Definition
OFF
No activity
Activity
Toggle
Blinking
LED Mode = [10], [11]Reserved
Chip Reset (active low).
Ground.
32
RST#
GND
Ipu
PADDLE
GND
Note 2-1
P = Power supply.
GND = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Ipu = Input with internal pull-up (see Electrical Characteristics for value).
Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset;
output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset;
output pin otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) and output with internal
pull-up (see Electrical Characteristics for value).
NC = Pin is not bonded to the die.
Note 2-2
RMII RX Mode: The RXD[1:0] bits are synchronous with the 50 MHz RMII Reference Clock. For each
clock period in which CRS_DV is asserted, two bits of recovered data are sent by the PHY to the
MAC.
Note 2-3
Note 2-4
RMII TX Mode: The TXD[1:0] bits are synchronous with the 50 MHz RMII Reference Clock. For each
clock period in which TXEN is asserted, two bits of data are received by the PHY from the MAC.
MII TX Mode: The TXD[3:0] bits are synchronous with TXC. When TXEN is asserted, TXD[3:0]
presents valid data from the MAC. TXD[3:0] has no effect on the PHY when TXEN is de-asserted.
DS00002202A-page 8
2016 Microchip Technology Inc.
KSZ8081MNX/RNB
STRAP-IN OPTIONS – KSZ8081MNX
The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC RMII receive input pins may drive
high/low during power-up or reset, and consequently cause the PHY strap-in pins on the RMII signals to be latched to
unintended high/low states. In this case, external pull-ups (4.7 kꢀ) or pull-downs (1.0 kꢀ) should be added on these
PHY strap-in pins to ensure that the intended values are strapped-in correctly.
TABLE 2-2:
STRAP-IN OPTIONS – KSZ8081MNX
Type
Pin
Number
Pin Name
(Note
2-1)
Pin Function
PHYAD[2:0] is latched at de-assertion of reset and is configurable to any value
from 0 to 7 with PHY Address 1 as the default value.
PHY Address 0 is assigned by default as the broadcast PHY address, but it can
be assigned as a unique PHY address after pulling the
B-CAST_OFF strap-in pin high or writing a ‘1’ to Register 16h, Bit [9].
PHY Address bits [4:3] are set to 00 by default.
15
14
13
PHYAD2
PHYAD1
PHYAD0
Ipd/O
Ipd/O
Ipu/O
The CONFIG[2:0] strap-in pins are latched at the de-assertion of reset.
CONFIG[2:0]
Mode
18
29
28
CONFIG2
CONFIG1
CONFIG0
Ipd/O
Ipd/O
Ipd/O
001
RMII
101
RMII back-to-back
Reserved – not used
000, 010 – 100, 110, 111
Isolate mode
Pull-up = Enable
Pull-down (default) = Disable
At the de-assertion of reset, this pin value is latched into Register 0h, Bit [10].
20
31
ISO
Ipd/O
Ipu/O
Speed Mode:
Pull-up (default) = 100 Mbps
Pull-down = 10 Mbps
At the de-assertion of reset, this pin value is latched into Register 0h, Bit [13] as
the speed select, and also is latched into Register 4h (auto-negotiation adver-
tisement) as the speed capability support.
SPEED
Duplex Mode:
Pull-up (default) = Half-duplex
Pull-down = Full-duplex
At the de-assertion of reset, this pin value is latched into Register 0h, Bit [8].
16
30
DUPLEX
NWAYEN
Ipu/O
Ipu/O
Nway auto-negotiation enable
Pull-up (default) = Enable auto-negotiation
Pull-down = Disable auto-negotiation
At the de-assertion of reset, this pin value is latched into Register 0h, Bit [12].
Broadcast off – for PHY Address 0
Pull-up = PHY Address 0 is set as an unique PHY address
Pull-down (default) = PHY Address 0 is set as a broadcast PHY address
At the de-assertion of reset, this pin value is latched by the chip.
19
B-CAST_OFF Ipd/O
NAND tree mode
Ipu/
NAND_Tree#
Opu
Pull-up (default) = Disable
Pull-down = Enable
21
At the de-assertion of reset, this pin value is latched by the chip.
Note 2-1
Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset;
output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset;
output pin otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) and output with internal
pull-up (see Electrical Characteristics for value).
2016 Microchip Technology Inc.
DS00002202A-page 9
KSZ8081MNX/RNB
FIGURE 2-2:
KSZ8081RNB 32-QFN PIN ASSIGNMENT (TOP VIEW)
32 31 30 29 28 27 26 25
1
2
24
23
GND
VDD_1.2
VDDA_3.3
RXM
TXD0
TXEN
3
4
5
22 NC
21
PADDLE
INTRP/NAND_TREE#
RXER/ISO
GROUND
20
(ON BOTTOM OF CHIP)
RXP
TXM
REF_CLK/B-CAST_OFF
6
7
8
19
18
17
TXP
XO
CRS_DV/CONFIG2
VDDIO
9
10 11 12 13 14 15 16
TABLE 2-3:
Pin Number
1
PIN DESCRIPTION — KSZ8081RNB
Pin Name
Type (Note 2-1)
Pin Function
GND
GND
Ground
1.2V core VDD (power supplied by KSZ8081RNB).
Decouple with 2.2 μF and 0.1 μF capacitors to ground.
2
VDD_1.2
P
3
4
5
6
7
VDDA_3.3
RXM
P
3.3V analog VDD.
I/O
I/O
I/O
I/O
Physical receive or transmit signal ( differential).
Physical receive or transmit signal (+ differential).
Physical transmit or receive signal ( differential).
Physical transmit or receive signal (+ differential).
RXP
TXM
TXP
Crystal feedback for 25 MHz crystal. This pin is a no con-
nect if an oscillator or external clock source is used.
8
XO
XI
O
25 MHz Mode: 25 MHz ±50 ppm Crystal / Oscillator /
External Clock Input
50 MHz Mode: 50 MHz ±50 ppm Oscillator / External
Clock Input
9
I
Set PHY transmit output current. Connect a 6.49 kΩ
resistor to ground on this pin.
10
11
12
REXT
MDIO
MDC
I
Management Interface (MII) Data I/O. This pin has a
weak pull-up, is open-drain, and requires an external
1.0 kΩ pull-up resistor.
Ipu/Opu
Ipu
Management Interface (MII) Clock Input. This clock pin is
synchronous to the MDIO data pin.
The pull-up/pull-down value is latched as PHYADDR[0] at
the de-assertion of reset.
See the Strap-in Options – KSZ8081RNB section for
details.
13
PHYAD0
Ipu/O
DS00002202A-page 10
2016 Microchip Technology Inc.
KSZ8081MNX/RNB
TABLE 2-3:
Pin Number
PIN DESCRIPTION — KSZ8081RNB
Pin Name
Type (Note 2-1)
Pin Function
The pull-up/pull-down value is latched as PHYADDR[1] at
the de-assertion of reset.
See the Strap-in Options – KSZ8081RNB section for
details.
14
15
PHYAD1
Ipd/O
RMII Mode: RMII Receive Data Output[1] (Note 2-2).
Config Mode: The pull-up/pull-down value is latched as
PHYADDR[2] at the de-assertion of reset.
See the Strap-in Options – KSZ8081RNB section for
details.
RXD1/
PHYAD2
Ipd/O
RMII Mode: RMII Receive Data Output[0] (Note 2-2).
Config Mode: The pull-up/pull-down value is latched as
DUPLEX at the de-assertion of reset.
See the Strap-in Options – KSZ8081RNB section for
details.
RXD0/
DUPLEX
16
17
Ipu/O
P
VDDIO
3.3V, 2.5V, or 1.8V digital VDD.
RMII Mode: RMII Carrier Sense/Receive Data Valid Out-
put.
CRS_DV/
CONFIG2
Config Mode: The pull-up/pull-down value is latched as
CONFIG2 at the de-assertion of reset.
See the Strap-in Options – KSZ8081RNB section for
details.
18
Ipd/O
RMII Mode:
25 MHz Mode: This pin provides the 50 MHz RMII refer-
ence clock output to the MAC. See also XI (Pin 9).
50 MHz mode: This pin is a no connect. See also XI (Pin
9).
Config Mode: The pull-up/pull-down value is latched as B-
CAST_OFF at the de-assertion of reset.
See the Strap-in Options – KSZ8081RNB section for
details.
REF_CLK/
19
20
Ipd/O
Ipd/O
B-CAST_OFF
RMII Mode: RMII Receive Error Output.
Config Mode: The pull-up/pull-down value is latched as
ISOLATE at the de-assertion of reset.
See the Strap-in Options – KSZ8081RNB section for
details.
RXER/
ISO
Interrupt Output: Programmable Interrupt Output.
This pin has a weak pull-up, is open-drain, and requires
an external 1.0 kꢀ pull-up resistor.
INTRP/
21
22
Ipu/Opu
—
Config Mode: The pull-up/pull-down value is latched as
NAND Tree# at the de-assertion of reset.
See the Strap-in Options – KSZ8081RNB section for
details.
NAND_Tree#
No Connect. This pin is not bonded and can be left
floating.
NC
23
24
25
TXEN
TXD0
TXD1
I
I
I
RMII Transmit Enable input.
RMII Transmit Data Input[0] (Note 2-3).
RMII Transmit Data Input[1] (Note 2-3).
No Connect. This pin is not bonded and can be left
floating.
26
27
NC
NC
—
—
No Connect. This pin is not bonded and can be left
floating.
2016 Microchip Technology Inc.
DS00002202A-page 11
KSZ8081MNX/RNB
TABLE 2-3:
Pin Number
PIN DESCRIPTION — KSZ8081RNB
Pin Name
Type (Note 2-1)
Pin Function
The pull-up/pull-down value is latched as CONFIG0 at the
de-assertion of reset. See the Strap-in Options –
KSZ8081RNB section for details.
28
29
CONFIG0
Ipd/O
The pull-up/pull-down value is latched as CONFIG1 at the
de-assertion of reset. See the Strap-in Options –
KSZ8081RNB section for details.
CONFIG1
Ipd/O
LED Output: Programmable LED0 Output.
Config Mode: Latched as auto-negotiation enable (Regis-
ter 0h, Bit [12]) at the de-assertion of reset.
See the Strap-in Options – KSZ8081RNB section for
details.
The LED0 pin is programmable using Register 1Fh bits
[5:4], and is defined as follows:
LED Mode = [00]
Link/Activity
No link
Pin State
High
LED Definition
OFF
LED0/
NWAYEN
30
Ipu/O
Link
Low
ON
Activity
Toggle
Blinking
LED Mode = [01]
Link
Pin State
High
LED Definition
No link
Link
OFF
ON
Low
LED Mode = [10], [11] Reserved
LED Output: Programmable LED1 Output.
Config Mode: Latched as Speed (Register 0h, Bit [13]) at
the de-assertion of reset.
See the Strap-in Options – KSZ8081RNB section for
details.
The LED1 pin is programmable using Register 1Fh bits
[5:4], and is defined as follows:
LED Mode = [00]
Speed
Pin State
High
LED Definition
31
LED1/ SPEED
Ipu/O
10Base-T
100Base-TX
OFF
ON
Low
LED Mode = [01]
Activity
Pin State
High
LED Definition
OFF
No activity
Activity
Toggle
Blinking
LED Mode = [10], [11] Reserved
Chip Reset (active low).
Ground.
32
PADDLE
Note 2-1
RST#
GND
Ipu
GND
P = Power supply. GND = Ground. I = Input. O = Output. I/O = Bi-directional. Ipu = Input with internal
pull-up (see Electrical Characteristics for value). Ipu/O = Input with internal pull-up (see Electrical
Characteristics for value) during power-up/reset; output pin otherwise. Ipd/O = Input with internal pull-
down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise. Ipu/Opu
DS00002202A-page 12
2016 Microchip Technology Inc.
KSZ8081MNX/RNB
= Input with internal pull-up (see Electrical Characteristics for value) and output with internal pull-up
(see Electrical Characteristics for value). NC = Pin is not bonded to the die.
Note 2-2
Note 2-3
RMII RX Mode: The RXD[1:0] bits are synchronous with the 50 MHz RMII Reference Clock. For each
clock period in which CRS_DV is asserted, two bits of recovered data are sent by the PHY to the
MAC.
RMII TX Mode: The TXD[1:0] bits are synchronous with the 50MHz RMII Reference Clock. For each
clock period in which TXEN is asserted, two bits of data are received by the PHY from the MAC.
2016 Microchip Technology Inc.
DS00002202A-page 13
KSZ8081MNX/RNB
STRAP-IN OPTIONS – KSZ8081RNB
The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC RMII receive input pins may drive
high/low during power-up or reset, and consequently cause the PHY strap-in pins on the RMII signals to be latched to
unintended high/low states. In this case, external pull-ups (4.7 kꢀ) or pull-downs (1.0 kꢀ) should be added on these
PHY strap-in pins to ensure that the intended values are strapped-in correctly.
TABLE 2-4:
STRAP-IN OPTIONS
Type
Pin
Number
Pin Name
(Note
2-1)
Pin Function
PHYAD[2:0] is latched at de-assertion of reset and is configurable to any value
from 0 to 7 with PHY Address 1 as the default value.
PHY Address 0 is assigned by default as the broadcast PHY address, but it can
be assigned as a unique PHY address after pulling the
B-CAST_OFF strapping pin high or writing a ‘1’ to Register 16h, Bit [9].
PHY Address bits [4:3] are set to 00 by default.
15
14
13
PHYAD2
PHYAD1
PHYAD0
Ipd/O
Ipd/O
Ipu/O
The CONFIG[2:0] strap-in pins are latched at the de-assertion of reset.
CONFIG[2:0]
Mode
18
29
28
CONFIG2
CONFIG1
CONFIG0
Ipd/O
Ipd/O
Ipd/O
001
RMII
101
RMII back-to-back
Reserved – not used
000, 010 – 100, 110, 111
Isolate mode
Pull-up = Enable
Pull-down (default) = Disable
At the de-assertion of reset, this pin value is latched into Register 0h, Bit [10].
20
31
ISO
Ipd/O
Ipu/O
Speed mode
Pull-up (default) = 100 Mbps
Pull-down = 10 Mbps
At the de-assertion of reset, this pin value is latched into Register 0h, Bit [13] as
the speed select, and also is latched into Register 4h (auto-negotiation adver-
tisement) as the speed capability support.
SPEED
Duplex mode
Pull-up (default) = Half-duplex
Pull-down = Full-duplex
At the de-assertion of reset, this pin value is latched into Register 0h, Bit [8].
16
30
DUPLEX
NWAYEN
Ipu/O
Ipu/O
Nway auto-negotiation enable
Pull-up (default) = Enable auto-negotiation
Pull-down = Disable auto-negotiation
At the de-assertion of reset, this pin value is latched into Register 0h, Bit [12].
Broadcast off – for PHY Address 0
Pull-up = PHY Address 0 is set as an unique PHY address
Pull-down (default) = PHY Address 0 is set as a broadcast PHY address
At the de-assertion of reset, this pin value is latched by the chip.
19
B-CAST_OFF Ipd/O
NAND tree mode
Ipu/
NAND_Tree#
Opu
Pull-up (default) = Disable
Pull-down = Enable
21
At the de-assertion of reset, this pin value is latched by the chip.
Note 2-1
Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset;
output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset;
output pin otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) and output with internal
pull-up (see Electrical Characteristics for value).
DS00002202A-page 14
2016 Microchip Technology Inc.
KSZ8081MNX/RNB
3.0
3.1
FUNCTIONAL DESCRIPTION
10BASE-T/100BASE-TX Transceiver
The KSZ8081 is an integrated single 3.3V supply Fast Ethernet transceiver. It is fully compliant with the IEEE 802.3
Specification, and reduces board cost and simplifies board layout by using on-chip termination resistors for the two dif-
ferential pairs and by integrating the regulator to supply the 1.2V core.
On the copper media side, the KSZ8081 supports 10BASE-T and 100BASE-TX for transmission and reception of data
over a standard CAT-5 unshielded twisted pair (UTP) cable, and HP Auto MDI/MDI–X for reliable detection of and cor-
rection for straight-through and crossover cables.
On the MAC processor side, the KSZ8081MNX offers the Media Independent Interface (MII) and the KSZ8081RNB
offers the Reduced Media Independent Interface (RMII) for direct connection with MII and RMII compliant Ethernet MAC
processors and switches, respectively.
The MII management bus option gives the MAC processor complete access to the KSZ8081 control and status regis-
ters. Additionally, an interrupt pin eliminates the need for the processor to poll for PHY status change.
The KSZ8081MNX/RNB is used to refer to both KSZ8081MNX and KSZ8081RNB versions in this datasheet.
3.1.1
100BASE-TX TRANSMIT
The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B encoding, scrambling, NRZ-to-NRZI
conversion, and MLT3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125 MHz serial
bit stream. The data and control stream is then converted into 4B/5B coding and followed by a scrambler. The serialized
data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is
set by an external 6.49 kΩ 1% resistor for the 1:1 transformer ratio.
The output signal has a typical rise/fall time of 4 ns and complies with the ANSI TP-PMD standard regarding amplitude
balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output is also incorporated into the 100BASE-TX
transmitter.
3.1.2
100BASE-TX RECEIVE
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted
pair cable. Because the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust
its characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on
comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization.
This is an ongoing process and self-adjusts against environmental changes such as temperature variations.
Next, the equalized signal goes through a DC-restoration and data-conversion block. The DC-restoration circuit com-
pensates for the effect of baseline wander and improves the dynamic range. The differential data-conversion circuit con-
verts MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock-recovery circuit extracts the 125 MHz clock from the edges of the NRZI signal. This recovered clock is then
used to convert the NRZI signal to NRZ format. This signal is sent through the de-scrambler, then the 4B/5B decoder.
Finally, the NRZ serial data is converted to MII format and provided as the input data to the MAC.
3.1.3
SCRAMBLER/DE-SCRAMBLER (100BASE-TX ONLY)
The scrambler spreads the power spectrum of the transmitted signal to reduce electromagnetic interference (EMI) and
baseline wander. The de-scrambler recovers the scrambled signal.
3.1.4
10BASE-T TRANSMIT
The 10BASE-T drivers are incorporated with the 100BASE-TX drivers to allow for transmission using the same mag-
netic. The drivers perform internal wave shaping and pre-emphasis, and output 10BASE-T signals with a typical ampli-
tude of 2.5V peak. The 10BASE-T signals have harmonic contents that are at least 27 dB below the fundamental
frequency when driven by an all-ones Manchester-encoded signal.
2016 Microchip Technology Inc.
DS00002202A-page 15
KSZ8081MNX/RNB
3.1.5
10BASE-T RECEIVE
On the receive side, input buffer and level detecting squelch circuits are used. A differential input receiver circuit and a
phase-locked loop (PLL) performs the decoding function. The Manchester-encoded data stream is separated into clock
signal and NRZ data. A squelch circuit rejects signals with levels less than 400 mV, or with short pulse widths, to prevent
noise at the RXP and RXM inputs from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL
locks onto the incoming signal and the KSZ8081MNX/RNB decodes a data frame. The receive clock is kept active
during idle periods between data receptions.
3.1.6
SQE AND JABBER FUNCTION (10BASE-T ONLY)
In 10BASE-T operation, a short pulse is put out on the COL pin after each frame is transmitted. This SQE test is needed
to test the 10BASE-T transmit/receive path. If transmit enable (TXEN) is high for more than 20 ms (jabbering), the
10BASE-T transmitter is disabled and COL is asserted high. If TXEN is then driven low for more than 250 ms, the
10BASE-T transmitter is re-enabled and COL is de-asserted (returns to low).
3.1.7
PLL CLOCK SYNTHESIZER
The KSZ8081MNX/RNB generates all internal clocks and all external clocks for system timing from an external 25 MHz
crystal, oscillator, or reference clock. For the KSZ8081RNB in RMII 50 MHz clock mode, these clocks are generated
from an external 50 MHz oscillator or system clock.
3.1.8
AUTO-NEGOTIATION
The KSZ8081MNX/RNB conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3 Specification.
Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation.
During auto-negotiation, link partners advertise capabilities across the UTP link to each other and then compare their
own capabilities with those they received from their link partners. The highest speed and duplex setting that is common
to the two link partners is selected as the mode of operation.
The following list shows the speed and duplex operation mode from highest to lowest priority.
• Priority 1: 100BASE-TX, full–duplex
• Priority 2: 100BASE-TX, half–duplex
• Priority 3: 10BASE-T, full–duplex
• Priority 4: 10BASE-T, half–duplex
If auto-negotiation is not supported or the KSZ8081MNX/RNB link partner is forced to bypass auto-negotiation, then the
KSZ8081MNX/RNB sets its operating mode by observing the signal at its receiver. This is known as parallel detection,
which allows the KSZ8081MNX/RNB to establish a link by listening for a fixed signal protocol in the absence of the auto-
negotiation advertisement protocol.
Auto-negotiation is enabled by either hardware pin strapping (NWAYEN, Pin 42) or software (Register 0h, Bit [12]).
By default, auto-negotiation is enabled after power-up or hardware reset. After that, auto-negotiation can be enabled or
disabled by Register 0h, Bit [12]. If auto-negotiation is disabled, the speed is set by Register 0h, Bit [13], and the duplex
is set by Register 0h, Bit [8].
The auto-negotiation link-up process is shown in Figure 3-1.
DS00002202A-page 16
2016 Microchip Technology Inc.
KSZ8081MNX/RNB
FIGURE 3-1:
AUTO-NEGOTIATION FLOW CHART
START AUTO-NEGOTIATION
PARALLEL
OPERATION
FORCE LINK SETTING
YES
NO
ATTEMPT AUTO-
NEGOTIATION
LISTEN FOR 100BASE-TX
IDLES
LISTEN FOR 10BASE-T
LINK PULSES
BYPASS AUTO-NEGOTIATION
AND SET LINK MODE
NO
JOIN FLOW
LINK MODE SET?
YES
LINK MODE SET
3.2
MII Interface (KSZ8081MNX Only)
The Media Independent Interface (MII) is compliant with the IEEE 802.3 Specification. It provides a common interface
between MII PHYs and MACs, and has the following key characteristics:
• Pin count is 15 pins (6 pins for data transmission, 7 pins for data reception, and 2 pins for carrier and collision
indication).
• 10 Mbps and 100 Mbps data rates are supported at both half- and full-duplex.
• Data transmission and reception are independent and belong to separate signal groups.
• Transmit data and receive data are each 4 bits wide, a nibble.
By default, the KSZ8081MNX is configured to MII mode after it is powered up or hardware reset with the following:
A 25 MHz crystal connected to XI, XO (pins 9, 8), or an external 25 MHz clock source (oscillator) connected to XI.
The CONFIG[2:0] strapping pins (pins 18, 29, 28) set to 000 (default setting).
2016 Microchip Technology Inc.
DS00002202A-page 17
KSZ8081MNX/RNB
3.2.1
MII SIGNAL DEFINITION
Table 3-1 describes the MII signals. Refer to Clause 22 of the IEEE 802.3 Specification for detailed information.
TABLE 3-1:
MII SIGNAL DEFINITION
Direction
(with respect to PHY,
Direction
(with respect to MAC)
MII Signal Name
Description
KSZ8081MNX
signal)
Transmit Clock
(2.5 MHz for 10 Mbps; 25 MHz for 100 Mbps)
TXC
Output
Input
TXEN
Input
Input
Output
Output
Transmit Enable
TXD[3:0]
Transmit Data[3:0]
Receive Clock
(2.5 MHz for 10 Mbps; 25 MHz for 100 Mbps)
RXC
Output
Input
RXDV
RXD[3:0]
RXER
CRS
Output
Output
Output
Output
Output
Input
Input
Receive Data Valid
Receive Data[3:0]
Input, or (not required) Receive Error
Input
Input
Carrier Sense
COL
Collision Detection
3.2.2
TRANSMIT CLOCK (TXC)
TXC is sourced by the PHY. It is a continuous clock that provides the timing reference for TXEN and TXD[3:0]. TXC is
2.5 MHz for 10 Mbps operation and 25 MHz for 100 Mbps operation.
3.2.3
TRANSMIT ENABLE (TXEN)
TXEN indicates that the MAC is presenting nibbles on TXD[3:0] for transmission. It is asserted synchronously with the
first nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the MII. It is
negated before the first TXC following the final nibble of a frame.
TXEN transitions synchronously with respect to TXC.
3.2.4
TRANSMIT DATA[3:0] (TXD[3:0])
TXD[3:0] transitions synchronously with respect to TXC. When TXEN is asserted, TXD[3:0] are accepted by the PHY
for transmission. TXD[3:0] is 00 to indicate idle when TXEN is de-asserted. Values other than 00 on TXD[3:0] while
TXEN is de-asserted are ignored by the PHY.
3.2.5
RECEIVE CLOCK (RXC)
RXC provides the timing reference for RXDV, RXD[3:0], and RXER.
• In 10 Mbps mode, RXC is recovered from the line while the carrier is active. RXC is derived from the PHY’s refer-
ence clock when the line is idle or the link is down.
• In 100 Mbps mode, RXC is continuously recovered from the line. If the link is down, RXC is derived from the
PHY’s reference clock.
RXC is 2.5 MHz for 10 Mbps operation and 25 MHz for 100 Mbps operation.
3.2.6
RECEIVE DATA VALID (RXDV)
RXDV is driven by the PHY to indicate that the PHY is presenting recovered and decoded nibbles on RXD[3:0].
• In 10 Mbps mode, RXDV is asserted with the first nibble of the start-of-frame delimiter (SFD), 5D, and remains
asserted until the end of the frame.
• In 100 Mbps mode, RXDV is asserted from the first nibble of the preamble to the last nibble of the frame.
RXDV transitions synchronously with respect to RXC.
DS00002202A-page 18
2016 Microchip Technology Inc.
KSZ8081MNX/RNB
3.2.7
RECEIVE DATA[3:0] (RXD[3:0])
RXD[3:0] transitions synchronously with respect to RXC. For each clock period in which RXDV is asserted, RXD[3:0]
transfers a nibble of recovered data from the PHY.
3.2.8
RECEIVE ERROR (RXER)
RXER is asserted for one or more RXC periods to indicate that a symbol error (for example, a coding error that a PHY
can detect that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame being
transferred from the PHY.
RXER transitions synchronously with respect to RXC. While RXDV is de-asserted, RXER has no effect on the MAC.
3.2.9
CARRIER SENSE (CRS)
CRS is asserted and de-asserted as follows:
• In 10 Mbps mode, CRS assertion is based on the reception of valid preambles. CRS de-assertion is based on the
reception of an end-of-frame (EOF) marker.
• In 100 Mbps mode, CRS is asserted when a start-of-stream delimiter or /J/K symbol pair is detected. CRS is de-
asserted when an end-of-stream delimiter or /T/R symbol pair is detected. Additionally, the PMA layer de-asserts
CRS if IDLE symbols are received without /T/R.
3.2.10
COLLISION (COL)
COL is asserted in half-duplex mode whenever the transmitter and receiver are simultaneously active on the line. This
informs the MAC that a collision has occurred during its transmission to the PHY. COL transitions asynchronously with
respect to TXC and RXC.
3.2.11
MII SIGNAL DIAGRAM
The KSZ8081MNX MII pin connections to the MAC are shown in Figure 3-2.
FIGURE 3-2:
KSZ8081MNX MII INTERFACE
TXC
TX_EN
TXC
TX_EN
TXD[3:0]
TXD[3:0]
RXC
RXC
RXDV
RXDV
RXD[3:0]
RXER
RXD[3:0]
RXER
CRS
COL
CRS
COL
2016 Microchip Technology Inc.
DS00002202A-page 19
KSZ8081MNX/RNB
3.3
RMII Data Interface (KSZ8081RNB Only)
The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). It pro-
vides a common interface between physical layer and MAC layer devices, and has the following key characteristics:
• Pin count is 8 pins (3 pins for data transmission, 4 pins for data reception, and 1 pin for the 50 MHz reference
clock).
• 10 Mbps and 100 Mbps data rates are supported at both half- and full-duplex.
• Data transmission and reception are independent and belong to separate signal groups.
• Transmit data and receive data are each 2 bits wide, a dibit.
3.3.1
RMII – 25 MHZ CLOCK MODE
The KSZ8081RNB is configured to RMII – 25 MHz clock mode after it is powered up or hardware reset with the following:
• A 25 MHz crystal connected to XI, XO (pins 9, 8), or an external 25 MHz clock source (oscillator) connected to XI.
• The CONFIG[2:0] strapping pins (pins 18, 29, 28) set to 001.
• Register 1Fh, Bit [7] is set to 0 (default value) to select 25 MHz clock mode.
3.3.2
RMII – 50 MHZ CLOCK MODE
The KSZ8081RNB is configured to RMII – 50 MHz clock mode after it is powered up or hardware reset with the following:
• An external 50 MHz clock source (oscillator) connected to XI (Pin 9).
• The CONFIG[2:0] strapping pins (pins 18, 29, 28) set to 001.
• Register 1Fh, Bit [7] is set to 1 to select 50 MHz clock mode.
3.3.3
RMII SIGNAL DEFINITION
Table 3-2 describes the RMII signals. Refer to RMII Specification v1.2 for detailed information.
TABLE 3-2:
RMII SIGNAL DEFINITION
Direction
Direction
(with respect to MAC)
MII Signal Name
(with respect to PHY,
KSZ8081MNX signal)
Description
Transmit Clock
TXC
Output
Input
(2.5 MHz for 10 Mbps;
25 MHz for 100 Mbps)
TXEN
Input
Input
Output
Output
Transmit Enable
TXD[3:0]
Transmit Data[3:0]
Receive Clock
RXC
Output
Input
(2.5 MHz for 10 Mbps;
25 MHz for 100 Mbps)
RXDV
Output
Output
Input
Input
Receive Data Valid
Receive Data[3:0]
RXD[3:0]
3.3.4
REFERENCE CLOCK (REF_CLK)
REF_CLK is a continuous 50 MHz clock that provides the timing reference for TXEN, TXD[1:0], CRS_DV, RXD[1:0],
and RX_ER.
For 25 MHz clock mode, the KSZ8081RNB generates and outputs the 50 MHz RMII REF_CLK to the MAC at REF_CLK
(Pin 19).
For 50 MHz clock mode, the KSZ8081RNB takes in the 50 MHz RMII REF_CLK from the MAC or system board at XI
(Pin 9) and leaves the REF_CLK (Pin 19) as a no connect.
DS00002202A-page 20
2016 Microchip Technology Inc.
KSZ8081MNX/RNB
3.3.5
TRANSMIT ENABLE (TXEN)
TXEN indicates that the MAC is presenting dibits on TXD[1:0] for transmission. It is asserted synchronously with the first
dibit of the preamble and remains asserted while all dibits to be transmitted are presented on the RMII. It is negated
before the first REF_CLK following the final dibit of a frame.
TXEN transitions synchronously with respect to REF_CLK.
3.3.6
TRANSMIT DATA[1:0] (TXD[1:0])
TXD[1:0] transitions synchronously with respect to REF_CLK. When TXEN is asserted, the PHY accepts TXD[1:0] for
transmission.
TXD[1:0] is 00 to indicate idle when TXEN is de-asserted. The PHY ignores values other than 00 on TXD[1:0] while
TXEN is de-asserted.
3.3.7
CARRIER SENSE/RECEIVE DATA VALID (CRS_DV)
The PHY asserts CRS_DV when the receive medium is non-idle. It is asserted asynchronously when a carrier is
detected. This happens when squelch is passed in 10 Mbps mode, and when two non-contiguous 0s in 10 bits are
detected in 100 Mbps mode. Loss of carrier results in the de-assertion of CRS_DV.
While carrier detection criteria are met, CRS_DV remains asserted continuously from the first recovered dibit of the
frame through the final recovered dibit. It is negated before the first REF_CLK that follows the final dibit. The data on
RXD[1:0] is considered valid after CRS_DV is asserted. However, because the assertion of CRS_DV is asynchronous
relative to REF_CLK, the data on RXD[1:0] is 00 until receive signals are properly decoded.
3.3.8
RECEIVE DATA[1:0] (RXD[1:0])
RXD[1:0] transitions synchronously with respect to REF_CLK. For each clock period in which CRS_DV is asserted,
RXD[1:0] transfers two bits of recovered data from the PHY.
RXD[1:0] is 00 to indicate idle when CRS_DV is de-asserted. The MAC ignores values other than 00 on RXD[1:0] while
CRS_DV is de-asserted.
3.3.9
RECEIVE ERROR (RXER)
RXER is asserted for one or more REF_CLK periods to indicate that a symbol error (for example, a coding error that a
PHY can detect that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame being
transferred from the PHY.
RXER transitions synchronously with respect to REF_CLK. . While CRS_DV is de-asserted, RXER has no effect on the
MAC.
3.3.10
COLLISION DETECTION (COL)
The MAC regenerates the COL signal of the MII from TXEN and CRS_DV.
3.3.11
RMII SIGNAL DIAGRAM
The KSZ8081RNB RMII pin connections to the MAC for 25 MHz clock mode are shown in Figure 3-3. The connections
for 50 MHz clock mode are shown in Figure 3-4.
2016 Microchip Technology Inc.
DS00002202A-page 21
KSZ8081MNX/RNB
FIGURE 3-3:
KSZ8081RNB RMII INTERFACE (25 MHZ CLOCK MODE)
RMII MAC
KSZ8081RNB
CRS_DV
RXD[1:0]
RXER
CRS_DV
RXD[1:0]
RX_ER
TXEN
TX_EN
TXD[1:0]
TXD[1:0]
REF_CLK
REF_CLK
XI
XO
25MHz
XTAL
22pF
22pF
FIGURE 3-4:
KSZ8081RNB RMII INTERFACE (50 MHZ CLOCK MODE)
RMII MAC
KSZ8081RNB
CRS_DV
RXD[1:0]
RXER
CRS_DV
RXD[1:0]
RX_ER
TXEN
TX_EN
TXD[1:0]
TXD[1:0]
REF_CLK
XI
50MHz
OSC
DS00002202A-page 22
2016 Microchip Technology Inc.
KSZ8081MNX/RNB
3.4
Back-to-Back Mode – 100 Mbps Copper Repeater
Two KSZ8081MNX/RNB devices can be connected back-to-back to form a 100BASE-TX copper repeater.
FIGURE 3-5:
KSZ8081MNX/RNB TO KSZ8081MNX/RNB BACK-TO-BACK COPPER
REPEATER
RxD
RXP/RXM
TXP/TXM
KSZ8081MNX/RNB
(COPPER MODE)
TxD
25MHz/
50MHz
XI
OSC
XI
KSZ8081MNX/RNB
(COPPER MODE)
TXP/TXM
RXP/RXM
TxD
RxD
3.4.1
MII BACK-TO-BACK MODE (KSZ8081MNX ONLY)
In MII back-to-back mode, a KSZ8081MNX interfaces with another KSZ8081MNX to provide a complete 100 Mbps
copper repeater solution.
The KSZ8081MNX devices are configured to MII back-to-back mode after power-up or reset with the following:
• Strapping pin CONFIG[2:0] (Pins 18, 29, 28) set to 110
• A common 25 MHz reference clock connected to XI (Pin 9) of both KSZ8081MNX devices
• MII signals connected as shown in Table 3-3.
TABLE 3-3:
MII SIGNAL CONNECTION FOR MII BACK-TO-BACK MODE (100BASE-TX COPPER
REPEATER)
KSZ8081MNX (100BASE-TX copper)
KSZ8081MNX (100BASE-TX copper)
[Device 2]
[Device 1]
Pin Name
Pin Number
Pin Type
Pin Name
Pin Number
Pin Type
RXDV
RXD3
RXD2
RXD1
RXD0
TXEN
TXD3
TXD2
TXD1
TXD0
18
13
14
15
16
23
27
26
25
24
Output
Output
Output
Output
Output
Input
TXEN
TXD3
TXD2
TXD1
TXD0
RXDV
RXD3
RXD2
RXD1
RXD0
23
27
26
25
24
18
13
14
15
16
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Input
Input
Input
Input
2016 Microchip Technology Inc.
DS00002202A-page 23
KSZ8081MNX/RNB
3.5
MII Management (MIIM) Interface
The KSZ8081MNX/RNB supports the IEEE 802.3 MII management interface, also known as the Management Data
Input/Output (MDIO) interface. This interface allows an upper-layer device, such as a MAC processor, to monitor and
control the state of the KSZ8081MNX/RNB. An external device with MIIM capability is used to read the PHY status and/
or configure the PHY settings. More details about the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3
Specification.
The MIIM interface consists of the following:
• A physical connection that incorporates the clock line (MDC) and the data line (MDIO).
• A specific protocol that operates across the physical connection mentioned earlier, which allows the external
controller to communicate with one or more PHY devices.
• A set of 16-bit MDIO registers. Registers [0:8] are standard registers, and their functions are defined in the IEEE
802.3 Specification. The additional registers are provided for expanded functionality. See the “Register Map”
section for details.
As the default, the KSZ8081MNX/RNB supports unique PHY addresses 1 to 7, and broadcast PHY address 0. The latter
is defined in the IEEE 802.3 Specification, and can be used to read/write to a single KSZ8081MNX/RNB device, or write
to multiple KSZ8081MNX/RNB devices simultaneously.
PHY address 0 can optionally be disabled as the broadcast address by either hardware pin strapping (B-CAST_OFF,
Pin 19) or software (Register 16h, Bit [9]), and assigned as a unique PHY address.
The PHYAD[2:0] strapping pins are used to assign a unique PHY address between 0 and 7 to each KSZ8081MNX/RNB
device.
The MIIM interface can operates up to a maximum clock speed of 10 MHz MAC clock.
Table 3-4 shows the MII management frame format for the KSZ8081MNX/RNB.
TABLE 3-4:
MII MANAGEMENT FRAME FORMAT FOR THE KSZ8081MNX/RNB
Read/
Write OP
Code
PHY
Address
Bits [4:0] Bits [4:0]
REG
Address TA
Start of
Frame
Data
Bits [15:0]
Preamble
Idle
Read
Write
32 1’s
32 1’s
01
01
10
01
00AAA
00AAA
RRRRR
RRRRR
Z0 DDDDDDDD_DDDDDDDD
10 DDDDDDDD_DDDDDDDD
Z
Z
3.6
Interrupt (INTRP)
INTRP (Pin 21) is an optional interrupt signal that is used to inform the external controller that there has been a status
update to the KSZ8081MNX/RNB PHY register. Bits [15:8] of Register 1Bh are the interrupt control bits to enable and
disable the conditions for asserting the INTRP signal. Bits [7:0] of Register 1Bh are the interrupt status bits to indicate
which interrupt conditions have occurred. The interrupt status bits are cleared after reading Register 1Bh.
Bit [9] of Register 1Fh sets the interrupt level to active high or active low. The default is active low.
The MII management bus option gives the MAC processor complete access to the KSZ8081MNX/RNB control and sta-
tus registers. Additionally, an interrupt pin eliminates the need for the processor to poll the PHY for status change.
3.7
HP Auto MDI/MDI-X
HP Auto MDI/MDI-X configuration eliminates the need to decide whether to use a straight cable or a crossover cable
between the KSZ8081MNX/RNB and its link partner. This feature allows the KSZ8081MNX/RNB to use either type of
cable to connect with a link partner that is in either MDI or MDI-X mode. The auto-sense function detects transmit and
receive pairs from the link partner and assigns transmit and receive pairs to the KSZ8081MNX/RNB accordingly.
HP Auto MDI/MDI-X is enabled by default. It is disabled by writing a ‘1’ to Register 1Fh, Bit [13]. MDI and MDI-X mode
is selected by Register 1Fh, Bit [14] if HP Auto MDI/MDI-X is disabled.
An isolation transformer with symmetrical transmit and receive data paths is recommended to support Auto MDI/MDI-X.
Table 3-5 shows how the IEEE 802.3 Standard defines MDI and MDI-X.
DS00002202A-page 24
2016 Microchip Technology Inc.
KSZ8081MNX/RNB
TABLE 3-5:
MDI/MDI-X PIN DEFINITION
MDI
MDI-X
RJ-45 Pin
Signal
RJ-45 Pin
Signal
1
2
3
6
TX+
TX–
RX+
RX–
1
2
3
6
RX+
RX–
TX+
TX–
3.7.1
STRAIGHT CABLE
A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 3-6 shows
a typical straight cable connection between a NIC card (MDI device) and a switch or hub (MDI-X device).
FIGURE 3-6:
TYPICAL STRAIGHT CABLE CONNECTION
10/100 ETHERNET
MEDIA DEPENDENT INTERFACE
10/100 ETHERNET
MEDIA DEPENDENT INTERFACE
1
1
TRANSMIT PAIR
RECEIVE PAIR
2
2
3
STRAIGHT
CABLE
3
4
4
RECEIVE PAIR
5
TRANSMIT PAIR
5
6
7
8
6
7
8
MODULAR CONNECTOR
(RJ-45)
MODULAR CONNECTOR
(RJ-45)
NIC
HUB
(REPEATER OR SWITCH)
3.7.2
CROSSOVER CABLE
A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device.
Figure 3-7 shows a typical crossover cable connection between two switches or hubs (two MDI-X devices).
FIGURE 3-7:
TYPICAL CROSSOVER CABLE CONNECTION
10/100 ETHERNET
MEDIA DEPENDENT INTERFACE
10/100 ETHERNET
MEDIA DEPENDENT INTERFACE
1
1
CROSSOVER
CABLE
RECEIVE PAIR
2
RECEIVE PAIR
2
3
3
4
4
TRANSMIT PAIR
5
TRANSMIT PAIR
5
6
7
8
6
7
8
MODULAR CONNECTOR
MODULAR CONNECTOR
(RJ-45)
HUB
(RJ-45)
HUB
(REPEATER OR SWITCH)
(REPEATER OR SWITCH)
2016 Microchip Technology Inc.
DS00002202A-page 25
KSZ8081MNX/RNB
3.8
Loopback Mode
The KSZ8081MNX/RNB supports the following loopback operations to verify analog and/or digital data paths.
• Local (digital) loopback
• Remote (analog) loopback
3.8.1
LOCAL (DIGITAL) LOOPBACK
This loopback mode checks the MII/RMII transmit and receive data paths between the KSZ8081MNX/RNB and the
external MAC, and is supported for both speeds (10 Mbps/100 Mbps) at full-duplex.
The loopback data path is shown in Figure 3-8.
1. The MII/RMII MAC transmits frames to the KSZ8081MNX/RNB.
2. Frames are wrapped around inside the KSZ8081MNX/RNB.
3. The KSZ8081MNX/RNB transmits frames back to the MII/RMII MAC.
4. Except the frames back to the RMII MAC, the transmit frames also go out from the copper port.
FIGURE 3-8:
LOCAL (DIGITAL) LOOPBACK
KSZ8081MNX/RNB
AFE
PCS
MII/
RMII
MII/RMII
MAC
(ANALOG)
(DIGITAL)
The following programming action and register settings are used for local loopback mode.
For 10 Mbps/100 Mbps loopback,
•Set Register 0h,
Bit [14] = 1
Bit [13] = 0/1
Bit [12] = 0
Bit [8] = 1
// Enable local loopback mode
// Select 10 Mbps/100 Mbps speed
// Disable auto-negotiation
// Select full-duplex mode
The following steps should be applied if unwanted frames appear outside the copper port in the local feedback.
1. Set register 1Fh bit [3] to ‘1’ to disable the transmitter.
2. Run local loopback test as above.
3. Set register 1Fh bit [3] to ‘0’ to enable the transmitter.
DS00002202A-page 26
2016 Microchip Technology Inc.
KSZ8081MNX/RNB
3.8.2
REMOTE (ANALOG) LOOPBACK
This loopback mode checks the line (differential pairs, transformer, RJ-45 connector, Ethernet cable) transmit and
receive data paths between the KSZ8081MNX/RNB and its link partner, and is supported for 100BASE-TX full-duplex
mode only.
The loopback data path is shown in Figure 3-9.
1. The Fast Ethernet (100BASE-TX) PHY link partner transmits frames to the KSZ8081MNX/RNB.
2. Frames are wrapped around inside the KSZ8081MNX/RNB.
3. The KSZ8081MNX/RNB transmits frames back to the Fast Ethernet (100BASE-TX) PHY link partner.
FIGURE 3-9:
REMOTE (ANALOG) LOOPBACK
KSZ8081MNX/RNB
AFE
(ANALOG)
PCS
(DIGITAL)
MII/
RMII
RJ-45
CAT-5
(UTP)
100BASE-TX
LINK PARTNER
RJ-45
The following programming steps and register settings are used for remote loopback mode.
1.Set Register 0h,
Bits [13] = 1
Bit [12] = 0
Bit [8] = 1
// Select 100 Mbps speed
// Disable auto-negotiation
// Select full-duplex mode
or just auto-negotiate and link up at 100BASE-TX full-duplex mode with the link partner.
2.Set Register 1Fh,
Bit [2] = 1
// Enable remote loopback mode
2016 Microchip Technology Inc.
DS00002202A-page 27
KSZ8081MNX/RNB
®
3.9
LinkMD Cable Diagnostic
The LinkMD function uses time-domain reflectometry (TDR) to analyze the cabling plant for common cabling problems.
These include open circuits, short circuits, and impedance mismatches.
LinkMD works by sending a pulse of known amplitude and duration down the MDI or MDI-X pair, then analyzing the
shape of the reflected signal to determine the type of fault. The time duration for the reflected signal to return provides
the approximate distance to the cabling fault. The LinkMD function processes this TDR information and presents it as
a numerical value that can be translated to a cable distance.
LinkMD is initiated by accessing Register 1Dh, the LinkMD Control/Status register, in conjunction with Register 1Fh, the
PHY Control 2 register. The latter register is used to disable Auto MDI/MDI-X and to select either MDI or MDI-X as the
cable differential pair for testing.
3.9.1
USAGE
The following is a sample procedure for using LinkMD with Registers 1Dh and 1Fh:
1. Disable auto MDI/MDI-X by writing a ‘1’ to Register 1Fh, bit [13].
2. Start cable diagnostic test by writing a ‘1’ to Register 1Dh, bit [15]. This enable bit is self-clearing.
3. Wait (poll) for Register 1Dh, bit [15] to return a ‘0’, and indicating cable diagnostic test is completed.
4. Read cable diagnostic test results in Register 1Dh, bits [14:13]. The results are as follows:
00 = normal condition (valid test)
01 = open condition detected in cable (valid test)
10 = short condition detected in cable (valid test)
11 = cable diagnostic test failed (invalid test)
The ‘11’ case, invalid test, occurs when the device is unable to shut down the link partner. In this instance, the test
is not run, since it would be impossible for the device to determine if the detected signal is a reflection of the signal
generated or a signal from another source.
5. Get distance to fault by concatenating Register 1Dh, bits [8:0] and multiplying the result by a constant of 0.38.
The distance to the cable fault can be determined by the following formula:
D (distance to cable fault) = 0.38 x (Register 1Dh, bits [8:0])
D (distance to cable fault) is expressed in meters.
Concatenated value of Registers 1Dh bits [8:0] should be converted to decimal before multiplying by 0.38.
The constant (0.38) may be calibrated for different cabling conditions, including cables with a velocity of propaga-
tion that varies significantly from the norm.
3.10 NAND Tree Support
The KSZ8081MNX/RNB provides parametric NAND tree support for fault detection between chip I/Os and board. The
NAND tree is a chain of nested NAND gates in which each KSZ8081MNX/RNB digital I/O (NAND tree input) pin is an
input to one NAND gate along the chain. At the end of the chain, the TXD1 pin provides the output for the nested NAND
gates.
The NAND tree test process includes:
• Enabling NAND tree mode
• Pulling all NAND tree input pins high
• Driving each NAND tree input pin low, sequentially, according to the NAND tree pin order
• Checking the NAND tree output to make sure there is a toggle high-to-low or low-to-high for each NAND tree input
driven low
Table 3-6 and Table 3-7 list the NAND tree pin orders for KSZ8081MNX and KSZ8081RNB, respectively.
DS00002202A-page 28
2016 Microchip Technology Inc.
KSZ8081MNX/RNB
TABLE 3-6:
NAND TREE TEST PIN ORDER FOR KSZ8081MNX
Pin Number
Pin Name
NAND Tree Description
11
12
15
16
18
19
21
23
30
24
25
MDIO
MDC
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
RXD1
RXD0
CRS_DV
REF_CLK
INTRP
TXEN
LED0
TXD0
TXD1
Note 3-1
KS8081MNX supports partial NAND tree test pins. Table 3-6 lists partial NAND tree test pins. If full
NAND tree testing is required, please use KSZ8091MNX device that supports all the required pins.
TABLE 3-7:
NAND TREE TEST PIN ORDER FOR KSZ8081RNB
Pin Number
Pin Name
NAND Tree Description
11
12
15
16
18
19
21
23
31
30
24
25
MDIO
MDC
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
RXD1
RXD0
CRS_DV
REF_CLK
INTRP
TXEN
LED1
LED0
TXD0
TXD1
3.10.1
NAND TREE I/O TESTING
Use the following procedure to check for faults on the KSZ8081MNX/RNB digital I/O pin connections to the board:
1. Enable NAND tree mode using either hardware (NAND_Tree#, Pin 21) or software (Register 16h, Bit [5]).
2. Use board logic to drive all KSZ8081MNX/RNB NAND tree input pins high.
3. Use board logic to drive each NAND tree input pin, in KSZ8081MNX/RNB NAND tree pin order, as follows:
a) Toggle the first pin (MDIO) from high to low, and verify that the TXD1 pin switches from high to low to indicate
that the first pin is connected properly.
b) Leave the first pin (MDIO) low.
c) Toggle the second pin (MDC) from high to low, and verify that the TXD1 pin switches from low to high to
indicate that the second pin is connected properly.
d) eave the first pin (MDIO) and the second pin (MDC) low.
e) Continue with this sequence until all KSZ8081MNX/RNB NAND tree input pins have been toggled.
2016 Microchip Technology Inc.
DS00002202A-page 29
KSZ8081MNX/RNB
Each KSZ8081MNX/RNB NAND tree input pin must cause the TXD1 output pin to toggle high-to-low or low-to-high to
indicate a good connection. If the TXD1 pin fails to toggle when the KSZ8081MNX/RNB input pin toggles from high to
low, the input pin has a fault.
3.11 Power Management
The KSZ8081MNX/RNB incorporates a number of power-management modes and features that provide methods to
consume less energy. These are discussed in the following sections.
3.11.1
POWER-SAVING MODE
Power-saving mode is used to reduce the transceiver power consumption when the cable is unplugged. It is enabled
by writing a ‘1’ to Register 1Fh, Bit [10], and is in effect when auto-negotiation mode is enabled and the cable is discon-
nected (no link).
In this mode, the KSZ8081MNX/RNB shuts down all transceiver blocks, except for the transmitter, energy detect, and
PLL circuits.
By default, power-saving mode is disabled after power-up.
3.11.2
ENERGY-DETECT POWER-DOWN MODE
Energy-detect power-down (EDPD) mode is used to further reduce transceiver power consumption when the cable is
unplugged. It is enabled by writing a ‘0’ to Register 18h, Bit [11], and is in effect when auto-negotiation mode is enabled
and the cable is disconnected (no link).
EDPD mode works with the PLL off (set by writing a ‘1’ to Register 10h, Bit [4] to automatically turn the PLL off in EDPD
mode) to turn off all KSZ8081MNX/RNB transceiver blocks except the transmitter and energy-detect circuits.
Power can be reduced further by extending the time interval between transmissions of link pulses to check for the pres-
ence of a link partner. The periodic transmission of link pulses is needed to ensure the KSZ8081MNX/RNB and its link
partner, when operating in the same low-power state and with Auto MDI/MDI-X disabled, can wake up when the cable
is connected between them.
By default, energy-detect power-down mode is disabled after power-up.
3.11.3
POWER-DOWN MODE
Power-down mode is used to power down the KSZ8081MNX/RNB device when it is not in use after power-up. It is
enabled by writing a ‘1’ to Register 0h, Bit [11].
In this mode, the KSZ8081MNX/RNB disables all internal functions except the MII management interface. The
KSZ8081MNX/RNB exits (disables) power-down mode after Register 0h, Bit [11] is set back to ‘0’.
3.11.4
SLOW-OSCILLATOR MODE
Slow-oscillator mode is used to disconnect the input reference crystal/clock on XI (Pin 8) and select the on-chip slow
oscillator when the KSZ8081MNX/RNB device is not in use after power-up. It is enabled by writing a ‘1’ to Register 11h,
Bit [5].
Slow-oscillator mode works in conjunction with power-down mode to put the KSZ8081MNX/RNB device in the lowest
power state, with all internal functions disabled except the MII management interface. To properly exit this mode and
return to normal PHY operation, use the following programming sequence:
1. Disable slow-oscillator mode by writing a ‘0’ to Register 11h, Bit [5].
2. Disable power-down mode by writing a ‘0’ to Register 0h, Bit [11].
3. Initiate software reset by writing a ‘1’ to Register 0h, Bit [15].
DS00002202A-page 30
2016 Microchip Technology Inc.
KSZ8081MNX/RNB
3.12 Reference Circuit for Power and Ground Connections
The KSZ8081MNX/RNB is a single 3.3V supply device with a built-in regulator to supply the 1.2V core. The power and
ground connections are shown in Figure 3-10 and Table 3-8 for 3.3V VDDIO.
FIGURE 3-10:
KSZ8081MNX/RNB POWER AND GROUND CONNECTIONS
2
2.2μF
0.1μF
VDD_1.2
FERRITE
BEAD
3
VDDA_3.3
22μF
0.1μF
KSZ8081MNX/RNB
3.3V
VDDIO
17
22μF
0.1μF
GND
PADDLE
1
TABLE 3-8:
KSZ8081MNX/RNB POWER PIN DESCRIPTIONS
Power Pin
Pin Number
Description
Decouple with 2.2 μF and 0.1 μF capacitors to ground.
VDD_1.2
2
Connect to board’s 3.3V supply through a ferrite bead.
Decouple with 22 μF and 0.1 μF capacitors to ground.
VDDA_3.3
VDDIO
3
Connect to board’s 3.3V supply for 3.3V VDDIO.
Decouple with 22 μF and 0.1 μF capacitors to ground.
17
2016 Microchip Technology Inc.
DS00002202A-page 31
KSZ8081MNX/RNB
3.13 Typical Current/Power Consumption
Table 3-9, Table 3-10 ,and Table 3-11 show typical values for current consumption by the transceiver (VDDA_3.3) and
digital I/O (VDDIO) power pins and typical values for power consumption by the KSZ8081MNX/RNB device for the indi-
cated nominal operating voltages. These current and power consumption values include the transmit driver current and
on-chip regulator current for the 1.2V core.
3.13.1
TRANSCEIVER (3.3V), DIGITAL I/OS (3.3V)
TABLE 3-9:
TYPICAL CURRENT/POWER CONSUMPTION (VDDA_3.3 = 3.3V, VDDIO = 3.3V)
3.3V Transceiver 3.3V Digital I/Os
Total Chip Power
(VDDA_3.3)
(VDDIO)
Condition
mA
mA
mW
100BASE-TX Link-up (no traffic)
34
34
15
27
15
11
12
12
10
10
10
10
152
142
74.5
114
100BASE-TX Full-duplex @ 100% utilization
10BASE-T Link-up (no traffic)
10BASE-T Full-duplex @ 100% utilization
Power-saving mode (Reg. 1Fh, Bit [10] = 1)
EDPD mode (Reg. 18h, Bit [11] = 0)
74.5
61.3
EDPD mode (Reg. 18h, Bit [11] = 0) and
PLL off (Reg. 10h, Bit [4] = 1)
3.55
2.29
1.15
1.35
1.34
0.29
15.1
10.9
4.52
Software power-down mode (Reg. 0h, Bit [11] =1)
Software power-down mode (Reg. 0h, Bit [11] =1) and
slow-oscillator mode (Reg. 11h, Bit [5] =1)
3.13.2
TRANSCEIVER (3.3V), DIGITAL I/OS (2.5V)
TABLE 3-10: TYPICAL CURRENT/POWER CONSUMPTION (VDDA_3.3 = 3.3V, VDDIO = 2.5V)
3.3V Transceiver 3.3V Digital I/Os
Total Chip Power
(VDDA_3.3)
(VDDIO)
Condition
mA
mA
mW
100BASE-TX Link-up (no traffic)
34
34
15
27
15
11
12
12
10
10
10
10
152
142
74.5
114
100BASE-TX Full-duplex @ 100% utilization
10BASE-T Link-up (no traffic)
10BASE-T Full-duplex @ 100% utilization
Power-saving mode (Reg. 1Fh, Bit [10] = 1)
EDPD mode (Reg. 18h, Bit [11] = 0)
74.5
61.3
EDPD mode (Reg. 18h, Bit [11] = 0) and
PLL off (Reg. 10h, Bit [4] = 1)
3.55
2.29
1.15
1.35
1.34
0.29
15.1
10.9
4.52
Software power-down mode (Reg. 0h, Bit [11] =1)
Software power-down mode (Reg. 0h, Bit [11] =1) and
slow-oscillator mode (Reg. 11h, Bit [5] =1)
DS00002202A-page 32
2016 Microchip Technology Inc.
KSZ8081MNX/RNB
3.13.3
TRANSCEIVER (3.3V), DIGITAL I/OS (1.8V)
TABLE 3-11: TYPICAL CURRENT/POWER CONSUMPTION (VDDA_3.3 = 3.3V, VDDIO = 1.8V)
3.3V Transceiver 1.8V Digital I/Os
Total Chip Power
(VDDA_3.3)
(VDDIO)
Condition
mA
mA
mW
100BASE-TX Link-up (no traffic)
34
34
15
27
15
11
11
12
132
134
65.7
105
65.7
52.5
100BASE-TX Full-duplex @ 100% utilization
10BASE-T Link-up (no traffic)
9.0
9.0
9.0
9.0
10BASE-T Full-duplex @ 100% utilization
Power-saving mode (Reg. 1Fh, Bit [10] = 1)
EDPD mode (Reg. 18h, Bit [11] = 0)
EDPD mode (Reg. 18h, Bit [11] = 0) and
PLL off (Reg. 10h, Bit [4] = 1)
4.05
2.79
1.65
1.21
1.21
0.19
15.5
11.4
5.79
Software power-down mode (Reg. 0h, Bit [11] =1)
Software power-down mode (Reg. 0h, Bit [11] =1) and
slow-oscillator mode (Reg. 11h, Bit [5] =1)
2016 Microchip Technology Inc.
DS00002202A-page 33
KSZ8081MNX/RNB
4.0
4.1
REGISTER DESCRIPTIONS
Register Map
TABLE 4-1:
REGISTER MAP
Register Number
Description
(Hex)
0
1h
Basic Control Register
Basic Status
2h
PHY Identifier 1
3h
PHY Identifier 2
4h
Auto-Negotiation Advertisement
Auto-Negotiation Link Partner Ability
Auto-Negotiation Expansion
Auto-Negotiation Next Page
Link Partner Next Page Ability
Reserved
5h
6h
7h
8h
9h
10h
11h
Digital Reserved Control
AFE Control 1
12h – 14h
15h
16h
17h
18h
19h – 1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
Reserved
RXER Counter
Operation Mode Strap Override
Operation Mode Strap Status
Expanded Control
Reserved
Interrupt Control/Status
Reserved
LinkMD Control/Status
PHY Control 1
PHY Control 2
DS00002202A-page 34
2016 Microchip Technology Inc.
KSZ8081MNX/RNB
4.2
Register Description
TABLE 4-2:
Address
REGISTER DESCRIPTION
Name
Description
Mode
Default
Register 0h – Basic Control
1 = Software reset
0 = Normal operation
0
0
0.15
Reset
RW/SC
RW
This bit is self-cleared after a ‘1’ is
written to it.
1 = Loopback mode
0 = Normal operation
1 = 100 Mbps
0.14
Loopback
Set by the SPEED strapping pin.
See the Strap-In Options –
KSZ8081MNX section for details.
0 = 10 Mbps
0.13
0.12
Speed Select
RW
RW
This bit is ignored if auto-
negotiation is enabled (Register
0.12 = 1).
1 = Enable auto-negotiation
process
Set by the NWAYEN strapping
pin.
See the Strap-In Options –
KSZ8081MNX section for details.
Auto-
Negotiation
Enable
0 = Disable auto-negotiation
process
If enabled, the auto-negotiation
result overrides the settings in
registers 0.13 and 0.8.
1 = Power-down mode
0 = Normal operation
If software reset (Register 0.15) is
used to exit power-down mode
(Register 0.11 = 1), two software
reset writes (Register 0.15 = 1) are
required. The first write clears
power-down mode; the second
write resets the chip and re-latches
the pin strapping pin values.
0
0.11
Power-Down
RW
1 = Electrical isolation of PHY from
MII/RMII
Set by the ISO strapping pin.
See the Strap-In Options –
KSZ8081MNX section for details.
0.10
0.9
Isolate
RW
0 = Normal operation
1 = Restart auto-negotiation
process
Restart Auto-
Negotiation
0
0 = Normal operation.
RW/SC
This bit is self-cleared after a ‘1’ is
written to it.
The inverse of the DUPLEX
strapping pin value.
See the Strap-In Options –
KSZ8081MNX section for details.
1 = Full-duplex
0 = Half-duplex
0.8
Duplex Mode
RW
1 = Enable COL test
0 = Disable COL test
Reserved
0
0.7
Collision Test
Reserved
RW
RO
000_0000
0.6:0
2016 Microchip Technology Inc.
DS00002202A-page 35
KSZ8081MNX/RNB
TABLE 4-2:
Address
REGISTER DESCRIPTION (CONTINUED)
Name
Description
Mode
Default
1 = Software reset
0 = Normal operation
This bit is self-cleared after a ‘1’ is
written to it.
0.15
0.14
0.13
Reset
0
RW/SC
1 = Loopback mode
0 = Normal operation
Loopback
0
RW
RW
1 = 100 Mbps
0 = 10 Mbps
This bit is ignored if auto-negotiation
is enabled (Register 0.12 = 1).
Set by the SPEED strapping pin.
See the Strap-In Options –
KSZ8081MNX section for details.
Speed Select
1 = Enable auto-negotiation process
0 = Disable auto-negotiation process
Negotiation If enabled, the auto-negotiation
Set by the NWAYEN strapping
pin.
See the Strap-In Options –
KSZ8081MNX section for details.
Auto-
0.12
0.11
RW
RW
Enable
Power-Down
Isolate
result overrides the settings in regis-
ters 0.13 and 0.8.
1 = Power-down mode
0 = Normal operation
If software reset (Register 0.15) is
used to exit power-down mode (Reg-
ister 0.11 = 1), two software reset
writes (Register 0.15 = 1) are
required. The first write clears
power-down mode; the second write
resets the chip and re-latches the pin
strapping pin values.
0
1 = Electrical isolation of PHY from
MII/RMII
0 = Normal operation
Set by the ISO strapping pin.
See the Strap-In Options –
KSZ8081MNX section for details.
0.10
0.9
RW
1 = Restart auto-negotiation process
Restart Auto- 0 = Normal operation.
Negotiation This bit is self-cleared after a ‘1’ is
written to it.
0
RW/SC
The inverse of the DUPLEX
strapping pin value.
See the Strap-In Options –
KSZ8081MNX section for details.
1 = Full-duplex
Duplex Mode
0.8
RW
0 = Half-duplex
1 = Enable COL test
Collision Test
0.7
0
RW
RO
0 = Disable COL test
0.6:0
Reserved
Reserved
000_0000
Register 1h – Basic Status
1 = T4 capable
0 = Not T4 capable
1.15
100BASE-T4
RO
RO
0
1
1 = Capable of 100 Mbps full-duplex
0 = Not capable of 100 Mbps
full-duplex
100BASE-TX
Full-Duplex
1.14
1 = Capable of 100 Mbps half-duplex
0 = Not capable of 100 Mbps
half-duplex
100BASE-TX
Half-Duplex
1.13
1.12
RO
RO
1
1
1 = Capable of 10 Mbps full-duplex
0 = Not capable of 10 Mbps full-
duplex
10BASE-T
Full-Duplex
DS00002202A-page 36
2016 Microchip Technology Inc.
KSZ8081MNX/RNB
TABLE 4-2:
Address
REGISTER DESCRIPTION (CONTINUED)
Name
Description
Mode
Default
1 = Capable of 10 Mbps half-duplex
0 = Not capable of 10 Mbps half-
duplex
10BASE-T
Half-Duplex
1.11
RO
1
1.10:7 Reserved
Reserved
RO
RO
000_0
1
1 = Preamble suppression
0 = Normal preamble
1.6
No Preamble
1 = Auto-negotiation process
completed
tion Complete 0 = Auto-negotiation process not
completed
Auto-Negotia-
1.5
RO
0
1 = Remote fault
Remote Fault
1.4
1.3
1.2
RO/LH
RO
0
1
0
0 = No remote fault
Auto-Negotia- 1 = Can perform auto-negotiation
tion Ability
0 = Cannot perform auto-negotiation
1 = Link is up
0 = Link is down
Link Status
RO/LL
1 = Jabber detected
1.1
Jabber Detect 0 = Jabber not detected (default is
low)
RO/LH
RO
0
1
Extended
Capability
1 = Supports extended capability
registers
1.0
Register 2h – PHY Identifier 1
Assigned to the 3rd through 18th bits
PHY ID Num- of the Organizationally Unique Identi-
2.15:0
RO
0022h
ber
fier (OUI). KENDIN Communication’s
OUI is 0010A1 (hex).
Register 3h – PHY Identifier 2
Assigned to the 19th through 24th
PHY ID Num- bits of the Organizationally Unique
RO
0001_01
01_0110
ber
Identifier (OUI). KENDIN Communi-
cation’s OUI is 0010A1 (hex).
3.15:10
3.9:4
Model Number Six-bit manufacturer’s model number
RO
RO
Revision Num- Four-bit manufacturer’s revision
Rev. A and Rev. A2=0x0.
Rev. A3=0x1
3.3:0
ber
number
Register 4h – Auto-Negotiation Advertisement
1 = Next page capable
0 = No next page capability
Note: Recommended to set this bit to
“0”.
4.15
Next Page
RW
0
4.14
4.13
4.12
Reserved
Remote Fault
Reserved
Reserved
RO
RW
RO
0
0
0
1 = Remote fault supported
0 = No remote fault
Reserved
[00] = No pause
[10] = Asymmetric pause
[01] = Symmetric pause
[11] = Asymmetric and symmetric
pause
4.11:10
4.9
Pause
RW
RO
00
0
1 = T4 capable
0 = No T4 capability
100BASE-T4
2016 Microchip Technology Inc.
DS00002202A-page 37
KSZ8081MNX/RNB
TABLE 4-2:
Address
REGISTER DESCRIPTION (CONTINUED)
Name
Description
Mode
Default
1 = 100 Mbps full-duplex capable
0 = No 100 Mbps full-duplex
capability
Set by the SPEED strapping pin.
See the Strap-In Options –
KSZ8081MNX section for details.
100BASE-TX
Full-Duplex
4.8
RW
1 = 100 Mbps half-duplex capable
0 = No 100 Mbps half-duplex
capability
Set by the SPEED strapping pin.
See the Strap-In Options –
KSZ8081MNX section for details.
100BASE-TX
Half-Duplex
4.7
4.6
RW
RW
10BASE-T
1 = 10 Mbps full-duplex capable
Full-Duplex 0 = No 10 Mbps full-duplex capability
1
1 = 10 Mbps half-duplex capable
10BASE-T
4.5
0 = No 10 Mbps half-duplex
Half-Duplex
RW
RW
1
capability
4.4:0
Selector Field [00001] = IEEE 802.3
0_0001
Register 5h – Auto-Negotiation Link Partner Ability
1 = Next page capable
0 = No next page capability
5.15
Next Page
RO
RO
0
0
1 = Link code word received from
partner
5.14
Acknowledge
0 = Link code word not yet received
1 = Remote fault detected
0 = No remote fault
5.13
5.12
Remote Fault
Reserved
RO
RO
0
0
Reserved
[00] = No pause
[10] = Asymmetric pause
[01] = Symmetric pause
[11] = Asymmetric and symmetric
pause
5.11:10
Pause
RO
00
1 = T4 capable
0 = No T4 capability
5.9
5.8
100BASE-T4
RO
RO
0
0
1 = 100 Mbps full-duplex capable
0 = No 100 Mbps full-duplex
capability
100BASE-TX
Full-Duplex
Register 5h – Auto-Negotiation Link Partner Ability
1 = 100 Mbps half-duplex capable
0 = No 100 Mbps half-duplex
capability
100BASE-TX
5.7
5.6
RO
RO
0
0
Half-Duplex
10BASE-T
1 = 10 Mbps full-duplex capable
Full-Duplex 0 = No 10 Mbps full-duplex capability
1 = 10 Mbps half-duplex capable
10BASE-T
5.5
0 = No 10 Mbps half-duplex
Half-Duplex
RO
RO
0
capability
5.4:0
Selector Field [00001] = IEEE 802.3
0_0001
Register 6h – Auto-Negotiation Expansion
6.15:5
6.4
Reserved
Reserved
RO
0000_0000_000
0
1 = Fault detected by parallel
Parallel Detec- detection
RO/LH
tion Fault
0 = No fault detected by parallel
detection
1 = Link partner has next page
capability
0 = Link partner does not have next
page capability
Link Partner
Next Page
Able
6.3
RO
0
DS00002202A-page 38
2016 Microchip Technology Inc.
KSZ8081MNX/RNB
TABLE 4-2:
Address
REGISTER DESCRIPTION (CONTINUED)
Name
Description
Mode
Default
1 = Local device has next page
capability
0 = Local device does not have next
page capability
Next Page
Able
6.2
6.1
RO
1
Page
Received
1 = New page received
0 = New page not received yet
RO/LH
RO
0
0
1 = Link partner has auto-negotiation
capability
0 = Link partner does not have auto-
negotiation capability
Link Partner
Auto-Negotia-
tion Able
6.0
Register 7h – Auto-Negotiation Next Page
1 = Additional next pages will follow
0 = Last page
7.15
7.14
7.13
Next Page
RW
RO
RW
0
0
1
Reserved
Reserved
1 = Message page
0 = Unformatted page
Message
Page
1 = Will comply with message
0 = Cannot comply with message
Acknowledge
2
7.12
7.11
RW
RO
RW
0
1 = Previous value of the transmitted
link code word equaled logic 1
0 = Logic 0
Toggle
0
11-bit wide field to encode 2048
messages
Message
Field
7.10:0
000_0000_0001
Register 8h – Link Partner Next Page Ability
1 = Additional next pages will follow
0 = Last page
8.15
8.14
8.13
8.12
Next Page
RO
RO
RO
RO
0
0
0
0
1 = Successful receipt of link word
0 = No successful receipt of link word
Acknowledge
Message
Page
1 = Message page
0 = Unformatted page
1 = Can act on the information
0 = Cannot act on the information
Acknowledge2
1 = Previous value of transmitted link
code word equal to logic 0
0 = Previous value of transmitted link
code word equal to logic 1
8.11
Toggle
RO
0
11-bit wide field to encode 2048
messages
8.10:0 Message Field
RO
RW
000_0000_0000
0000_0000_000
Register 10h – Digital Reserved Control
10.15:5
10.4
Reserved
PLL Off
Reserved
1 = Turn PLL off automatically in
EDPD mode
0 = Keep PLL on in EDPD mode.
See also Register 18h, Bit [11] for
EDPD mode
RW
0
10.3:0
Reserved
Reserved
RW
RW
0000
Register 11h – AFE Control 1
11.15:6 Reserved Reserved
0000_0000_00
2016 Microchip Technology Inc.
DS00002202A-page 39
KSZ8081MNX/RNB
TABLE 4-2:
Address
REGISTER DESCRIPTION (CONTINUED)
Name
Description
Mode
Default
Slow-oscillator mode is used to
disconnect the input reference
crystal/clock on the XI pin and select
the on-chip slow oscillator when the
Slow-Oscilla- KSZ8081MNX/RNB device is not in
11.5
tor Mode
Enable
use after power-up.
1 = Enable
RW
0
0 = Disable
This bit automatically sets software
power-down to the analog side when
enabled.
11.4:0
Reserved
Reserved
RW
0_0000
0000h
Register 15h – RXER Counter
RXER
Counter
Receive error counter for symbol
error frames
15.15:0
RO/SC
Register 16h – Operation Mode Strap Override
0 = Normal operation
1 = Factory test mode
If TXC (Pin 22) latches in a pull-up
value at the de-assertion of reset,
Factory Mode write a ‘0’ to this bit to clear
Reserved Factory Mode.
This bit applies only to
0
Reserved
16.15
RW
Set by the pull-up/pull-down
value of TXC (Pin 22).
KSZ8081MNX.
16.14:11
16.10
Reserved
Reserved
Reserved
RW
RO
000_0
0
Reserved
1 = Override strap-in for B-
B-CAST_OFF CAST_OFF
16.9
16.8
RW
RW
0
0
Override
If bit is ‘1’, PHY Address 0 is non-
broadcast.
Reserved
Reserved
1 = Override strap-in for MII back-to-
back mode (also set Bit 0 of this reg-
ister to ‘1’)
This bit applies only to
KSZ8081MNX.
MII B-to-B
Override
16.7
16.6
RW
RW
0
0
1 = Override strap-in for RMII Back-
to-Back mode (also set Bit 1 of this
register to ‘1’)
This bit applies only to
KSZ8081RNB.
RMII B-to-B
Override
NAND Tree 1 = Override strap-in for NAND tree
16.5
RW
RW
0
Override
mode
16.4:2
Reserved
Reserved
0_00
1 = Override strap-in for RMII mode
16.1
16.0
RMII Override This bit applies only to
KSZ8081RNB.
RW
RW
0
1
1 = Override strap-in for MII mode
MII Override This bit applies only to
KSZ8081MNX.
DS00002202A-page 40
2016 Microchip Technology Inc.
KSZ8081MNX/RNB
TABLE 4-2:
Address
REGISTER DESCRIPTION (CONTINUED)
Name
Description
Mode
Default
Register 17h – Operation Mode Strap Status
[000] = Strap to PHY Address 0
[001] = Strap to PHY Address 1
[010] = Strap to PHY Address 2
PHYAD[2:0] [011] = Strap to PHY Address 3
Strap-InStatus [100] = Strap to PHY Address 4
[101] = Strap to PHY Address 5
17.15:13
RO
—
[110] = Strap to PHY Address 6
[111] = Strap to PHY Address 7
17.12:10
17.9
Reserved
Reserved
RO
RO
RO
RO
—
—
—
—
1 = Strap to B-CAST_OFF
If bit is ‘1’, PHY Address 0 is non-
broadcast.
B-CAST_OFF
Strap-InStatus
17.8
Reserved
Reserved
1 = Strap to MII back-to-back mode
This bit applies only to
KSZ8081MNX.
MII B-to-B
Strap-InStatus
17.7
1 = Strap to RMII Back-to-Back
RMII B-to-B mode
Strap-InStatus This bit applies only to
KSZ8081RNB.
17.6
RO
—
NAND Tree
17.5
1 = Strap to NAND tree mode
Strap-InStatus
RO
RO
—
—
17.4:2
Reserved
Reserved
1 = Strap to RMII mode
This bit applies only to
KSZ8081RNB.
RMII Strap-In
Status
17.1
17.0
RO
RO
—
—
1 = Strap to MII mode
This bit applies only to
KSZ8081MNX.
MII Strap-In
Status
Register 18h – Expanded Control
18.15:12
Reserved
Reserved
RW
RW
0000
1
Energy-detect power-down mode
1 = Disable
0 = Enable
See also Register 10h, Bit [4] for PLL
off.
EDPD
Disabled
18.11
1 = MII output is random latency
0 = MII output is fixed latency
For both settings, all bytes of
received preamble are passed to the
MII output.
100BASE-TX
Latency
18.10
18.9:7
18.6
RW
RW
RW
0
00_0
0
This bit applies only to
KSZ8081MNX.
Reserved
Reserved
1 = Restore received preamble to MII
output
0 = Remove all seven bytes of pre-
amble before sending frame (starting
with SFD) to MII output
This bit applies only to
10BASE-T
Preamble
Restore
KSZ8081MNX,
2016 Microchip Technology Inc.
DS00002202A-page 41
KSZ8081MNX/RNB
TABLE 4-2:
Address
18.5:0
REGISTER DESCRIPTION (CONTINUED)
Name
Description
Mode
Default
Reserved
Reserved
RW
00_0000
Register 1Bh – Interrupt Control/Status
Jabber
Interrupt
Enable
1 = Enable jabber interrupt
0 = Disable jabber interrupt
1B.15
1B.14
RW
RW
0
0
Receive Error
Interrupt
1 = Enable receive error interrupt
0 = Disable receive error interrupt
Enable
Page
Received
Interrupt
Enable
1 = Enable page received interrupt
0 = Disable page received interrupt
1B.13
1B.12
1B.11
RW
RW
RW
0
0
0
1 = Enable parallel detect fault inter-
rupt
0 = Disable parallel detect fault inter-
rupt
ParallelDetect
Fault Interrupt
Enable
Link Partner 1 = Enable link partner acknowledge
Acknowledge interrupt
Interrupt
Enable
0 = Disable link partner acknowledge
interrupt
Link-Down
Interrupt
Enable
1= Enable link-down interrupt
0 = Disable link-down interrupt
1B.10
1B.9
1B.8
RW
RW
RW
0
0
0
Remote Fault
Interrupt
1 = Enable remote fault interrupt
0 = Disable remote fault interrupt
Enable
Link-Up
Interrupt
Enable
1 = Enable link-up interrupt
0 = Disable link-up interrupt
Jabber
Interrupt
1 = Jabber occurred
0 = Jabber did not occur
1B.7
1B.6
1B.5
1B.4
RO/SC
RO/SC
RO/SC
RO/SC
0
0
0
0
Receive Error 1 = Receive error occurred
Interrupt 0 = Receive error did not occur
Page Receive 1 = Page receive occurred
Interrupt 0 = Page receive did not occur
ParallelDetect 1 = Parallel detect fault occurred
Fault Interrupt 0 = Parallel detect fault did not occur
1 = Link partner acknowledge
occurred
Link Partner
Acknowledge
1B.3
RO/SC
0
0 = Link partner acknowledge did not
Interrupt
occur
Link-Down
Interrupt
1 = Link-down occurred
0 = Link-down did not occur
1B.2
1B.1
1B.0
RO/SC
RO/SC
RO/SC
0
0
0
Remote Fault 1 = Remote fault occurred
Interrupt
0 = Remote fault did not occur
Link-Up
Interrupt
1 = Link-up occurred
0 = Link-up did not occur
DS00002202A-page 42
2016 Microchip Technology Inc.
KSZ8081MNX/RNB
TABLE 4-2:
Address
REGISTER DESCRIPTION (CONTINUED)
Name
Description
Mode
Default
Register 1Dh – LinkMD Control/Status
1 = Enable cable diagnostic test.
After test has completed, this bit is
self-cleared.
0 = Indicates cable diagnostic test (if
enabled) has completed and the sta-
tus information is valid for read.
Cable Diag-
nostic Test
Enable
1D.15
RW/SC
0
[00] = Normal condition
[01] = Open condition has been
Cable Diag- detected in cable
1D.14:13
nostic Test
Result
[10] = Short condition has been
RO
00
detected in cable
[11] = Cable diagnostic test has
failed
Short Cable 1 = Short cable (<10 meter) has
1D.12
1D.11:9
1D.8:0
RO
RW
RO
0
Indicator
been detected by LinkMD
Reserved
Reserved
000
Cable Fault
Counter
Distance to fault
0_0000_0000
Register 1Eh – PHY Control 1
1E.15:1
0000_00
0
Reserved
Reserved
RO
RO
0
Enable
Pause (Flow
Control)
1 = Flow control capable
1E.9
0 = No flow control capability
1 = Link is up
0
0
1E.8
Link Status
RO
0 = Link is down
1 = Polarity is reversed
0 = Polarity is not reversed
Reserved
Polarity
Status
1E.7
1E.6
1E.5
RO
RO
RO
Reserved
1 = MDI-X
MDI/MDI-X
State
0 = MDI
1 = Signal present on receive
differential pair
Energy
Detect
0
0
1E.4
1E.3
RO
0 = No signal detected on receive
differential pair
1 = PHY in isolate mode
0 = PHY in normal operation
[000] = Still in auto-negotiation
[001] = 10BASE-T half-duplex
[010] = 100BASE-TX half-duplex
[011] = Reserved
PHY Isolate
RW
Operation
Mode
Indication
000
1E.2:0
RO
[100] = Reserved
[101] = 10BASE-T full-duplex
[110] = 100BASE-TX full-duplex
[111] = Reserved
2016 Microchip Technology Inc.
DS00002202A-page 43
KSZ8081MNX/RNB
TABLE 4-2:
Address
REGISTER DESCRIPTION (CONTINUED)
Name
Description
Mode
Default
Register 1Fh – PHY Control 2
1 = HP Auto MDI/MDI-X mode
0 = Auto MDI/MDI-X mode
1F.15
1F.14
HP_MDIX
RW
1
When Auto MDI/MDI-X is disabled,
1 = MDI-X mode
Transmit on RXP,RXM (pins 5, 4)
andReceive on TXP,TXM (pins 7, 6)
0 = MDI mode
MDI/MDI-X
Select
RW
0
Transmit on TXP,TXM (pins 7, 6) and
Receive on RXP,RXM (pins 5, 4)
Pair Swap
Disable
1 = Disable Auto MDI/MDI-X
0 = Enable Auto MDI/MDI-X
1F.13
1F.12
RW
RW
0
0
Reserved
Reserved
1 = Force link pass
0 = Normal link operation
1F.11
Force Link
This bit bypasses the control logic
and allows the transmitter to send a
pattern even if there is no link.
RW
0
1 = Enable power saving
0 = Disable power saving
1F.10
1F.9
1F.8
Power Saving
Interrupt Level
Enable Jabber
RW
RW
RW
0
0
1
1 = Interrupt pin active high
0 = Interrupt pin active low
1 = Enable jabber counter
0 = Disable jabber counter
1 = RMII 50 MHz clock mode; clock
input to XI (Pin 9) is 50 MHz
0 = RMII 25 MHz clock mode; clock
input to XI (Pin 9) is 25 MHz
This bit applies only to
RMII Refer-
ence Clock
Select
1F.7
RW
0
KSZ8081RNB.
1F.6
Reserved
LED Mode
Disable
Reserved
RW
RW
0
[00] =LED1: Speed
LED0: Link/Activity
[01] = LED1: Activity
LED0: Link
1F.5:4
00
[10], [11] = Reserved
1 = Disable transmitter
1F.3
1F.2
RW
RW
0
0
Transmitter 0 = Enable transmitter
1 = Remote (analog) loopback is
enabled
0 = Normal mode
Remote
Loopback
Enable SQE 1 = Enable SQE test
Test 0 = Disable SQE test
1F.1
1F.0
RW
RW
0
0
Disable Data 1 = Disable scrambler
Scrambling 0 = Enable scrambler
DS00002202A-page 44
2016 Microchip Technology Inc.
KSZ8081MNX/RNB
5.0
5.1
OPERATIONAL CHARACTERISTICS
Absolute Maximum Ratings*
Supply Voltage (VIN)
(VDD_1.2).................................................................................................................................................... –0.5V to +1.8V
(VDDIO, VDDA_3.3)...................................................................................................................................... –0.5V to +5.0V
Input Voltage (all inputs)............................................................................................................................ –0.5V to +5.0V
Output Voltage (all outputs)....................................................................................................................... –0.5V to +5.0V
Lead Temperature (soldering, 10s) .........................................................................................................................260°C
Storage Temperature (TS)......................................................................................................................–55°C to +150°C
* Exceeding the absolute maximum ratings can damage the device. Stresses greater than the absolute maximum rating
can cause permanent damage to the device. Operation of the device at these or any other conditions above
those specified in the operating sections of this specification is not implied. Maximum conditions for extended
periods may affect reliability.
5.2
Operating Ratings**
Supply Voltage
(VDDIO_3.3, VDDA_3.3) ........................................................................................................................+3.135V to +3.465V
(VDDIO_2.5).........................................................................................................................................+2.375V to +2.625V
(VDDIO_1.8).........................................................................................................................................+1.710V to +1.890V
Ambient Temperature
(TA, Commercial)..........................................................................................................................................0°C to +70°C
(TA, Industrial) ..........................................................................................................................................–40°C to +85°C
Maximum Junction Temperature (TJ max.) ...........................................................................................................+125°C
Thermal Resistance (TJA) ............................................................................................................................... 45.87°C/W
Thermal Resistance (TJC) ............................................................................................................................... 15.85°C/W
** The device is not guaranteed to function outside its operating ratings.
2016 Microchip Technology Inc.
DS00002202A-page 45
KSZ8081MNX/RNB
6.0
ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
Supply Current (VDDIO, VDDA_3.3 = 3.3V)
Full-duplex traffic @ 100%
utilization
—
—
—
—
—
—
—
—
IDD1_3.3V 10BASE-T
41
47
20
4
mA
mA
mA
mA
Full-duplex traffic @ 100%
utilization
IDD2_3.3V 100BASE-TX
IDD3_3.3V EDPD Mode
Ethernet cable disconnected
(reg. 18h.11 = 0)
Software power-down (reg.
0h.11 = 1)
IDD4_3.3V Power-Down Mode
CMOS Level Inputs
—
—
—
—
—
—
—
—
—
V
DDIO = 3.3V
2.0
1.8
1.3
—
VIH
Input High Voltage
VDDIO = 2.5V
VDDIO = 1.8V
V
—
VDDIO = 3.3V
0.8
0.7
0.5
10
—
VIL
Input Low Voltage
Input Current
VDDIO = 2.5V
V
—
VDDIO = 1.8V
—
|IIN|
VIN = GND ~ VDDIO
μA
CMOS Level Outputs
—
—
—
—
—
—
—
—
—
VDDIO = 3.3V
VDDIO = 2.5V
VDDIO = 1.8V
2.4
2.0
1.5
—
VOH
Output High Voltage
V
—
VDDIO = 3.3V
0.4
0.4
0.3
10
—
VOL
|Ioz|
Output Low Voltage
VDDIO = 2.5V
VDDIO = 1.8V
—
V
—
—
Output Tri-State Leakage
μA
mA
LED Output
ILED Output Drive Current
Each LED pin (LED0, LED1)
—
8
—
All Pull-Up/Pull-Down Pins (including Strapping Pins)
VDDIO = 3.3V
30
39
48
26
34
53
45
61
99
43
59
99
73
102
178
79
VDDIO = 2.5V
VDDIO = 1.8V
VDDIO = 3.3V
VDDIO = 2.5V
pu
pd
Internal Pull-Up Resistance
kΩ
kΩ
Internal Pull-Down
Resistance
113
200
VDDIO = 1.8V
100BASE-TX Transmit (measured differentially after 1:1 transformer)
Peak Differential Output Volt- 100Ω termination across dif-
VO
0.95
—
—
—
1.05
2
V
age
ferential output
100Ω termination across dif-
ferential output
VIMB
tr, tf
Output Voltage Imbalance
%
Rise/Fall Time
—
3
—
—
5
0.5
±0.25
5
ns
ns
ns
%
—
Rise/Fall Time Imbalance
Duty Cycle Distortion
Overshoot
—
0
—
—
—
—
—
—
—
—
—
—
Output Jitter
Peak-to-peak
0.7
—
ns
DS00002202A-page 46
2016 Microchip Technology Inc.
KSZ8081MNX/RNB
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
10BASE-T Transmit (measured differentially after 1:1 transformer)
Peak Differential Output Volt- 100Ω termination across dif-
VP
2.2
—
2.8
V
age
ferential output
Peak-to-peak
—
Jitter Added
Rise/Fall Time
—
—
—
3.5
—
ns
ns
tr, tf
25
10BASE-T Receive
VSQ
Squelch Threshold
5 MHz square wave
—
—
400
—
—
mV
V
Transmitter – Drive Setting
VSET
Reference Voltage of ISET
R(ISET) = 6.49 kΩ
0.65
REF_CLK Output
Peak-to-peak. (Applies only to
KSZ8081RNB in RMII –
25 MHz clock mode)
50 MHz RMII Clock Output
Jitter
—
—
300
20
—
ps
ns
100 Mbps Mode – Industrial Applications Parameters
XI (25 MHz clock input) to MII
TXC (25 MHz clock output)
Clock Phase Delay – XI Input delay, referenced to rising
—
15
25
to MII TXC Output
edges of both clocks. (Applies
only to KSZ8081MNX in MII
mode)
Link loss detected at receive
differential inputs to PHY sig-
nal indication time for each of
the following:
1. For LED mode 00, Speed
LED output changes from low
(100 Mbps) to high (10 Mbps,
default state for link-down).
2. For LED mode 01, Link
LED output changes from low
(link-up) to high (link-down).
3. INTRP pin asserts for link-
down status change.
Link Loss Reaction
(Indication) Time
tllr
—
4.4
—
μs
2016 Microchip Technology Inc.
DS00002202A-page 47
KSZ8081MNX/RNB
7.0
7.1
TIMING DIAGRAMS
MII SQE Timing (10BASE-T)
FIGURE 7-1:
MII SQE TIMING (10BASE-T)
tWL
TXC
tWH
tP
TXEN
tSQE
COL
tSQEP
TABLE 7-1:
MII SQE TIMING (10BASE-T) PARAMETERS
Timing Parameters
Description
TXC period
Min.
Typ.
Max.
Units
tP
—
—
—
400
200
200
—
—
—
ns
ns
ns
tWL
tWH
TXC pulse width low
TXC pulse width high
COL (SQE) delay after
TXEN de-asserted
—
—
—
—
tSQE
2.2
1.0
μs
μs
tSQEP
COL (SQE) pulse duration
7.2
MII Transmit Timing (10BASE-T)
FIGURE 7-2:
MII TRANSMIT TIMING (10BASE-T)
tP
tWL
TXC
tWH
tSU2
TXEN
tHD2
TXD[3:0]
tSU1
tHD1
tCRS1
CRS
tCRS2
TABLE 7-2:
MII TRANSMIT TIMING (10BASE-T) PARAMETERS
Timing Parameters
Description
Min.
Typ.
Max.
Units
tP
TXC period
—
—
—
400
200
200
—
—
—
—
—
—
ns
ns
ns
ns
ns
tWL
TXC pulse width low
tWH
tSU1
tSU2
TXC pulse width high
TXD[3:0] setup to rising edge of TXC
TXEN setup to rising edge of TXC
120
120
—
DS00002202A-page 48
2016 Microchip Technology Inc.
KSZ8081MNX/RNB
TABLE 7-2:
MII TRANSMIT TIMING (10BASE-T) PARAMETERS
Timing Parameters
tHD1
Description
Min.
Typ.
—
Max.
—
Units
TXD[3:0] hold from rising edge of TXC
TXEN hold from rising edge of TXC
TXEN high to CRS asserted latency
TXEN low to CRS de-asserted latency
0
0
ns
ns
ns
μs
—
—
tHD2
—
tCRS1
tCRS2
600
1.0
—
7.3
MII Receive Timing (10BASE-T)
FIGURE 7-3:
MII RECEIVE TIMING (10BASE-T)
CRS
tRLAT
tOD
RXDV
RXD[3:0]
RXER
tP
tWL
RXC
tWH
TABLE 7-3:
MII RECEIVE TIMING (10BASE-T) PARAMETERS
Timing Parameters
Description
RXC period
Min.
Typ.
Max.
Units
tP
—
—
—
400
200
200
—
—
—
ns
ns
ns
tWL
tWH
RXC pulse width low
RXC pulse width high
(RXDV, RXD[3:0], RXER) output
delay from rising edge of RXC
—
—
205
7.2
—
—
tOD
ns
tRLAT
CRS to (RXDV, RXD[3:0]) latency
μs
2016 Microchip Technology Inc.
DS00002202A-page 49
KSZ8081MNX/RNB
7.4
MII Transmit Timing (BASE100BASE-TX)
FIGURE 7-4:
MII TRANSMIT TIMING (BASE100BASE-TX)
tWL
TXC
tWH
tHD2
tSU2
tP
TXEN
TXD[3:0]
CRS
tHD1
tSU1
DATA
IN
tCRS2
tCRS1
TABLE 7-4:
MII TRANSMIT TIMING (BASE100BASE-TX) PARAMETERS
Timing
Parameter
Description
Min.
Typ.
Max.
Units
tP
TXC Period
—
—
—
40
20
20
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWL
TXC pulse width low
—
tWH
TXC pulse width high
—
tSU1
tSU2
tHD1
tHD2
tCRS1
tCRS2
TXD[3:0] setup to rising edge of TXC
TXEN setup to rising edge of TXC
TXD[3:0] hold from rising edge of TXC
TXEN hold from rising edge of TXC
TXEN high to CRS asserted latency
TXEN low to CRS de-asserted latency
10
10
0
—
—
—
0
—
—
—
72
72
—S
7.5
MII Receive Timing (BASE100BASE-TX)
FIGURE 7-5:
MII RECEIVE TIMING (BASE100BASE-TX)
CRS
tRLAT
RXDV
tOD
RXD[3:0]
RXER
tWL
RXC
tWH
tP
DS00002202A-page 50
2016 Microchip Technology Inc.
KSZ8081MNX/RNB
TABLE 7-5:
MII RECEIVE TIMING (BASE100BASE-TX) PARAMETERS
Timing
Parameter
Description
Min.
Typ.
Max.
Units
tP
RXC period
—
—
—
40
20
20
—
—
—
ns
ns
ns
tWL
tWH
tOD
RXC pulse width low
RXC pulse width high
(RXDV, RXD[3:0], RXER) output delay from ris-
ing edge of RXC
21
25
—
16
—
ns
ns
tFLAT
CRS to (RXDV, RXD[3:0] latency
170
7.6
RMII Timing
FIGURE 7-6:
TRANSMIT TIMING
RMII TIMING – DATA RECEIVED FROM RMII
tCYC
REF_CLK
t1
t2
TXEN
TXD[1:0]
FIGURE 7-7:
RMII TIMING – DATA INPUT TO RMII
tCYC
RECEIVE
TIMING
REF_CLK
CRS_DV
RXD[1:0]
RXER
tOD
2016 Microchip Technology Inc.
DS00002202A-page 51
KSZ8081MNX/RNB
TABLE 7-6:
RMII TIMING PARAMETERS – KSZ8081RNB (25 MHZ INPUT TO XI PIN, 50 MHZ
OUTPUT FROM REF_CLK PIN)
Timing Parameter
Description
Clock cycle
Min.
Typ.
Max
Units
tCYC
t1
—
4
20
—
—
10
—
—
—
13
ns
ns
ns
ns
Setup time
Hold time
t2
2
tOD
Output delay
7
TABLE 7-7:
RMII TIMING PARAMETERS – KSZ8081RNB (25 MHZ INPUT TO XI PIN)
Timing Parameter
Description
Clock cycle
Min.
Typ.
Max
Units
tCYC
t1
—
4
20
—
—
11
—
—
—
13
ns
ns
ns
ns
Setup time
Hold time
t2
2
tOD
Output delay
8
7.7
Auto-Negotiation Timing
FIGURE 7-8:
AUTO-NEGOTIATION TIMING
AUTO -NEGOTIATION
FAST LINK PULSE (FLP) TIMING
FLP
BURST
FLP
BURST
TX+/TX-
tFLPW
tBTB
CLOCK
PULSE
DATA
PULSE
CLOCK
PULSE
DATA
PULSE
TX+/TX-
tPW
tPW
tCTD
tCTC
DS00002202A-page 52
2016 Microchip Technology Inc.
KSZ8081MNX/RNB
TABLE 7-8:
AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING PARAMETERS
Timing Parameter
Description
Min.
Typ.
Max.
Units
tBTB
tFLPW
tPW
FLP burst to FLP burst
FLP burst width
8
—
16
2
24
—
ms
ms
ns
Clock/Data pulse width
Clock pulse to data pulse
Clock pulse to clock pulse
—
100
64
—
tCTD
tCTC
55.5
111
69.5
139
μs
μs
128
Number of clock/data pulses per
FLP burst
—
17
—
33
—
7.8
MDC/MDIO Timing
FIGURE 7-9:
MDC/MDIO TIMING
tP
MDC
tMD1
tMD2
MDIO
(PHY INPUT)
VALID
DATA
VALID
DATA
tMD3
MDIO
(PHY OUTPUT)
VALID
DATA
TABLE 7-9:
MDC/MDIO TIMING PARAMETERS
Description
Timing
Parameter
Min.
Typ.
Max.
Units
fc
MDC Clock Frequency
—
—
2.5
400
—
10
—
—
—
—
MHz
ns
tP
MDC period
tMD1
tMD2
tMD3
MDIO (PHY input) setup to rising edge of MDC
MDIO (PHY input) hold from rising edge of MDC
MDIO (PHY output) delay from rising edge of MDC
10
4
ns
—
ns
5
222
ns
2016 Microchip Technology Inc.
DS00002202A-page 53
KSZ8081MNX/RNB
7.9
Power-up/Reset Timing
The KSZ8081MNX/RNB reset timing requirement is summarized in Figure 7-10 and Table 7-10.
FIGURE 7-10:
POWER-UP/RESET TIMING
SUPPLY
VOLTAGES
tSR
tVR
RST#
tCS
tCH
STRAP-IN
VALUE
tRC
STRAP-IN /
OUTPUT PIN
TABLE 7-10: POWER-UP/RESET TIMING PARAMETERS
Parameter
tVR
Description
Min.
Max.
Units
Supply voltage (VDDIO, VDDA_3.3) rise time
300
—
μs
Stable supply voltage (VDDIO, VDDA_3.3) to reset
high
tSR
10
ms
—
tCS
tCH
tRC
Configuration setup time
Configuration hold time
Reset to strap-in pin output
5
5
6
ns
ns
ns
—
—
—
The supply voltage (VDDIO and VDDA_3.3) power-up waveform should be monotonic. The 300 μs minimum rise time is
from 10% to 90%.
For warm reset, the reset (RST#) pin should be asserted low for a minimum of 500 μs. The strap-in pin values are read
and updated at the de-assertion of reset.
After the de-assertion of reset, wait a minimum of 100 μs before starting programming on the MIIM (MDC/MDIO) inter-
face.
DS00002202A-page 54
2016 Microchip Technology Inc.
KSZ8081MNX/RNB
7.10 Reset Circuit
Figure 7-11 shows a reset circuit recommended for powering up the KSZ8081MNX/RNB if reset is triggered by the
power supply.
FIGURE 7-11:
RECOMMENDED RESET CIRCUIT
VDDIO
D1: 1N4148
D1
R 10K
KSZ8081MNX/RNB
RST#
C 10μF
Figure 7-12 Shows a reset circuit recommended for applications where reset is driven by another device (for example,
the CPU or an FPGA). The reset out RST_OUT_n from CPU/FPGA provides the warm reset after power up reset. D2
is used if using different VDDIO between the switch and CPU/FPGA, otherwise, the different VDDIO will fight each other.
If different VDDIO have to use in a special case, a low VF (<0.3V) diode is required (For example, VISHAY’s BAT54,
MSS1P2L and so on), or a level shifter device can be used too. If Ethernet device and CPU/FPGA use same VDDIO
voltage, D2 can be removed to connect both devices directly. Usually, Ethernet device and CPU/FPGA should use same
VDDIO voltage.
FIGURE 7-12:
RECOMMENDED RESET CIRCUIT FOR INTERFACING WITH CPU/FPGA RESET
OUTPUT
VDDIO
R 10K
D1
KSZ8081MNX/RNB
RST#
CPU/FPGA
RST_OUT_N
D2
C 10μF
D1, D2: 1N4148
2016 Microchip Technology Inc.
DS00002202A-page 55
KSZ8081MNX/RNB
7.11 Reference Circuits – LED Strap-In Pins
The pull-up, float, and pull-down reference circuits for the LED1/SPEED and LED0/NWAYEN strapping pins are shown
in Figure 7-13 for 3.3V and 2.5V VDDIO.
FIGURE 7-13:
REFERENCE CIRCUITS FOR LED STRAPPING PINS
VDDIO = 3.3V, 2.5V
PULL_UP
4.7kΩ
220Ω
KSZ8081MNX/RXB
LED PIN
VDDIO = 3.3V, 2.5V
220Ω
FLOAT
KSZ8081MNX/RXB
LED PIN
VDDIO = 3.3V, 2.5V
220Ω
PULL-DOWN
KSZ8081MNX/RXB
LED PIN
1kΩ
For using 1.8V VDDIO, should select parts with low 1.8V operation voltage and forwarding current IF about 2 mA LED
indicator. It is okay to use internal pull-up or external pull-up resistor for the LED pin pull-up strap function, and use an
external 0.75 kΩ to 1 kΩ pull-down resistor for the LED pin pull-down strap function.
Note: If using RJ45 jacks with integrated LEDs and 1.8V VDDIO, a level shifting is required from LED 3.3V to 1.8V. For
example, use a bipolar transistor or a level shift device.
DS00002202A-page 56
2016 Microchip Technology Inc.
KSZ8081MNX/RNB
7.12 Reference Clock – Connection and Selection
A crystal or external clock source, such as an oscillator, is used to provide the reference clock for the KSZ8081MNX/
RNB. For the KSZ8081MNX in all operating modes and for the KSZ8081RNB in RMII – 25 MHz Clock Mode, the refer-
ence clock is 25 MHz. The reference clock connections to XI (Pin 9) and XO (Pin 8), and the reference clock selection
criteria, are provided in Figure 7-14 and Table 7-11.
FIGURE 7-14:
25 MHZ CRYSTAL/OSCILLATOR REFERENCE CLOCK CONNECTION
22pF
XI
XI
22pF
25MHz OSC
50PPM
NC
XO
XO
25MHz XTAL
50PPM
TABLE 7-11: 25 MHZ CRYSTAL/REFERENCE CLOCK SELECTION CRITERIA
Characteristics
Value
Units
Frequency
25
±50
40
MHz
ppm
Ω
Frequency tolerance (max) (Note 7-1)
Crystal series resistance (typ)
Crystal load capacitance (typ)
22
pF
Note 7-1
±60 ppm for overtemperature crystal.
For the KSZ8081RNB in RMII – 50 MHz clock mode, the reference clock is 50 MHz. The reference clock connections
to XI (Pin 9), and the reference clock selection criteria are provided in Figure 7-15 and Table 7-12.
FIGURE 7-15:
50 MHZ OSCILLATOR REFERENCE CLOCK CONNECTION
XI
50MHz OSC
50PPM
NC
XO
TABLE 7-12: 50 MHZ OSCILLATOR/REFERENCE CLOCK SELECTION CRITERIA
Characteristics
Frequency
Value
Units
50
MHz
ppm
Frequency tolerance (maximum)
±50
2016 Microchip Technology Inc.
DS00002202A-page 57
KSZ8081MNX/RNB
7.13 Magnetic – Connection and Selection
The KSZ8081MNX/RNB design incorporates voltage-mode transmit drivers and on-chip terminations.
With the voltage-mode implementation, the transmit drivers supply the common-mode voltages to the two differential
pairs. Therefore, the two transformer center tap pins on the KSZ8081MNX/RNB side should not be connected to any
power supply source on the board; instead, the center tap pins should be separated from one another and connected
through separate 0.1 μF common-mode capacitors to ground. Separation is required because the common-mode volt-
age is different between transmitting and receiving differential pairs.
Figure 7-16 shows the typical magnetic interface circuit for the KSZ8081MNX/RNB.
FIGURE 7-16:
TYPICAL MAGNETIC INTERFACE CIRCUIT
1
TXP
2
3
TXM
RXP
RXM
4
5
6
7
8
4 x 75Ω
(2 x 0.1μF)
1000pF/2kV
CHASSIS GROUND
SIGNAL GROUND
Table 7-13 lists recommended magnetic characteristics.
TABLE 7-13: MAGNETICS SELECTION CRITERIA
Parameter
Value
Test Condition
Turns ratio
1 CT : 1 CT
350 μH
—
Open-circuit inductance (minimum)
Insertion loss (typical)
100 mV, 100 kHz, 8 mA
100 kHz to 100 MHz
—
–1.1 dB
HIPOT (minimum)
1500 Vrms
DS00002202A-page 58
2016 Microchip Technology Inc.
KSZ8081MNX/RNB
Table 7-14 is a list of compatible single-port magnetics with separated transformer center tap pins on the PHY chip side
that can be used with the KSZ8081MNX/RNB.
TABLE 7-14: COMPATIBLE SINGLE-PORT 10/100 MAGNETICS
Manufacturer
Bel Fuse
Part Number
S558-5999-U7
Temperature Range
Magnetic + RJ-45
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
–40°C to 85°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
0°C to 70°C
0°C to 70°C
–40°C to 85°C
No
Yes
Yes
No
Bel Fuse
Bel Fuse
Delta
SI-46001-F
SI-50170-F
LF8505
HALO
HFJ11-2450E
TG110-E055N5
LF-H41S-1
H1102
Yes
No
HALO
LANKom
Pulse
No
No
Pulse
H1260
No
Pulse
HX1188
No
Pulse
J00-0014
Yes
Yes
Yes
No
Pulse
JX0011D21NL
TLA-6T718A
HB726
TDK
Transpower
Wurth/Midcom
000-7090-37R-LF1
No
2016 Microchip Technology Inc.
DS00002202A-page 59
KSZ8081MNX/RNB
8.0
PACKAGE OUTLINE
FIGURE 8-1:
32-LEAD QFN 5 MM × 5 MM PACKAGE AND RECOMMENDED PCB LAND
PATTERN
DS00002202A-page 60
2016 Microchip Technology Inc.
KSZ8081MNX/RNB
APPENDIX A: DATA SHEET REVISION HISTORY
TABLE A-1:
REVISION HISTORY
Revision
Section/Figure/Entry
ALL
Correction
DS00002202A (10-27-16)
Converted Micrel document KSZ8081MNX/RNB to
Microchip DS00002202A. Minor text edits through-
out.
2016 Microchip Technology Inc.
DS00002202A-page 61
KSZ8081MNX/RNB
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make
files and information easily available to customers. Accessible by using your favorite Internet browser, the web site con-
tains the following information:
• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
guides and hardware support documents, latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion
groups, Microchip consultant program member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of semi-
nars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive
e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or
development tool of interest.
To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notifi-
cation” and follow the registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales
offices are also available to help customers. A listing of sales offices and locations is included in the back of this docu-
ment.
Technical support is available through the web site at: http://microchip.com/support
DS00002202A-page 62
2016 Microchip Technology Inc.
KSZ8081MNX/RNB
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PART NO.
Device
X
X
X
X
a)
b)
c)
KSZ8081MNXCA
10BASE-T/100BASE-TX Physical Layer
Transceiver, MII, 32-pin QFN,
Commercial Temperature.
Package
Option
Temperature
Range
Interface
Special
Attribute
KSZ8081MNXIA
Device:
KSZ8081 - 10BASE-T/100BASE-TX Physical Layer
Transceiver
10BASE-T/100BASE-TX Physical Layer
Transceiver, MII, 32-pin QFN,
Industrial Temperature.
Interface:
M
R
=
=
MII, GMII
RMII, RGMII
KSZ8081RNBCA
10BASE-T/100BASE-TX Physical Layer
Transceiver, RMII, 32-pin QFN,
REF_CLK output (power-up default),
Commercial Temperature.
Package Option:
Special Attribute:
N
=
32-pin QFN
X
B
=
=
None
d)
KSZ8081RNBIA
REF_CLK output (power-up default)
10BASE-T/100BASE-TX Physical Layer
Transceiver, RMII, 32-pin QFN,
REF_CLK output (power-up default),
Industrial Temperature.
Temperature
Range:
IA
CA
=
=
Industrial (–40°C to +85°C)
Commercial (0°C to +70°C)
2015 Microchip Technology Inc.
DS00002202A-page 63
KSZ8081MNX/RNB
DS00002202A-page 64
2015 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be
superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO
REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Micro-
chip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold
harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or
otherwise, under any Microchip intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo,
Kleer, LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other
countries.
ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial
Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless
DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their respective companies.
© 2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-1048-5
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
2016 Microchip Technology Inc.
DS00002202A-page 65
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Asia Pacific Office
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
Hong Kong
Tel: 852-2943-5100
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Web Address:
www.microchip.com
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Germany - Dusseldorf
Tel: 49-2129-3766400
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
Germany - Karlsruhe
Tel: 49-721-625370
India - Pune
Tel: 91-20-3019-1500
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Austin, TX
Tel: 512-257-3370
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Boston
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
China - Dongguan
Tel: 86-769-8702-9880
Italy - Venice
Tel: 39-049-7625286
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Guangzhou
Tel: 86-20-8755-8029
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
Korea - Seoul
Cleveland
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Poland - Warsaw
Tel: 48-22-3325737
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Sweden - Stockholm
Tel: 46-8-5090-4654
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Detroit
Novi, MI
Tel: 248-848-4000
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Houston, TX
Tel: 281-894-5983
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Los Angeles
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Taiwan - Kaohsiung
Tel: 886-7-213-7828
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
06/23/16
DS00002202A-page 66
2016 Microchip Technology Inc.
相关型号：
©2020 ICPDF网 联系我们和版权申明