MCP3201T-CI/SNVAO [MICROCHIP]
ADC, Successive Approximation, 12-Bit, 1 Func, 1 Channel, Serial Access, CMOS, PDSO8;
| 型号： | MCP3201T-CI/SNVAO |
| 厂家： | 
MICROCHIP |
| 描述： | ADC, Successive Approximation, 12-Bit, 1 Func, 1 Channel, Serial Access, CMOS, PDSO8 转换器 |
| 文件： | 总20页 (文件大小：367K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP3201
2.7V 12-Bit A/D Converter with SPI® Serial Interface
FEATURES
PACKAGE TYPES
• 12-bit resolution
• ±1 LSB max DNL
PDIP
• ±1 LSB max INL (MCP3201-B)
• ±2 LSB max INL (MCP3201-C)
• On-chip sample and hold
VREF
1
8
VDD
IN+
IN–
VSS
2
3
4
7
6
5
CLK
DOUT
• SPI® serial interface (modes 0,0 and 1,1)
• Single supply operation: 2.7V - 5.5V
• 100ksps max. sampling rate at VDD = 5V
• 50ksps max. sampling rate at VDD = 2.7V
CS/SHDN
SOIC, TSSOP
• Low power CMOS technology
- 500nA typical standby current, 2µA max.
- 400µA max. active current at 5V
• Industrial temp range: -40°C to +85°C
8
1
2
3
4
VDD
VREF
7
6
5
CLK
IN+
IN–
VSS
DOUT
• 8-pin PDIP, SOIC and TSSOP packages
CS/SHDN
APPLICATIONS
• Sensor Interface
• Process Control
FUNCTIONAL BLOCK DIAGRAM
• Data Acquisition
VSS
VDD
• Battery Operated Systems
VREF
DESCRIPTION
The Microchip Technology Inc. MCP3201 is a succes-
sive approximation 12-bit Analog-to-Digital (A/D) Con-
verter with on-board sample and hold circuitry. The
device provides a single pseudo-differential input. Dif-
ferential Nonlinearity (DNL) is specified at ±1 LSB, and
Integral Nonlinearity (INL) is offered in ±1 LSB
(MCP3201-B) and ±2 LSB (MCP3201-C) versions.
Communication with the device is done using a simple
serial interface compatible with the SPI protocol. The
device is capable of sample rates of up to 100ksps at a
clock rate of 1.6MHz. The MCP3201 operates over a
broad voltage range (2.7V - 5.5V). Low current design
permits operation with typical standby and active cur-
rents of only 500nA and 300µA, respectively. The
device is offered in 8-pin PDIP, TSSOP and 150mil
SOIC packages.
DAC
Comparator
12-Bit SAR
IN+
IN-
Sample
and
Hold
Shift
Register
Control Logic
CS/SHDN CLK
DOUT
1999 Microchip Technology Inc.
Preliminary
DS21290B-page 1
MCP3201
1.0
ELECTRICAL
PIN FUNCTION TABLE
CHARACTERISTICS
NAME
FUNCTION
1.1
Maximum Ratings*
VDD
VSS
IN+
IN-
CLK
DOUT
CS/SHDN
VREF
+2.7V to 5.5V Power Supply
Ground
Positive Analog Input
Negative Analog Input
Serial Clock
Serial Data Out
Chip select/Shutdown Input
Reference Voltage Input
VDD.........................................................................7.0V
All inputs and outputs w.r.t. VSS ...... -0.6V to VDD +0.6V
Storage temperature ..........................-65°C to +150°C
Ambient temp. with power applied......-65°C to +125°C
Soldering temperature of leads (10 seconds) ..+300°C
ESD protection on all pins...................................> 4kV
*Notice: Stresses above those listed under “Maximum ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended peri-
ods may affect device reliability.
ELECTRICAL CHARACTERISTICS
All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TAMB = -40°C to +85°C, fSAMPLE = 100ksps
and fCLK = 16*fSAMPLE unless otherwise noted.
PARAMETER
Conversion Rate
SYMBOL
MIN.
TYP.
MAX.
UNITS
CONDITIONS
Conversion Time
tCONV
12
clock
cycles
Analog Input Sample Time
Throughput Rate
tSAMPLE
fSAMPLE
1.5
clock
cycles
100
50
ksps VDD = VREF = 5V
ksps VDD = VREF = 2.7V
DC Accuracy
Resolution
12
bits
Integral Nonlinearity
INL
±0.75
±1
±1
±2
LSB
LSB
MCP3201-B
MCP3201-C
Differential Nonlinearity
DNL
±0.5
±1
LSB
No missing codes over tem-
perature
Offset Error
±1.25
±1.25
±3
±5
LSB
LSB
Gain Error
Dynamic Performance
Total Harmonic Distortion
-82
72
dB
dB
VIN = 0.1V to 4.9V@1kHz
VIN = 0.1V to 4.9V@1kHz
Signal to Noise and Distortion
(SINAD)
Spurious Free Dynamic Range
Reference Input
86
dB
VIN = 0.1V to 4.9V@1kHz
Voltage Range
0.25
VDD
V
Note 2
Current Drain
100
.001
150
3
µA
µA
CS = VDD = 5V
Analog Inputs
Input Voltage Range (IN+)
IN-
VREF+IN-
V
Input Voltage Range (IN-)
VSS-100
VSS+100
±1
mV
Leakage Current
Switch Resistance
0.001
1K
µA
RSS
Ω
See Figure 4-1
See Figure 4-1
Sample Capacitor
CSAMPLE
20
pF
DS21290B-page 2
Preliminary
1999 Microchip Technology Inc.
MCP3201
ELECTRICAL CHARACTERISTICS (CONTINUED)
All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TAMB = -40°C to +85°C, fSAMPLE = 100ksps
and fCLK = 16*fSAMPLE unless otherwise noted.
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNITS
CONDITIONS
Digital Input/Output
Data Coding Format
High Level Input Voltage
Straight Binary
VIH
VIL
0.7 VDD
V
V
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Output Leakage Current
0.3 VDD
VOH
4.1
V
IOH = -1mA, VDD = 4.5V
IOL = 1mA, VDD = 4.5V
VIN = VSS or VDD
VOL
0.4
10
10
10
V
ILI
-10
µA
µA
pF
ILO
-10
VOUT = VSS or VDD
Pin Capacitance (all
inputs/outputs)
CIN, COUT
VDD = 5.0V (Note 1)
TAMB = 25°C, f = 1 MHz
Timing Parameters
Clock Frequency
fCLK
1.6
0.8
MHz VDD = 5V (Note 3)
MHz VDD = 2.7V (Note 3)
Clock High Time
Clock Low Time
tHI
tLO
312
312
100
ns
ns
ns
CS Fall To First Rising CLK
Edge
tSUCS
CLK Fall To Output Data Valid
CLK Fall To Output Enable
CS Rise To Output Disable
tDO
tEN
tDIS
200
200
100
ns
ns
ns
See Test Circuits, Figure 1-2
See Test Circuits, Figure 1-2
See Test Circuits, Figure 1-2
(Note 1)
CS Disable Time
tCSH
tR
625
2.7
ns
ns
DOUT Rise Time
100
100
See Test Circuits, Figure 1-2
(Note 1)
DOUT Fall Time
tF
ns
See Test Circuits, Figure 1-2
(Note 1)
Power Requirements
Operating Voltage
VDD
IDD
5.5
V
Operating Current
300
210
400
µA
µA
VDD = 5.0V, DOUT unloaded
VDD = 2.7V, DOUT unloaded
Standby Current
IDDS
0.5
2
µA
CS = VDD = 5.0V
Note 1: This parameter is guaranteed by characterization and not 100% tested.
2: See graph that relates linearity performance to VREF level.
3: Because the sample cap will eventually lose charge, effective clock rates below 10kHz can affect linearity
performance, especially at elevated temperatures. See Section 6.2 for more information.
1999 Microchip Technology Inc.
Preliminary
DS21290B-page 3
MCP3201
tCSH
CS
tSUCS
tHI
tLO
CLK
tEN
tDO
tDIS
tR
tF
HI-Z
HI-Z
DOUT
LSB
MSB OUT
NULL BIT
FIGURE 1-1: Serial Timing.
Load circuit for tDIS and tEN
Load circuit for tR, tF, tDO
1.4V
Test Point
VDD
t
DIS Waveform 2
EN Waveform
DIS Waveform 1
3K
Test Point
VDD/2
3K
100pF
t
DOUT
DOUT
t
CL = 100pF
VSS
Voltage Waveforms for tR, tF
Voltage Waveforms for tEN
VOH
VOL
DOUT
CS
tF
tR
1
2
3
4
CLK
DOUT
B11
tEN
Voltage Waveforms for tDO
Voltage Waveforms for tDIS
VIH
CS
DOUT
CLK
DOUT
90%
tDO
Waveform 1*
TDIS
10%
DOUT
Waveform 2†
*
Waveform 1 is for an output with internal condi-
tions such that the output is high, unless dis-
abled by the output control.
†
Waveform 2 is for an output with internal condi-
tions such that the output is low, unless disabled
by the output control.
FIGURE 1-2: Test Circuits.
DS21290B-page 4
Preliminary
1999 Microchip Technology Inc.
MCP3201
2.0
TYPICAL PERFORMANCE CHARACTERISTICS
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 16*fSAMPLE,TA = 25°C
1.0
0.8
0.6
0.4
0.2
2.0
Positive INL
VDD = VREF = 2.7V
1.5
1.0
Positive INL
0.5
0.0
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
Negative INL
-0.5
-1.0
-1.5
-2.0
Negative INL
0
20
40
60
80
100
0
25
50
75
100
125
150
Sample Rate (ksps)
Sample Rate (ksps)
FIGURE 2-1: Integral Nonlinearity (INL) vs. Sample
FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample
Rate.
Rate (VDD = 2.7V).
2.0
2.0
1.5
VDD = 2.7V
1.5
F
SAMPLE = 50ksps
Positive INL
1.0
0.5
1.0
Positive INL
0.5
0.0
0.0
-0.5
-1.0
-1.5
-2.0
-0.5
-1.0
-1.5
-2.0
Negative INL
Negative INL
0
1
2
3
4
5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VREF (V)
VREF (V)
FIGURE 2-2: Integral Nonlinearity (INL) vs. VREF.
FIGURE 2-5: Integral Nonlinearity (INL) vs. VREF
(VDD = 2.7V).
1.0
0.8
1.0
VDD = VREF = 2.7V
0.8
FSAMPLE = 50ksps
0.6
0.6
0.4
0.4
0.2
0.2
0.0
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
512 1024 1536 2048 2560 3072 3584 4096
Digital Code
0
512 1024 1536 2048 2560 3072 3584 4096
Digital Code
FIGURE 2-3: Integral Nonlinearity (INL) vs. Code
FIGURE 2-6: Integral Nonlinearity (INL) vs. Code
(Representative Part).
(Representative Part, VDD = 2.7V).
1999 Microchip Technology Inc.
Preliminary
DS21290B-page 5
MCP3201
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 16*fSAMPLE,TA = 25°C
1.0
0.8
1.0
0.8
VDD = VREF = 2.7V
FSAMPLE = 50ksps
Positive INL
0.6
0.6
Positive INL
0.4
0.4
0.2
0.2
0.0
0.0
Negative INL
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
Negative INL
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
FIGURE 2-10: Integral
Nonlinearity
(INL)
vs.
FIGURE 2-7: Integral
Nonlinearity
(INL)
vs.
Temperature (VDD = 2.7V).
Temperature.
1.0
0.8
0.6
0.4
0.2
0.0
2.0
VDD = VREF = 2.7V
1.5
1.0
Positive DNL
Positive DNL
0.5
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
Negative DNL
-0.5
-1.0
-1.5
-2.0
Negative DNL
0
25
50
75
100
125
150
0
20
40
60
80
100
Sample Rate (ksps)
Sample Rate (ksps)
FIGURE 2-11: Differential Nonlinearity (DNL) vs.
Sample Rate (VDD = 2.7V).
FIGURE 2-8: Differential Nonlinearity (DNL) vs.
Sample Rate.
3.0
3.0
2.0
VDD = 2.7V
2.0
1.0
FSAMPLE = 50ksps
Positive DNL
1.0
Positive DNL
0.0
0.0
Negative DNL
-1.0
-2.0
-3.0
Negative DNL
-1.0
-2.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0
1
2
3
4
5
VREF(V)
VREF (V)
FIGURE 2-12: Differential Nonlinearity (DNL) vs. VREF
FIGURE 2-9: Differential Nonlinearity (DNL) vs.
(VDD = 2.7V).
VREF.
DS21290B-page 6
Preliminary
1999 Microchip Technology Inc.
MCP3201
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 16*fSAMPLE,TA = 25°C
1.0
0.8
1.0
0.8
VDD = VREF = 2.7V
F
SAMPLE = 50ksps
0.6
0.6
0.4
0.4
0.2
0.2
0.0
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
512 1024 1536 2048 2560 3072 3584 4096
Digital Code
0
512 1024 1536 2048 2560 3072 3584 4096
Digital Code
FIGURE 2-13: Differential Nonlinearity (DNL) vs.
FIGURE 2-16: Differential Nonlinearity (DNL) vs.
Code (Representative Part).
Code (Representative Part, VDD = 2.7V).
1.0
0.8
0.6
1.0
VDD = VREF = 2.7V
0.8
F
SAMPLE = 50ksps
0.6
0.4
Positive DNL
Negative DNL
0.4
Positive DNL
0.2
0.0
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
Negative DNL
-0.4
-0.6
-0.8
-1.0
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
FIGURE 2-14: Differential Nonlinearity (DNL) vs.
FIGURE 2-17: Differential Nonlinearity (DNL) vs.
Temperature.
Temperature (VDD = 2.7V).
20
18
5
4
VDD = 5V
16
VDD = 2.7V
SAMPLE = 50ksps
F
SAMPLE = 100ksps
3
14
12
10
8
F
2
1
VDD = 2.7V
SAMPLE = 50ksps
6
0
F
VDD = 5V
SAMPLE = 100ksps
4
-1
-2
F
2
0
0
1
2
3
4
5
0
1
2
3
4
5
VREF(V)
VREF (V)
FIGURE 2-15: Gain Error vs. VREF.
FIGURE 2-18: Offset Error vs. VREF.
1999 Microchip Technology Inc.
Preliminary
DS21290B-page 7
MCP3201
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 16*fSAMPLE,TA = 25°C
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.0
0.8
0.6
VDD = VREF = 5V
SAMPLE = 100ksps
VDD = VREF = 2.7V
FSAMPLE = 50ksps
F
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
VDD = VREF = 2.7V
SAMPLE = 50ksps
F
VDD = VREF = 5V
FSAMPLE = 100ksps
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
FIGURE 2-19: Gain Error vs. Temperature.
FIGURE 2-22: Offset Error vs. Temperature.
100
100
VDD = VREF = 5V
FSAMPLE = 100ksps
90
80
70
60
50
40
30
20
10
0
VDD = VREF = 5V
FSAMPLE = 100ksps
90
80
70
60
50
40
30
20
10
0
VDD = VREF = 2.7V
FSAMPLE = 50ksps
VDD = VREF = 2.7V
FSAMPLE = 50ksps
1
10
100
1
10
100
Input Frequency (kHz)
Input Frequency (kHz)
FIGURE 2-20: Signal to Noise Ratio (SNR) vs. Input
FIGURE 2-23:
Signal to Noise and Distortion
Frequency.
(SINAD) vs. Input Frequency.
0
-10
-20
-30
80
VDD = 5V
FSAMPLE = 100ksps
70
60
50
40
30
20
10
0
-40
VDD = VREF = 2.7V
VDD = 2.7V
F
SAMPLE = 50ksps
-50
-60
FSAMPLE = 50ksps
-70
-80
VDD = VREF = 5V
SAMPLE = 100ksps
-90
F
-100
-40
-35
-30
-25
-20
-15
-10
-5
0
1
10
100
Input Signal Level (dB)
Input Frequency (kHz)
FIGURE 2-21: Total Harmonic Distortion (THD) vs.
FIGURE 2-24:
Signal to Noise and Distortion
Input Frequency.
(SINAD) vs. Input Signal Level.
DS21290B-page 8
Preliminary
1999 Microchip Technology Inc.
MCP3201
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 16*fSAMPLE,TA = 25°C
12.0
11.5
11.0
10.5
10.0
9.5
12.00
11.75
11.50
11.25
11.00
10.75
10.50
10.25
10.00
9.75
VDD = 5V
FSAMPLE = 100ksps
VDD = VREF = 5V
FSAMPLE =100ksps
VDD = VREF = 2.7V
FSAMPLE = 50ksps
9.0
VDD = 2.7V
9.50
9.25
FSAMPLE = 50ksps
8.5
9.00
8.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VREF (V)
1
10
100
Input Frequency (kHz)
FIGURE 2-25: Effective Number of Bits (ENOB) vs.
FIGURE 2-28: Effective Number of Bits (ENOB) vs.
VREF.
Input Frequency.
0
-10
-20
-30
-40
-50
-60
-70
-80
100
VDD = VREF = 5V
SAMPLE = 100ksps
90
F
80
70
60
50
40
30
20
10
0
VDD = VREF = 2.7V
SAMPLE = 50ksps
F
1
10
100
1
10
100
1000
10000
Input Frequency (kHz)
Ripple Frequency (kHz)
FIGURE 2-26: Spurious Free Dynamic Range
FIGURE 2-29: Power Supply Rejection (PSR) vs.
(SFDR) vs. Input Frequency.
Ripple Frequency.
0
0
-10
-20
-30
-10
-20
-30
VDD = VREF = 2.7V
VDD = VREF = 5V
F
F
SAMPLE = 50ksps
INPUT = 998.76Hz
FSAMPLE = 100ksps
FINPUT = 9.985kHz
4096 points
-40
-40
4096 points
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-130
-100
-110
-120
-130
0
10000
20000
30000
40000
50000
0
5000
10000
15000
20000
25000
Frequency (Hz)
Frequency (Hz)
FIGURE 2-27: Frequency Spectrum of 10kHz input
FIGURE 2-30: Frequency Spectrum of 1kHz input
(Representative Part).
(Representative Part, VDD = 2.7V).
1999 Microchip Technology Inc.
Preliminary
DS21290B-page 9
MCP3201
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 16*fSAMPLE,TA = 25°C
500
450
400
350
300
250
200
150
100
50
100
90
80
70
60
50
40
30
20
10
0
VREF = VDD
VREF = VDD
All points at FCLK = 1.6MHz except
at VREF = VDD = 2.5V, FCLK = 800kHz
All points at FCLK = 1.6MHz except
at VREF = VDD = 2.5V, FCLK = 800kHz
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
10000
100
VDD (V)
VDD (V)
FIGURE 2-31: IDD vs. VDD.
FIGURE 2-34: IREF vs. VDD.
100
90
400
350
VDD = VREF = 5V
80
70
60
50
40
30
20
10
0
VDD = VREF = 5V
300
250
200
150
100
50
VDD = VREF = 2.7V
VDD = VREF = 2.7V
0
10
100
1000
10000
10
100
1000
Clock Frequency (kHz)
Clock Frequency (kHz)
FIGURE 2-35: IREF vs. Clock Frequency.
FIGURE 2-32: IDD vs. Clock Frequency.
100
400
VDD = VREF = 5V
90
350
F
CLK = 1.6MHz
VDD = VREF = 5V
80
70
60
50
40
30
20
10
0
F
CLK = 1.6MHz
300
250
200
150
100
50
VDD = VREF = 2.7V
CLK = 800kHz
VDD = VREF = 2.7V
F
F
CLK = 800kHz
0
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
Temperature (°C)
Temperature (°C)
FIGURE 2-36: IREF vs. Temperature.
FIGURE 2-33: IDD vs. Temperature.
DS21290B-page 10
Preliminary
1999 Microchip Technology Inc.
MCP3201
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 16*fSAMPLE,TA = 25°C
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
80
70
60
50
40
30
20
10
0
VREF = CS = VDD
VDD = VREF = 5V
CLK = 1.6Mhz
F
-50
-25
0
25
50
75
100
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
Temperature (°C)
FIGURE 2-39: Analog Input Leakage Current vs.
Temperature.
FIGURE 2-37: IDDS vs. VDD.
100.00
VDD = VREF = CS = 5V
10.00
1.00
0.10
0.01
-50
-25
0
25
50
75
100
Temperature (°C)
FIGURE 2-38: IDDS vs. Temperature.
1999 Microchip Technology Inc.
Preliminary
DS21290B-page 11
MCP3201
In this diagram, it is shown that the source impedance
(RS) adds to the internal sampling switch (RSS) imped-
ance, directly affecting the time that is required to
charge the capacitor (CSAMPLE). Consequently, a larger
source impedance increases the offset, gain, and inte-
gral linearity errors of the conversion.
3.0
PIN DESCRIPTIONS
3.1
IN+
Positive analog input. This input can vary from IN- to
VREF + IN-.
Ideally, the impedance of the signal source should be
near zero. This is achievable with an operational ampli-
fier such as the MCP601, which has a closed loop out-
put impedance of tens of ohms. The adverse affects of
higher source impedances are shown in Figure 4-2.
3.2
IN-
Negative analog input. This input can vary ±100mV
from VSS.
3.3
CS/SHDN(Chip Select/Shutdown)
If the voltage level of IN+ is equal to or less than IN-, the
resultant code will be 000h. If the voltage at IN+ is equal
to or greater than {[VREF + (IN-)] - 1 LSB}, then the out-
put code will be FFFh. If the voltage level at IN- is more
than 1 LSB below VSS, then the voltage level at the IN+
input will have to go below VSS to see the 000h output
code. Conversely, if IN- is more than 1 LSB above Vss,
then the FFFh code will not be seen unless the IN+
input level goes above VREF level.
The CS/SHDN pin is used to initiate communication
with the device when pulled low and will end a conver-
sion and put the device in low power standby when
pulled high. The CS/SHDN pin must be pulled high
between conversions.
3.4
CLK (Serial Clock)
The SPI clock pin is used to initiate a conversion and to
clock out each bit of the conversion as it takes place.
See Section 6.2 for constraints on clock speed.
4.2
Reference Input
3.5
DOUT (Serial Data output)
The reference input (VREF) determines the analog input
voltage range and the LSB size, as shown below.
The SPI serial data output pin is used to shift out the
results of the A/D conversion. Data will always change
on the falling edge of each clock as the conversion
takes place.
LSB Size = VREF
4096
As the reference input is reduced, the LSB size is
reduced accordingly. The theoretical digital output code
produced by the A/D Converter is a function of the ana-
log input signal and the reference input as shown
below.
4.0
DEVICE OPERATION
The MCP3201 A/D Converter employs a conventional
SAR architecture. With this architecture, a sample is
acquired on an internal sample/hold capacitor for
1.5 clock cycles starting on the first rising edge of the
serial clock after CS has been pulled low. Following this
sample time, the input switch of the converter opens
and the device uses the collected charge on the inter-
nal sample and hold capacitor to produce a serial 12-bit
digital output code. Conversion rates of 100ksps are
possible on the MCP3201. See Section 6.2 for informa-
tion on minimum clock rates. Communication with the
device is done using a 3-wire SPI-compatible interface.
Digital Output Code = 4096 * VIN
VREF
where:
VIN = analog input voltage = V(IN+) - V(IN-)
VREF = reference voltage
When using an external voltage reference device, the
system designer should always refer to the manufac-
turer’s recommendations for circuit layout. Any instabil-
ity in the operation of the reference device will have a
direct effect on the operation of the A/D Converter.
4.1
Analog Inputs
The MCP3201 provides a single pseudo-differential
input. The IN+ input can range from IN- to VREF
(VREF +IN-). The IN- input is limited to ±100mV from the
VSS rail. The IN- input can be used to cancel small sig-
nal common-mode noise which is present on both the
IN+ and IN- inputs.
For the A/D Converter to meet specification, the charge
holding capacitor (CSAMPLE) must be given enough time
to acquire a 12-bit accurate voltage level during the
1.5 clock cycle sampling period. The analog input
model is shown in Figure 4-1.
DS21290B-page 12
Preliminary
1999 Microchip Technology Inc.
MCP3201
VDD
Sampling
Switch
VT = 0.6V
VT = 0.6V
RSS = 1kΩ
CHx
SS
RS
CSAMPLE
= DAC capacitance
= 20 pF
CPIN
7pF
ILEAKAGE
±1nA
VA
VSS
Legend
VA = Signal Source
RS = Source Impedance
CHx = Input Channel Pad
CPIN = Input Capacitance
VT = Threshold Voltage
ILEAKAGE = Leakage Current at the pin
due to various junctions
SS = Sampling Switch
RSS = Sampling Switch Resistor
CSAMPLE = Sample/Hold Capacitance
FIGURE 4-1: Analog Input Model.
1.8
VDD = VREF = 5V
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
VDD = VREF = 2.7V
100
1000
Input Resistance (Ohms)
10000
FIGURE 4-2: Maximum Clock Frequency vs. Input
Resistance (RS) to maintain less than a 0.1 LSB
deviation in INL from nominal conditions.
1999 Microchip Technology Inc.
Preliminary
DS21290B-page 13
MCP3201
sion with MSB first, as shown in Figure 5-1. Data is
always output from the device on the falling edge of the
clock. If all 12 data bits have been transmitted and the
device continues to receive clocks while the CS is held
low, the device will output the conversion result LSB
first, as shown in Figure 5-2. If more clocks are pro-
vided to the device while CS is still low (after the LSB
first data has been transmitted), the device will clock
out zeros indefinitely.
5.0
SERIAL COMMUNICATIONS
Communication with the device is done using a stan-
dard SPI-compatible serial interface. Initiating commu-
nication with the MCP3201 begins with the CS going
low. If the device was powered up with the CS pin low,
it must be brought high and back low to initiate commu-
nication. The device will begin to sample the analog
input on the first rising edge after CS goes low. The
sample period will end in the falling edge of the second
clock, at which time the device will output a low null bit.
The next 12 clocks will output the result of the conver-
tCYC
tCSH
CS
Power
Down
tSUCS
CLK
tDATA**
tCONV
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*
tSAMPLE
HI-Z
HI-Z
NULL
BIT
NULL
BIT
DOUT
B11 B10 B9 B8
* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output LSB first data, followed
by zeros indefinitely. See Figure below.
** tDATA: during this time, the bias current and the comparator power down and the reference input becomes a high impedance
node, leaving the CLK running to clock out the LSB-first data or zeros.
FIGURE 5-1: Communication with MCP3201 using MSB first Format.
tCYC
tCSH
CS
tSUCS
Power Down
CLK
tSAMPLE
tDATA**
tCONV
HI-Z
HI-Z
NULL
BIT
DOUT
B4 B5 B6 B7 B8 B9 B10 B11*
B1 B2 B3
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely.
** tDATA: during this time, the bias current and the comparator power down and the reference input becomes a high impedance
node, leaving the CLK running to clock out the LSB-first data or zeros.
FIGURE 5-2: Communication with MCP3201 using LSB first Format.
DS21290B-page 14
Preliminary
1999 Microchip Technology Inc.
MCP3201
(the output is at high impedance for the first two clocks),
the null bit and the highest order five bits of the conver-
sion. After the second eight clocks have been sent to
the device, the MCU receive register will contain the
lowest order seven bits and the B1 bit repeated as the
A/D Converter has begun to shift out LSB first data with
the extra clock. Typical procedure would then call for
the lower order byte of data to be shifted right by one bit
to remove the extra B1 bit. The B7 bit is then trans-
ferred from the high order byte to the lower order byte,
and then the higher order byte is shifted one bit to the
right as well. Easier manipulation of the converted data
can be obtained by using this method.
6.0
APPLICATIONS INFORMATION
6.1
Using the MCP3201 with
Microcontroller SPI Ports
With most microcontroller SPI ports, it is required to
clock out eight bits at a time. If this is the case, it will be
necessary to provide more clocks than are required for
the MCP3201. As an example, Figure 6-1 and
Figure 6-2 show how the MCP3201 can be interfaced
to a microcontroller with a standard SPI port. Since the
MCP3201 always clocks data out on the falling edge of
clock, the MCU SPI port must be configured to match
this operation. SPI Mode 0,0 (clock idles low) and SPI
Mode 1,1 (clock idles high) are both compatible with the
MCP3201. Figure 6-1 depicts the operation shown in
SPI Mode 0,0, which requires that the CLK from the
microcontroller idles in the ‘low’ state. As shown in the
diagram, the MSB is clocked out of the A/D Converter
on the falling edge of the third clock pulse. After the first
eight clocks have been sent to the device, the micro-
controller’s receive buffer will contain two unknown bits
Figure 6-2 shows the same thing in SPI Mode 1,1
which requires that the clock idles in the high state. As
with mode 0,0, the A/D Converter outputs data on the
falling edge of the clock and the MCU latches data from
the A/D Converter in on the rising edge of the clock.
CS
MCU latches data from A/D Converter
on rising edges of SCLK
1
2
3
4
5
6
7
8
CLK
9
10
11
12
13
14
15
16
Data is clocked out of
A/D Converter on falling edges
HI-Z
HI-Z
NULL
BIT
B2
B6
B5
B5
B4
B4
B3
B3
B2
B2
B1
B1
B0
B0
B1
B1
B11 B10 B9
B8
B8
B7
B7
DOUT
LSB first data begins
to come out
?
?
0
B11 B10 B9
B6
Data stored into MCU receive register
after transmission of first 8 bits
Data stored into MCU receive register
after transmission of second 8 bits
FIGURE 6-1: SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low).
CS
MCU latches data from A/D Converter
on rising edges of SCLK
8
1
2
3
4
5
6
7
CLK
9
10
11
B4
12
B3
13
14
B1
15
16
Data is clocked out of
A/D Converter on falling edges
HI-Z
HI-Z
NULL
BIT
B6
B5
B2
B0
B1
B1
B11 B10 B9
B8
B7
DOUT
LSB first data begins
to come out
?
?
0
B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Data stored into MCU receive register
after transmission of first 8 bits
Data stored into MCU receive register
after transmission of second 8 bits
FIGURE 6-2: SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high).
1999 Microchip Technology Inc.
Preliminary
DS21290B-page 15
MCP3201
6.2
Maintaining Minimum Clock Speed
6.4
Layout Considerations
When the MCP3201 initiates the sample period,
charge is stored on the sample capacitor. When the
sample period is complete, the device converts one bit
for each clock that is received. It is important for the
user to note that a slow clock rate will allow charge to
bleed off the sample cap while the conversion is taking
place. At 85°C (worst case condition), the part will
maintain proper charge on the sample capacitor for at
least 1.2ms after the sample period has ended. This
means that the time between the end of the sample
period and the time that all 12 data bits have been
clocked out must not exceed 1.2ms (effective clock fre-
quency of 10kHz). Failure to meet this criteria may
induce linearity errors into the conversion outside the
rated specifications. It should be noted that during the
entire conversion cycle, the A/D Converter does not
require a constant clock speed or duty cycle, as long as
all timing specifications are met.
When laying out a printed circuit board for use with ana-
log components, care should be taken to reduce noise
wherever possible. A bypass capacitor should always
be used with this device and should be placed as close
as possible to the device pin. A bypass capacitor value
of 1µF is recommended.
Digital and analog traces should be separated as much
as possible on the board and no traces should run
underneath the device or the bypass capacitor. Extra
precautions should be taken to keep traces with high
frequency signals (such as clock lines) as far as possi-
ble from analog traces.
Use of an analog ground plane is recommended in
order to keep the ground potential the same for all
devices on the board. Providing VDD connections to
devices in a “star” configuration can also reduce noise
by eliminating current return paths and associated
errors. See Figure 6-4. For more information on layout
tips when using A/D Converter, refer to AN688 “Layout
Tips for 12-Bit A/D Converter Applications”.
6.3
Buffering/Filtering the Analog Inputs
If the signal source for the A/D Converter is not a low
impedance source, it will have to be buffered or inaccu-
rate conversion results may occur. See Figure 4-2. It is
also recommended that a filter be used to eliminate any
signals that may be aliased back into the conversion
results. This is illustrated in Figure 6-3 where an op
amp is used to drive the analog input of the MCP3201.
This amplifier provides a low impedance source for the
converter input and a low pass filter, which eliminates
unwanted high frequency noise.
VDD
Connection
Device 4
Device 1
Low pass (anti-aliasing) filters can be designed using
Microchip’s interactive FilterLab™ software. FilterLab
will calculate capacitor and resistor values, as well as
determine the number of poles that are required for the
application. For more information on filtering signals,
see the application note AN699 “Anti-Aliasing Analog
Filters for Data Acquisition Systems.”
Device 3
Device 2
VDD
FIGURE 6-4: VDD traces arranged in
a
‘Star’
10µF
configuration in order to reduce errors caused by
current return paths.
4.096V
Reference
1µF
Tant.
0.1µF
0.1µF
ADI
REF198
1µF
VREF
IN+
MCP3201
IN-
C
1
MCP601
R
1
+
-
R
2
VIN
C
2
R
4
R
3
FIGURE 6-3: The MCP601 Operational Amplifier is
used to implement a 2nd order anti-aliasing filter for
the signal being converted by the MCP3201.
FilterLab is a trademark of Microchip Technology Inc. in
the U.S.A and other countries. All rights reserved.
DS21290B-page 16
Preliminary
1999 Microchip Technology Inc.
MCP3201
MCP3201 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
MCP3201 - G /P
T
Package:
P = PDIP (8 lead)
SN = SOIC (150 mil Body), 8 lead
ST = TSSOP, 8 lead (C Grade only)
Temperature
Range:
I = –40°C to +85°C
Performance
Grade:
B = ±1 LSB INL (TSSOP not available in this grade)
C = ±2 LSB INL
Device:
MCP3201
MCP3201T
12-Bit Serial A/D Converter
12-Bit Serial A/D Converter on tape and reel
(SOIC and TSSOP packages only)
=
=
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277. After September 1, 1999, (480) 786-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
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Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
1999 Microchip Technology Inc.
Preliminary
DS21290B-page 17
MCP3201
NOTES:
DS21290B-page 18
Preliminary
1999 Microchip Technology Inc.
MCP3201
NOTES:
1999 Microchip Technology Inc.
Preliminary
DS21290B-page 19
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All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 11/99
Printed on recycled paper.
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