MCP661T-E/SL [MICROCHIP]

OP-AMP, 8000 uV OFFSET-MAX, 60 MHz BAND WIDTH, PDSO14, 3.90 MM, ROHS COMPLIANT, PLASTIC, SOIC-14;
MCP661T-E/SL
型号: MCP661T-E/SL
厂家: MICROCHIP    MICROCHIP
描述:

OP-AMP, 8000 uV OFFSET-MAX, 60 MHz BAND WIDTH, PDSO14, 3.90 MM, ROHS COMPLIANT, PLASTIC, SOIC-14

光电二极管
文件: 总68页 (文件大小:2680K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
MCP660/1/2/3/4/5/9  
60 MHz, 6 mA Op Amps  
Description  
Features  
• Gain Bandwidth Product: 60 MHz (typical)  
• Short Circuit Current: 90 mA (typical)  
• Noise: 6.8 nV/Hz (typical, at 1 MHz)  
• Rail-to-Rail Output  
The Microchip Technology, Inc. MCP660/1/2/3/4/5/9  
family of operational amplifiers (op amps) features high  
gain bandwidth product (60 MHz, typical) and high  
output short circuit current (90 mA, typical). Some also  
provide a Chip Select pin (CS) that supports a Low  
Power mode of operation. These amplifiers are  
optimized for high speed, low noise and distortion,  
single-supply operation with rail-to-rail output and an  
input that includes the negative rail.  
• Slew Rate: 32 V/µs (typical)  
• Supply Current: 6.0 mA (typical)  
• Power Supply: 2.5V to 5.5V  
• Extended Temperature Range: -40°C to +125°C  
This family is offered in single (MCP661), single with  
CS pin (MCP663), dual (MCP662) and dual with two  
CS pins (MCP665), triple (MCP660), quad (MCP664)  
and quad with two CS pins (MCP669). All devices are  
fully specified from -40°C to +125°C.  
Typical Applications  
• Driving A/D Converters  
• Power Amplifier Control Loops  
• Barcode Scanners  
Typical Application Circuit  
• Optical Detector Amplifier  
R1  
R2  
Design Aids  
VDD/2  
VOUT  
RL  
• SPICE Macro Models  
• FilterLab® Software  
R3  
VIN  
MCP66X  
Power Driver with High Gain  
• Microchip Advanced Part Selector (MAPS)  
• Analog Demonstration and Evaluation Boards  
• Application Notes  
2009-2012 Microchip Technology Inc.  
DS22194D-page 1  
MCP660/1/2/3/4/5/9  
Package Types  
MCP660  
MCP660  
MCP661  
4x4 QFN*  
SOIC, TSSOP  
SOT-23-5  
V
NC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
OUTC  
V
V
V
1
2
3
5
4
DD  
OUT  
V
V
V
-
NC  
NC  
INC  
V
16 15 14 13  
SS  
+
INC  
NC  
NC  
V
V
V
V
+
1
12  
11  
10  
9
INC  
V
DD  
SS  
-
V
+
IN  
IN  
2
3
4
SS  
EP  
17  
V
+
V
V
V
+
INA  
INB  
+
-
V
V
-
INB  
DD  
-
INA  
INB  
V
+
INB  
INA  
V
OUTA  
8
OUTB  
5
6
7
8
MCP661  
SOIC  
MCP661  
2x3 TDFN *  
MCP662  
MSOP, SOIC  
MCP662  
3x3 DFN*  
V
1
8
V
V
DD  
NC  
NC  
V
1
2
3
4
8
NC  
CS  
V
1
2
3
4
8
7
6
5
1
2
8
7
V
OUTA  
DD  
OUTA  
V
V
V
2
3
4
7
6
5
V
-
V
-
V
V
V
7
6
5
V
-
OUTB  
V
INA  
OUTB  
IN  
DD  
INA  
EP  
9
IN  
DD  
EP  
9
-
V
+
V
+
V
V
+
-
INB  
INA  
IN  
OUT  
INA  
INB  
V
+
V
OUT  
3
4
6
5
IN  
+
V
INB  
V
NC  
SS  
V
+
V
NC  
SS  
SS  
INB  
SS  
MCP663  
SOIC  
MCP663  
SOT-23-6  
MCP664  
SOIC, TSSOP  
1
8
7
6
5
NC  
CS  
V
V
V
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
OUTD  
6
5
OUTA  
V
1
2
3
DD  
OUT  
2
3
4
V
-
V
V
V
-
V
V
V
-
IN  
DD  
INA  
IND  
CS  
V
SS  
V
+
V
+
+
INA  
IN  
OUT  
IND  
V
V
NC  
DD  
SS  
SS  
V
-
4
V
+
IN  
IN  
V
+
V
V
V
+
INB  
INC  
V
-
-
INB  
INC  
V
8
OUTB  
OUTC  
MCP665  
MCP665  
MCP669  
3x3 DFN*  
MSOP  
4x4 QFN*  
V
V
1
2
3
4
5
10  
9
8
7
6
V
V
V
V
1
2
3
10  
DD  
OUTA  
OUTA  
DD  
-
V
V
V
INA  
OUTB  
V
-
V
V
V
9
8
7
6
INA  
OUTB  
EP  
11  
+
-
+
INA  
INB  
V
+
16 15 14 13  
-
INA  
INB  
V
SS  
INB  
V
-
V
V
V
V
+
V
+
1
12  
11  
10  
9
INA  
IND  
SS 4  
INB  
CSA  
CSB  
V
+
CSA  
CSB  
2
3
4
5
INA  
SS  
EP  
17  
+
-
V
INC  
DD  
V
+
INC  
INB  
5
6
7
8
* Includes Exposed Thermal Pad (EP); see Table 3-1.  
DS22194D-page 2  
2009-2012 Microchip Technology Inc.  
MCP660/1/2/3/4/5/9  
† Notice: Stresses above those listed under “Absolute  
Maximum Ratings” may cause permanent damage to  
the device. This is a stress rating only and functional  
operation of the device at those or any other conditions  
above those indicated in the operational listings of this  
specification is not implied. Exposure to maximum rat-  
ing conditions for extended periods may affect device  
reliability.  
1.0  
1.1  
ELECTRICAL  
CHARACTERISTICS  
Absolute Maximum Ratings †  
V
– V  
.......................................................................6.5V  
SS  
DD  
Current at Input Pins ....................................................±2 mA  
Analog Inputs (V + and V –) †† . V – 1.0V to V + 1.0V  
IN  
IN  
SS  
DD  
†† See Section 4.1.2 “Input Voltage and Current  
Limits”.  
All other Inputs and Outputs .......... V – 0.3V to V + 0.3V  
SS  
DD  
Output Short Circuit Current ................................Continuous  
Current at Output and Supply Pins ..........................±150 mA  
Storage Temperature ...................................-65°C to +150°C  
Max. Junction Temperature ........................................+150°C  
ESD protection on all pins (HBM, MM)  1 kV, 200V  
1.2  
Specifications  
DC ELECTRICAL SPECIFICATIONS  
TABLE 1-1:  
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND,  
CM = VDD/3, VOUT VDD/2, VL = VDD/2, RL = 1 kto VL and CS = VSS (refer to Figure 1-2).  
V
Parameters  
Sym  
Min  
Typ  
Max  
Units  
Conditions  
Input Offset  
Input Offset Voltage  
VOS  
-8  
61  
±1.8  
±2.0  
76  
+8  
mV  
Input Offset Voltage Drift  
Power Supply Rejection Ratio  
Input Current and Impedance  
Input Bias Current  
VOS/TA  
PSRR  
µV/°C TA= -40°C to +125°C  
dB  
IB  
IB  
6
pA  
Across Temperature  
Across Temperature  
Input Offset Current  
130  
pA TA = +85°C  
pA TA = +125°C  
pA  
IB  
1700  
5,000  
IOS  
ZCM  
±10  
1013||9  
Common Mode Input  
Impedance  
||pF  
Differential Input Impedance  
ZDIFF  
VCMR  
1013||2  
||pF  
Common Mode  
Common-Mode Input Voltage  
Range  
VSS0.3  
VDD 1.3  
V
(Note 1)  
Common-Mode Rejection Ratio  
CMRR  
CMRR  
64  
66  
79  
81  
dB VDD = 2.5V, VCM = -0.3 to 1.2V  
dB VDD = 5.5V, VCM = -0.3 to 4.2V  
Open Loop Gain  
DC Open Loop Gain  
(large signal)  
AOL  
AOL  
88  
94  
117  
126  
dB VDD = 2.5V, VOUT = 0.3V to  
2.2V  
dB VDD = 5.5V, VOUT = 0.3V to  
5.2V  
Note 1: See Figure 2-5 for temperature effects.  
2: The ISC specifications are for design guidance only; they are not tested.  
2009-2012 Microchip Technology Inc.  
DS22194D-page 3  
MCP660/1/2/3/4/5/9  
TABLE 1-1:  
DC ELECTRICAL SPECIFICATIONS (CONTINUED)  
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND,  
VCM = VDD/3, VOUT VDD/2, VL = VDD/2, RL = 1 kto VL and CS = VSS (refer to Figure 1-2).  
Parameters  
Sym  
Min  
Typ  
Max  
Units  
Conditions  
Output  
Maximum Output Voltage Swing VOL, VOH VSS + 25  
VDD 25 mV VDD = 2.5V, G = +2,  
0.5V Input Overdrive  
VOL, VOH VSS + 50  
VDD 50 mV VDD = 5.5V, G = +2,  
0.5V Input Overdrive  
Output Short Circuit Current  
ISC  
ISC  
±45  
±40  
±90  
±80  
±145  
±150  
mA VDD = 2.5V (Note 2)  
mA VDD = 5.5V (Note 2)  
Power Supply  
Supply Voltage  
VDD  
IQ  
2.5  
3
6
5.5  
9
V
Quiescent Current per Amplifier  
mA No Load Current  
Note 1: See Figure 2-5 for temperature effects.  
2: The ISC specifications are for design guidance only; they are not tested.  
TABLE 1-2:  
AC ELECTRICAL SPECIFICATIONS  
Electrical Characteristics: Unless indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2,  
VOUT VDD/2, VL = VDD/2, RL = 1 kto VL, CL = 20 pF and CS = VSS (refer to Figure 1-2).  
Parameters  
AC Response  
Sym  
Min  
Typ  
Max Units  
Conditions  
Gain Bandwidth Product  
Phase Margin  
GBWP  
PM  
60  
65  
10  
MHz  
°
G = +1  
Open Loop Output Impedance  
AC Distortion  
ROUT  
Total Harmonic Distortion plus Noise  
THD+N  
DG  
0.003  
0.3  
%
%
G = +1, VOUT = 2VP-P, f = 1 kHz,  
VDD = 5.5V, BW = 80 kHz  
Differential Gain, Positive Video  
(Note 1)  
NTSC, VDD = +2.5V, VSS = -2.5V,  
G = +2, VL = 0V, DC VIN = 0V to  
0.7V  
Differential Gain, Negative Video  
(Note 1)  
DG  
DP  
DP  
0.3  
0.3  
0.9  
%
°
NTSC, VDD = +2.5V, VSS = -2.5V,  
G = +2, VL = 0V,  
DC VIN = 0V to -0.7V  
Differential Phase, Positive Video  
(Note 1)  
NTSC, VDD = +2.5V, VSS = -2.5V,  
G = +2, VL = 0V,  
DC VIN = 0V to 0.7V  
Differential Phase, Negative Video  
(Note 1)  
°
NTSC, VDD = +2.5V, VSS = -2.5V,  
G = +2, VL = 0V,  
DC VIN = 0V to -0.7V  
Step Response  
Rise Time, 10% to 90%  
Slew Rate  
tr  
5
ns  
G = +1, VOUT = 100 mVP-P  
SR  
32  
V/µs G = +1  
Noise  
Input Noise Voltage  
Input Noise Voltage Density  
Input Noise Current Density  
Eni  
eni  
ini  
14  
6.8  
4
µVP-P f = 0.1 Hz to 10 Hz  
nV/Hz f = 1 MHz  
fA/Hz f = 1 kHz  
Note 1: These specifications are described in detail in Section 4.3 “Distortion”. (NTSC refers to a National  
Television Standards Committee signal.)  
DS22194D-page 4  
2009-2012 Microchip Technology Inc.  
MCP660/1/2/3/4/5/9  
TABLE 1-3:  
DIGITAL ELECTRICAL SPECIFICATIONS  
Electrical Characteristics: Unless indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2,  
VOUT VDD/2, VL = VDD/2, RL = 1 kto VL, CL = 20 pF and CS = VSS (refer to Figure 1-1 and Figure 1-2).  
Parameters  
Sym  
Min  
Typ  
Max Units  
Conditions  
CS Low Specifications  
CS Logic Threshold, Low  
VIL  
VSS  
0.2VD  
D
V
CS Input Current, Low  
ICSL  
-0.1  
nA CS = 0V  
CS High Specifications  
CS Logic Threshold, High  
VIH  
0.8VD  
D
VDD  
V
CS Input Current, High  
GND Current  
ICSH  
ISS  
-0.7  
-1  
µA CS = VDD  
-2  
µA  
CS Internal Pull Down Resistor  
Amplifier Output Leakage  
RPD  
5
M  
IO(LEAK  
40  
nA CS = VDD, TA = +125°C  
)
CS Dynamic Specifications  
CS Input Hysteresis  
VHYST  
tOFF  
0.25  
200  
V
CS High to Amplifier Off Time  
(output goes High-Z)  
ns G = +1 V/V, VL = VSS  
CS = 0.8VDD to VOUT = 0.1(VDD/2)  
G = +1 V/V, VL = VSS  
CS = 0.2VDD to VOUT = 0.9(VDD/2)  
,
CS Low to Amplifier On Time  
tON  
2
10  
µs  
TABLE 1-4:  
TEMPERATURE SPECIFICATIONS  
Electrical Characteristics: Unless indicated, all limits are specified for: VDD = +2.5V to +5.5V, VSS = GND.  
Parameters  
Temperature Ranges  
Sym  
Min  
Typ  
Max Units  
Conditions  
Specified Temperature Range  
TA  
TA  
TA  
-40  
-40  
-65  
+125  
+125  
+150  
°C  
°C  
°C  
Operating Temperature Range  
Storage Temperature Range  
(Note 1)  
Thermal Package Resistances  
Thermal Resistance, 5L-SOT-23  
Thermal Resistance, 6L-SOT-23  
Thermal Resistance, 8L-3x3 DFN  
Thermal Resistance, 8L-MSOP  
Thermal Resistance, 8L-SOIC  
Thermal Resistance, 8L-2x3 TDFN  
Thermal Resistance, 10L-3x3 DFN  
Thermal Resistance, 10L-MSOP  
Thermal Resistance, 14L-SOIC  
Thermal Resistance, 14L-TSSOP  
Thermal Resistance, 16L-QFN  
θJA  
θJA  
JA  
JA  
JA  
θJA  
JA  
JA  
JA  
JA  
JA  
220.7  
190.5  
56.7  
211  
°C/W  
°C/W  
°C/W (Note 2)  
°C/W  
149.5  
52.5  
53.3  
202  
°C/W  
°C/W  
°C/W (Note 2)  
°C/W  
95.3  
100  
°C/W  
°C/W  
45.7  
°C/W  
Note 1: Operation must not cause TJ to exceed Maximum Junction Temperature specification (+150°C).  
2: Measured on a standard JC51-7, four layer printed circuit board with ground plane and vias.  
2009-2012 Microchip Technology Inc.  
DS22194D-page 5  
MCP660/1/2/3/4/5/9  
1.3  
Timing Diagram  
CF  
6.8 pF  
0 nA  
(typical)  
1 µA  
(typical)  
1 µA  
(typical)  
ICS  
CS  
RG  
RF  
10 k  
10 k  
VIH  
VIL  
VDD/2  
VP  
VDD  
tON  
tOFF  
VIN+  
CB1  
100 nF  
CB2  
2.2 µF  
VOUT  
High-Z  
High-Z  
On  
MCP66X  
-6 mA  
(typical)  
-1 µA  
(typical)  
-1 µA  
(typical)  
VIN-  
ISS  
VOUT  
VM  
RL  
1 k  
CL  
20 pF  
RG  
10 k  
RF  
10 k  
FIGURE 1-1:  
Timing Diagram.  
1.4 Test Circuits  
CF  
VL  
The circuit used for most DC and AC tests is shown in  
Figure 1-2. This circuit can independently set VCM and  
VOUT; see Equation 1-1. Note that VCM is not the  
circuit’s Common mode voltage ((VP + VM)/2), and that  
VOST includes VOS plus the effects (on the input offset  
6.8 pF  
FIGURE 1-2:  
AC and DC Test Circuit for  
Most Specifications.  
error, VOST) of temperature, CMRR, PSRR and AOL  
.
EQUATION 1-1:  
GDM = RF RG  
VCM = VP + VDD 22  
VOST = VINVIN+  
VOUT = VDD 2+ VP VM+ VOST1 + GDM  
Where:  
GDM = Differential Mode Gain  
(V/V)  
(V)  
VCM = Op Amp’s Common Mode  
Input Voltage  
VOST = Op Amp’s Total Input Offset (mV)  
Voltage  
DS22194D-page 6  
2009-2012 Microchip Technology Inc.  
MCP660/1/2/3/4/5/9  
2.0  
TYPICAL PERFORMANCE CURVES  
Note:  
The graphs and tables provided following this note are a statistical summary based on a limited number of  
samples and are provided for informational purposes only. The performance characteristics listed herein  
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified  
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.  
Note: Unless indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2,  
RL = 1 kto VL, CL = 20 pF and CS = VSS  
.
2.1  
DC Signal Inputs  
1.4  
1.3  
1.2  
1.1  
1.0  
0.9  
0.8  
0.7  
0.6  
22%  
20%  
18%  
16%  
14%  
12%  
10%  
8%  
6%  
4%  
2%  
0%  
Representative Part  
VDD = 5.5V  
100 Samples  
TA = +25°C  
VDD = 2.5V and 5.5V  
VDD = 2.5V  
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5  
Output Voltage (V)  
-6 -5 -4 -3 -2 -1  
0
1
2
3
4
5
6
Input Offset Voltage (mV)  
FIGURE 2-1:  
Input Offset Voltage.  
FIGURE 2-4:  
Input Offset Voltage vs.  
Output Voltage.  
24%  
0.0  
100 Samples  
DD = 2.5V and 5.5V  
A = -40°C to +125°C  
1 Lot  
Low (VCMR_L – VSS  
22%  
20%  
18%  
16%  
14%  
12%  
10%  
8%  
6%  
4%  
2%  
0%  
V
T
)
-0.1  
-0.2  
-0.3  
-0.4  
-0.5  
VDD = 2.5V  
VDD = 5.5V  
-50  
-25  
0
25  
50  
75  
100 125  
-12 -10 -8 -6 -4 -2  
0
2
4
6
8
10 12  
Ambient Temperature (°C)  
Input Offset Voltage Drift (µV/°C)  
FIGURE 2-2:  
Input Offset Voltage Drift.  
FIGURE 2-5:  
Low Input Common Mode  
Voltage Headroom vs. Ambient Temperature.  
0.0  
1.4  
1 Lot  
High (VDD – VCMR_H  
Representative Part  
CM = VSS  
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
-1.2  
-1.4  
-1.6  
-1.8  
-2.0  
)
V
1.3  
VDD = 2.5V  
1.2  
+125°C  
+85°C  
+25°C  
-40°C  
1.1  
VDD = 5.5V  
1.0  
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5  
Power Supply Voltage (V)  
-50  
-25  
0
25  
50  
75  
100  
125  
Ambient Temperature (°C)  
FIGURE 2-3:  
Input Offset Voltage vs.  
FIGURE 2-6:  
High Input Common Mode  
Power Supply Voltage with VCM = 0V.  
Voltage Headroom vs. Ambient Temperature.  
2009-2012 Microchip Technology Inc.  
DS22194D-page 7  
MCP660/1/2/3/4/5/9  
Note: Unless indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2,  
RL = 1 kto VL, CL = 20 pF and CS = VSS  
.
130  
125  
120  
115  
110  
105  
100  
2.0  
VDD = 2.5V  
Representative Part  
1.5  
1.0  
VDD = 5.5V  
VDD = 2.5V  
-40°C  
+25°C  
+85°C  
+125°  
0.5  
0.0  
-0.5  
-1.0  
-1.5  
-2.0  
-50  
-25  
0
25  
50  
75  
100  
125  
Input Common Mode Voltage (V)  
Ambient Temperature (°C)  
FIGURE 2-7:  
Input Offset Voltage vs.  
FIGURE 2-10:  
DC Open-Loop Gain vs.  
Common Mode Voltage with VDD = 2.5V.  
Ambient Temperature.  
130  
2.0  
VDD = 5.5V  
VDD = 5.5V  
1.5 Representative Part  
125  
120  
115  
110  
105  
100  
95  
1.0  
0.5  
+125°  
VDD = 2.5V  
C
+85°C  
+25°C  
0.0  
-0.5  
-1.0  
-1.5  
-2.0  
100  
1k  
1.E+03  
10k  
1.E+04  
100k  
1.E+05  
1.E+02  
Input Common Mode Voltage (V)  
Load Resistance ()  
FIGURE 2-8:  
Input Offset Voltage vs.  
FIGURE 2-11:  
DC Open-Loop Gain vs.  
Common Mode Voltage with VDD = 5.5V.  
Load Resistance.  
110  
105  
100  
95  
1.E-08  
10n  
VDD = 5.5V  
V
CM = VCMR_H  
1n  
1.E-09  
90  
IB  
PSRR  
85  
80  
100p  
1.E-10  
75  
CMRR, VDD = 2.5V  
CMRR, VDD = 5.5V  
10p  
1.E-11  
70  
65  
60  
| IOS  
|
1p  
1.E-12  
-50  
-25  
0
25  
50  
75  
100  
125  
25  
45  
65  
85  
105  
125  
Ambient Temperature (°C)  
Ambient Temperature (°C)  
FIGURE 2-9:  
CMRR and PSRR vs.  
FIGURE 2-12:  
Input Bias and Offset  
Ambient Temperature.  
Currents vs. Ambient Temperature with  
DD = +5.5V.  
V
DS22194D-page 8  
2009-2012 Microchip Technology Inc.  
MCP660/1/2/3/4/5/9  
Note: Unless indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2,  
RL = 1 kto VL, CL = 20 pF and CS = VSS  
.
1000  
800  
600  
400  
200  
0
1.E-10m3  
1.E10-004µ  
IB  
10µ  
1.E-05  
1µ  
1.E-06  
Representative Part  
A = +125°C  
DD = 5.5V  
100n  
1.E-07  
T
V
10n  
1.E- 8  
1n  
1.E-09  
+125°C  
+85°C  
+25°C  
-40°C  
100p  
1.E-10  
IOS  
-200  
-400  
10p  
1.E-11  
1p  
1.E-12  
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0  
Input Voltage (V)  
Common Mode Input Voltage (V)  
FIGURE 2-13:  
Input Bias Current vs. Input  
FIGURE 2-15:  
Input Bias and Offset  
Voltage (below VSS).  
Currents vs. Common Mode Input Voltage with  
TA = +125°C.  
60  
40  
20  
0
IB  
IOS  
-20  
-40  
-60  
Representative Part  
TA = +85°C  
VDD = 5.5V  
-80  
-100  
-120  
Common Mode Input Voltage (V)  
FIGURE 2-14:  
Input Bias and Offset  
Currents vs. Common Mode Input Voltage with  
TA = +85°C.  
2009-2012 Microchip Technology Inc.  
DS22194D-page 9  
MCP660/1/2/3/4/5/9  
Note: Unless indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2,  
RL = 1 kto VL, CL = 20 pF and CS = VSS  
.
2.2  
Other DC Voltages and Currents  
1000  
9
8
7
6
5
4
3
2
1
0
VDD = 5.5V  
100  
10  
1
VDD = 2.5V  
VOL – VSS  
+125°C  
+85°C  
+25°C  
-40°C  
VDD – VOH  
0.1  
1
10  
100  
Power Supply Voltage (V)  
Output Current Magnitude (mA)  
FIGURE 2-16:  
Output Voltage Headroom  
FIGURE 2-19:  
Supply Current vs. Power  
vs. Output Current.  
Supply Voltage.  
45  
7
6
5
RL = 1 k  
40  
35  
VOL – VSS  
VDD = 5.5V  
VDD = 5.5V  
30  
VDD = 2.5V  
4
3
2
1
0
25  
20  
15  
10  
5
VDD = 2.5V  
VDD – VOH  
0
-50  
-25  
0
25  
50  
75  
100  
125  
Common Mode Input Voltage (V)  
Ambient Temperature (°C)  
FIGURE 2-17:  
Output Voltage Headroom  
FIGURE 2-20:  
Supply Current vs. Common  
vs. Ambient Temperature.  
Mode Input Voltage.  
100  
80  
60  
+125°C  
+85°C  
+25°C  
-40°C  
40  
20  
0
-20  
-40  
-60  
-80  
-100  
Power Supply Voltage (V)  
FIGURE 2-18:  
Output Short Circuit Current  
vs. Power Supply Voltage.  
DS22194D-page 10  
2009-2012 Microchip Technology Inc.  
MCP660/1/2/3/4/5/9  
Note: Unless indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2,  
RL = 1 kto VL, CL = 20 pF and CS = VSS  
.
2.3  
Frequency Response  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
80  
75  
70  
65  
60  
55  
50  
45  
40  
80  
75  
70  
65  
60  
55  
50  
45  
40  
PM  
VDD = 5.5V  
VDD = 2.5V  
CMRR  
PSRR+  
PSRR-  
GBWP  
100  
1k  
10k  
100k  
1M  
10M  
1.E+7  
1.E+2  
1.E+3  
1.E+4  
1.E+5  
1.E+6  
Common Mode Input Voltage (V)  
Frequency (Hz)  
FIGURE 2-21:  
CMRR and PSRR vs.  
FIGURE 2-24:  
Gain Bandwidth Product  
Frequency.  
and Phase Margin vs. Common Mode Input  
Voltage.  
140  
120  
100  
80  
0
80  
75  
70  
65  
60  
55  
50  
45  
40  
80  
-30  
-60  
-90  
75  
70  
65  
60  
55  
50  
45  
40  
PM  
AOL  
VDD = 5.5V  
VDD = 2.5V  
60  
-120  
-150  
-180  
-210  
-240  
40  
| AOL  
|
20  
GBWP  
0
-20  
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5  
Output Voltage (V)  
1
0
10 100 1k 10k100k 11.ME+ 10M 100M11.EG+  
1.E+ 1.E+  
1.E+ 1.E+ 1.E+ 1.E+ 1.E+ 1.E+  
1
2
3
4
6
7
8
9
Frequenc5y (Hz)  
FIGURE 2-22:  
Open-Loop Gain vs.  
FIGURE 2-25:  
Gain Bandwidth Product  
Frequency.  
and Phase Margin vs. Output Voltage.  
100  
80  
75  
70  
65  
80  
75  
70  
65  
60  
55  
50  
45  
40  
10  
PM  
G = 101 V/V  
G = 11 V/V  
G = 1 V/V  
VDD = 5.5V  
VDD = 2.5V  
60  
55  
50  
45  
40  
1
GBWP  
0.1  
-50 -25  
0
25  
50  
75 100 125  
10k  
100k  
1.0E+05  
1M  
10M  
1.0E+07  
100M  
1.0E+04  
1.0E+06  
1.0E+08  
Ambient Temperature (°C)  
Frequency (Hz)  
FIGURE 2-23:  
Gain Bandwidth Product  
FIGURE 2-26:  
Closed-Loop Output  
and Phase Margin vs. Ambient Temperature.  
Impedance vs. Frequency.  
2009-2012 Microchip Technology Inc.  
DS22194D-page 11  
MCP660/1/2/3/4/5/9  
Note: Unless indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2,  
RL = 1 kto VL, CL = 20 pF and CS = VSS  
.
10  
9
150  
140  
130  
120  
110  
100  
90  
RS = 0  
RS = 100Ω  
RS = 1 kΩ  
8
VCM = VDD/2  
G = +1 V/V  
7
GN = 1 V/V  
GN = 2 V/V  
GN 4 V/V  
6
5
4
3
2
1
0
80  
70  
RS = 10 kΩ  
RS = 100 kΩ  
60  
50  
10p  
1.0E-11  
100p  
1.0E-10  
Normalized Capacitive Load; CL/GN (F)  
1n  
1.0E-09  
1k  
10k  
1.E+04  
100k  
1.E+05  
1M  
1.E+06  
10M  
1.E+07  
1.E+03  
Frequency (Hz)  
FIGURE 2-27:  
Gain Peaking vs.  
FIGURE 2-28:  
Channel-to-Channel  
Normalized Capacitive Load.  
Separation vs. Frequency.  
DS22194D-page 12  
2009-2012 Microchip Technology Inc.  
MCP660/1/2/3/4/5/9  
Note: Unless indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2,  
RL = 1 kto VL, CL = 20 pF and CS = VSS  
.
2.4  
Noise and Distortion  
1.E+4  
10µ  
20  
15  
10  
5
Representative Part  
1.E1+µ3  
0
1.E+2  
100n  
-5  
-10  
-15  
-20  
Analog NPBW = 0.1 Hz  
Sample Rate = 2 SPS  
VOS = -953 µV  
11.E0+n1  
1.E1+n0  
0
5 10 15 20 25 30 35 40 45 50 55 60 65  
0.1  
1
10 100 1.1E+k3 10k 100k 11.EM+6 10M  
1.E-1 1.E+0 1.E+1 1.E+2 1.E+4 1.E+5 1.E+7  
Frequency (Hz)  
Time (min)  
FIGURE 2-29:  
Input Noise Voltage Density  
FIGURE 2-32:  
Input Noise vs. Time with  
vs. Frequency.  
0.1 Hz Filter.  
200  
180  
1
VDD = 5.0V  
VOUT = 2 VP-P  
VDD = 2.5V  
160  
140  
120  
100  
80  
0.1  
0.01  
G = 1 V/V  
G = 11 V/V  
BW = 22 Hz to > 500 kHz  
BW = 22 Hz to 80 kHz  
VDD = 5.5V  
60  
0.001  
40  
20  
f = 100 Hz  
0
0.0001  
100  
1.E+2  
1k  
1.E+3  
10k  
1.E+4  
100k  
1.E+5  
Frequency (Hz)  
Common Mode Input Voltage (V)  
FIGURE 2-30:  
Input Noise Voltage Density  
FIGURE 2-33:  
THD+N vs. Frequency.  
vs. Input Common Mode Voltage with f = 100 Hz.  
20  
18  
16  
0.2  
0.1  
0.0  
0.2  
Positive Video  
0.1  
Negative Video  
0.0  
-0.1  
-0.2  
-0.3  
-0.4  
-0.5  
-0.6  
-0.7  
-0.8  
-0.9  
-1.0  
-0.1  
-0.2  
-0.3  
14  
VDD = 2.5V  
12  
10  
8
VDD = 5.5V  
Δ(|G|)  
Representative Part  
DD = 2.5V  
VSS = -2.5V  
VL = 0V  
RL = 150  
-0.4  
V
-0.5  
-0.6  
-0.7  
-0.8  
-0.9  
-1.0  
6
4
Normalized to DC VIN = 0V  
NTSC  
2
f = 1 MHz  
Δ( G)  
0
-0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8  
DC Input Voltage (V)  
Common Mode Input Voltage (V)  
FIGURE 2-31:  
Input Noise Voltage Density  
FIGURE 2-34:  
Change in Gain Magnitude  
vs. Input Common Mode Voltage with f = 1 MHz.  
and Phase vs. DC Input Voltage.  
2009-2012 Microchip Technology Inc.  
DS22194D-page 13  
MCP660/1/2/3/4/5/9  
Note: Unless indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2,  
RL = 1 kto VL, CL = 20 pF and CS = VSS  
.
2.5  
Time Response  
5.5  
5.0  
4.5  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
VDD = 5.5V  
G = 1  
VDD = 5.5V  
G = -1  
RF = 402Ω  
VIN  
VIN  
VOUT  
VOUT  
0
20 40 60 80 100 120 140 160 180 200  
Time (ns)  
0
100  
200  
300  
Time (ns)  
400  
500  
600  
FIGURE 2-35:  
Non-inverting Small Signal  
FIGURE 2-38:  
Inverting Large Signal Step  
Step Response.  
Response.  
5.5  
5.0  
4.5  
4.0  
3.5  
3.0  
7
6
VDD = 5.5V  
G = 2  
VDD = 5.5V  
G = 1  
VOUT  
5
VIN  
4
3
2.5  
VIN  
VOUT  
2
2.0  
1.5  
1.0  
0.5  
0.0  
1
0
-1  
0
100 200 300 400 500 600 700 800  
Time (ns)  
0
1
2
3
4
5
6
7
8
9
10  
Time (µs)  
FIGURE 2-36:  
Non-inverting Large Signal  
FIGURE 2-39:  
The MCP660/1/2/3/4/5/9  
Step Response.  
family shows no input phase reversal with  
overdrive.  
50  
Falling Edge  
VIN  
45  
VDD = 5.5V  
40  
35  
30  
25  
20  
15  
10  
5
VDD = 5.5V  
G = -1  
RF = 402Ω  
VDD = 2.5V  
Rising Edge  
VOUT  
0
0
50 100 150 200 250 300 350 400 450 500  
Time (ns)  
-50  
-25  
0
25  
50  
75  
100  
125  
Ambient Temperature (°C)  
FIGURE 2-37:  
Inverting Small Signal Step  
FIGURE 2-40:  
Slew Rate vs. Ambient  
Response.  
Temperature.  
DS22194D-page 14  
2009-2012 Microchip Technology Inc.  
MCP660/1/2/3/4/5/9  
Note: Unless indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2,  
RL = 1 kto VL, CL = 20 pF and CS = VSS  
.
10  
VDD = 5.5V  
VDD = 2.5V  
1
0.1  
100k  
1M  
1.E+06  
10M  
1.E+07  
100M  
1.E+08  
1.E+05  
Frequency (Hz)  
FIGURE 2-41:  
Maximum Output Voltage  
Swing vs. Frequency.  
2009-2012 Microchip Technology Inc.  
DS22194D-page 15  
MCP660/1/2/3/4/5/9  
Note: Unless indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2,  
RL = 1 kto VL, CL = 20 pF and CS = VSS  
.
2.6  
Chip Select Response  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0.0  
0.40  
0.35  
0.30  
0.25  
0.20  
0.15  
0.10  
0.05  
0.00  
CS = VDD  
VDD = 5.5V  
VDD = 2.5V  
-50  
-25  
0
25  
50  
75  
100  
125  
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5  
Power Supply Voltage (V)  
Ambient Temperature (°C)  
FIGURE 2-42:  
CS Current vs. Power  
FIGURE 2-45:  
CS Hysteresis vs. Ambient  
Supply Voltage.  
Temperature.  
3.0  
5
4
3
2
1
0
VDD = 2.5V  
G = 1  
VL = 0V  
2.5  
CS  
2.0  
1.5  
1.0  
0.5  
VDD = 2.5V  
VOUT  
On  
VDD = 5.5V  
0.0  
Off  
Off  
-0.5  
-50  
-25  
0
25  
50  
75  
100  
125  
0
2
4
6
8
10 12 14 16 18 20  
Time (µs)  
Ambient Temperature (°C)  
FIGURE 2-43:  
CS and Output Voltages vs.  
FIGURE 2-46:  
CS Turn On Time vs.  
Time with VDD = 2.5V.  
Ambient Temperature.  
6
8
VDD = 5.5V  
G = 1  
VL = 0V  
Representative Part  
CS  
7
6
5
4
3
2
1
0
5
4
3
VOUT  
2
On  
1
0
Off  
Off  
-1  
-50  
-25  
0
25  
50  
75  
100  
125  
0
1
2
3
4
5
6
7
8
9
10  
Time (µs)  
Ambient Temperature (°C)  
FIGURE 2-44:  
CS and Output Voltages vs.  
FIGURE 2-47:  
CS’s Pull-down Resistor  
Time with VDD = 5.5V.  
(RPD) vs. Ambient Temperature.  
DS22194D-page 16  
2009-2012 Microchip Technology Inc.  
MCP660/1/2/3/4/5/9  
Note: Unless indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2,  
RL = 1 kto VL, CL = 20 pF and CS = VSS  
.
0.0  
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
1.E-016µ  
CS = VDD  
CS = VDD = 5.5V  
100n  
1.E-07  
+125°C  
+85°C  
10n  
1.E-08  
-1.2  
-1.4  
-1.6  
-1.8  
-2.0  
1n  
1.E-09  
+125°C  
+85°C  
+25°C  
-40°C  
100p  
1.E-10  
+25°C  
10p  
1.E-11  
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0  
Output Voltage (V)  
Power Supply Voltage (V)  
FIGURE 2-48:  
Shutdown vs. Power Supply Voltage.  
Quiescent Current in  
FIGURE 2-49:  
Output Voltage.  
Output Leakage Current vs.  
2009-2012 Microchip Technology Inc.  
DS22194D-page 17  
MCP660/1/2/3/4/5/9  
NOTES:  
DS22194D-page 18  
2009-2012 Microchip Technology Inc.  
3.0  
PIN DESCRIPTIONS  
Descriptions of the pins are listed in Table 3-1.  
TABLE 3-1:  
MCP660  
PIN FUNCTION TABLE  
MCP661  
MCP662  
MCP663  
MCP664 MCP665 MCP669  
Symbol  
Description  
2
5
4
6
5
2
4
2
3
2
3
2
4
2
3
2
3
2
3
1
2
VIN-, VINA  
VIN+, VINA  
VDD  
-
Inverting Input (op amp A)  
Non-inverting Input (op amp A)  
Positive Power Supply  
3
3
3
3
3
+
7
3
4
7
5
8
8
7
6
4
10  
7
10  
7
3
4
10  
9
10  
9
4
2
5
5
4
2
5
4
VINB+  
Non-inverting Input (op amp B)  
Inverting Input (op amp B)  
Output (op amp B)  
6
6
6
8
8
5
VINB  
-
8
8
7
7
7
9
9
6
VOUTB  
CSBC  
14  
13  
12  
11  
6
14  
13  
12  
11  
7
4
4
8
4
4
7
Chip Select Digital Input (op amps B and C)  
Output (op amp C)  
8
VOUTC  
9
9
VINC  
VINC  
VSS  
-
Inverting Input (op amp C)  
Non-inverting Input (op amp C)  
Negative Power Supply  
10  
11  
12  
13  
14  
1
10  
11  
12  
13  
14  
15  
16  
17  
+
6
6
1
1
1
6
1
1
1
VIND+  
Inverting Input (op amp D)  
Inverting Input (op amp D)  
Output (op amp D)  
VIND  
-
VOUTD  
CSAD  
Chip Select Digital Input (op amps A and D)  
Output (op amp A)  
V
OUT, VOUTA  
EP  
17  
9
11  
Exposed Thermal Pad (EP); must be  
connected to VSS  
8
5
5
6
5
6
CS, CSA  
CSB  
Chip Select Digital Input (op amp A)  
Chip Select Digital Input (op amp B)  
No Internal Connection  
1,2  
1, 2, 7, 1, 2, 3 1, 5, 8  
15, 16  
1, 5  
NC  
MCP660/1/2/3/4/5/9  
3.1  
Analog Outputs  
3.4  
Chip Select Digital Input (CS)  
The analog output pins (VOUT) are low-impedance  
voltage sources.  
The input (CS) is a CMOS, Schmitt-triggered input that  
places the part into a Low Power mode of operation.  
3.2  
Analog Inputs  
3.5  
Exposed Thermal Pad (EP)  
The non-inverting and inverting inputs (VIN+, VIN-, …)  
are high-impedance CMOS inputs with low bias  
currents.  
There is an internal connection between the exposed  
thermal pad (EP) and the VSS pin; they must be con-  
nected to the same potential on the printed circuit  
board (PCB).  
3.3  
Power Supply Pins  
This pad can be connected to a PCB ground plane to  
provide a larger heat sink. This improves the package  
thermal resistance (JA).  
The positive power supply (VDD) is 2.5V to 5.5V higher  
than the negative power supply (VSS). For normal  
operation, the other pins are between VSS and VDD  
.
Typically, these parts are used in a single (positive)  
supply configuration. In that case, VSS is connected to  
ground and VDD is connected to the supply. VDD will  
need bypass capacitors.  
DS22194D-page 20  
2009-2012 Microchip Technology Inc.  
MCP660/1/2/3/4/5/9  
When implemented as shown, resistors R1 and R2 also  
limit the current through D1 and D2.  
4.0  
APPLICATIONS  
The MCP660/1/2/3/4/5/9 family is manufactured using  
the Microchip state-of-the-art CMOS process. It is  
designed for low-cost, low-power and high-speed  
applications. Its low supply voltage, low quiescent cur-  
rent and wide bandwidth make the MCP660/1/2/3/4/5/9  
ideal for battery-powered applications.  
VDD  
D1  
R1  
D2  
MCP66X  
V1  
V2  
4.1  
Input  
PHASE REVERSAL  
VOUT  
4.1.1  
R2  
The input devices are designed to not exhibit phase  
inversion when the input pins exceed the supply volt-  
ages. Figure 2-39 shows an input voltage exceeding  
both supplies with no phase inversion.  
VSS – (minimum expected V1)  
R1 >  
R2 >  
2 mA  
VSS – (minimum expected V2)  
2 mA  
4.1.2  
INPUT VOLTAGE AND CURRENT  
LIMITS  
FIGURE 4-2:  
Protecting the Analog  
The electrostatic discharge (ESD) protection on the  
inputs can be depicted as shown in Figure 4-1. This  
structure was chosen to protect the input transistors,  
and to minimize input bias current (IB). The input ESD  
diodes clamp the inputs when they try to go more than  
one diode drop below VSS. They also clamp any  
voltages that go too far above VDD; their breakdown  
voltage is high enough to allow normal operation, and  
low enough to bypass quick ESD events within the  
specified limits.  
Inputs.  
It is also possible to connect the diodes to the left of the  
resistors R1 and R2. If they are, the currents through  
the diodes D1 and D2 need to be limited by some other  
mechanism. The resistors then serve as in-rush current  
limiters; the DC current into the input pins (VIN+ and  
VIN-) should be very small.  
A significant amount of current can flow out of the  
inputs (through the ESD diodes) when the Common  
mode voltage (VCM) is below ground (VSS); see  
Figure 2-13. Applications that are high impedance may  
need to limit the usable voltage range.  
Bond  
VDD  
Pad  
4.1.3  
NORMAL OPERATION  
The input stage of the MCP660/1/2/3/4/5/9 op amps  
uses a differential PMOS input stage. It operates at low  
Common mode input voltages (VCM), with VCM  
between VSS – 0.3V and VDD – 1.3V. To ensure proper  
operation, the input offset voltage (VOS) is measured at  
both VCM = VSS – 0.3V and VDD – 1.3V. See Figure 2-  
5 and Figure 2-6 for temperature effects.  
Bond  
Pad  
Bond  
Pad  
Input  
Stage  
VIN+  
VIN-  
Bond  
Pad  
VSS  
When operating at very low non-inverting gains, the  
output voltage is limited at the top by the VCM range  
(<VDD – 1.3V); see Figure 4-3.  
FIGURE 4-1:  
Simplified Analog Input ESD  
Structures.  
In order to prevent damage and/or improper operation  
of these amplifiers, the circuit must limit the currents  
(and voltages) at the input pins (see Section 1.1  
“Absolute Maximum Ratings †”). Figure 4-2 shows  
the recommended approach to protecting these inputs.  
VDD  
MCP66X  
VIN  
VOUT  
The internal ESD diodes prevent the input pins (VIN+  
and VIN-) from going too far below ground, and the  
resistors R1 and R2 limit the possible current drawn out  
of the input pins. Diodes D1 and D2 prevent the input  
pins (VIN+ and VIN-) from going too far above VDD, and  
VSS VINVOUT VDD 1.3V  
FIGURE 4-3:  
Unity Gain Voltage  
Limitations for Linear Operation.  
dump any currents onto VDD  
.
2009-2012 Microchip Technology Inc.  
DS22194D-page 21  
MCP660/1/2/3/4/5/9  
Figure 4-5 shows the power calculations used for a sin-  
gle op amp:  
4.2  
Rail-to-Rail Output  
4.2.1  
MAXIMUM OUTPUT VOLTAGE  
• RSER is 0in most applications, and can be used  
to limit IOUT  
.
The Maximum Output Voltage (see Figure 2-16 and  
Figure 2-17) describes the output range for a given  
load. For example, the output voltage swings to within  
50 mV of the negative rail with a 1 kload tied to  
• VOUT is the op amp’s output voltage.  
• VL is the voltage at the load.  
• VLG is the load’s ground point.  
• VSS is usually ground (0V).  
VDD/2.  
4.2.2  
OUTPUT CURRENT  
The input currents are assumed to be negligible. The  
currents shown in Figure 4-5 can be approximated  
using Equation 4-1:  
Figure 4-4 shows the possible combinations of output  
voltage (VOUT) and output current (IOUT), when VDD  
5.5V.  
=
EQUATION 4-1:  
IOUT is positive when it flows out of the op amp into the  
external circuit.  
VOUT – VLG  
IOUT = IL =  
R
SER + RL  
6.0  
5.5  
5.0  
4.5  
IDD IQ + max(0, IOUT  
)
VOH Limited  
(VDD = 5.5V)  
ISS –IQ + min(0, IOUT  
)
RL = 1 kΩ  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
-0.5  
RL = 100Ω  
Where:  
IQ  
=
quiescent supply current  
RL = 10Ω  
The instantaneous op amp power (POA(t)), RSER power  
(PRSER(t)) and load power (PL(t)) are calculated in  
Equation 4-2:  
VOL Limited  
EQUATION 4-2:  
IOUT (mA)  
POA(t) = IDD (VDD – VOUT) + ISS (VSS – VOUT  
)
FIGURE 4-4:  
Output Current.  
2
PRSER(t) = IOUT RSER  
4.2.3 POWER DISSIPATION  
PL(t) = IL2RL  
Since the output short circuit current (ISC) is specified  
at ±90 mA (typical), these op amps are capable of both  
delivering and dissipating significant power.  
The maximum op amp power, for resistive loads,  
occurs when VOUT is halfway between VDD and VLG or  
halfway between VSS and VLG  
.
EQUATION 4-3:  
VDD  
max2(VDD – VLG, – VSS)  
4(RSER + RL)  
VOUT  
IDD  
POAmax  
IOUT  
RSER  
VL  
The maximum ambient to junction temperature rise  
(TJA) and junction temperature (TJ) can be calculated  
using POAmax, ambient temperature (TA), the package  
thermal resistance (JA – found in Table 1-4), and the  
number of op amps in the package (assuming equal  
power dissipations), as shown in Equation 4-4:  
MCP66X  
IL  
RL  
ISS  
VLG  
VSS  
FIGURE 4-5:  
Calculations.  
Diagram for Power  
EQUATION 4-4:  
TJA = POA(t) JA n POAmax JA  
TJ = TA + TJA  
Where:  
n
=
number of op amps in package (1, 2)  
DS22194D-page 22  
2009-2012 Microchip Technology Inc.  
MCP660/1/2/3/4/5/9  
The power derating across temperature for an op amp  
in a particular package can be easily calculated  
(assuming equal power dissipations):  
4.4  
4.4.1  
Improving Stability  
CAPACITIVE LOADS  
Driving large capacitive loads can cause stability  
problems for voltage feedback op amps. As the load  
capacitance increases, the phase margin (stability) of  
the feedback loop decreases and the closed-loop  
bandwidth is reduced. This produces gain peaking in  
the frequency response, with overshoot and ringing in  
the step response. A unity gain buffer (G = +1) is the  
most sensitive to capacitive loads, though all gains  
show the same general behavior.  
EQUATION 4-5:  
TJmax – TA  
POAmax  
n JA  
Where:  
TJmax  
=
absolute max. junction temperature  
When driving large capacitive loads with these op  
amps (e.g., >20 pF when G = +1), a small series resis-  
tor at the output (RISO in Figure 4-6) improves the  
phase margin of the feedback loop by making the out-  
put load resistive at higher frequencies. The bandwidth  
generally will be lower than bandwidth without the  
capacitive load.  
Several techniques are available to reduce TJA for a  
given POAmax  
:
• Lower JA  
- Use another package  
- PCB layout (ground plane, etc.)  
- Heat sinks and air flow  
• Reduce POAmax  
RISO  
CL  
RG  
RF  
- Increase RL  
VOUT  
- Limit IOUT (using RSER  
)
- Decrease VDD  
MCP66X  
RN  
4.3  
Distortion  
Differential gain (DG) and differential phase (DP) refer  
to the non-linear distortion produced by an NTSC or a  
phase-alternating line (PAL) video component. Table 1-  
2 and Figure 2-34 show the typical performance of the  
MCP661, configured as a gain of +2 amplifier (see  
Figure 4-10), when driving one back-matched video  
load (150, for 75cable). Microchip tests use a sine  
wave at NTSC’s color sub-carrier frequency of 3.58  
MHz, with a 0.286VP-P magnitude. The DC input volt-  
age is changed over a +0.7V range (positive video) or  
a -0.7V range (negative video).  
FIGURE 4-6:  
Stabilizes Large Capacitive Loads.  
Output Resistor, RISO  
Figure 4-7 gives recommended RISO values for  
different capacitive loads and gains. The x-axis is the  
normalized load capacitance (CL/GN), where GN is the  
circuit’s noise gain. For non-inverting gains, GN and the  
Signal Gain are equal. For inverting gains, GN is  
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).  
100  
DG is the peak-to-peak change in the AC gain magni-  
tude (color hue), as the DC level (luminance) is  
changed, in percentile units (%). DP is the peak-to-  
peak change in the AC gain phase (color saturation),  
as the DC level (luminance) is changed, in degree (°)  
units.  
10  
GN = +1  
GN +2  
1
10p  
100p  
1.E-10  
1n  
1.E-09  
10n  
1.E-08  
1.E-11  
Normalized Capacitance; CL/GN (F)  
FIGURE 4-7:  
Recommended RISO Values  
for Capacitive Loads.  
After selecting RISO for the circuit, double-check the  
resulting frequency response peaking and step  
response overshoot. Modify the value of RISO until the  
response is reasonable. Bench evaluation and simula-  
tions with the MCP660/1/2/3/4/5/9 SPICE macro model  
are helpful.  
2009-2012 Microchip Technology Inc.  
DS22194D-page 23  
MCP660/1/2/3/4/5/9  
The largest value of RF that should be used, depends  
on noise gain (see GN in Section 4.4.1 “Capacitive  
Loads”), CG and the open-loop gain’s phase shift.  
Figure 4-9 shows the maximum recommended RF for  
several CG values. Some applications may modify  
these values to reduce either output loading or gain  
peaking (step response overshoot).  
4.4.2  
GAIN PEAKING  
Figure 4-8 shows an op amp circuit that represents  
non-inverting amplifiers (VM is a DC voltage and VP is  
the input) or inverting amplifiers (VP is a DC voltage  
and VM is the input). The capacitances CN and CG rep-  
resent the total capacitance at the input pins; they  
include the op amp’s Common mode input capacitance  
(CCM), board parasitic capacitance and any capacitor  
placed in parallel.  
1.E+05  
100k  
GN > +1 V/V  
CG = 10 pF  
CG = 32 pF  
CG = 100 pF  
CG = 320 pF  
CG = 1 nF  
10k  
1.E+04  
CN  
RN  
MCP66X  
VP  
VOUT  
1k  
1.E+03  
VM  
RG  
RF  
100  
1.E+02  
CG  
1
10  
100  
Noise Gain; GN (V/V)  
FIGURE 4-8:  
Capacitance.  
Amplifier with Parasitic  
FIGURE 4-9:  
RF vs. Gain.  
Maximum Recommended  
CG acts in parallel with RG (except for a gain of +1 V/V),  
which causes an increase in gain at high frequencies.  
CG also reduces the phase margin of the feedback  
loop, which becomes less stable. This effect can be  
reduced by either reducing CG or RF.  
Figure 2-35 and Figure 2-36 show the small signal and  
large signal step responses at G = +1 V/V. The unity  
gain buffer usually has RF = 0and RG open.  
Figure 2-37 and Figure 2-38 show the small signal and  
large signal step responses at G = -1 V/V. Since the  
noise gain is 2 V/V and CG 10 pF, the resistors were  
chosen to be RF = RG = 401and RN = 200.  
CN and RN form a low-pass filter that affects the signal  
at VP. This filter has a single real pole at 1/(2RNCN).  
It is also possible to add a capacitor (CF) in parallel with  
RF to compensate for the destabilizing effect of CG.  
This makes it possible to use larger values of RF. The  
conditions for stability are summarized in Equation 4-6.  
EQUATION 4-6:  
Given:  
GN1 = 1 + RF RG  
GN2 = 1 + CG CF  
fF = 1 2RFCF  
fZ = fFGN1 GN2  
We need:  
fF fGBWP 2GN2, GN1 GN2  
fF fGBWP 4GN1, GN1 GN2  
DS22194D-page 24  
2009-2012 Microchip Technology Inc.  
MCP660/1/2/3/4/5/9  
4.5  
MCP663 and MCP665 Chip Select  
4.7  
High Speed PCB Layout  
The MCP663 is a single amplifier with Chip Select  
(CS). When CS is pulled high, the supply current drops  
These op amps are fast enough that a little extra care  
in the printed circuit board (PCB) layout can make a  
significant difference in performance. Good PC board  
layout techniques will help you achieve the perfor-  
mance shown in the specifications and typical  
performance curves; it will also help to minimize  
electromagnetic compatibility (EMC) issues.  
to 1 µA (typical) and flows through the CS pin to VSS  
.
When this happens, the amplifier output is put into a  
high-impedance state. By pulling CS low, the amplifier  
is enabled. The CS pin has an internal 5 M(typical)  
pulldown resistor connected to VSS, so it will go low if  
the CS pin is left floating. Figure 1-1, Figure 2-43 and  
Figure 2-44 show the output voltage and supply current  
response to a CS pulse.  
Use a solid ground plane. Connect the bypass local  
capacitor(s) to this plane with minimal length traces.  
This cuts down inductive and capacitive crosstalk.  
The MCP665 is a dual amplifier with two CS pins; CSA  
controls op amp A, and CSB controls op amp B. These  
op amps are controlled independently, with an enabled  
quiescent current (IQ) of 6 mA/amplifier (typical) and a  
disabled IQ of 1 µA/amplifier (typical). The IQ seen at  
the supply pins is the sum of the two op amps’ IQ; the  
typical value for the IQ of the MCP665 will be 2 µA, 6  
mA or 12 mA when there are 0, 1 or 2 amplifiers  
enabled, respectively.  
Separate digital from analog, low speed from high  
speed, and low power from high power. This will reduce  
interference.  
Keep sensitive traces short and straight. Separate  
them from interfering components and traces. This is  
especially important for high frequency (low rise time)  
signals.  
Sometimes, it helps to place guard traces next to victim  
traces. They should be on both sides of the victim  
trace, and as close as possible. Connect guard traces  
to ground plane at both ends, and in the middle for long  
traces.  
4.6  
Power Supply  
With this family of operational amplifiers, the power  
supply pin (VDD for single supply) should have a local  
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm  
for good high frequency performance. Surface mount,  
multilayer ceramic capacitors, or their equivalent,  
should be used.  
Use coax cables, or low inductance wiring, to route sig-  
nal and power to and from the PCB. Mutual and self  
inductance of power wires is often a cause of crosstalk  
and unusual behavior.  
These op amps require a bulk capacitor (i.e., 2.2 µF or  
larger) within 50 mm to provide large, slow currents.  
Tantalum capacitors, or their equivalent, may be a good  
choice. This bulk capacitor can be shared with other  
nearby analog parts as long as crosstalk through the  
power supplies does not prove to be a problem.  
2009-2012 Microchip Technology Inc.  
DS22194D-page 25  
MCP660/1/2/3/4/5/9  
4.8.3  
H-BRIDGE DRIVER  
4.8  
Typical Applications  
Figure 4-12 shows the MCP662 dual op amp used as  
an H-bridge driver. The load could be a speaker or a  
DC motor.  
4.8.1  
50LINE DRIVER  
Figure 4-10 shows the MCP661 driving a 50line. The  
large output current (e.g., see Figure 2-18) makes it  
possible to drive a back-matched line (RM2, the 50  
line and the 50load at the far end) to more than ±2V  
(the load at the far end sees ±1V). It is worth mention-  
ing that the 50line and the 50load at the far end  
together can be modeled as a simple 50resistor to  
ground.  
½ MCP662  
VIN  
VOT  
RF  
RF  
RF  
RL  
RGT  
RGB  
50  
Line  
+2.5V  
-2.5V  
MCP66X  
VOB  
RM1  
RM2  
49.9  
49.9  
50  
VDD/2  
½ MCP662  
H-Bridge Driver.  
RG  
RF  
301  
301  
FIGURE 4-12:  
This circuit automatically makes the noise gains (GN)  
equal, when the gains are set properly, so that the fre-  
quency responses match well (in magnitude and in  
phase). Equation 4-7 shows how to calculate RGT and  
RGB so that both op amps have the same DC gains;  
FIGURE 4-10:  
50Line Driver.  
The output headroom limits would be VOL = -2.3V and  
VOH = +2.3V (see Figure 2-16), leaving some design  
room for the ±2V signal. The open-loop gain (AOL  
)
GDM needs to be selected first.  
typically does not decrease significantly with a 100  
load (see Figure 2-11). The maximum power dissipated  
is about 48 mW (see Section 4.2.3 “Power  
Dissipation”), so the temperature rise (for the  
MCP661 in the SOIC-8 package) is under 8°C.  
EQUATION 4-7:  
VOT VOB  
GDM -------------------------------- 1 V/V  
VIN VDD 2  
4.8.2  
OPTICAL DETECTOR AMPLIFIER  
RF  
RGT = ---------------------------------  
Figure 4-11 shows a transimpedance amplifier, using  
the MCP661 op amp, in a photo detector circuit. The  
photo detector is a capacitive current source. RF pro-  
vides enough gain to produce 10 mV at VOUT. CF stabi-  
lizes the gain and limits the transimpedance bandwidth  
to about 1.1 MHz. The parasitic capacitance of RF (e.g.,  
0.2 pF for a 0805 SMD) acts in parallel with CF.  
GDM 21  
RF  
RGB = ------------------  
GDM 2  
Equation 4-8 gives the resulting Common mode and  
Differential mode output voltages.  
CF  
1.5 pF  
EQUATION 4-8:  
VOT + VOB  
-------------------------- = ----------  
VDD  
Photo  
Detector  
RF  
2
2
100 k  
VDD  
VOUT  
VIN ----------  
VOT VOB = G  
DM  
2
ID  
CD  
100 nA  
30pF  
MCP661  
VDD/2  
FIGURE 4-11:  
Transimpedance Amplifier  
for an Optical Detector.  
DS22194D-page 26  
2009-2012 Microchip Technology Inc.  
MCP660/1/2/3/4/5/9  
5.4  
Analog Demonstration and  
Evaluation Boards  
5.0  
DESIGN AIDS  
Microchip provides the basic design aids needed for  
the MCP660/1/2/3/4/5/9 family of op amps.  
Microchip offers a broad spectrum of analog demon-  
stration and evaluation boards that are designed to  
help customers achieve faster time to market. For a  
complete listing of these boards and their correspond-  
ing user’s guides and technical information, visit the  
Microchip web site at www.microchip.com/analog  
tools.  
5.1  
SPICE Macro Model  
The latest SPICE macro model for the  
MCP660/1/2/3/4/5/9 op amps is available on the Micro-  
chip web site at www.microchip.com. This model is  
intended to be an initial design tool that works well in  
the linear region of operation over the temperature  
range of the op amp. See the model file for information  
on its capabilities.  
Some boards that are especially useful are:  
MCP6XXX Amplifier Evaluation Board 1,  
part number: MCP6XXXEV-AMP1  
MCP6XXX Amplifier Evaluation Board 2,  
part number: MCP6XXXEV-AMP2  
Bench testing is a very important part of any design and  
cannot be replaced with simulations. Also, simulation  
results using this macro model need to be validated, by  
comparing them to the data sheet specifications and  
characteristic curves.  
MCP6XXX Amplifier Evaluation Board 3,  
part number: MCP6XXXEV-AMP3  
MCP6XXX Amplifier Evaluation Board 4,  
part number: MCP6XXXEV-AMP3  
®
5.2  
FilterLab Software  
Active Filter Demo Board Kit,  
part number: MCP6XXXDM-FLTR  
Microchip’s FilterLab® software is an innovative soft-  
ware tool that simplifies analog active filter (using op  
amps) design. Available at no cost from the Microchip  
web site at www.microchip.com/filterlab, the Filter-Lab  
design tool provides full schematic diagrams of the filter  
circuit with component values. It also outputs the filter  
circuit in SPICE format, which can be used with the  
macro model to simulate actual filter performance.  
8-Pin SOIC/MSOP/TSSOP/DIP Evaluation  
Board, part number: SOIC8EV  
MCP661 Line Driver Demo Board,  
part number: MCP661DM-LD  
5.5  
Design and Application Notes  
The following Microchip Analog Design Note and Appli-  
cation Notes are recommended as supplemental refer-  
ence resources. They are available on the Microchip  
web site at www.microchip.com/appnotes.  
5.3  
Microchip Advanced Part Selector  
(MAPS)  
MAPS is a software tool that helps efficiently identify  
Microchip devices that fit particular design  
ADN003: “Select the Right Operational Amplifier  
for your Filtering Circuits”, DS21821  
a
requirement. Available at no cost from the Microchip  
web site at www.microchip.com/maps, the MAPS is an  
overall selection tool for Microchip’s product portfolio  
that includes Analog, Memory, MCUs and DSCs. Using  
this tool, a filter can be defined to sort features for a  
parametric search of device, and export side-by-side  
technical comparison reports. Helpful links are also  
provided for data sheets, purchase and sampling of  
Microchip parts.  
AN722: “Operational Amplifier Topologies and DC  
Specifications”, DS00722  
AN723: “Operational Amplifier AC Specifications  
and Applications”, DS00723  
AN884: “Driving Capacitive Loads With Op  
Amps”, DS00884  
AN990: “Analog Sensor Conditioning Circuits –  
An Overview”, DS00990  
AN1228: “Op Amp Precision Design: Random  
Noise”, DS01228  
Some of these application notes, and others, are listed  
in the “Signal Chain Design Guide”, DS21825.  
2009-2012 Microchip Technology Inc.  
DS22194D-page 27  
MCP660/1/2/3/4/5/9  
NOTES:  
DS22194D-page 28  
2009-2012 Microchip Technology Inc.  
MCP660/1/2/3/4/5/9  
6.0  
6.1  
PACKAGING INFORMATION  
Package Marking Information  
5-Lead SOT-23(MCP661)  
Example  
YX25  
XXNN  
6-Lead SOT-23 (MCP663)  
Example  
JE25  
XXNN  
Example:  
8-Lead TDFN (2 x 3)(MCP661)  
ABJ  
210  
25  
8-Lead DFN (3x3)(MCP662)  
Example  
DABQ  
1210  
256  
Device  
MCP662T-E/MF  
Code  
DABQ  
Note: Applies to 8-Lead 3x3 DFN  
Legend: XX...X Customer-specific information  
Y
YY  
WW  
NNN  
Year code (last digit of calendar year)  
Year code (last 2 digits of calendar year)  
Week code (week of January 1 is week ‘01’)  
Alphanumeric traceability code  
Pb-free JEDEC designator for Matte Tin (Sn)  
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (  
can be found on the outer packaging for this package.  
)
e3  
Note: In the event the full Microchip part number cannot be marked on one line, it will  
be carried over to the next line, thus limiting the number of available  
characters for customer-specific information.  
2009-2012 Microchip Technology Inc.  
DS22194D-page 29  
MCP660/1/2/3/4/5/9  
Package Marking Information (Continued)  
8-Lead MSOP (3x3 mm) (MCP662)  
Example:  
662E  
210256  
8-Lead SOIC (150 mil) (MCP661, MCP662, MCP663)  
Example:  
MCP661E  
e
3
SN 1210  
256  
NNN  
10-Lead DFN (3×3) (MCP665)  
Example  
BAFD  
1210  
256  
Device  
Code  
MCP665  
BAFD  
Note: Applies to 10-Lead 3x3 DFN  
Pin 1  
Pin 1  
10-Lead MSOP (MCP665)  
Example:  
665EUN  
210256  
Legend: XX...X Customer-specific information  
Y
YY  
WW  
NNN  
Year code (last digit of calendar year)  
Year code (last 2 digits of calendar year)  
Week code (week of January 1 is week ‘01’)  
Alphanumeric traceability code  
Pb-free JEDEC designator for Matte Tin (Sn)  
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (  
can be found on the outer packaging for this package.  
)
e3  
Note: In the event the full Microchip part number cannot be marked on one line, it will  
be carried over to the next line, thus limiting the number of available  
characters for customer-specific information.  
DS22194D-page 30  
2009-2012 Microchip Technology Inc.  
MCP660/1/2/3/4/5/9  
Package Marking Information (Continued)  
14-Lead SOIC (.150”) (MCP660, MCP664)  
Example  
MCP660  
e
3
E/SL
1210256  
14-Lead TSSOP (MCP660, MCP664)  
Example  
XXXXXXXX  
YYWW  
664E/ST  
1210  
256  
NNN  
16-Lead QFN (4x4) (MCP669)  
Example  
PIN 1  
PIN 1  
669  
E/ML
110256  
e
3
Legend: XX...X Customer-specific information  
Y
YY  
Year code (last digit of calendar year)  
Year code (last 2 digits of calendar year)  
WW  
NNN  
Week code (week of January 1 is week ‘01’)  
Alphanumeric traceability code  
Pb-free JEDEC designator for Matte Tin (Sn)  
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (  
can be found on the outer packaging for this package.  
)
e3  
Note: In the event the full Microchip part number cannot be marked on one line, it will  
be carried over to the next line, thus limiting the number of available  
characters for customer-specific information.  
2009-2012 Microchip Technology Inc.  
DS22194D-page 31  
MCP660/1/2/3/4/5/9  
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢒꢓꢄꢑꢉꢋꢉꢊꢔꢓꢆꢕꢏꢒꢖꢆꢗꢍꢏꢒꢁꢘꢙꢚ  
ꢛꢔꢊꢃꢜ ꢧꢈꢓꢉꢍꢒꢅꢉꢄꢈꢇꢍꢉꢎꢐꢓꢓꢅꢆꢍꢉꢔꢊꢎꢨꢊꢚꢅꢉꢋꢓꢊꢦꢃꢆꢚꢇꢩꢉꢔꢏꢅꢊꢇꢅꢉꢇꢅꢅꢉꢍꢒꢅꢉꢕꢃꢎꢓꢈꢎꢒꢃꢔꢉꢪꢊꢎꢨꢊꢚꢃꢆꢚꢉꢜꢔꢅꢎꢃꢑꢃꢎꢊꢍꢃꢈꢆꢉꢏꢈꢎꢊꢍꢅꢋꢉꢊꢍꢉ  
ꢒꢍꢍꢔꢢꢫꢫꢦꢦꢦꢁꢄꢃꢎꢓꢈꢎꢒꢃꢔꢁꢎꢈꢄꢫꢔꢊꢎꢨꢊꢚꢃꢆꢚ  
b
N
E
E1  
3
2
1
e
e1  
D
A2  
c
A
φ
A1  
L
L1  
ꢬꢆꢃꢍꢇꢕꢭꢮꢮꢭꢕꢌꢣꢌꢯꢜ  
ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢉꢮꢃꢄꢃꢍꢇ  
ꢕꢭꢰ  
ꢰꢱꢕ  
ꢕꢛꢲ  
ꢰꢐꢄꢳꢅꢓꢉꢈꢑꢉꢪꢃꢆꢇꢰ  
ꢮꢅꢊꢋꢉꢪꢃꢍꢎꢒ  
ꢗꢁꢴꢟꢉꢠꢜꢡ  
ꢱꢐꢍꢇꢃꢋꢅꢉꢮꢅꢊꢋꢉꢪꢃꢍꢎꢒ  
ꢱꢥꢅꢓꢊꢏꢏꢉꢵꢅꢃꢚꢒꢍ  
ꢕꢈꢏꢋꢅꢋꢉꢪꢊꢎꢨꢊꢚꢅꢉꢣꢒꢃꢎꢨꢆꢅꢇꢇ  
ꢜꢍꢊꢆꢋꢈꢑꢑ  
ꢱꢥꢅꢓꢊꢏꢏꢉꢹꢃꢋꢍꢒ  
ꢕꢈꢏꢋꢅꢋꢉꢪꢊꢎꢨꢊꢚꢅꢉꢹꢃꢋꢍꢒ  
ꢱꢥꢅꢓꢊꢏꢏꢉꢮꢅꢆꢚꢍꢒ  
ꢧꢈꢈꢍꢉꢮꢅꢆꢚꢍꢒ  
ꢧꢈꢈꢍꢔꢓꢃꢆꢍ  
ꢧꢈꢈꢍꢉꢛꢆꢚꢏꢅ  
ꢮꢅꢊꢋꢉꢣꢒꢃꢎꢨꢆꢅꢇꢇ  
ꢮꢅꢊꢋꢉꢹꢃꢋꢍꢒ  
ꢅꢀ  
ꢛꢘ  
ꢛꢀ  
ꢌꢀ  
ꢀꢁꢴꢗꢉꢠꢜꢡ  
ꢗꢁꢴꢗ  
ꢗꢁꢷꢴ  
ꢗꢁꢗꢗ  
ꢘꢁꢘꢗ  
ꢀꢁꢸꢗ  
ꢘꢁꢙꢗ  
ꢗꢁꢀꢗ  
ꢗꢁꢸꢟ  
ꢗꢻ  
ꢀꢁꢞꢟ  
ꢀꢁꢸꢗ  
ꢗꢁꢀꢟ  
ꢸꢁꢘꢗ  
ꢀꢁꢷꢗ  
ꢸꢁꢀꢗ  
ꢗꢁꢺꢗ  
ꢗꢁꢷꢗ  
ꢸꢗꢻ  
ꢮꢀ  
ꢗꢁꢗꢷ  
ꢗꢁꢘꢗ  
ꢗꢁꢘꢺ  
ꢗꢁꢟꢀ  
ꢛꢔꢊꢃꢉꢜ  
ꢀꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢇꢉꢂꢉꢊꢆꢋꢉꢌꢀꢉꢋꢈꢉꢆꢈꢍꢉꢃꢆꢎꢏꢐꢋꢅꢉꢄꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢁꢉꢕꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢉꢇꢒꢊꢏꢏꢉꢆꢈꢍꢉꢅꢖꢎꢅꢅꢋꢉꢗꢁꢀꢘꢙꢉꢄꢄꢉꢔꢅꢓꢉꢇꢃꢋꢅꢁ  
ꢘꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢃꢆꢚꢉꢊꢆꢋꢉꢍꢈꢏꢅꢓꢊꢆꢎꢃꢆꢚꢉꢔꢅꢓꢉꢛꢜꢕꢌꢉꢝꢀꢞꢁꢟꢕꢁ  
ꢠꢜꢡꢢ ꢠꢊꢇꢃꢎꢉꢂꢃꢄꢅꢆꢇꢃꢈꢆꢁꢉꢣꢒꢅꢈꢓꢅꢍꢃꢎꢊꢏꢏꢤꢉꢅꢖꢊꢎꢍꢉꢥꢊꢏꢐꢅꢉꢇꢒꢈꢦꢆꢉꢦꢃꢍꢒꢈꢐꢍꢉꢍꢈꢏꢅꢓꢊꢆꢎꢅꢇꢁ  
ꢕꢃꢎꢓꢈꢎꢒꢃꢔ ꢎꢒꢆꢈꢏꢈꢚꢤ ꢂꢓꢊꢦꢃꢆꢚ ꢡꢗꢞꢼꢗꢴꢀꢠ  
DS22194D-page 32  
2009-2012 Microchip Technology Inc.  
MCP660/1/2/3/4/5/9  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
2009-2012 Microchip Technology Inc.  
DS22194D-page 33  
MCP660/1/2/3/4/5/9  
6-Lead Plastic Small Outline Transistor (CHY) [SOT-23]  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
b
4
N
E
E1  
PIN 1 ID BY  
LASER MARK  
1
2
3
e
e1  
D
c
A
φ
A2  
L
A1  
L1  
Units  
MILLIMETERS  
Dimension Limits  
MIN  
NOM  
MAX  
Number of Pins  
Pitch  
N
e
6
0.95 BSC  
Outside Lead Pitch  
Overall Height  
Molded Package Thickness  
Standoff  
Overall Width  
Molded Package Width  
Overall Length  
Foot Length  
Footprint  
Foot Angle  
Lead Thickness  
Lead Width  
e1  
A
A2  
A1  
E
E1  
D
L
1.90 BSC  
0.90  
0.89  
0.00  
2.20  
1.30  
2.70  
0.10  
0.35  
0°  
–
–
–
–
–
–
–
–
–
–
–
1.45  
1.30  
0.15  
3.20  
1.80  
3.10  
0.60  
0.80  
30°  
L1  
c
b
0.08  
0.20  
0.26  
0.51  
Notes:  
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side.  
2. Dimensioning and tolerancing per ASME Y14.5M.  
BSC: Basic Dimension. Theoretically exact value shown without tolerances.  
Microchip Technology Drawing C04-028B  
DS22194D-page 34  
2009-2012 Microchip Technology Inc.  
MCP660/1/2/3/4/5/9  
6-Lead Plastic Small Outline Transistor (CHY) [SOT-23]  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
2009-2012 Microchip Technology Inc.  
DS22194D-page 35  
MCP660/1/2/3/4/5/9  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
DS22194D-page 36  
2009-2012 Microchip Technology Inc.  
MCP660/1/2/3/4/5/9  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
2009-2012 Microchip Technology Inc.  
DS22194D-page 37  
MCP660/1/2/3/4/5/9  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
DS22194D-page 38  
2009-2012 Microchip Technology Inc.  
MCP660/1/2/3/4/5/9  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
2009-2012 Microchip Technology Inc.  
DS22194D-page 39  
MCP660/1/2/3/4/5/9  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
DS22194D-page 40  
2009-2012 Microchip Technology Inc.  
MCP660/1/2/3/4/5/9  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
2009-2012 Microchip Technology Inc.  
DS22194D-page 41  
MCP660/1/2/3/4/5/9  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
DS22194D-page 42  
2009-2012 Microchip Technology Inc.  
MCP660/1/2/3/4/5/9  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
2009-2012 Microchip Technology Inc.  
DS22194D-page 43  
MCP660/1/2/3/4/5/9  
ꢝꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢕꢍꢛꢖꢆMꢆꢛꢄꢓꢓꢔ"#ꢆꢙ$%&ꢆꢎꢎꢆ'ꢔꢅ*ꢆꢗꢍꢏ+,ꢚ  
ꢛꢔꢊꢃꢜ ꢧꢈꢓꢉꢍꢒꢅꢉꢄꢈꢇꢍꢉꢎꢐꢓꢓꢅꢆꢍꢉꢔꢊꢎꢨꢊꢚꢅꢉꢋꢓꢊꢦꢃꢆꢚꢇꢩꢉꢔꢏꢅꢊꢇꢅꢉꢇꢅꢅꢉꢍꢒꢅꢉꢕꢃꢎꢓꢈꢎꢒꢃꢔꢉꢪꢊꢎꢨꢊꢚꢃꢆꢚꢉꢜꢔꢅꢎꢃꢑꢃꢎꢊꢍꢃꢈꢆꢉꢏꢈꢎꢊꢍꢅꢋꢉꢊꢍꢉ  
ꢒꢍꢍꢔꢢꢫꢫꢦꢦꢦꢁꢄꢃꢎꢓꢈꢎꢒꢃꢔꢁꢎꢈꢄꢫꢔꢊꢎꢨꢊꢚꢃꢆꢚ  
DS22194D-page 44  
2009-2012 Microchip Technology Inc.  
MCP660/1/2/3/4/5/9  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
2009-2012 Microchip Technology Inc.  
DS22194D-page 45  
MCP660/1/2/3/4/5/9  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
DS22194D-page 46  
2009-2012 Microchip Technology Inc.  
MCP660/1/2/3/4/5/9  
ꢝꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ.ꢐꢄꢈꢆ/ꢈꢄꢊ#ꢆꢛꢔꢆꢂꢃꢄꢅꢆꢇꢄꢌ0ꢄ1ꢃꢆꢕ4ꢛꢖꢆMꢆꢘ5ꢙ5&$7ꢀꢆꢎꢎꢆ'ꢔꢅ*ꢆꢗꢒ./ꢛꢚ  
ꢛꢔꢊꢃꢜ ꢧꢈꢓꢉꢍꢒꢅꢉꢄꢈꢇꢍꢉꢎꢐꢓꢓꢅꢆꢍꢉꢔꢊꢎꢨꢊꢚꢅꢉꢋꢓꢊꢦꢃꢆꢚꢇꢩꢉꢔꢏꢅꢊꢇꢅꢉꢇꢅꢅꢉꢍꢒꢅꢉꢕꢃꢎꢓꢈꢎꢒꢃꢔꢉꢪꢊꢎꢨꢊꢚꢃꢆꢚꢉꢜꢔꢅꢎꢃꢑꢃꢎꢊꢍꢃꢈꢆꢉꢏꢈꢎꢊꢍꢅꢋꢉꢊꢍꢉ  
ꢒꢍꢍꢔꢢꢫꢫꢦꢦꢦꢁꢄꢃꢎꢓꢈꢎꢒꢃꢔꢁꢎꢈꢄꢫꢔꢊꢎꢨꢊꢚꢃꢆꢚ  
2009-2012 Microchip Technology Inc.  
DS22194D-page 47  
MCP660/1/2/3/4/5/9  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
DS22194D-page 48  
2009-2012 Microchip Technology Inc.  
MCP660/1/2/3/4/5/9  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
2009-2012 Microchip Technology Inc.  
DS22194D-page 49  
MCP660/1/2/3/4/5/9  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
DS22194D-page 50  
2009-2012 Microchip Technology Inc.  
MCP660/1/2/3/4/5/9  
UN  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
2009-2012 Microchip Technology Inc.  
DS22194D-page 51  
MCP660/1/2/3/4/5/9  
UN  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
DS22194D-page 52  
2009-2012 Microchip Technology Inc.  
MCP660/1/2/3/4/5/9  
10-Lead Plastic Micro Small Outline Package (UN) [MSOP]  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
2009-2012 Microchip Technology Inc.  
DS22194D-page 53  
MCP660/1/2/3/4/5/9  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
DS22194D-page 54  
2009-2012 Microchip Technology Inc.  
MCP660/1/2/3/4/5/9  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
2009-2012 Microchip Technology Inc.  
DS22194D-page 55  
MCP660/1/2/3/4/5/9  
ꢛꢔꢊꢃꢜ ꢧꢈꢓꢉꢍꢒꢅꢉꢄꢈꢇꢍꢉꢎꢐꢓꢓꢅꢆꢍꢉꢔꢊꢎꢨꢊꢚꢅꢉꢋꢓꢊꢦꢃꢆꢚꢇꢩꢉꢔꢏꢅꢊꢇꢅꢉꢇꢅꢅꢉꢍꢒꢅꢉꢕꢃꢎꢓꢈꢎꢒꢃꢔꢉꢪꢊꢎꢨꢊꢚꢃꢆꢚꢉꢜꢔꢅꢎꢃꢑꢃꢎꢊꢍꢃꢈꢆꢉꢏꢈꢎꢊꢍꢅꢋꢉꢊꢍꢉ  
ꢒꢍꢍꢔꢢꢫꢫꢦꢦꢦꢁꢄꢃꢎꢓꢈꢎꢒꢃꢔꢁꢎꢈꢄꢫꢔꢊꢎꢨꢊꢚꢃꢆꢚ  
DS22194D-page 56  
2009-2012 Microchip Technology Inc.  
MCP660/1/2/3/4/5/9  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
2009-2012 Microchip Technology Inc.  
DS22194D-page 57  
MCP660/1/2/3/4/5/9  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
DS22194D-page 58  
2009-2012 Microchip Technology Inc.  
MCP660/1/2/3/4/5/9  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
2009-2012 Microchip Technology Inc.  
DS22194D-page 59  
MCP660/1/2/3/4/5/9  
89ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ;ꢐꢄꢅꢆ/ꢈꢄꢊ#ꢆꢛꢔꢆꢂꢃꢄꢅꢆꢇꢄꢌ0ꢄ1ꢃꢆꢕ4ꢂꢖꢆMꢆ<5<5&$%ꢆꢎꢎꢆ'ꢔꢅ*ꢆꢗ;/ꢛꢚ  
ꢛꢔꢊꢃꢜ ꢧꢈꢓꢉꢍꢒꢅꢉꢄꢈꢇꢍꢉꢎꢐꢓꢓꢅꢆꢍꢉꢔꢊꢎꢨꢊꢚꢅꢉꢋꢓꢊꢦꢃꢆꢚꢇꢩꢉꢔꢏꢅꢊꢇꢅꢉꢇꢅꢅꢉꢍꢒꢅꢉꢕꢃꢎꢓꢈꢎꢒꢃꢔꢉꢪꢊꢎꢨꢊꢚꢃꢆꢚꢉꢜꢔꢅꢎꢃꢑꢃꢎꢊꢍꢃꢈꢆꢉꢏꢈꢎꢊꢍꢅꢋꢉꢊꢍꢉ  
ꢒꢍꢍꢔꢢꢫꢫꢦꢦꢦꢁꢄꢃꢎꢓꢈꢎꢒꢃꢔꢁꢎꢈꢄꢫꢔꢊꢎꢨꢊꢚꢃꢆꢚ  
D
D2  
EXPOSED  
PAD  
e
E
E2  
2
1
2
b
1
K
N
N
NOTE 1  
L
TOP VIEW  
BOTTOM VIEW  
A3  
A
A1  
ꢬꢆꢃꢍꢇꢕꢭꢮꢮꢭꢕꢌꢣꢌꢯꢜ  
ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢉꢮꢃꢄꢃꢍꢇ  
ꢕꢭꢰ  
ꢰꢱꢕ  
ꢕꢛꢲ  
ꢰꢐꢄꢳꢅꢓꢉꢈꢑꢉꢪꢃꢆꢇꢰ  
ꢪꢃꢍꢎꢒ  
ꢱꢥꢅꢓꢊꢏꢏꢉꢵꢅꢃꢚꢒꢍ  
ꢜꢍꢊꢆꢋꢈꢑꢑꢉ  
ꢡꢈꢆꢍꢊꢎꢍꢉꢣꢒꢃꢎꢨꢆꢅꢇꢇ  
ꢱꢥꢅꢓꢊꢏꢏꢉꢹꢃꢋꢍꢒ  
ꢌꢖꢔꢈꢇꢅꢋꢉꢪꢊꢋꢉꢹꢃꢋꢍꢒ  
ꢱꢥꢅꢓꢊꢏꢏꢉꢮꢅꢆꢚꢍꢒ  
ꢌꢖꢔꢈꢇꢅꢋꢉꢪꢊꢋꢉꢮꢅꢆꢚꢍꢒ  
ꢡꢈꢆꢍꢊꢎꢍꢉꢹꢃꢋꢍꢒ  
ꢡꢈꢆꢍꢊꢎꢍꢉꢮꢅꢆꢚꢍꢒ  
ꢀꢺ  
ꢗꢁꢺꢟꢉꢠꢜꢡ  
ꢗꢁꢴꢗ  
ꢗꢁꢗꢘ  
ꢗꢁꢘꢗꢉꢯꢌꢧ  
ꢞꢁꢗꢗꢉꢠꢜꢡ  
ꢘꢁꢺꢟ  
ꢞꢁꢗꢗꢉꢠꢜꢡ  
ꢘꢁꢺꢟ  
ꢗꢁꢷꢗ  
ꢗꢁꢗꢗ  
ꢀꢁꢗꢗ  
ꢗꢁꢗꢟ  
ꢛꢀ  
ꢛꢸ  
ꢌꢘ  
ꢂꢘ  
ꢘꢁꢟꢗ  
ꢘꢁꢷꢗ  
ꢘꢁꢟꢗ  
ꢗꢁꢘꢟ  
ꢗꢁꢸꢗ  
ꢗꢁꢘꢗ  
ꢘꢁꢷꢗ  
ꢗꢁꢸꢟ  
ꢗꢁꢟꢗ  
ꢗꢁꢸꢗ  
ꢗꢁꢞꢗ  
ꢡꢈꢆꢍꢊꢎꢍꢼꢍꢈꢼꢌꢖꢔꢈꢇꢅꢋꢉꢪꢊꢋ  
|
ꢛꢔꢊꢃꢉꢜ  
ꢀꢁ ꢪꢃꢆꢉꢀꢉꢥꢃꢇꢐꢊꢏꢉꢃꢆꢋꢅꢖꢉꢑꢅꢊꢍꢐꢓꢅꢉꢄꢊꢤꢉꢥꢊꢓꢤꢩꢉꢳꢐꢍꢉꢄꢐꢇꢍꢉꢳꢅꢉꢏꢈꢎꢊꢍꢅꢋꢉꢦꢃꢍꢒꢃꢆꢉꢍꢒꢅꢉꢒꢊꢍꢎꢒꢅꢋꢉꢊꢓꢅꢊꢁ  
ꢘꢁ ꢪꢊꢎꢨꢊꢚꢅꢉꢃꢇꢉꢇꢊꢦꢉꢇꢃꢆꢚꢐꢏꢊꢍꢅꢋꢁ  
ꢸꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢃꢆꢚꢉꢊꢆꢋꢉꢍꢈꢏꢅꢓꢊꢆꢎꢃꢆꢚꢉꢔꢅꢓꢉꢛꢜꢕꢌꢉꢝꢀꢞꢁꢟꢕꢁ  
ꢠꢜꢡꢢ ꢠꢊꢇꢃꢎꢉꢂꢃꢄꢅꢆꢇꢃꢈꢆꢁꢉꢣꢒꢅꢈꢓꢅꢍꢃꢎꢊꢏꢏꢤꢉꢅꢖꢊꢎꢍꢉꢥꢊꢏꢐꢅꢉꢇꢒꢈꢦꢆꢉꢦꢃꢍꢒꢈꢐꢍꢉꢍꢈꢏꢅꢓꢊꢆꢎꢅꢇꢁ  
ꢯꢌꢧꢢ ꢯꢅꢑꢅꢓꢅꢆꢎꢅꢉꢂꢃꢄꢅꢆꢇꢃꢈꢆꢩꢉꢐꢇꢐꢊꢏꢏꢤꢉꢦꢃꢍꢒꢈꢐꢍꢉꢍꢈꢏꢅꢓꢊꢆꢎꢅꢩꢉꢑꢈꢓꢉꢃꢆꢑꢈꢓꢄꢊꢍꢃꢈꢆꢉꢔꢐꢓꢔꢈꢇꢅꢇꢉꢈꢆꢏꢤꢁ  
ꢕꢃꢎꢓꢈꢎꢒꢃꢔ ꢎꢒꢆꢈꢏꢈꢚꢤ ꢂꢓꢊꢦꢃꢆꢚ ꢡꢗꢞꢼꢀꢘꢙꢠ  
DS22194D-page 60  
2009-2012 Microchip Technology Inc.  
MCP660/1/2/3/4/5/9  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
2009-2012 Microchip Technology Inc.  
DS22194D-page 61  
MCP660/1/2/3/4/5/9  
NOTES:  
DS22194D-page 62  
2009-2012 Microchip Technology Inc.  
MCP660/1/2/3/4/5/9  
APPENDIX A: REVISION HISTORY  
Revision D (March 2012)  
The following is the list of modifications:  
Added the MSOP (8L) package for MCP662 and  
all related information throughout the document.  
Revision C (November 2011)  
The following is the list of modifications:  
1. Added the SOT-23 (5L) and TDFN (8L) package  
option for MCP661 and SOT-23 (6L) package  
options for MCP663 and the related information  
throughout the document. Updated Package  
Types drawing with pin designation for each  
new package.  
2. Updated Table 1-4 to show the temperature  
specifications for new packages.  
3. Updated Table 3-1 to show all the pin functions.  
4. Updated Section 6.0 “Packaging Informa-  
tion” with markings for the new additions.  
Added the corresponding SOT-23 (5L and 6L)  
and 2x3 TDFN (8L) package options and related  
information.  
5. Updated table description and examples in the  
Product Identification System section.  
Revision B (September 2011)  
The following is the list of modifications:  
1. Added the MCP660, MCP664 and MCP669  
amplifiers to the product family and the related  
information throughout the document.  
2. Added the 4x4 QFN (16L) package option for  
MCP660 and MCP669, SOIC and TSSOP (14L)  
package options for MCP660 and MCP665 and  
the related information throughout the  
document. Updated Package Types drawing  
with pin designation for each new package.  
3. Updated Table 1-4 to show the temperature  
specifications for new packages.  
4. Updated Table 3-1 to show all the pin functions.  
5. Updated Section 6.0 “Packaging Informa-  
tion” with markings for the new additions.  
Added the corresponding SOIC and TSSOP  
(14L), and 4x4 QFN (16L) package options and  
related information.  
6. Updated table description and examples in  
Product Identification System.  
Revision A (July 2009)  
Original release of this document.  
2009-2012 Microchip Technology Inc.  
DS22194D-page 63  
MCP660/1/2/3/4/5/9  
NOTES:  
DS22194D-page 64  
2009-2012 Microchip Technology Inc.  
MCP660/1/2/3/4/5/9  
PRODUCT IDENTIFICATION SYSTEM  
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.  
Examples:  
PART NO.  
Device  
-X  
/XX  
a)  
b)  
c)  
MCP660T-E/ML:  
MCP660T-E/SN:  
MCP660T-E/ST:  
Tape and Reel  
Extended temperature,  
16LD QFN package  
Tape and Reel  
Extended temperature,  
14LD SOIC package  
Temperature  
Range  
Package  
Device:  
MCP660  
MCP660T  
Triple Op Amp  
Triple Op Amp (Tape and Reel)  
(SOIC, TSSOP, QFN)  
Tape and Reel  
Extended temperature,  
14LD TSSOP package  
MCP661  
MCP661T  
Single Op Amp  
Single Op Amp (Tape and Reel)  
(SOIC SOT-23 and TDFN)  
Dual Op Amp  
Dual Op Amp (Tape and Reel)  
(DFN, MSOP and SOIC)  
Single Op Amp with CS  
Single Op Amp with CS (Tape and Reel)  
(SOIC and SOT-23)  
d)  
e)  
MCP661T-E/SN:  
Tape and Reel  
Extended temperature,  
8LD SOIC package  
MCP662  
MCP662T  
MCP661T-E/MNY: Tape and Reel,  
Extended Temperature  
MCP663  
MCP663T  
8LD TDFN package  
MCP664  
MCP664T  
Quad Op Amp  
Quad Op Amp (Tape and Reel)  
(SOIC, TSSOP)  
Dual Op Amp with CS  
Dual Op Amp with CS (Tape and Reel)  
(DFN and MSOP)  
Quad Op Amp with CS  
Quad Op Amp with CS (Tape and Reel)  
(QFN)  
f)  
MCP662T-E/MF:  
Tape and Reel  
Extended temperature,  
8LD DFN package  
MCP665  
MCP665T  
g)  
h)  
MCP662T-E/MS: Tape and Reel  
Extended temperature,  
8LD MSOP package  
Tape and Reel  
Extended temperature,  
8LD SOIC package  
MCP669  
MCP669T  
MCP662T-E/SN:  
i)  
j)  
MCP663T-E/SN:  
Tape and Reel  
Extended temperature,  
8LD SOIC package  
Temperature Range:  
Package:  
E
= -40°C to +125°C  
MCP663T-E/CHY: Tape and Reel,  
Extended Temperature,  
CHY = Plastic Small Outline (SOT-23), 6-lead  
MF  
=
Plastic Dual Flat, No Lead (3×3 DFN),  
8-lead, 10-lead  
6LD SOT-23 package  
ML  
=
Plastic Quad Flat, No Lead Package (4x4 QFN),  
(4x4x0.9 mm), 16-lead  
k)  
l)  
MCP664T-E/SN:  
MCP664T-E/ST:  
Tape and Reel  
Extended temperature,  
14LD SOIC package  
Tape and Reel  
Extended temperature,  
14LD TSSOP package  
MNY= Plastic Dual Flat, No Lead (2x3 TDFN),  
8-lead  
MS  
OT  
SL  
=
=
=
Plastic Micro Small Outline (MSOP), 8-lead  
Plastic Small Outline (SOT-23), 5-lead  
Plastic Small Outline, Narrow, (3.90 mm SOIC),  
14-lead  
Plastic Small Outline (3.90 mm), 8-lead  
Plastic Thin Shrink Small Outline, (4.4 mm TSSOP),  
14-lead  
m) MCP665T-E/MF:  
Tape and Reel  
Extended temperature,  
10LD DFN package  
SN  
ST  
=
=
n)  
o)  
MCP665T-E/UN:  
MCP669T-E/ML:  
Tape and Reel  
Extended temperature,  
10LD MSOP package  
UN  
=
Plastic Micro Small Outline (MSOP), 10-lead  
* Y = Nickel palladium gold manufacturing designator.  
Only available on the TDFN package.  
Tape and Reel  
Extended temperature,  
16LD QFN package  
2009-2012 Microchip Technology Inc.  
DS22194D-page 65  
MCP660/1/2/3/4/5/9  
NOTES:  
DS22194D-page 66  
2009-2012 Microchip Technology Inc.  
Note the following details of the code protection feature on Microchip devices:  
Microchip products meet the specification contained in their particular Microchip Data Sheet.  
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the  
intended manner and under normal conditions.  
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our  
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data  
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.  
Microchip is willing to work with the customer who is concerned about the integrity of their code.  
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not  
mean that we are guaranteeing the product as “unbreakable.”  
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our  
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts  
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.  
Information contained in this publication regarding device  
applications and the like is provided only for your convenience  
and may be superseded by updates. It is your responsibility to  
ensure that your application meets with your specifications.  
MICROCHIP MAKES NO REPRESENTATIONS OR  
WARRANTIES OF ANY KIND WHETHER EXPRESS OR  
IMPLIED, WRITTEN OR ORAL, STATUTORY OR  
OTHERWISE, RELATED TO THE INFORMATION,  
INCLUDING BUT NOT LIMITED TO ITS CONDITION,  
QUALITY, PERFORMANCE, MERCHANTABILITY OR  
FITNESS FOR PURPOSE. Microchip disclaims all liability  
arising from this information and its use. Use of Microchip  
devices in life support and/or safety applications is entirely at  
the buyer’s risk, and the buyer agrees to defend, indemnify and  
hold harmless Microchip from any and all damages, claims,  
suits, or expenses resulting from such use. No licenses are  
conveyed, implicitly or otherwise, under any Microchip  
intellectual property rights.  
Trademarks  
The Microchip name and logo, the Microchip logo, dsPIC,  
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,  
32  
PIC logo, rfPIC and UNI/O are registered trademarks of  
Microchip Technology Incorporated in the U.S.A. and other  
countries.  
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,  
MXDEV, MXLAB, SEEVAL and The Embedded Control  
Solutions Company are registered trademarks of Microchip  
Technology Incorporated in the U.S.A.  
Analog-for-the-Digital Age, Application Maestro, chipKIT,  
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,  
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,  
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,  
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,  
MPLINK, mTouch, Omniscient Code Generation, PICC,  
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,  
rfLAB, Select Mode, Total Endurance, TSHARC,  
UniWinDriver, WiperLock and ZENA are trademarks of  
Microchip Technology Incorporated in the U.S.A. and other  
countries.  
SQTP is a service mark of Microchip Technology Incorporated  
in the U.S.A.  
All other trademarks mentioned herein are property of their  
respective companies.  
© 2009-2012, Microchip Technology Incorporated, Printed in  
the U.S.A., All Rights Reserved.  
Printed on recycled paper.  
ISBN: 978-1-62076-073-4  
QUALITY MANAGEMENT SYSTEM  
CERTIFIED BY DNV  
Microchip received ISO/TS-16949:2009 certification for its worldwide  
headquarters, design and wafer fabrication facilities in Chandler and  
Tempe, Arizona; Gresham, Oregon and design centers in California  
and India. The Company’s quality system processes and procedures  
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping  
devices, Serial EEPROMs, microperipherals, nonvolatile memory and  
analog products. In addition, Microchip’s quality system for the design  
and manufacture of development systems is ISO 9001:2000 certified.  
== ISO/TS 16949 ==  
2009-2012 Microchip Technology Inc.  
DS22194D-page 67  
Worldwide Sales and Service  
AMERICAS  
ASIA/PACIFIC  
ASIA/PACIFIC  
EUROPE  
Corporate Office  
2355 West Chandler Blvd.  
Chandler, AZ 85224-6199  
Tel: 480-792-7200  
Fax: 480-792-7277  
Technical Support:  
http://www.microchip.com/  
support  
Asia Pacific Office  
Suites 3707-14, 37th Floor  
Tower 6, The Gateway  
Harbour City, Kowloon  
Hong Kong  
Tel: 852-2401-1200  
Fax: 852-2401-3431  
India - Bangalore  
Tel: 91-80-3090-4444  
Fax: 91-80-3090-4123  
Austria - Wels  
Tel: 43-7242-2244-39  
Fax: 43-7242-2244-393  
Denmark - Copenhagen  
Tel: 45-4450-2828  
Fax: 45-4485-2829  
India - New Delhi  
Tel: 91-11-4160-8631  
Fax: 91-11-4160-8632  
France - Paris  
Tel: 33-1-69-53-63-20  
Fax: 33-1-69-30-90-79  
India - Pune  
Tel: 91-20-2566-1512  
Fax: 91-20-2566-1513  
Australia - Sydney  
Tel: 61-2-9868-6733  
Fax: 61-2-9868-6755  
Web Address:  
www.microchip.com  
Germany - Munich  
Tel: 49-89-627-144-0  
Fax: 49-89-627-144-44  
Japan - Osaka  
Tel: 81-66-152-7160  
Fax: 81-66-152-9310  
Atlanta  
Duluth, GA  
Tel: 678-957-9614  
Fax: 678-957-1455  
China - Beijing  
Tel: 86-10-8569-7000  
Fax: 86-10-8528-2104  
Italy - Milan  
Tel: 39-0331-742611  
Fax: 39-0331-466781  
Japan - Yokohama  
Tel: 81-45-471- 6166  
Fax: 81-45-471-6122  
China - Chengdu  
Tel: 86-28-8665-5511  
Fax: 86-28-8665-7889  
Boston  
Westborough, MA  
Tel: 774-760-0087  
Fax: 774-760-0088  
Netherlands - Drunen  
Tel: 31-416-690399  
Fax: 31-416-690340  
Korea - Daegu  
Tel: 82-53-744-4301  
Fax: 82-53-744-4302  
China - Chongqing  
Tel: 86-23-8980-9588  
Fax: 86-23-8980-9500  
Chicago  
Itasca, IL  
Tel: 630-285-0071  
Fax: 630-285-0075  
Spain - Madrid  
Tel: 34-91-708-08-90  
Fax: 34-91-708-08-91  
Korea - Seoul  
China - Hangzhou  
Tel: 86-571-2819-3187  
Fax: 86-571-2819-3189  
Tel: 82-2-554-7200  
Fax: 82-2-558-5932 or  
82-2-558-5934  
UK - Wokingham  
Tel: 44-118-921-5869  
Fax: 44-118-921-5820  
Cleveland  
Independence, OH  
Tel: 216-447-0464  
Fax: 216-447-0643  
China - Hong Kong SAR  
Tel: 852-2401-1200  
Fax: 852-2401-3431  
Malaysia - Kuala Lumpur  
Tel: 60-3-6201-9857  
Fax: 60-3-6201-9859  
Dallas  
Addison, TX  
Tel: 972-818-7423  
Fax: 972-818-2924  
China - Nanjing  
Tel: 86-25-8473-2460  
Fax: 86-25-8473-2470  
Malaysia - Penang  
Tel: 60-4-227-8870  
Fax: 60-4-227-4068  
China - Qingdao  
Tel: 86-532-8502-7355  
Fax: 86-532-8502-7205  
Philippines - Manila  
Tel: 63-2-634-9065  
Fax: 63-2-634-9069  
Detroit  
Farmington Hills, MI  
Tel: 248-538-2250  
Fax: 248-538-2260  
China - Shanghai  
Tel: 86-21-5407-5533  
Fax: 86-21-5407-5066  
Singapore  
Tel: 65-6334-8870  
Fax: 65-6334-8850  
Indianapolis  
Noblesville, IN  
Tel: 317-773-8323  
Fax: 317-773-5453  
China - Shenyang  
Tel: 86-24-2334-2829  
Fax: 86-24-2334-2393  
Taiwan - Hsin Chu  
Tel: 886-3-5778-366  
Fax: 886-3-5770-955  
Los Angeles  
China - Shenzhen  
Tel: 86-755-8203-2660  
Fax: 86-755-8203-1760  
Taiwan - Kaohsiung  
Tel: 886-7-536-4818  
Fax: 886-7-330-9305  
Mission Viejo, CA  
Tel: 949-462-9523  
Fax: 949-462-9608  
China - Wuhan  
Tel: 86-27-5980-5300  
Fax: 86-27-5980-5118  
Taiwan - Taipei  
Tel: 886-2-2500-6610  
Fax: 886-2-2508-0102  
Santa Clara  
Santa Clara, CA  
Tel: 408-961-6444  
Fax: 408-961-6445  
China - Xian  
Tel: 86-29-8833-7252  
Fax: 86-29-8833-7256  
Thailand - Bangkok  
Tel: 66-2-694-1351  
Fax: 66-2-694-1350  
Toronto  
Mississauga, Ontario,  
Canada  
China - Xiamen  
Tel: 905-673-0699  
Fax: 905-673-6509  
Tel: 86-592-2388138  
Fax: 86-592-2388130  
China - Zhuhai  
Tel: 86-756-3210040  
Fax: 86-756-3210049  
11/29/11  
DS22194D-page 68  
2009-2012 Microchip Technology Inc.  

相关型号:

MCP661T-E/SN

60 MHz, 6 mA Op Amps
MICROCHIP

MCP661T-E/UN

60 MHz, 6 mA Op Amps
MICROCHIP

MCP662

60 MHz, 6 mA Op Amps
MICROCHIP

MCP662-E/MF

60 MHz, 6 mA Op Amps
MICROCHIP

MCP662-E/MS

MCP662-E/MS
MICROCHIP

MCP662-E/SL

DUAL OP-AMP, 8000 uV OFFSET-MAX, 60 MHz BAND WIDTH, PDSO14, 3.90 MM, ROHS COMPLIANT, PLASTIC, SOIC-14
MICROCHIP

MCP662-E/SN

60 MHz, 6 mA Op Amps
MICROCHIP

MCP662-E/UN

60 MHz, 6 mA Op Amps
MICROCHIP

MCP662T

60 MHz, 6 mA Op Amps
MICROCHIP

MCP662T-E/MF

60 MHz, 6 mA Op Amps
MICROCHIP
MICROCHIP

MCP662T-E/SN

60 MHz, 6 mA Op Amps
MICROCHIP