PIC24FV32KA304_13 [MICROCHIP]
20/28/44/48-Pin, General Purpose, 16-Bit Flash Microcontrollers with XLP Technology; 二十八分之二十/ 44/ 48引脚,通用, 16位闪存微控制器与XLP技术型号: | PIC24FV32KA304_13 |
厂家: | MICROCHIP |
描述: | 20/28/44/48-Pin, General Purpose, 16-Bit Flash Microcontrollers with XLP Technology |
文件: | 总364页 (文件大小:4558K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PIC24FV32KA304 FAMILY
20/28/44/48-Pin, General Purpose, 16-Bit Flash
Microcontrollers with XLP Technology
Power Management Modes
Analog Features
• Run – CPU, Flash, SRAM and Peripherals On
• Doze – CPU Clock Runs Slower than Peripherals
• Idle – CPU Off, Flash, SRAM and Peripherals On
• Sleep – CPU, Flash and Peripherals Off, and
SRAM On
• 12-Bit, Up to 16-Channel Analog-to-Digital Converter:
- 100 ksps conversion rate
- Conversion available during Sleep and Idle
- Auto-sampling, timer-based option for Sleep and
Idle modes
• Deep Sleep – CPU, Flash, SRAM and Most Peripherals
Off; Multiple Autonomous Wake-up Sources
• Low-Power Consumption:
- Wake on auto-compare option
• Dual Rail-to-Rail Analog Comparators with
Programmable Input/Output Configuration
• On-Chip Voltage Reference
- Run mode currents down to 8 μA, typical
- Idle mode currents down to 2.2 μA, typical
- Deep Sleep mode currents down to 20 nA, typical
- Real-Time Clock/Calendar currents down to
700 nA, 32 kHz, 1.8V
• Internal Temperature Sensor
• Charge Time Measurement Unit (CTMU):
- Used for capacitance sensing, 16 channels
- Time measurement, down to 200 ps resolution
-
Watchdog Timer is 500 nA, 1.8V typical
-
Delay/pulse generation, down to 1 ns resolution
High-Performance CPU
Special Microcontroller Features
• Modified Harvard Architecture
• Wide Operating Voltage Range:
• Up to 16 MIPS Operation @ 32 MHz
• 8 MHz Internal Oscillator with 4x PLL Option and
Multiple Divide Options
- 1.8V to 3.6V (PIC24F devices)
- 2.0V to 5.5V (PIC24FV devices)
• Low-Power Wake-up Sources and Supervisors:
- Ultra Low-Power Wake-up (ULPWU) for
Sleep/Deep Sleep
• 17-Bit by 17-Bit Single-Cycle Hardware Multiplier
• 32-Bit by 16-Bit Hardware Divider, 16-Bit x 16-Bit
Working Register Array
- Low-Power Watchdog Timer (DSWDT) for
Deep Sleep
• C Compiler Optimized Instruction Set Architecture
- Extreme Low-Power Brown-out Reset (DSBOR)
for Deep Sleep, LPBOR for all other modes
• System Frequency Range Declaration bits:
- Declaring the frequency range optimizes the
current consumption.
Peripheral Features
• Hardware Real-Time Clock and Calendar (RTCC):
- Provides clock, calendar and alarm functions
- Can run in Deep Sleep mode
- Can use 50/60 Hz power line input as clock source
• Programmable 32-Bit Cyclic Redundancy Check
(CRC)
• Standard Watchdog Timer (WDT) with On-Chip,
Low-Power RC Oscillator for Reliable Operation
• Programmable High/Low-Voltage Detect (HLVD)
• Standard Brown-out Reset (BOR) with 3 Programmable
Trip Points that can be Disabled in Sleep
• Multiple Serial Communication modules:
- Two 3/4-wire SPI modules
2
•
High-Current Sink/Source (18 mA/18 mA) on All I/O Pins
- Two I C™ modules with multi-master/slave support
• Flash Program Memory:
- Two UART modules supporting RS-485, RS-232,
®
- Erase/write cycles: 10,000 minimum
- 40 years’ data retention minimum
• Data EEPROM:
LIN/J2602, IrDA
• Five 16-Bit Timers/Counters with Programmable
Prescaler:
- Can be paired as 32-bit timers/counters
• Three 16-Bit Capture Inputs with Dedicated Timers
• Three 16-Bit Compare/PWM Outputs with Dedicated
Timers
• Configurable Open-Drain Outputs on Digital I/O Pins
• Up to Three External Interrupt Sources
- Erase/write cycles: 100,000 minimum
- 40 years’ data retention minimum
• Fail-Safe Clock Monitor (FSCM)
• Programmable Reference Clock Output
• Self-Programmable under Software Control
• In-Circuit Serial Programming™ (ICSP™) and
In-Circuit Debug (ICD) via 2 Pins
2011-2013 Microchip Technology Inc.
DS39995D-page 1
PIC24FV32KA304 FAMILY
Memory
PIC24F
Device
PIC24FV16KA301/
PIC24F16KA301
20
20
28
28
44
44
16K
32K
16K
32K
16K
32K
2K
2K
2K
2K
2K
2K
512
512
512
512
512
512
5
5
5
5
5
5
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
12
12
13
13
16
16
3
3
3
3
3
3
12
12
13
13
16
16
Y
Y
Y
Y
Y
Y
PIC24FV32KA301/
PIC24F32KA301
PIC24FV16KA302/
PIC24F16KA302
PIC24FV32KA302/
PIC24F32KA302
PIC24FV16KA304/
PIC24F16KA304
PIC24FV32KA304/
PIC24F32KA304
DS39995D-page 2
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
Pin Diagrams
20-Pin SPDIP/SSOP/SOIC(1)
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
12
11
VDD
VSS
MCLR/RA5
RA0
RA1
RB0
RB1
RB2
RA2
RA3
RB4
RA4
RB15
RB14
RB13
RB12
RA6 or VCAP
RB9
9
10
RB8
RB7
Pin Features
Pin
PIC24FVXXKA301
PIC24FXXKA301
1
MCLR/VPP/RA5
MCLR/VPP/RA5
2
3
4
PGEC2/VREF+/CVREF+/AN0/C3INC/SCK2/CN2/RA0
PGED2/CVREF-/VREF-/AN1/SDO2/CN3/RA1
PGEC2/VREF+/CVREF+/AN0/C3INC/SCK2/CN2/RA0
PGED2/CVREF-/VREF-/AN1/SDO2/CN3/RA1
PGED1/AN2/ULPWU/CTCMP/C1IND/C2INB/C3IND/U2TX/SDI2/
OC2/CN4/RB0
PGED1/AN2/ULPWU/CTCMP/C1IND/C2INB/C3IND/U2TX/SDI2/
OC2/CN4/RB0
5
6
7
8
PGEC1/AN3/C1INC/C2INA/U2RX/OC3/CTED12/CN5/RB1
AN4/SDA2/T5CK/T4CK/U1RX/CTED13/CN6/RB2
OSCI/AN13/C1INB/C2IND/CLKI/CN30/RA2
PGEC1/AN3/C1INC/C2INA/U2RX/OC3/CTED12/CN5/RB1
AN4/SDA2/T5CK/T4CK/U1RX/CTED13/CN6/RB2
OSCI/AN13/C1INB/C2IND/CLKI/CN30/RA2
OSCO/AN14/C1INA/C2INC/CLKO/CN29/RA3
OSCO/AN14/C1INA/C2INC/CLKO/CN29/RA3
9
PGED3/SOSCI/AN15/U2RTS/CN1/RB4
PGEC3/SOSCO/SCLKI/U2CTS/CN0/RA4
U1TX/C2OUT/OC1/IC1/CTED1/INT0/CN23/RB7
SCL1/U1CTS/C3OUT/CTED10/CN22/RB8
PGED3/SOSCI/AN15/U2RTS/CN1/RB4
PGEC3/SOSCO/SCLKI/U2CTS/CN0/RA4
U1TX/INT0/CN23/RB7
10
11
12
SCL1/U1CTS/C3OUT/CTED10/CN22/RB8
13
14
15
16
17
SDA1/T1CK/U1RTS/IC2/CTED4/CN21/RB9
VCAP
SDA1/T1CK/U1RTS/IC2/CTED4/CN21/RB9
C2OUT/OC1/IC1/CTED1/INT2/CN8/RA6
AN12/HLVDIN/SCK1/SS2/IC3/CTED2/CN14/RB12
AN11/SDO1/OCFB/CTPLS/CN13/RB13
AN12/HLVDIN/SCK1/SS2/IC3/CTED2/INT2/CN14/RB12
AN11/SDO1/OCFB/CTPLS/CN13/RB13
CVREF/AN10/C3INB/RTCC/SDI1/C1OUT/OCFA/CTED5/INT1/
CVREF/AN10/C3INB/RTCC/SDI1/C1OUT/OCFA/CTED5/INT1/
CN12/RB14
CN12/RB14
18
19
20
AN9/C3INA/SCL2/T3CK/T2CK/REFO/SS1/CTED6/CN11/RB15
AN9/C3INA/SCL2/T3CK/T2CK/REFO/SS1/CTED6/CN11/RB15
VSS/AVSS
VDD/AVDD
VSS/AVSS
VDD/AVDD
Legend:
Pin numbers in bold indicate pin function differences between PIC24FV and PIC24F devices.
Note 1: PIC24F32KA304 device pins have a maximum voltage of 3.6V and are not 5V tolerant.
2011-2013 Microchip Technology Inc.
DS39995D-page 3
PIC24FV32KA304 FAMILY
Pin Diagrams
28-Pin SPDIP/SSOP/SOIC(1,2)
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
VSS
MCLR/RA5
RA0
RB15
RB14
RB13
RB12
RB11
RB10
RA6 or VCAP
RA7
RB9
RB8
RB7
RB6
RA1
RB0
RB1
RB2
RB3
VSS
RA2
RA3
RB4
RA4
VDD
RB5
9
10
11
12
13
14
Pin Features
Pin
PIC24FVXXKA302
PIC24FXXKA302
1
MCLR/VPP/RA5
MCLR/VPP/RA5
2
VREF+/CVREF+/AN0/C3INC/CTED1/CN2/RA0
CVREF-/VREF-/AN1/CN3/RA1
VREF+/CVREF+/AN0/C3INC/CTED1/CN2/RA0
CVREF-/VREF-/AN1/CN3/RA1
3
4
PGED1/AN2/ULPWU/CTCMP/C1IND/C2INB/C3IND/U2TX/CN4/RB0 PGED1/AN2/ULPWU/CTCMP/C1IND/C2INB/C3IND/U2TX/CN4/RB0
5
PGEC1/AN3/C1INC/C2INA/U2RX/CTED12/CN5/RB1
AN4/C1INB/C2IND/SDA2/T5CK/T4CK/U1RX/CTED13/CN6/RB2
AN5/C1INA/C2INC/SCL2/CN7/RB3
VSS
PGEC1/AN3/C1INC/C2INA/U2RX/CN5/RB1
AN4/C1INB/C2IND/SDA2/T5CK/T4CK/U1RX/CTED13/CN6/RB2
AN5/C1INA/C2INC/SCL2/CN7/RB3
VSS
6
7
8
9
OSCI/AN13/CLKI/CN30/RA2
OSCI/AN13/CLKI/CN30/RA2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
OSCO/AN14/CLKO/CN29/RA3
SOSCI/AN15/U2RTS/CN1/RB4
SOSCO/SCLKI/U2CTS/CN0/RA4
VDD
PGED3/ASDA(1)/SCK2/CN27/RB5
PGEC3/ASCL(1)/SDO2/CN24/RB6
U1TX/C2OUT/OC1/INT0/CN23/RB7
SCL1/U1CTS/C3OUT/CTED10/CN22/RB8
SDA1/T1CK/U1RTS/IC2/CTED4/CN21/RB9
SDI2/IC1/CTED3/CN9/RA7
OSCO/AN14/CLKO/CN29/RA3
SOSCI/AN15/U2RTS/CN1/RB4
SOSCO/SCLKI/U2CTS/CN0/RA4
VDD
PGED3/ASDA(1)/SCK2/CN27/RB5
PGEC3/ASCL(1)/SDO2/CN24/RB6
U1TX/INT0/CN23/RB7
SCL1/U1CTS/C3OUT/CTED10/CN22/RB8
SDA1/T1CK/U1RTS/IC2/CTED4/CN21/RB9
SDI2/IC1/CTED3/CN9/RA7
VCAP
C2OUT/OC1/CTED1/INT2/CN8/RA6
PGED2/SDI1/OC3/CTED11/CN16/RB10
PGEC2/SCK1/OC2/CTED9/CN15/RB11
AN12/HLVDIN/SS2/IC3/CTED2/CN14/RB12
AN11/SDO1/OCFB/CTPLS/CN13/RB13
PGED2/SDI1/OC3/CTED11/CN16/RB10
PGEC2/SCK1/OC2/CTED9/CN15/RB11
AN12/HLVDIN/SS2/IC3/CTED2/INT2/CN14/RB12
AN11/SDO1/OCFB/CTPLS/CN13/RB13
CVREF/AN10/C3INB/RTCC/C1OUT/OCFA/CTED5/INT1/CN12/RB14 CVREF/AN10/C3INB/RTCC/C1OUT/OCFA/CTED5/INT1/CN12/
RB14
26
27
28
AN9/C3INA/T3CK/T2CK/REFO/SS1/CTED6/CN11/RB15
AN9/C3INA/T3CK/T2CK/REFO/SS1/CTED6/CN11/RB15
VSS/AVSS
VDD/AVDD
VSS/AVSS
VDD/AVDD
Legend:
Pin numbers in bold indicate pin function differences between PIC24FV and PIC24F devices.
Note 1: Alternative multiplexing for SDA1 (ASDA1) and SCL1 (ASCL1) when the I2CSEL Configuration bit is set.
2: PIC24F32KA304 device pins have a maximum voltage of 3.6V and are not 5V tolerant.
DS39995D-page 4
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
Pin Diagrams
28-Pin QFN(1,2,3)
28272625242322
RB0
RB1
RB2
RB13
21
1
2
3
4
5
6
7
RB12
20
RB11
RB10
RA6 or VCAP
RA7
RB9
19
18
17
16
15
PIC24FVXXKA302
PIC24FXXKA302
RB3
VSS
RA2
RA3
8
9 1011 121314
Pin Features
Pin
PIC24FVXXKA302
PIC24FXXKA302
1
2
3
4
5
6
7
PGED1/AN2/ULPWU/CTCMP/C1IND/C2INB/C3IND/U2TX/CN4/RB0 PGED1/AN2/ULPWU/CTCMP/C1IND/C2INB/C3IND/U2TX/CN4/RB0
PGEC1/AN3/C1INC/C2INA/U2RX/CTED12/CN5/RB1
AN4/C1INB/C2IND/SDA2/T5CK/T4CK/U1RX/CTED13/CN6/RB2
AN5/C1INA/C2INC/SCL2/CN7/RB3
VSS
PGEC1/AN3/C1INC/C2INA/U2RX/CTED12/CN5/RB1
AN4/C1INB/C2IND/SDA2/T5CK/T4CK/U1RX/CTED13/CN6/RB2
AN5/C1INA/C2INC/SCL2/CN7/RB3
VSS
OSCI/AN13/CLKI/CN30/RA2
OSCI/AN13/CLKI/CN30/RA2
OSCO/AN14/CLKO/CN29/RA3
OSCO/AN14/CLKO/CN29/RA3
8
9
SOSCI/AN15/U2RTS/CN1/RB4
SOSCO/SCLKI/U2CTS/CN0/RA4
VDD
SOSCI/AN15/U2RTS/CN1/RB4
SOSCO/SCLKI/U2CTS/CN0/RA4
VDD
10
11 PGED3/ASDA1(2)/SCK2/CN27/RB5
12 PGEC3/ASCL1(2)/SDO2/CN24/RB6
13 U1TX/C2OUT/OC1/INT0/CN23/RB7
14 SCL1/U1CTS/C3OUT/CTED10/CN22/RB8
PGED3/ASDA1(2)/SCK2/CN27/RB5
PGEC3/ASCL1(2)/SDO2/CN24/RB6
U1TX/INT0/CN23/RB7
SCL1/U1CTS/C3OUT/CTED10/CN22/RB8
15 SDA1/T1CK/U1RTS/IC2/CTED4/CN21/RB9
16 SDI2/IC1/CTED3/CN9/RA7
SDA1/T1CK/U1RTS/IC2/CTED4/CN21/RB9
SDI2/IC1/CTED3/CN9/RA7
17
VCAP
C2OUT/OC1/CTED1/INT2/CN8/RA6
PGED2/SDI1/OC3/CTED11/CN16/RB10
PGEC2/SCK1/OC2/CTED9/CN15/RB11
AN12/HLVDIN/SS2/IC3/CTED2/CN14/RB12
AN11/SDO1/OCFB/CTPLS/CN13/RB13
18 PGED2/SDI1/OC3/CTED11/CN16/RB10
19 PGEC2/SCK1/OC2/CTED9/CN15/RB11
20 AN12/HLVDIN/SS2/IC3/CTED2/INT2/CN14/RB12
21 AN11/SDO1/OCFB/CTPLS/CN13/RB13
22 CVREF/AN10/C3INB/RTCC/C1OUT/OCFA/CTED5/INT1/CN12/
CVREF/AN10/C3INB/RTCC/C1OUT/OCFA/CTED5/INT1/CN12/
RB14
RB14
23 AN9/C3INA/T3CK/T2CK/REFO/SS1/CTED6/CN11/RB15
AN9/C3INA/T3CK/T2CK/REFO/SS1/CTED6/CN11/RB15
VSS/AVSS
24
25
VSS/AVSS
VDD/AVDD
VDD/AVDD
26 MCLR/VPP/RA5
MCLR/VPP/RA5
27 VREF+/CVREF+/AN0/C3INC/CTED1/CN2/RA0
28 CVREF-/VREF-/AN1/CN3/RA1
VREF+/CVREF+/AN0/C3INC/CN2/RA0
CVREF-/VREF-/AN1/CN3/RA1
Legend:
Note 1:
Pin numbers in bold indicate pin function differences between PIC24FV and PIC24F devices.
Exposed pad on underside of device is connected to VSS.
2: Alternative multiplexing for SDA1 (ASDA1) and SCL1 (ASCL1) when the I2CSEL Configuration bit is set.
3: PIC24F32KA304 device pins have a maximum voltage of 3.6V and are not 5V tolerant.
2011-2013 Microchip Technology Inc.
DS39995D-page 5
PIC24FV32KA304 FAMILY
Pin Diagrams
Pin Features
Pin
44-Pin TQFP/QFN(1,2,3)
PIC24FVXXKA304
PIC24FXXKA304
1
SDA1/T1CK/U1RTS/CTED4/CN21/ SDA1/T1CK/U1RTS/CTED4/CN21/
RB9
RB9
2
U1RX/CN18/RC6
U1TX/CN17/RC7
OC2/CN20/RC8
IC2/CTED7/CN19/RC9
IC1/CTED3/CN9/RA7
VCAP
U1RX/CN18/RC6
3
U1TX/CN17/RC7
4
OC2/CN20/RC8
5
IC2/CTED7/CN19/RC9
IC1/CTED3/CN9/RA7
C2OUT/OC1/CTED1/INT2/CN8/RA6
6
RB9
RC6
RC7
RC8
RC9
RB4
RA8
RA3
RA2
VSS
33
32
31
30
1
2
3
4
5
6
7
8
7
8
PGED2/SDI1/CTED11/CN16/RB10 PGED2/SDI1/CTED11/CN16/RB10
PGEC2/SCK1/CTED9/CN15/RB11 PGEC2/SCK1/CTED9/CN15/RB11
9
29
PIC24FVXXKA304
PIC24FXXKA304
RA7
28 VDD
10
AN12/HLVDIN/CTED2/INT2/CN14/ AN12/HLVDIN/CTED2/CN14/RB12
RB12
RA6 or VCAP
RB10
RC2
RC1
RC0
RB3
RB2
27
26
25
24
23
11
12
13
14
AN11/SDO1/CTPLS/CN13/RB13
OC3/CN35/RA10
AN11/SDO1/CTPLS/CN13/RB13
OC3/CN35/RA10
RB11
RB12
RB13
9
10
11
IC3/CTED8/CN36/RA11
CVREF/AN10/C3INB/RTCC/
IC3/CTED8/CN36/RA11
CVREF/AN10/C3INB/RTCC/
C1OUT/OCFA/CTED5/INT1/CN12/ C1OUT/OCFA/CTED5/INT1/CN12/
RB14
RB14
15
AN9/C3INA/T3CK/T2CK/REFO/
SS1/CTED6/CN11/RB15
AN9/C3INA/T3CK/T2CK/REFO/
SS1/CTED6/CN11/RB15
16
17
VSS/AVSS
VDD/AVDD
VSS/AVSS
VDD/AVDD
18
19
MCLR/VPP/RA5
MCLR/VPP/RA5
VREF+/CVREF+/AN0/C3INC/
CTED1/CN2/RA0
VREF+/CVREF+/AN0/C3INC/CN2/
RA0
20
21
CVREF-/VREF-/AN1/CN3/RA1
PGED1/AN2/ULPWU/CTCMP/
CVREF-/VREF-/AN1/CN3/RA1
PGED1/AN2/ULPWU/CTCMP/C1IND/
C1IND/C2INB/C3IND/U2TX/CN4/RB0 C2INB/C3IND/U2TX/CN4/RB0
22
23
24
PGEC1/AN3/C1INC/C2INA/U2RX/ PGEC1/AN3/C1INC/C2INA/U2RX/
CTED12/CN5/RB1
CTED12/CN5/RB1
AN4/C1INB/C2IND/SDA2/T5CK/
T4CK/CTED13/CN6/RB2
AN4/C1INB/C2IND/SDA2/T5CK/
T4CK/CTED13/CN6/RB2
AN5/C1INA/C2INC/SCL2/CN7/
RB3
AN5/C1INA/C2INC/SCL2/CN7/RB3
25
26
27
28
29
30
31
32
AN6/CN32/RC0
AN7/CN31/RC1
AN8/CN10/RC2
VDD
AN6/CN32/RC0
AN7/CN31/RC1
AN8/CN10/RC2
VDD
VSS
VSS
OSCI/AN13/CLKI/CN30/RA2
OSCO/AN14/CLKO/CN29/RA3
OCFB/CN33/RA8
OSCI/AN13/CLKI/CN30/RA2
OSCO/AN14/CLKO/CN29/RA3
OCFB/CN33/RA8
33
34
SOSCI/AN15/U2RTS/CN1/RB4
SOSCO/SCLKI/U2CTS/CN0/RA4
SOSCI/AN15/U2RTS/CN1/RB4
SOSCO/SCLKI/U2CTS/CN0/RA4
Legend:
Note 1:
Pin numbers in bold indicate pin
function differences between
PIC24FV and PIC24F devices.
35
36
37
38
39
40
41
42
43
SS2/CN34/RA9
SS2/CN34/RA9
SDI2/CN28/RC3
SDO2/CN25/RC4
SCK2/CN26/RC5
VSS
SDI2/CN28/RC3
SDO2/CN25/RC4
SCK2/CN26/RC5
VSS
Exposed pad on underside of device
is connected to VSS.
2: Alternative multiplexing for SDA1
(ASDA1) and SCL1 (ASCL1) when
the I2CSEL Configuration bit is set.
3: PIC24F32KA304 device pins have a
maximum voltage of 3.6V and are not
5V tolerant.
VDD
VDD
PGED3/ASDA1(2)/CN27/RB5
PGEC3/ASCL1(2)/CN24/RB6
C2OUT/OC1/INT0/CN23/RB7
PGED3/ASDA1(2)/CN27/RB5
PGEC3/ASCL1(2)/CN24/RB6
INT0/CN23/RB7
44
SCL1/U1CTS/C3OUT/CTED10/
CN22/RB8
SCL1/U1CTS/C3OUT/CTED10/
CN22/RB8
DS39995D-page 6
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
Pin Diagrams
Pin Features
Pin
48-Pin UQFN(1,2,3)
PIC24FVXXKA304
PIC24FXXKA304
1
SDA1/T1CK/U1RTS/CTED4/CN21/RB9 SDA1/T1CK/U1RTS/CTED4/CN21/
RB9
2
3
4
5
6
7
8
9
U1RX/CN18/RC6
U1TX/CN17/RC7
OC2/CN20/RC8
IC2/CTED7/CN19/RC9
IC1/CTED3/CN9/RA7
VCAP
U1RX/CN18/RC6
U1TX/CN17/RC7
OC2/CN20/RC8
IC2/CTED7/CN19/RC9
IC1/CTED3/CN9/RA7
C20UT/OC1/CTED1/INT2CN8/RA6
N/C
RB9
RC6
RC7
RC8
RC9
RA7
1
2
3
4
5
6
7
8
36 RB4
35 RA8
34 RA3
33 RA2
32 N/C
N/C
PGED2/SDI1/CTED11/CN16/RB10
PGED2/SDI1/CTED11/CN16/RB10
PGEC2/SCK1/CTED9/CN15/RB11
PIC24FVXXKA304
PIC24FXXKA304
31
30
V
VDD
SS
10 PGEC2/SCK1/CTED9/CN15/RB11
RA6 or VCAP
N/C
29 RC2
28 RC1
27 RC0
26 RB3
25 RB2
11 AN12/HLVDIN/CTED2/INT2/CN14/RB12 AN12/HLVDIN/CTED2/CN14/RB12
RB10
RB11
RB12
RB13
9
12 AN11/SDO1/CTPLS/CN13/RB13
13 OC3/CN35/RA10
AN11/SDO1/CTPLS/CN13/RB13
OC3/CN35/RA10
10
11
12
14 IC3/CTED8/CN36/RA11
IC3/CTED8/CN36/RA11
15 CVREF/AN10/C3INB/RTCC/
CVREF/AN10/C3INB/RTCC/C1OUT/
C1OUT/OCFA/CTED5/INT1/CN12/RB14 OCFA/CTED5/INT1/CN12/RB14
16 AN9/C3INA/T3CK/T2CK/REFO/
SS1/CTED6/CN11/RB15
AN9/C3INA/T3CK/T2CK/REFO/
SS1/CTED6/CN11/RB15
17 VSS/AVSS
18 VDD/AVDD
VSS/AVSS
VDD/AVDD
19 MCLR/RA5
20 N/C
MCLR/RA5
N/C
21
VREF+/CVREF+/AN0/C3INC/
VREF+/CVREF+/AN0/C3INC/CN2/
CTED1/CN2/RA0
RA0
22 CVREF-/VREF-/AN1/CN3/RA1
CVREF-/VREF-/AN1/CN3/RA1
23 PGED1/AN2/ULPWU/CTCMP/C1IND/
C2INB/C3IND/U2TX/CN4/RB0
PGED1/AN2/ULPWU/CTCMP/C1IND/
C2INB/C3IND/U2TX/CN4/RB0
24 PGEC1/AN3/C1INC/C2INA/U2RX/
CTED12/CN5/RB1
PGEC1/AN3/C1INC/C2INA/U2RX/
CTED12/CN5/RB1
25 AN4/C1INB/C2IND/SDA2/T5CK/
T4CK/CTED13/CN6/RB2
AN4/C1INB/C2IND/SDA2/T5CK/
T4CK/CTED13/CN6/RB2
26 AN5/C1INA/C2INC/SCL2/CN7/RB3
27 AN6/CN32/RC0
28 AN7/CN31/RC1
29 AN8/CN10/RC2
30 VDD
AN5/C1INA/C2INC/SCL2/CN7/RB3
AN6/CN32/RC0
AN7/CN31/RC1
AN8/CN10/RC2
VDD
31 VSS
VSS
32 N/C
N/C
33 OSCI/AN13/CLKI/CN30/RA2
34 OSCO/AN14/CLKO/CN29/RA3
35 OCFB/CN33/RA8
OSCI/AN13/CLKI/CN30/RA2
OSCO/AN14/CLKO/CN29/RA3
OCFB/CN33/RA8
36 SOSCI/AN15/U2RTS/CN1/RB4
37 SOSCO/SCLKI/U2CTS/CN0/RA4
SOSCI/AN15/U2RTS/CN1/RB4
SOSCO/SCLKI/U2CTS/CN0/RA4
38 SS2/CN34/RA9
39 SDI2/CN28/RC3
40 SDO2/CN25/RC4
41 SCK2/CN26/RC5
42 VSS
SS2/CN34/RA9
SDI2/CN28/RC3
SDO2/CN25/RC4
SCK2/CN26/RC5
VSS
Legend:
Note 1:
Pin numbers in bold indicate pin func-
tion differences between PIC24FV and
PIC24F devices.
Exposed pad on underside of device is
connected to VSS.
43 VDD
VDD
2: Alternative multiplexing for SDA1
(ASDA1) and SCL1 (ASCL1) when the
I2CSEL Configuration bit is set.
3: PIC24F32KA3XX device pins have a
maximum voltage of 3.6V and are not
5V tolerant.
44 N/C
N/C
45 PGED3/ASDA1(2)/CN27/RB5
46 PGEC3/ASCL1(2)/CN24/RB6
47 C2OUT/OC1/INT0/CN23/RB7
PGED3/ASDA1(2)/CN27/RB5
PGEC3/ASCL1(2)/CN24/RB6
INT0/CN23/RB7
48 SCL1/U1CTS/C3OUT/CTED10/
CN22/RB8
SCL1/U1CTS/C3OUT/CTED10/
CN22/RB8
2011-2013 Microchip Technology Inc.
DS39995D-page 7
PIC24FV32KA304 FAMILY
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 11
2.0 Guidelines for Getting Started with 16-Bit Microcontrollers........................................................................................................ 23
3.0 CPU ........................................................................................................................................................................................... 29
4.0 Memory Organization................................................................................................................................................................. 35
5.0 Flash Program Memory.............................................................................................................................................................. 57
6.0 Data EEPROM Memory ............................................................................................................................................................. 63
7.0 Resets ........................................................................................................................................................................................ 69
8.0 Interrupt Controller ..................................................................................................................................................................... 75
9.0 Oscillator Configuration ............................................................................................................................................................ 115
10.0 Power-Saving Features............................................................................................................................................................ 125
11.0 I/O Ports ................................................................................................................................................................................... 135
12.0 Timer1 ..................................................................................................................................................................................... 139
13.0 Timer2/3 and Timer4/5............................................................................................................................................................. 141
14.0 Input Capture with Dedicated Timers....................................................................................................................................... 147
15.0 Output Compare with Dedicated Timers .................................................................................................................................. 151
16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 161
2
17.0 Inter-Integrated Circuit™ (I C™).............................................................................................................................................. 169
18.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 177
19.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 185
20.0 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator........................................................................................ 199
21.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 205
22.0 12-Bit A/D Converter with Threshold Detect ............................................................................................................................ 207
23.0 Comparator Module.................................................................................................................................................................. 225
24.0 Comparator Voltage Reference................................................................................................................................................ 229
25.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 231
26.0 Special Features ...................................................................................................................................................................... 239
27.0 Development Support............................................................................................................................................................... 251
28.0 Instruction Set Summary.......................................................................................................................................................... 255
29.0 Electrical Characteristics .......................................................................................................................................................... 263
30.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 295
31.0 Packaging Information.............................................................................................................................................................. 325
Appendix A: Revision History............................................................................................................................................................. 351
Index .................................................................................................................................................................................................. 353
The Microchip Web Site..................................................................................................................................................................... 359
Customer Change Notification Service .............................................................................................................................................. 359
Customer Support.............................................................................................................................................................................. 359
Reader Response .............................................................................................................................................................................. 360
Product Identification System............................................................................................................................................................. 361
DS39995D-page 8
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
•
•
Microchip’s Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
2011-2013 Microchip Technology Inc.
DS39995D-page 9
PIC24FV32KA304 FAMILY
NOTES:
DS39995D-page 10
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
1.1.2
POWER-SAVING TECHNOLOGY
1.0
DEVICE OVERVIEW
All of the devices in the PIC24FV32KA304 family
incorporate a range of features that can significantly
reduce power consumption during operation. Key
features include:
This document contains device-specific information for
the following devices:
• PIC24FV16KA301, PIC24F16KA301
• PIC24FV16KA302, PIC24F16KA302
• PIC24FV16KA304, PIC24F16KA304
• PIC24FV32KA301, PIC24F32KA301
• PIC24FV32KA302, PIC24F32KA302
• PIC24FV32KA304, PIC24F32KA304
• On-the-Fly Clock Switching: The device clock
can be changed under software control to the
Timer1 source or the internal, low-power RC
oscillator during operation, allowing users to
incorporate power-saving ideas into their software
designs.
• Doze Mode Operation: When timing-sensitive
applications, such as serial communications,
require the uninterrupted operation of peripherals,
the CPU clock speed can be selectively reduced,
allowing incremental power savings without
missing a beat.
The PIC24FV32KA304 family introduces a new line of
extreme low-power Microchip devices. This is a 16-bit
microcontroller family with a broad peripheral feature set
and enhanced computational performance. This family
also offers
a
new migration option for those
high-performance applications which may be
outgrowing their 8-bit platforms, but do not require the
numerical processing power of a digital signal processor.
• Instruction-Based Power-Saving Modes: There
are three instruction-based power-saving modes:
- Idle Mode: The core is shut down while leaving
the peripherals active.
1.1
Core Features
1.1.1
16-BIT ARCHITECTURE
- Sleep Mode: The core and peripherals that
require the system clock are shut down, leaving
the peripherals that use their own clock, or the
clock from other devices, active.
- Deep Sleep Mode: The core, peripherals
(except RTCC and DSWDT), Flash and SRAM
are shut down.
Central to all PIC24F devices is the 16-bit modified
Harvard architecture, first introduced with Microchip’s
dsPIC® digital signal controllers. The PIC24F CPU core
offers a wide range of enhancements, such as:
• 16-bit data and 24-bit address paths with the
ability to move information between data and
memory spaces
1.1.3
OSCILLATOR OPTIONS AND
FEATURES
• Linear addressing of up to 12 Mbytes (program
space) and 64 Kbytes (data)
• A 16-element working register array with built-in
software stack support
• A 17 x 17 hardware multiplier with support for
integer math
• Hardware support for 32-bit by 16-bit division
• An instruction set that supports multiple
addressing modes and is optimized for high-level
languages, such as C
The PIC24FV32KA304 family offers five different
oscillator options, allowing users a range of choices in
developing application hardware. These include:
• Two Crystal modes using crystals or ceramic
resonators.
• Two External Clock modes offering the option of a
divide-by-2 clock output.
• Two Fast Internal oscillators (FRCs): One with a
nominal 8 MHz output and the other with a
nominal 500 kHz output. These outputs can also
be divided under software control to provide clock
speed as low as 31 kHz or 2 kHz.
• Operational performance up to 16 MIPS
• A Phase Locked Loop (PLL) frequency multiplier,
available to the external Oscillator modes and the
8 MHz FRC oscillator, which allows clock speeds
of up to 32 MHz.
• A separate internal RC oscillator (LPRC) with a
fixed 31 kHz output, which provides a low-power
option for timing-insensitive applications.
2011-2013 Microchip Technology Inc.
DS39995D-page 11
PIC24FV32KA304 FAMILY
The internal oscillator block also provides a stable
reference source for the Fail-Safe Clock Monitor
(FSCM). This option constantly monitors the main clock
1.3
Details on Individual Family
Members
Devices in the PIC24FV32KA304 family are available
in 20-pin, 28-pin, 44-pin and 48-pin packages. The
general block diagram for all devices is shown in
Figure 1-1.
source against a reference signal provided by the
internal oscillator and enables the controller to switch to
the internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.
The devices are different from each other in four ways:
1.1.4
EASY MIGRATION
1. Flash program memory (16 Kbytes for
PIC24FV16KA devices, 32 Kbytes for
PIC24FV32KA devices).
Regardless of the memory size, all the devices share
the same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve.
2. Available I/O pins and ports (18 pins on two
ports for 20-pin devices, 22 pins on two ports for
28-pin devices and 38 pins on three ports for
44/48-pin devices).
The consistent pinout scheme used throughout the
entire family also helps in migrating to the next larger
device. This is true when moving between devices with
the same pin count, or even jumping from 20-pin or
28-pin devices to 44-pin/48-pin devices.
3. Alternate SCLx and SDAx pins are available
only in 28-pin, 44-pin and 48-pin devices and not
in 20-pin devices.
The PIC24F family is pin compatible with devices in the
dsPIC33 family, and shares some compatibility with the
pinout schema for PIC18 and dsPIC30. This extends
the ability of applications to grow from the relatively
simple, to the powerful and complex.
4. Members of the PIC24FV32KA301 family are
available as both standard and high-voltage
devices. High-voltage devices, designated with
an “FV” in the part number (such as
PIC24FV32KA304), accommodate an operating
VDD range of 2.0V to 5.5V, and have an
on-board Voltage Regulator that powers the
core. Peripherals operate at VDD. Standard
devices, designated by “F” (such as
PIC24F32KA304), function over a lower VDD
range of 1.8V to 3.6V. These parts do not have
an internal regulator, and both the core and
peripherals operate directly from VDD.
1.2
Other Special Features
• Communications: The PIC24FV32KA304 family
incorporates a range of serial communication
peripherals to handle a range of application
requirements. There is an I2C™ module that
supports both the Master and Slave modes of
operation. It also comprises UARTs with built-in
IrDA® encoders/decoders and an SPI module.
• Real-Time Clock/Calendar: This module
implements a full-featured clock and calendar with
alarm functions in hardware, freeing up timer
resources and program memory space for use of
the core application.
All other features for devices in this family are identical;
these are summarized in Table 1-1.
A
list of the pin features available on the
PIC24FV32KA304 family devices, sorted by function,
is provided in Table 1-3.
• 12-Bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period, and
faster sampling speed. The 16-deep result buffer
can be used either in Sleep to reduce power, or in
Active mode to improve throughput.
• Charge Time Measurement Unit (CTMU)
Interface: The PIC24FV32KA304 family includes
the new CTMU interface module, which can be
used for capacitive touch sensing, proximity
sensing, and also for precision time measurement
and pulse generation.
Note:
Table 1-1 provides the pin location of
individual peripheral features and not how
they are multiplexed on the same pin. This
information is provided in the pinout
diagrams on pages 3, 4, 5, 6 and 7 of the
data sheet. Multiplexed features are
sorted by the priority given to a feature,
with the highest priority peripheral being
listed first.
DS39995D-page 12
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
TABLE 1-1:
DEVICE FEATURES FOR THE PIC24FV32KA304 FAMILY
Features
Operating Frequency
DC – 32 MHz
16K
Program Memory (bytes)
Program Memory (instructions)
Data Memory (bytes)
16K
32K
32K
11264
16K
32K
5632
11264
5632
2048
5632
11264
Data EEPROM Memory (bytes)
512
Interrupt Sources (soft vectors/
NMI traps)
30 (26/4)
I/O Ports
PORTA<5:0>
PORTB<15:12,9:7,4,2:0>
PORTA<7,5:0>
PORTB<15:0>
PORTA<11:7,5:0>
PORTB<15:0>
PORTC<9:0>
Total I/O Pins
17
23
5
38
Timers: Total Number (16-bit)
32-Bit (from paired 16-bit timers)
Input Capture Channels
2
3
Output Compare/PWM Channels
Input Change Notification Interrupt
3
16
12
22
2
37
16
Serial Communications: UART
SPI (3-wire/4-wire)
I2C™
2
12-Bit Analog-to-Digital Module
(input channels)
13
Analog Comparators
Resets (and delays)
3
POR, BOR, RESETInstruction, MCLR, WDT, Illegal Opcode,
REPEATInstruction, Hardware Traps, Configuration Word Mismatch
(PWRT, OST, PLL Lock)
Instruction Set
Packages
76 Base Instructions, Multiple Addressing Mode Variations
20-Pin
28-Pin
44-Pin QFN/TQFP
48-Pin UQFN
PDIP/SSOP/SOIC
SPDIP/SSOP/SOIC/QFN
2011-2013 Microchip Technology Inc.
DS39995D-page 13
PIC24FV32KA304 FAMILY
TABLE 1-2:
DEVICE FEATURES FOR THE PIC24F32KA304 FAMILY
Features
Operating Frequency
DC – 32 MHz
16K
Program Memory (bytes)
Program Memory (instructions)
Data Memory (bytes)
16K
32K
32K
11264
16K
32K
5632
11264
5632
2048
5632
11264
Data EEPROM Memory (bytes)
512
Interrupt Sources (soft vectors/
NMI traps)
30 (26/4)
I/O Ports
PORTA<6:0>,
PORTB<15:12, 9:7, 4, 2:0>
PORTA<7:0>,
PORTB<15:0>
PORTA<11:0>,
PORTB<15:0>,
PORTC<9:0>
Total I/O Pins
18
24
5
39
Timers: Total Number (16-bit)
32-Bit (from paired 16-bit timers)
Input Capture Channels
2
3
Output Compare/PWM Channels
Input Change Notification Interrupt
3
17
12
23
2
38
16
Serial Communications: UART
SPI (3-wire/4-wire)
I2C™
2
12-Bit Analog-to-Digital Module
(input channels)
13
Analog Comparators
Resets (and delays)
3
POR, BOR, RESETInstruction, MCLR, WDT, Illegal Opcode,
REPEATInstruction, Hardware Traps, Configuration Word Mismatch
(PWRT, OST, PLL Lock)
Instruction Set
Packages
76 Base Instructions, Multiple Addressing Mode Variations
20-Pin
28-Pin
44-Pin QFN/TQFP
48-Pin UQFN
PDIP/SSOP/SOIC
SPDIP/SSOP/SOIC/QFN
DS39995D-page 14
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
FIGURE 1-1:
PIC24FV32KA304 FAMILY GENERAL BLOCK DIAGRAM
Data Bus
Interrupt
Controller
16
16
8
16
Data Latch
Data RAM
PSV and Table
Data Access
Control Block
PCH
PCL
Program Counter
23
Address
Latch
PORTA(1)
RA<0:7>
Stack
Control
Logic
Repeat
Control
Logic
16
23
16
Read AGU
Write AGU
Address Latch
Program Memory
PORTB(1)
RB<0:15>
Data EEPROM
Data Latch
16
EA MUX
Address Bus
24
16
16
PORTC(1)
RC<9:0>
Inst Latch
Inst Register
Instruction
Decode and
Control
Divide
Support
Control Signals
16 x 16
W Reg Array
17x17
Multiplier
Power-up
Timer
OSCO/CLKO
OSCI/CLKI
Timing
Generation
Oscillator
FRC/LPRC
Oscillators
Start-up Timer
Power-on
Reset
16-Bit ALU
16
Precision
Band Gap
Reference
Watchdog
Timer
DSWDT
Voltage
Regulator
BOR
VCAP
VDD, VSS MCLR
12-Bit
A/D
RTCC
REFO
Timer1
Timer2/3
Timer4/5
CTMU
Comparators
UART1/2
HLVD
PWM/
OC1-3
CN1-22(1)
IC1-3
SPI1
I2C1
Note 1: All pins or features are not implemented on all device pinout configurations. See Table 1-3 for I/O port
pin descriptions.
2011-2013 Microchip Technology Inc.
DS39995D-page 15
TABLE 1-3:
PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS
F
FV
Pin Number
Pin Number
Function
I/O Buffer
Description
20-Pin
PDIP/
SSOP/
SOIC
28-Pin
SPDIP/
SSOP/
SOIC
20-Pin
PDIP/
SSOP/
SOIC
28-Pin
SPDIP/
SSOP/
SOIC
44-Pin
QFN/
TQFP
44-Pin
QFN/
TQFP
28-Pin
QFN
48-Pin
UQFN
28-Pin
QFN
48-Pin
UQFN
AN0
2
3
2
3
27
28
1
19
20
21
22
23
24
25
26
27
15
14
11
10
30
31
33
42
41
17
16
24
23
22
21
14
22
21
24
23
7
21
22
23
24
25
26
27
28
29
16
15
12
11
33
34
36
46
45
18
17
26
25
24
23
15
24
23
26
25
7
2
3
2
3
27
28
1
19
20
21
22
23
24
25
26
27
15
14
11
10
30
31
33
42
41
17
16
24
23
22
21
14
22
21
24
23
43
21
22
23
24
25
26
27
28
29
16
15
12
11
33
34
36
46
45
18
17
26
25
24
23
15
24
23
26
25
47
I
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
A/D Analog Inputs
AN1
I
AN2
4
4
4
4
I
AN3
5
5
2
5
5
2
I
AN4
6
6
3
6
6
3
I
AN5
—
—
—
—
18
17
16
15
7
7
4
—
—
—
—
18
17
16
15
7
7
4
I
AN6
—
—
—
26
25
24
23
9
—
—
—
23
22
21
20
6
—
—
—
26
25
24
23
9
—
—
—
23
22
21
20
6
I
AN7
I
AN8
I
AN9
I
AN10
AN11
AN12
AN13
AN14
AN15
ASCL1
ASDA1
AVDD
AVSS
C1INA
C1INB
C1INC
C1IND
C1OUT
C2INA
C2INB
C2INC
C2IND
C2OUT
I
I
I
I
8
10
11
15
14
28
27
7
7
8
10
11
15
14
28
27
7
7
I
9
8
9
8
I
—
—
20
19
8
12
11
25
24
4
—
—
20
19
8
12
11
25
24
4
I/O
I2C™ Alternate I2C1 Clock Input/Output
I/O
I2C
ANA
ANA
ANA
ANA
ANA
ANA
—
Alternate I2C1 Data Input/Output
A/D Supply Pins
I
I
I
Comparator 1 Input A (+)
Comparator 1 Input B (-)
Comparator 1 Input C (+)
Comparator 1 Input D (-)
Comparator 1 Output
7
6
3
7
6
3
I
5
5
2
5
5
2
I
4
4
1
4
4
1
I
17
5
25
5
22
2
17
5
25
5
22
2
O
I
ANA
ANA
ANA
ANA
—
Comparator 2 Input A (+)
Comparator 2 Input B (-)
Comparator 2 Input C (+)
Comparator 2 Input D (-)
Comparator 2 Output
4
4
1
4
4
1
I
8
7
4
8
7
4
I
7
6
3
7
6
3
I
14
20
17
11
16
13
O
TABLE 1-3:
PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
F
FV
Pin Number
Pin Number
Function
I/O Buffer
Description
20-Pin
PDIP/
SSOP/
SOIC
28-Pin
SPDIP/
SSOP/
SOIC
20-Pin
PDIP/
SSOP/
SOIC
28-Pin
SPDIP/
SSOP/
SOIC
44-Pin
QFN/
TQFP
44-Pin
QFN/
TQFP
28-Pin
QFN
48-Pin
UQFN
28-Pin
QFN
48-Pin
UQFN
C3INA
C3INB
C3INC
C3IND
C3OUT
CLK I
CLKO
CN0
18
17
2
26
25
2
23
22
27
1
15
14
19
21
44
30
31
34
33
19
20
21
22
23
24
7
16
15
21
23
48
33
34
37
36
21
22
23
24
25
26
7
18
17
2
26
25
2
23
22
27
1
15
14
19
21
44
30
31
34
33
19
20
21
22
23
24
—
6
16
15
21
23
48
33
34
37
36
21
22
23
24
25
26
–-
I
I
ANA
ANA
ANA
ANA
—
Comparator 3 Input A (+)
Comparator 3 Input B (-)
Comparator 3 Input C (+)
Comparator 3 Input D (-)
Comparator 3 Output
Main Clock Input
I
4
4
4
4
I
12
7
17
9
14
6
12
7
17
9
14
6
O
I
ANA
—
8
10
12
11
2
7
8
10
12
11
2
7
O
I
System Clock Output
Interrupt-on-Change Inputs
10
9
9
10
9
9
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
CN1
8
8
I
CN2
2
27
28
1
2
27
28
1
I
CN3
3
3
3
3
I
CN4
4
4
4
4
I
CN5
5
5
2
5
5
2
I
CN6
6
6
3
6
6
3
I
CN7
—
14
–-
–-
18
17
16
15
–-
–-
–-
—
–-
–-
13
12
7
4
–-
–-
–-
–-
18
17
16
15
–-
–-
–-
—
—
—
13
12
7
4
I
CN8
20
19
—
26
25
24
23
22
21
—
—
—
—
18
17
17
16
—
23
22
21
20
19
18
—
—
—
—
15
14
–-
19
–-
26
25
24
23
22
21
—
—
—
–-
18
17
–-
16
–-
23
22
21
20
19
18
—
—
–-
–-
15
14
I
CN9
6
6
6
I
CN10
CN11
CN12
CN13
CN14
CN15
CN16
CN17
CN18
CN19
CN20
CN21
CN22
27
15
14
11
10
9
29
16
15
12
11
10
9
27
15
14
11
10
9
29
16
15
12
11
10
9
I
I
I
I
I
I
8
8
I
3
3
3
3
I
2
2
2
2
I
5
5
5
5
I
4
4
4
4
I
1
1
1
1
I
44
48
44
48
I
TABLE 1-3:
PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
F
FV
Pin Number
Pin Number
Function
I/O Buffer
Description
20-Pin
PDIP/
SSOP/
SOIC
28-Pin
SPDIP/
SSOP/
SOIC
20-Pin
PDIP/
SSOP/
SOIC
28-Pin
SPDIP/
SSOP/
SOIC
44-Pin
QFN/
TQFP
44-Pin
QFN/
TQFP
28-Pin
QFN
48-Pin
UQFN
28-Pin
QFN
48-Pin
UQFN
CN23
11
–-
–-
–-
–-
–-
8
16
15
—
—
14
—
10
9
13
12
—
—
11
—
7
43
42
37
38
41
36
31
30
26
25
32
35
12
13
14
19
20
21
7
47
46
40
41
45
39
34
33
28
27
35
38
13
14
15
21
22
23
7
11
–-
–-
–-
–-
–-
8
16
15
–-
–-
14
–-
10
9
13
12
–-
–-
11
–-
7
43
42
37
38
41
36
31
30
26
25
32
35
12
13
14
19
20
21
19
10
6
47
46
40
41
45
39
34
33
28
27
35
38
13
14
15
21
22
23
21
11
6
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ANA
ANA
ANA
ANA
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
Interrupt-on-Change Inputs
CN24
CN25
CN26
CN27
CN28
CN29
CN30
7
6
7
6
CN31
–-
–-
–-
–-
–-
–-
17
2
—
—
—
—
—
—
25
2
—
—
—
—
—
—
22
27
28
1
—
—
—
—
—
—
17
2
—
—
—
—
—
—
25
2
—
—
—
—
—
—
22
27
28
1
CN32
CN33
CN34
CN35
CN36
CVREF
CVREF+
CVREF-
CTCMP
CTED1
CTED2
CTED3
CTED4
CTED5
CTED6
CTED7
CTED8
CTED9
CTED10
CTED11
CTED12
CTED13
Comparator Voltage Reference Output
Comparator Reference Positive Input Voltage
Comparator Reference Negative Input Voltage
CTMU Comparator Input
3
3
3
3
4
4
4
4
14
15
—
13
17
18
—
—
—
12
—
5
20
23
19
18
25
26
—
—
22
17
21
5
17
20
16
15
22
23
—
—
19
14
18
2
11
15
—
13
17
18
—
—
—
12
—
5
2
27
20
16
15
22
23
—
—
19
14
18
2
CTMU Trigger Edge Inputs
10
6
11
6
23
19
18
25
26
—
—
22
17
21
5
1
1
1
1
14
15
5
15
16
5
14
15
5
15
16
5
13
9
14
10
48
9
13
9
14
10
48
9
44
8
44
8
22
23
24
25
22
23
24
25
6
6
3
6
6
3
TABLE 1-3:
PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
F
FV
Pin Number
Pin Number
Function
I/O Buffer
Description
20-Pin
PDIP/
SSOP/
SOIC
28-Pin
SPDIP/
SSOP/
SOIC
20-Pin
PDIP/
SSOP/
SOIC
28-Pin
SPDIP/
SSOP/
SOIC
44-Pin
QFN/
TQFP
44-Pin
QFN/
TQFP
28-Pin
QFN
48-Pin
UQFN
28-Pin
QFN
48-Pin
UQFN
CTPLS
HLVDIN
IC1
16
15
14
13
15
11
17
14
24
23
19
18
23
16
25
20
21
20
16
15
20
13
22
17
11
10
6
12
11
6
16
15
11
13
15
11
17
15
24
23
19
18
23
16
25
23
21
20
16
15
20
13
22
20
11
10
6
12
11
6
O
I
—
CTMU Pulse Output
ST
ST
ST
ST
ST
ST
ST
High/Low-Voltage Detect Input
Input Capture 1 Input
Input Capture 2 Input
Input Capture 3 Input
Interrupt 0 Input
I
IC2
5
5
5
5
I
IC3
13
43
14
7
14
47
15
7
13
43
14
10
14
47
15
11
I
INT0
INT1
INT2
I
I
Interrupt 1 Input
I
Interrupt 2 Input
MCLR
OC1
1
14
4
1
26
17
19
18
22
21
6
18
7
19
7
1
11
4
1
26
13
19
18
22
21
6
18
43
4
19
47
4
I
ST
—
Master Clear (Device Reset) Input (active-low)
Output Compare/PWM1 Output
Output Compare/PWM2 Output
Output Compare/PWM3 Output
Output Compare Fault A
Output Compare Fault B
Main Oscillator Input
Main Oscillator Output
ICSP™ Clock 1
20
22
21
25
24
9
16
22
21
25
24
9
O
OC2
4
4
O
—
OC3
5
12
14
32
30
31
22
21
19
8
13
15
35
33
34
24
23
10
9
5
12
14
32
30
31
22
21
19
8
13
15
35
33
34
24
23
10
9
O
—
OCFA
OFCB
OSCI
17
16
7
17
16
7
O
—
O
—
I
ANA
ANA
ST
ST
ST
ST
ST
ST
OSCO
PGEC1
PCED1
PGEC2
PGED2
PGEC3
PGED3
8
10
5
7
8
10
5
7
O
5
2
5
2
I/O
I/O
I/O
I/O
I/O
I/O
4
4
1
4
4
1
ICSP Data 1
2
22
21
15
14
19
18
12
11
2
22
21
15
14
19
18
12
11
ICSP Clock 2
3
3
ICSP Data 2
10
9
42
41
46
45
10
9
42
41
46
45
ICSP Clock 3
ICSP Data 3
TABLE 1-3:
PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
F
FV
Pin Number
Pin Number
Function
I/O Buffer
Description
20-Pin
PDIP/
SSOP/
SOIC
28-Pin
SPDIP/
SSOP/
SOIC
20-Pin
PDIP/
SSOP/
SOIC
28-Pin
SPDIP/
SSOP/
SOIC
44-Pin
QFN/
TQFP
44-Pin
QFN/
TQFP
28-Pin
QFN
48-Pin
UQFN
28-Pin
QFN
48-Pin
UQFN
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RA8
RA9
RA10
RA11
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
RB8
RB9
RB10
RB11
RB12
RB13
RB14
RB15
2
3
2
27
28
6
19
20
30
31
34
18
7
21
22
33
34
37
19
7
2
3
2
27
28
6
19
20
30
31
34
18
—
6
21
22
33
34
37
19
—
6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
PORTA Pins
3
3
7
9
7
9
8
10
12
1
7
8
10
12
1
7
10
1
9
10
1
9
26
17
16
—
—
—
—
1
26
—
16
—
—
—
—
1
14
—
—
—
—
—
4
20
19
—
—
—
—
4
—
—
—
—
—
—
4
—
19
—
—
—
—
4
6
6
32
35
12
13
21
22
23
24
33
41
42
43
44
1
35
38
13
14
23
24
25
26
36
45
46
47
48
1
32
35
12
13
21
22
23
24
33
41
42
43
44
1
35
38
13
14
23
24
25
26
36
45
46
47
48
1
PORTB Pins
5
5
2
5
5
2
6
6
3
6
6
3
—
9
7
4
—
9
7
4
11
14
15
16
17
18
21
22
23
24
25
26
8
11
14
15
16
17
18
21
22
23
24
25
26
8
—
—
11
12
13
—
—
15
16
17
18
11
12
13
14
15
18
19
20
21
22
23
—
—
11
12
13
—
—
15
16
17
18
11
12
13
14
15
18
19
20
21
22
23
8
9
8
9
9
10
11
12
15
16
9
10
11
12
15
16
10
11
14
15
10
11
14
15
TABLE 1-3:
PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
F
FV
Pin Number
Pin Number
Function
I/O Buffer
Description
20-Pin
PDIP/
SSOP/
SOIC
28-Pin
SPDIP/
SSOP/
SOIC
20-Pin
PDIP/
SSOP/
SOIC
28-Pin
SPDIP/
SSOP/
SOIC
44-Pin
QFN/
TQFP
44-Pin
QFN/
TQFP
28-Pin
QFN
48-Pin
UQFN
28-Pin
QFN
48-Pin
UQFN
RC0
—
—
—
—
—
—
—
—
—
—
18
17
15
2
—
—
—
—
—
—
—
—
—
—
26
25
22
14
17
7
—
—
—
—
—
—
—
—
—
—
23
22
19
11
14
4
25
26
27
36
37
38
2
27
28
29
39
40
41
2
—
—
—
—
—
—
—
—
—
—
18
17
15
2
—
—
—
—
—
—
—
—
—
—
26
25
22
14
17
7
—
—
—
—
—
—
—
—
—
—
23
22
19
11
14
4
25
26
27
36
37
38
2
27
28
29
39
40
41
2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
—
PORTC Pins
RC1
RC2
RC3
RC4
RC5
RC6
RC7
3
3
3
3
RC8
4
4
4
4
RC9
5
5
5
5
REFO
RTCC
SCK1
SCK2
SCL1
SCL2
SCLKI
SDA1
SDA2
SDI1
SDI2
SDO1
SDO2
SOSCI
SOSCO
15
14
9
16
15
10
41
48
26
37
1
15
14
9
16
15
10
41
48
26
37
1
Reference Clock Output
Real-Time Clock/Calendar Output
SPI1 Serial Input/Output Clock
SPI2 Serial Input/Output Clock
I2C1 Clock Input/Output
I2C2 Clock Input/Output
Digital Secondary Clock Input
I2C1 Data Input/Output
O
—
I/O
I/O
I/O
I/O
I
ST
ST
I2C
I2C
ST
I2C
I2C
ST
ST
—
38
44
24
34
1
38
44
24
34
1
12
18
10
13
6
12
18
10
13
6
12
18
6
9
12
18
6
9
15
3
15
3
I/O
I/O
I
23
8
25
9
23
8
25
9
I2C2 Data Input/Output
17
4
21
19
24
15
11
12
18
16
21
12
8
17
4
21
19
24
15
11
12
18
16
21
12
8
SPI1 Serial Data Input
36
11
37
33
34
39
12
40
36
37
36
11
37
33
34
39
12
40
36
37
I
SPI2 Serial Data Input
16
3
16
3
O
SPI1 Serial Data Output
SPI2 Serial Data Output
Secondary Oscillator Input
Secondary Oscillator Output
O
—
9
9
I
ANA
ANA
10
9
10
9
O
SS1
SS2
18
15
26
23
23
20
15
35
16
38
18
15
26
23
23
20
15
35
16
38
O
O
—
—
SPI1 Slave Select
SPI2 Slave Select
TABLE 1-3:
PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
F
FV
Pin Number
Pin Number
Function
I/O Buffer
Description
20-Pin
PDIP/
SSOP/
SOIC
28-Pin
SPDIP/
SSOP/
SOIC
20-Pin
PDIP/
SSOP/
SOIC
28-Pin
SPDIP/
SSOP/
SOIC
44-Pin
QFN/
TQFP
44-Pin
QFN/
TQFP
28-Pin
QFN
48-Pin
UQFN
28-Pin
QFN
48-Pin
UQFN
T1CK
T2CK
T3CK
T4CK
T5CK
13
18
18
6
18
26
26
6
15
23
23
3
1
1
13
18
18
6
18
26
26
6
15
23
23
3
1
1
I
I
I
I
I
ST
ST
ST
ST
ST
Timer1 Clock
Timer2 Clock
Timer3 Clock
Timer4 Clock
Timer5 Clock
15
15
23
23
16
16
25
25
15
15
23
23
16
16
25
25
6
6
3
6
6
3
U1CTS
U1RTS
U1RX
12
13
6
17
18
6
14
15
3
44
1
48
1
12
13
6
17
18
6
14
15
3
44
1
48
1
I
O
I
ST
—
UART1 Clear-to-Send Input
UART1 Request-to-Send Output
UART1 Receive
2
2
2
2
ST
—
U1TX
11
10
16
12
13
9
3
3
11
10
16
12
13
9
3
3
O
I
UART1 Transmit
U2CTS
34
37
34
37
ST
UART2 Clear-to-Send Input
U2RTS
U2RX
U2TX
ULPWU
VCAP
9
5
11
5
8
2
33
22
36
24
9
5
11
5
8
2
33
36
O
I
—
ST
UART2 Request-to-Send Output
UART2 Receive
22
24
4
4
1
21
23
4
4
1
21
21
23
23
O
I
—
UART2 Transmit
4
4
1
21
23
4
4
1
ANA
—
Ultra Low-Power Wake-up Input
Core Power
—
20
2
—
—
—
—
14
20
2
20
28,13
2
17
7
7
P
P
I
VDD
28,13
2
25,10
27
28
24,5
17,28,40
19
18,30,43
21
25,10
27
17,28,40
19
18,30,43
21
—
Device Digital Supply Voltage
A/D Reference Voltage Input (+)
A/D Reference Voltage Input (-)
Device Digital Ground Return
VREF+
VREF-
VSS
ANA
ANA
—
3
3
20
22
3
3
28
20
22
I
19
27,8
16,29,39
17,31,42
19
27,8
24,5
16,29,39
17,31,42
P
PIC24FV32KA304 FAMILY
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTIONS
2.0
2.1
GUIDELINES FOR GETTING
STARTED WITH 16-BIT
MICROCONTROLLERS
C2(2)
VDD
Basic Connection Requirements
Getting started with the PIC24FV32KA304 family of
16-bit microcontrollers requires attention to a minimal
set of device pin connections before proceeding with
development.
R1
R2
MCLR
VCAP
(1)
C1
The following pins must always be connected:
C7
PIC24FXXKXX(3)
• All VDD and VSS pins
(see Section 2.2 “Power Supply Pins”)
VDD
VSS
VDD
C3(2)
C6(2)
• All AVDD and AVSS pins, regardless of whether or
not the analog device features are used
VSS
(see Section 2.2 “Power Supply Pins”)
• MCLR pin
(see Section 2.3 “Master Clear (MCLR) Pin”)
C5(2)
C4(2)
• VCAP pins
(see Section 2.4 “Voltage Regulator Pin (VCAP)”)
These pins must also be connected if they are being
used in the end application:
Key (all values are recommendations):
C1 through C6: 0.1 F, 20V ceramic
C7: 10 F, 16V tantalum or ceramic
R1: 10 kΩ
• PGECx/PGEDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
R2: 100Ω to 470Ω
• OSCI and OSCO pins when an external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
Note 1: See Section 2.4 “Voltage Regulator Pin
(VCAP)” for explanation of VCAP pin
connections.
2: The example shown is for a PIC24F device
with five VDD/VSS and AVDD/AVSS pairs.
Other devices may have more or less pairs;
adjust the number of decoupling capacitors
appropriately.
Additionally, the following pins may be required:
• VREF+/VREF- pins are used when external voltage
reference for analog modules is implemented
Note:
The AVDD and AVSS pins must always be
connected, regardless of whether any of
the analog modules are being used.
3: Some PIC24F K parts do not have a
regulator.
The minimum mandatory connections are shown in
Figure 2-1.
2011-2013 Microchip Technology Inc.
DS39995D-page 23
PIC24FV32KA304 FAMILY
2.2
Power Supply Pins
2.3
Master Clear (MCLR) Pin
The MCLR pin provides two specific device
functions: Device Reset, and Device Programming
and Debugging. If programming and debugging are
2.2.1
DECOUPLING CAPACITORS
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS, is required.
not required in the end application,
a
direct
connection to VDD may be all that is required. The
addition of other components, to help increase the
application’s resistance to spurious Resets from
Consider the following criteria when using decoupling
capacitors:
voltage sags, may be beneficial.
A
typical
• Value and type of capacitor: A 0.1 F (100 nF),
10-20V capacitor is recommended. The capacitor
should be a low-ESR device, with a resonance
frequency in the range of 200 MHz and higher.
Ceramic capacitors are recommended.
configuration is shown in Figure 2-1. Other circuit
designs may be implemented, depending on the
application’s requirements.
During programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR pin. Consequently, specific voltage
levels (VIH and VIL) and fast signal transitions must
not be adversely affected. Therefore, specific values
of R1 and C1 will need to be adjusted based on the
application and PCB requirements. For example, it is
recommended that the capacitor, C1, be isolated
from the MCLR pin during programming and
debugging operations by using a jumper (Figure 2-2).
The jumper is replaced for normal run-time
operations.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is no greater
than 0.25 inch (6 mm).
• Handling high-frequency noise: If the board is
experiencing high-frequency noise (upward of
tens of MHz), add a second ceramic type capaci-
tor in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 F to 0.001 F. Place this
second capacitor next to each primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible
(e.g., 0.1 F in parallel with 0.001 F).
Any components associated with the MCLR pin
should be placed within 0.25 inch (6 mm) of the pin.
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS
VDD
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB trace
R1
R2
MCLR
PIC24FXXKXX
JP
C1
inductance.
Note 1: R1 10 k is recommended. A suggested
starting value is 10 k. Ensure that the
MCLR pin VIH and VIL specifications are
met.
2.2.2
TANK CAPACITORS
On boards with power traces running longer than
six inches in length, it is suggested to use a tank capac-
itor for integrated circuits, including microcontrollers, to
supply a local power source. The value of the tank
capacitor should be determined based on the trace
resistance that connects the power supply source to
the device, and the maximum current drawn by the
device in the application. In other words, select the tank
capacitor so that it meets the acceptable voltage sag at
the device. Typical values range from 4.7 F to 47 F.
2: R2 470 will limit any current flowing
into MCLR from the external capacitor, C,
in the event of MCLR pin breakdown due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR
pin VIH and VIL specifications are met.
DS39995D-page 24
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
Refer to Section 29.0 “Electrical Characteristics” for
information on VDD and VDDCORE.
2.4
Voltage Regulator Pin (VCAP)
Note:
This section applies only to PIC24F K
devices with an On-Chip Voltage Regulator.
FIGURE 2-3:
FREQUENCY vs. ESR
PERFORMANCE FOR
SUGGESTED VCAP
Some of the PIC24F K devices have an internal Voltage
Regulator. These devices have the Voltage Regulator
output brought out on the VCAP pin. On the PIC24F K
devices with regulators, a low-ESR (< 5Ω) capacitor is
required on the VCAP pin to stabilize the Voltage
Regulator output. The VCAP pin must not be connected
to VDD and must use a capacitor of 10 µF connected to
ground. The type can be ceramic or tantalum. Suitable
examples of capacitors are shown in Table 2-1.
Capacitors with equivalent specifications can be used.
10
1
0.1
0.01
Designers may use Figure 2-3 to evaluate ESR
equivalence of candidate devices.
0.001
0.01
The placement of this capacitor should be close to VCAP.
It is recommended that the trace length not exceed
0.25 inch (6 mm). Refer to Section 29.0 “Electrical
Characteristics” for additional information.
0.1
1
10
100
1000 10,000
Frequency (MHz)
Note:
Typical data measurement at 25°C, 0V DC bias.
TABLE 2-1:
Make
SUITABLE CAPACITOR EQUIVALENTS
Nominal
Part #
Base Tolerance Rated Voltage Temp. Range
Capacitance
TDK
TDK
C3216X7R1C106K
C3216X5R1C106K
10 µF
10 µF
10 µF
10 µF
10 µF
10 µF
±10%
±10%
±10%
±10%
±10%
±10%
16V
16V
16V
16V
16V
16V
-55 to 125ºC
-55 to 85ºC
-55 to 125ºC
-55 to 85ºC
-55 to 125ºC
-55 to 85ºC
Panasonic
Panasonic
Murata
ECJ-3YX1C106K
ECJ-4YB1C106K
GRM32DR71C106KA01L
GRM31CR61C106KC31L
Murata
2011-2013 Microchip Technology Inc.
DS39995D-page 25
PIC24FV32KA304 FAMILY
2.4.1
CONSIDERATIONS FOR CERAMIC
CAPACITORS
FIGURE 2-4:
DC BIAS VOLTAGE vs.
CAPACITANCE
CHARACTERISTICS
In recent years, large value, low-voltage, surface-mount
ceramic capacitors have become very cost effective in
sizes up to a few tens of microfarad. The low-ESR, small
physical size and other properties make ceramic
capacitors very attractive in many types of applications.
10
0
-10
-20
-30
-40
-50
-60
-70
16V Capacitor
10V Capacitor
Ceramic capacitors are suitable for use with the inter-
nal Voltage Regulator of this microcontroller. However,
some care is needed in selecting the capacitor to
ensure that it maintains sufficient capacitance over the
intended operating range of the application.
6.3V Capacitor
-80
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
16 17
DC Bias Voltage (VDC)
Typical low-cost, 10 F ceramic capacitors are available
in X5R, X7R and Y5V dielectric ratings (other types are
also available, but are less common). The initial toler-
ance specifications for these types of capacitors are
often specified as ±10% to ±20% (X5R and X7R), or
-20%/+80% (Y5V). However, the effective capacitance
that these capacitors provide in an application circuit will
also vary based on additional factors, such as the
applied DC bias voltage and the temperature. The total
in-circuit tolerance is, therefore, much wider than the
initial tolerance specification.
When selecting a ceramic capacitor to be used with the
internal Voltage Regulator, it is suggested to select a
high-voltage rating, so that the operating voltage is a
small percentage of the maximum rated capacitor volt-
age. For example, choose a ceramic capacitor rated at
16V for the 3.3V or 2.5V core voltage. Suggested
capacitors are shown in Table 2-1.
2.5
ICSP Pins
The X5R and X7R capacitors typically exhibit satisfac-
tory temperature stability (ex: ±15% over a wide
temperature range, but consult the manufacturer’s data
sheets for exact specifications). However, Y5V capaci-
tors typically have extreme temperature tolerance
specifications of +22%/-82%. Due to the extreme
temperature tolerance, a 10 F nominal rated Y5V type
capacitor may not deliver enough total capacitance to
meet minimum internal Voltage Regulator stability and
transient response requirements. Therefore, Y5V
capacitors are not recommended for use with the
internal regulator if the application must operate over a
wide temperature range.
The PGC and PGD pins are used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes. It
is recommended to keep the trace length between the
ICSP connector and the ICSP pins on the device as
short as possible. If the ICSP connector is expected to
experience an ESD event, a series resistor is recom-
mended, with the value in the range of a few tens of
ohms, not to exceed 100Ω.
Pull-up resistors, series diodes and capacitors on the
PGC and PGD pins are not recommended as they will
interfere with the programmer/debugger communica-
tions to the device. If such discrete components are an
application requirement, they should be removed from
the circuit during programming and debugging. Alter-
natively, refer to the AC/DC characteristics and timing
requirements information in the respective device
Flash programming specification for information on
capacitive loading limits, and pin input voltage high
(VIH) and input low (VIL) requirements.
In addition to temperature tolerance, the effective
capacitance of large value ceramic capacitors can vary
substantially, based on the amount of DC voltage
applied to the capacitor. This effect can be very signifi-
cant, but is often overlooked or is not always
documented.
A typical DC bias voltage vs. capacitance graph for
X7R type capacitors is shown in Figure 2-4.
For device emulation, ensure that the “Communication
Channel Select” (i.e., PGCx/PGDx pins), programmed
into the device, matches the physical connections for
the ICSP to the Microchip debugger/emulator tool.
For more information on available Microchip
development tools connection requirements, refer to
Section 27.0 “Development Support”.
DS39995D-page 26
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
FIGURE 2-5:
SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
2.6
External Oscillator Pins
Many microcontrollers have options for at least two
oscillators: a high-frequency primary oscillator and a
low-frequency secondary oscillator (refer to Section 9.0
“Oscillator Configuration” for details).
Single-Sided and In-Line Layouts:
Copper Pour
(tied to ground)
Primary Oscillator
Crystal
The oscillator circuit should be placed on the same
side of the board as the device. Place the oscillator
circuit close to the respective oscillator pins with no
more than 0.5 inch (12 mm) between the circuit
components and the pins. The load capacitors should
be placed next to the oscillator itself, on the same side
of the board.
DEVICE PINS
Primary
OSC1
OSC2
GND
Oscillator
C1
C2
`
`
Use a grounded copper pour around the oscillator cir-
cuit to isolate it from surrounding circuits. The
grounded copper pour should be routed directly to the
MCU ground. Do not run any signal traces or power
traces inside the ground pour. Also, if using a two-sided
board, avoid any traces on the other side of the board
where the crystal is placed.
T1OSO
T1OS I
Timer1 Oscillator
Crystal
`
Layout suggestions are shown in Figure 2-5. In-line
packages may be handled with a single-sided layout
that completely encompasses the oscillator pins. With
fine-pitch packages, it is not always possible to com-
pletely surround the pins and components. A suitable
solution is to tie the broken guard sections to a mirrored
ground layer. In all cases, the guard trace(s) must be
returned to ground.
T1 Oscillator: C2
T1 Oscillator: C1
Fine-Pitch (Dual-Sided) Layouts:
Top Layer Copper Pour
(tied to ground)
In planning the application’s routing and I/O assign-
ments, ensure that adjacent port pins and other
signals, in close proximity to the oscillator, are benign
(i.e., free of high frequencies, short rise and fall times,
and other similar noise).
Bottom Layer
Copper Pour
(tied to ground)
OSCO
For additional information and design guidance on
oscillator circuits, please refer to these Microchip
Application Notes, available at the corporate web site
(www.microchip.com):
C2
Oscillator
Crystal
GND
• AN826, “Crystal Oscillator Basics and Crystal
C1
Selection for rfPIC™ and PICmicro® Devices”
• AN849, “Basic PICmicro® Oscillator Design”
OSCI
• AN943, “Practical PICmicro® Oscillator Analysis
and Design”
• AN949, “Making Your Oscillator Work”
DEVICE PINS
2.7
Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic low state. Alternatively, connect a 1 kΩ
to 10 kΩ resistor to VSS on unused pins and drive the
output to logic low.
2011-2013 Microchip Technology Inc.
DS39995D-page 27
PIC24FV32KA304 FAMILY
NOTES:
DS39995D-page 28
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
For most instructions, the core is capable of executing
a data (or program data) memory read, a working
3.0
CPU
Note:
This data sheet summarizes the features
of this group of PIC24F devices. It is not
register (data) read, a data memory write and a pro-
gram (instruction) memory read per instruction cycle.
As a result, three parameter instructions can be
supported, allowing trinary operations (i.e., A + B = C)
to be executed in a single cycle.
intended to be a comprehensive refer-
ence source. For more information on the
CPU, refer to the “PIC24F Family
Reference Manual”, Section 2. “CPU”
(DS39703).
A high-speed, 17-bit by 17-bit multiplier has been
included to significantly enhance the core arithmetic
capability and throughput. The multiplier supports
Signed, Unsigned and Mixed mode, 16-bit by 16-bit or
8-bit by 8-bit integer multiplication. All multiply
instructions execute in a single cycle.
The PIC24F CPU has a 16-bit (data) modified Harvard
architecture with an enhanced instruction set and a
24-bit instruction word with a variable length opcode
field. The Program Counter (PC) is 23 bits wide and
addresses up to 4M instructions of user program
memory space. A single-cycle instruction prefetch
mechanism is used to help maintain throughput and
provides predictable execution. All instructions execute
in a single cycle, with the exception of instructions that
change the program flow, the double-word move
(MOV.D) instruction and the table instructions.
Overhead-free program loop constructs are supported
using the REPEATinstructions, which are interruptible
at any point.
The 16-bit ALU has been enhanced with integer divide
assist hardware that supports an iterative non-restoring
divide algorithm. It operates in conjunction with the
REPEATinstruction looping mechanism and a selection
of iterative divide instructions to support 32-bit (or
16-bit), divided by 16-bit integer signed and unsigned
division. All divide operations require 19 cycles to
complete but are interruptible at any cycle boundary.
The PIC24F has a vectored exception scheme with up
to eight sources of non-maskable traps and up to
118 interrupt sources. Each interrupt source can be
assigned to one of seven priority levels.
PIC24F devices have sixteen, 16-bit working registers
in the programmer’s model. Each of the working
registers can act as a data, address or address offset
register. The 16th working register (W15) operates as a
Software Stack Pointer (SSP) for interrupts and calls.
A block diagram of the CPU is illustrated in Figure 3-1.
3.1
Programmer’s Model
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K word boundary of either program memory or data
EEPROM memory, defined by the 8-bit Program Space
Visibility Page Address (PSVPAG) register. The
program to data space mapping feature lets any
instruction access program space as if it were data
space.
Figure 3-2 displays the programmer’s model for the
PIC24F. All registers in the programmer’s model are
memory mapped and can be manipulated directly by
instructions.
Table 3-1 provides a description of each register. All
registers associated with the programmer’s model are
memory mapped.
The Instruction Set Architecture (ISA) has been signifi-
cantly enhanced beyond that of the PIC18, but
maintains an acceptable level of backward compatibil-
ity. All PIC18 instructions and addressing modes are
supported, either directly, or through simple macros.
Many of the ISA enhancements have been driven by
compiler efficiency needs.
The core supports Inherent (no operand), Relative,
Literal, Memory Direct and three groups of addressing
modes. All modes support Register Direct and various
Register Indirect modes. Each group offers up to seven
addressing modes. Instructions are associated with
predefined addressing modes depending upon their
functional requirements.
2011-2013 Microchip Technology Inc.
DS39995D-page 29
PIC24FV32KA304 FAMILY
FIGURE 3-1:
PIC24F CPU CORE BLOCK DIAGRAM
PSV and Table
Data Access
Control Block
Data Bus
Interrupt
Controller
16
16
16
8
Data Latch
Data RAM
23
16
PCH
PCL
Program Counter
23
Address
Latch
Loop
Control
Logic
Stack
Control
Logic
23
16
RAGU
WAGU
Address Latch
Program Memory
EA MUX
Data EEPROM
Data Latch
Address Bus
ROM Latch
24
16
16
Instruction
Decode and
Control
Instruction Reg
Control Signals
to Various Blocks
Hardware
Multiplier
16 x 16
W Register Array
Divide
16
Support
16-Bit ALU
16
To Peripheral Modules
TABLE 3-1:
CPU CORE REGISTERS
Register(s) Name
Description
W0 through W15
PC
Working Register Array
23-Bit Program Counter
ALU STATUS Register
SR
SPLIM
Stack Pointer Limit Value Register
TBLPAG
PSVPAG
RCOUNT
CORCON
Table Memory Page Address Register
Program Space Visibility Page Address Register
Repeat Loop Counter Register
CPU Control Register
DS39995D-page 30
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
FIGURE 3-2:
PROGRAMMER’S MODEL
15
0
W0 (WREG)
W1
Divider Working Registers
W2
Multiplier Registers
W3
W4
W5
W6
W7
Working/Address
Registers
W8
W9
W10
W11
W12
W13
W14
W15
Frame Pointer
Stack Pointer
0
Stack Pointer Limit
Value Register
0
SPLIM
22
0
0
PC
Program Counter
7
0
0
0
Table Memory Page
Address Register
TBLPAG
7
Program Space Visibility
Page Address Register
PSVPAG
15
15
Repeat Loop Counter
Register
RCOUNT
IPL
SRH
SRL
0
— — — — — — —
ALU STATUS Register (SR)
DC
RA N OV Z
C
2 1 0
15
0
— — — — — — — — — — — — IPL3 PSV — —
CPU Control Register (CORCON)
Registers or bits are shadowed for PUSH.Sand POP.Sinstructions.
2011-2013 Microchip Technology Inc.
DS39995D-page 31
PIC24FV32KA304 FAMILY
3.2
CPU Control Registers
REGISTER 3-1:
SR: ALU STATUS REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0, HSC
DC
bit 15
bit 8
R/W-0, HSC(1) R/W-0, HSC(1) R/W-0, HSC(1) R-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC
IPL2(2) IPL1(2) IPL0(2)
RA OV
N
Z
C
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-9
bit 8
Unimplemented: Read as ‘0’
DC: ALU Half Carry/Borrow bit
1= A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0= No carry-out from the 4th or 8th low-order bit of the result has occurred
bit 7-5
IPL<2:0>: CPU Interrupt Priority Level Status bits(1,2)
111= CPU Interrupt Priority Level is 7 (15); user interrupts are disabled
110= CPU Interrupt Priority Level is 6 (14)
101= CPU Interrupt Priority Level is 5 (13)
100= CPU Interrupt Priority Level is 4 (12)
011= CPU Interrupt Priority Level is 3 (11)
010= CPU Interrupt Priority Level is 2 (10)
001= CPU Interrupt Priority Level is 1 (9)
000= CPU Interrupt Priority Level is 0 (8)
bit 4
bit 3
bit 2
bit 1
bit 0
RA: REPEATLoop Active bit
1= REPEATloop in progress
0= REPEATloop not in progress
N: ALU Negative bit
1= Result was negative
0= Result was non-negative (zero or positive)
OV: ALU Overflow bit
1= Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation
0= No overflow has occurred
Z: ALU Zero bit
1= An operation, which effects the Z bit, has set it at some time in the past
0= The most recent operation, which effects the Z bit, has cleared it (i.e., a non-zero result)
C: ALU Carry/Borrow bit
1= A carry-out from the Most Significant bit (MSb) of the result occurred
0= No carry-out from the Most Significant bit (MSb) of the result occurred
Note 1: The IPLx Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
2: The IPL<2:0> Status bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt
Priority Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1.
DS39995D-page 32
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
REGISTER 3-2:
CORCON: CPU CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
R/C-0, HSC
IPL3(1)
R/W-0
PSV
U-0
—
U-0
—
bit 7
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-4
bit 3
Unimplemented: Read as ‘0’
IPL3: CPU Interrupt Priority Level Status bit(1)
1= CPU Interrupt Priority Level is greater than 7
0= CPU Interrupt Priority Level is 7 or less
bit 2
PSV: Program Space Visibility in Data Space Enable bit
1= Program space is visible in data space
0= Program space is not visible in data space
bit 1-0
Unimplemented: Read as ‘0’
Note 1: User interrupts are disabled when IPL3 = 1.
The PIC24F CPU incorporates hardware support for
both multiplication and division. This includes a
dedicated hardware multiplier and support hardware
division for 16-bit divisor.
3.3
Arithmetic Logic Unit (ALU)
The PIC24F ALU is 16 bits wide and is capable of
addition, subtraction, bit shifts and logic operations.
Unless otherwise mentioned, arithmetic operations are
2’s complement in nature. Depending on the operation,
the ALU may affect the values of the Carry (C), Zero
(Z), Negative (N), Overflow (OV) and Digit Carry (DC)
Status bits in the SR register. The C and DC Status bits
operate as Borrow and Digit Borrow bits, respectively,
for subtraction operations.
3.3.1
MULTIPLIER
The ALU contains a high-speed, 17-bit x 17-bit
multiplier. It supports unsigned, signed or mixed sign
operation in several multiplication modes:
• 16-bit x 16-bit signed
• 16-bit x 16-bit unsigned
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array, or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
• 16-bit signed x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit unsigned
• 16-bit unsigned x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit signed
• 8-bit unsigned x 8-bit unsigned
2011-2013 Microchip Technology Inc.
DS39995D-page 33
PIC24FV32KA304 FAMILY
3.3.2
DIVIDER
3.3.3
MULTI-BIT SHIFT SUPPORT
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
The PIC24F ALU supports both single bit and
single-cycle, multi-bit arithmetic and logic shifts.
Multi-bit shifts are implemented using a shifter block,
capable of performing up to a 15-bit arithmetic right
shift, or up to a 15-bit left shift, in a single cycle. All
multi-bit shift instructions only support Register Direct
Addressing for both the operand source and result
destination.
1. 32-bit signed/16-bit signed divide
2. 32-bit unsigned/16-bit unsigned divide
3. 16-bit signed/16-bit signed divide
4. 16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0
and the remainder in W1. Sixteen-bit signed and
unsigned DIV instructions can specify any W register
for both the 16-bit divisor (Wn), and any W register
(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.
The divide algorithm takes one cycle per bit of divisor,
so both 32-bit/16-bit and 16-bit/16-bit instructions take
the same number of cycles to execute.
A full summary of instructions that use the shift
operation is provided in Table 3-2.
TABLE 3-2:
Instruction
INSTRUCTIONS THAT USE THE SINGLE AND MULTI-BIT SHIFT OPERATION
Description
ASR
SL
Arithmetic shift right source register by one or more bits.
Shift left source register by one or more bits.
LSR
Logical shift right source register by one or more bits.
DS39995D-page 34
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
User access to the program memory space is restricted
to the lower half of the address range (000000h to
7FFFFFh). The exception is the use of TBLRD/TBLWT
operations, which use TBLPAG<7> to permit access to
the Configuration bits and Device ID sections of the
configuration memory space.
4.0
MEMORY ORGANIZATION
As Harvard architecture devices, the PIC24F
microcontrollers feature separate program and data
memory space and bussing. This architecture also
allows the direct access of program memory from the
data space during code execution.
Memory maps for the PIC24FV32KA304 family of
devices are shown in Figure 4-1.
4.1
Program Address Space
The program address memory space of the
PIC24FV32KA304 family is 4M instructions. The space
is addressable by a 24-bit value derived from either the
23-bit Program Counter (PC) during program execution,
or from a table operation or data space remapping, as
described in Section 4.3 “Interfacing Program and
Data Memory Spaces”.
FIGURE 4-1:
PROGRAM SPACE MEMORY MAP FOR PIC24FV32KA304 FAMILY DEVICES
PIC24FV16KA304
PIC24FV32KA304
000000h
000002h
000004h
GOTOInstruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
GOTOInstruction
Reset Address
Interrupt Vector Table
Reserved
0000FEh
000100h
000104h
0001FEh
000200h
Alternate Vector Table
Flash
Program Memory
(5632 instructions)
User Flash
Program Memory
(11264 instructions)
002BFEh
Unimplemented
Read ‘0’
0057FEh
7FFE00h
Unimplemented
Read ‘0’
Data EEPROM
Reserved
Data EEPROM
7FFFFFh
800000h
Reserved
Device Config Registers
Reserved
F7FFFEh
F80000h
F80010h
F80012h
Device Config Registers
Reserved
FEFFFEh
FF0000h
FFFFFFh
DEVID (2)
DEVID (2)
Note:
Memory areas are not displayed to scale.
DS39995D-page 35
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
4.1.1
PROGRAM MEMORY
ORGANIZATION
4.1.3
DATA EEPROM
In the PIC24FV32KA304 family, the data EEPROM is
mapped to the top of the user program memory space,
starting at address, 7FFE00, and expanding up to
address, 7FFFFF.
The program memory space is organized in
word-addressable blocks. Although it is treated as
24 bits wide, it is more appropriate to think of each
address of the program memory as a lower and upper
word, with the upper byte of the upper word being
unimplemented. The lower word always has an even
address, while the upper word has an odd address, as
shown in Figure 4-2.
The data EEPROM is organized as 16-bit wide memory
and 256 words deep. This memory is accessed using
table read and write operations similar to the user code
memory.
4.1.4
DEVICE CONFIGURATION WORDS
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two during code execution. This
arrangement also provides compatibility with data
memory space addressing and makes it possible to
access data in the program memory space.
Table 4-1 provides the addresses of the device
Configuration Words for the PIC24FV32KA304 family.
Their location in the memory map is shown in
Figure 4-1.
For more information on device Configuration Words,
see Section 26.0 “Special Features”.
4.1.2
HARD MEMORY VECTORS
All PIC24F devices reserve the addresses between
00000h and 000200h for hard coded program execu-
tion vectors. A hardware Reset vector is provided to
redirect code execution from the default value of the
PC on device Reset to the actual start of code. A GOTO
instruction is programmed by the user at 000000h, with
the actual address for the start of code at 000002h.
TABLE 4-1:
DEVICE CONFIGURATION
WORDS FOR PIC24FV32KA304
FAMILY DEVICES
Configuration Word
Configuration Words
Addresses
FBS
F80000
F80004
F80006
F80008
F8000A
F8000C
F8000E
F80010
PIC24F devices also have two Interrupt Vector Tables,
located from 000004h to 0000FFh and 000104h to
0001FFh. These vector tables allow each of the many
device interrupt sources to be handled by separate
Interrupt Service Routines (ISRs). A more detailed
discussion of the Interrupt Vector Tables (IVT) is
provided in Section 8.1 “Interrupt Vector Table
(IVT)”.
FGS
FOSCSEL
FOSC
FWDT
FPOR
FICD
FDS
FIGURE 4-2:
PROGRAM MEMORY ORGANIZATION
least significant word
msw
Address
PC Address
(lsw Address)
most significant word
23
16
8
0
000000h
000002h
000004h
000006h
00000000
000001h
000003h
000005h
000007h
00000000
00000000
00000000
Program Memory
‘Phantom’ Byte
Instruction Width
(read as ‘0’)
2011-2013 Microchip Technology Inc.
DS39995D-page 36
PIC24FV32KA304 FAMILY
PIC24FV32KA304 family devices implement a total of
1024 words of data memory. If an EA points to a
location outside of this area, an all zero word or byte will
be returned.
4.2
Data Address Space
The PIC24F core has a separate, 16-bit wide data
memory space, addressable as a single linear range.
The data space is accessed using two Address
Generation Units (AGUs), one each for read and write
operations. The data space memory map is shown in
Figure 4-3.
4.2.1
DATA SPACE WIDTH
The data memory space is organized in
byte-addressable, 16-bit wide blocks. Data is aligned in
data memory and registers as 16-bit words, but all the
data space EAs resolve to bytes. The Least Significant
Bytes (LSBs) of each word have even addresses, while
the Most Significant Bytes (MSBs) have odd
addresses.
All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the data space.
This gives a data space address range of 64 Kbytes or
32K words. The lower half of the data memory space
(that is, when EA<15> = 0) is used for implemented
memory addresses, while the upper half (EA<15> = 1) is
reserved for the Program Space Visibility (PSV) area
(see Section 4.3.3 “Reading Data From Program
Memory Using Program Space Visibility”).
FIGURE 4-3:
DATA SPACE MEMORY MAP FOR PIC24FV32KA304 FAMILY DEVICES
MSB
Address
LSB
Address
MSB
LSB
0000h
07FEh
0800h
0001h
07FFh
0801h
SFR
Space
SFR Space
Data RAM
Implemented
Data RAM
Near
Data Space
0FFFh
1FFF
0FFEh
1FFEh
Unimplemented
Read as ‘0’
7FFFh
8001h
7FFFh
8000h
Program Space
Visibility Area
FFFFh
FFFEh
Note:
Data memory areas are not shown to scale.
DS39995D-page 37
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
can clear the MSB of any W register by executing a
Zero-Extend (ZE) instruction on the appropriate
address.
4.2.2
DATA MEMORY ORGANIZATION
AND ALIGNMENT
To maintain backward compatibility with PIC® MCU
devices and improve data space memory usage
efficiency, the PIC24F instruction set supports both
word and byte operations. As a consequence of byte
accessibility, all Effective Address (EA) calculations are
internally scaled to step through word-aligned memory.
For example, the core recognizes that Post-Modified
Register Indirect Addressing mode [Ws++] will result in
a value of Ws + 1 for byte operations and Ws + 2 for
word operations.
Although most instructions are capable of operating on
word or byte data sizes, it should be noted that some
instructions operate only on words.
4.2.3
NEAR DATA SPACE
The 8-Kbyte area between 0000h and 1FFFh is
referred to as the Near Data Space (NDS). Locations in
this space are directly addressable via a 13-bit abso-
lute address field within all memory direct instructions.
The remainder of the data space is addressable
indirectly. Additionally, the whole data space is
addressable using MOV instructions, which support
Memory Direct Addressing (MDA) with a 16-bit address
field. For PIC24FV32KA304 family devices, the entire
implemented data memory lies in Near Data Space.
Data byte reads will read the complete word, which
contains the byte, using the LSB of any EA to
determine which byte to select. The selected byte is
placed onto the LSB of the data path. That is, data
memory and the registers are organized as two
parallel, byte-wide entities with shared (word) address
decode, but separate write lines. Data byte writes only
write to the corresponding side of the array or register,
which matches the byte address.
4.2.4
SFR SPACE
The first 2 Kbytes of the Near Data Space, from 0000h
to 07FFh, are primarily occupied with Special Function
Registers (SFRs). These are used by the PIC24F core
and peripheral modules for controlling the operation of
the device.
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word
operations, or translating from 8-bit MCU code. If a
misaligned read or write is attempted, an address error
trap will be generated. If the error occurred on a read,
the instruction underway is completed; if it occurred on
a write, the instruction will be executed, but the write
will not occur. In either case, a trap is then executed,
allowing the system and/or user to examine the
machine state prior to execution of the address Fault.
SFRs are distributed among the modules that they
control and are generally grouped together by the
module. Much of the SFR space contains unused
addresses; these are read as ‘0’. The SFR space,
where the SFRs are actually implemented, is provided
in Table 4-2. Each implemented area indicates a
32-byte region, where at least one address is
implemented as an SFR. A complete listing of
implemented SFRs, including their addresses, is
provided in Table 4-3 through Table 4-25.
All byte loads into any W register are loaded into the
LSB; the MSB is not modified.
A Sign-Extend (SE) instruction is provided to allow the
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
TABLE 4-2:
IMPLEMENTED REGIONS OF SFR DATA SPACE
SFR Space Address
xx00
xx20
xx40
xx60
xx80
xxA0
xxC0
xxE0
000h
100h
200h
300h
400h
500h
600h
700h
Core
ICN
—
Interrupts
—
—
Timers
Capture
Compare
—
—
—
—
—
—
I2C™
UART
SPI
—
—
—
—
I/O
A/D/CMTU
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RTC/Comp
—
CRC
—
—
System/DS/HLVD
NVM/PMD
—
—
—
—
Legend: — = No implemented SFRs in this block.
2011-2013 Microchip Technology Inc.
DS39995D-page 38
TABLE 4-3:
CPU CORE REGISTERS MAP
Start
Addr
All
Resets
File Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
WREG0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WREG0
WREG1
WREG2
WREG3
WREG4
WREG5
WREG6
WREG7
WREG8
WREG9
WREG10
WREG11
WREG12
WREG13
0000
0002
0004
0006
0008
000A
000C
000E
0010
0012
0014
0016
0018
001A
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
xxxx
0000
0000
0000
0000
xxxxx
0000
0000
xxxx
WREG1
WREG2
WREG3
WREG4
WREG5
WREG6
WREG7
WREG8
WREG9
WREG10
WREG11
WREG12
WREG13
WREG14
WREG15
SPLIM
WREG14 001C
WREG15
SPLIM
PCL
001E
0020
002E
0030
0032
0034
0036
0042
PCL
PCH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PCH
TBLPAG
PSVPAG
TBLPAG
PSVPAG
RCOUNT
SR
RCOUNT
IPL2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DC
—
IPL1
—
IPL0
—
RA
N
OV
Z
C
CORCON 0044
DISICNT 0052
—
—
IPL3
PSV
—
—
DISICNT
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-4:
ICN REGISTER MAP
File
Addr
Name
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CNPD1 0056 CN15PDE(1)
CN14PDE
CN13PDE
CN12PDE
CN11PDE CN10PDE(1,2) CN9PDE(1) CN8PDE(3) CN7PDE(1) CN6PDE CN5PDE
CN4PDE
CN3PDE
CN2PDE
CN1PDE
CN0PDE
0000
(1,2)
CNPD2 0058 CN31PDE(1,2) CN30PDE
CN29PDE CN28PDE(1,2) CN27PDE(1) CN26PDE(1,2) CN25PDE(1,2) CN24PDE(1) CN23PDE CN22PDE CN21PDE CN20PDE
CN19PDE(1,2) CN18PDE(1,2) CN17PDE(1,2) CN16PDE(1) 0000
CN35PDE(1,2) CN34PDE(1,2) CN33PDE(1,2) CN32PDE(1,2) 0000
(1,2)
CNPD3 005A
—
—
CN14IE
CN30IE
—
—
CN13IE
CN29IE
—
—
—
CN11IE
CN27IE(1)
—
—
—
CN9IE(1)
CN25IE(1,2)
—
—
CN8IE(3)
CN24IE(1)
—
—
CN7IE(1)
CN23IE
—
—
CN6IE
CN22IE
—
—
CN5IE
CN21IE
—
CN36PDE
CNEN1 0062
CN15IE(1)
CN12IE
CN28IE(1,2)
—
CN10IE(1,2)
CN26IE(1,2)
—
CN4IE
CN3IE
CN2IE
CN1IE
CN0IE
CN16IE(1)
CN32IE(1,2)
CN0PUE
0000
0000
0000
0000
CNEN2 0064 CN31IE(1,2)
CNEN3 0066
CNPU1 006E CN15PUE(1)
CN20IE(1,2)
CN36IE(1,2)
CN4PUE
CN19IE(1,2)
CN35IE(1,2)
CN3PUE
CN18IE(1,2)
CN34IE(1,2)
CN2PUE
CN17IE(1,2)
CN33IE(1,2)
CN1PUE
—
CN14PUE
CN13PUE
CN12PUE
CN11PUE CN10PUE(1,2) CN9PUE(1) CN8PUE(3) CN7PUE(1) CN6PUE CN5PUE
(1,2)
CNPU2 0070 CN31PUE(1,2) CN30PUE
CN29PUE CN28PUE(1,2) CN27PUE(1) CN26PUE(1,2) CN25PUE(1,2) CN24PUE(1) CN23PUE CN22PUE CN21PUE CN20PUE
CN19PUE(1,2) CN18PUE(1,2) CN17PUE(1,2) CN16PUE(1) 0000
CN35PUE(1,2) CN34PUE(1,2) CN33PUE(1,2) CN32PUE(1,2) 0000
(1,2)
CNPU3 0072
—
—
—
—
—
—
—
—
—
—
—
CN36PUE
Legend:
Note 1:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
These bits are not implemented in 20-pin devices.
2:
3:
These bits are not implemented in 28-pin devices.
These bits are not implemented in FV devices.
TABLE 4-5:
INTERRUPT CONTROLLER REGISTER MAP
File
Name
All
Resets
Addr Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON1 0080 NSTDIS
INTCON2 0082 ALTIVT
—
DISI
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T2IF
—
—
—
—
—
T2IE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MATHERR ADDRERR STKERR
OSCFAIL
INT1EP
IC1IF
—
INT0EP
INT0IF
SI2C1IF
SPF2IF
—
0000
0000
0000
0000
0000
0000
0000
—
—
—
T1IF
CNIF
—
INT2EP
OC1IF
CMIF
—
IFS0
IFS1
IFS2
IFS3
IFS4
IFS5
IEC0
IEC1
IEC2
IEC3
IEC4
IEC5
IPC0
IPC1
IPC2
IPC3
IPC4
IPC5
IPC6
IPC7
IPC8
IPC9
IPC12
IPC15
IPC16
IPC18
IPC19
IPC20
0084 NVMIF
AD1IF
INT2IF
—
U1TXIF U1RXIF
SPI1IF
—
SPF1IF
OC3IF
—
T3IF
—
OC2IF
—
IC2IF
—
0086 U2TXIF U2RXIF
T5IF
—
T4IF
—
INT1IF
—
MI2C1IF
SPI2IF
SI2C2IF
U1ERIF
—
0088
008A
008C
008E
—
—
—
—
—
RTCIF
—
—
—
—
IC3IF
—
—
—
—
—
—
—
—
—
—
MI2C2IF
U2ERIF
—
CTMUIF
—
—
—
—
—
HLVDIF
—
—
—
—
CRCIF
—
—
—
—
—
—
—
—
—
—
ULPWUIF 0000
0094 NVMIE
—
AD1IE
U1TXIE U1RXIE
SPI1IE
—
SPF1IE
OC3IE
—
T3IE
—
OC2IE
—
IC2IE
—
—
T1IE
CNIE
—
OC1IE
CMIE
—
IC1IE
MI2C1IE
SPI2IE
SI2C2IE
U1ERIE
—
INT0IE
SI2C1IE
SPF2IE
—
0000
0000
0000
0000
0000
0096 U2TXIE U2RXIE INT2IE
T5IE
—
T4IE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ILR3
INT1IE
—
0098
009A
009C
009E
00A4
00A6
00A8
00AA
00AC
00AE
00B0
00B2
00B4
00B6
00BC
00C2
00C4
00C8
00CA
00CC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RTCIE
—
—
—
—
—
—
IC3IE
—
—
—
—
—
—
—
—
MI2C2IE
U2ERIE
—
CTMUIE
—
—
—
—
HLVDIE
—
—
—
—
CRCIE
—
—
—
—
—
—
—
—
—
ULPWUIE 0000
T1IP2
T2IP2
T1IP1
T2IP1
T1IP0
T2IP0
OC1IP2
OC2IP2
SPI1IP2
—
OC1IP1
OC2IP1
SPI1IP1
—
OC1IP0
OC2IP0
SPI1IP0
—
IC1IP2
IC2IP2
IC1IP1
IC2IP1
IC1IP0
IC2IP0
—
INT0IP2
—
INT0IP1
—
INT0IP0
—
4444
4444
4444
4044
4444
0004
4040
4440
0044
0040
0440
0400
4440
0004
0040
—
U1RXIP2 U1RXIP1 U1RXIP0
NVMIP2 NVMIP1 NVMIP0
SPF1IP2 SPF1IP1 SPF1IP0
AD1IP2 AD1IP1 AD1IP0
MI2C1P2 MI2C1P1 MI2C1P0
—
T3IP2
U1TXIP2
SI2C1P2
INT1IP2
—
T3IP1
U1TXIP1
SI2C1P1
INT1IP1
—
T3IP0
U1TXIP0
SI2C1P0
INT1IP0
—
—
CNIP2
—
CNIP1
—
CNIP0
—
CMIP2
—
CMIP1
—
CMIP0
—
—
—
—
—
—
T4IP2
T4IP1
T4IP0
—
—
—
OC3IP2
INT2IP2
SPI2IP2
IC3IP2
OC3IP1
INT2IP1
SPI2IP1
IC3IP1
OC3IP0
INT2IP0
SPI2IP0
IC3IP0
—
U2TXIP2 U2TXIP1 U2TXIP0
U2RXIP2 U2RXIP1 U2RXIP0
—
T5IP2
SPF2IP2
—
T5IP1
SPF2IP1
—
T5IP0
SPF2IP0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MI2C2IP2 MI2C2IP1 MI2C2IP0
RTCIP2 RTCIP1 RTCIP0
U2ERIP2 U2ERIP1 U2ERIP0
SI2C2IP2 SI2C2IP1 SI2C2IP0
—
—
—
—
—
—
—
—
—
—
—
CRCIP2 CRCIP1 CRCIP0
U1ERIP2 U1ERIP1 U1ERIP0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
HLVDIP2
—
HLVDIP1
—
HLVDIP0
—
CTMUIP2 CTMUIP1 CTMUIP0
—
—
—
—
—
—
—
—
—
ULPWUIP2 ULPWUIP1 ULPWUIP0 0000
INTTREG 00E0 CPUIRQ
VHOLD
ILR2
ILR1
ILR0
VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-6:
TIMER REGISTER MAP
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR1
PR1
0100
0102
0104
0106
0108
010A
010C
010E
0110
0112
0114
0116
0118
011A
011C
011E
0120
TMR1
PR1
0000
FFFF
0000
0000
0000
0000
0000
FFFF
FFFF
0000
0000
0000
0000
FFFF
FFFF
0000
0000
T1CON
TMR2
TMR3HLD
TMR3
PR2
TON
—
TSIDL
—
—
—
T1ECS1 T1ECS0
TMR2
—
TGATE TCKPS1 TCKPS0
—
TSYNC
TCS
—
TMR3HLD
TMR3
PR2
PR3
PR3
T2CON
T3CON
TMR4
TMR5HLD
TMR5
PR4
TON
TON
—
—
TSIDL
TSIDL
—
—
—
—
—
—
—
—
—
—
—
TGATE TCKPS1 TCKPS0
TGATE TCKPS1 TCKPS0
T32
—
—
—
TCS
TCS
—
—
—
TMR4
TMR5HLD
TMR5
PR4
PR5
PR5
T4CON
T5CON
TON
TON
—
—
TSIDL
TSIDL
—
—
—
—
—
—
—
—
—
—
—
TGATE TCKPS1 TCKPS0
TGATE TCKPS1 TCKPS0
T45
—
—
—
TCS
TCS
—
—
—
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-7:
INPUT CAPTURE REGISTER MAP
File
Name
All
Resets
Addr Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
ICI1
Bit 5
Bit 4
Bit 3
Bit 2
ICM2
Bit 1
ICM1
Bit 0
IC1CON1 0140
IC1CON2 0142
—
—
—
—
ICSIDL ICTSEL2 ICTSEL1 ICTSEL0
—
—
—
—
ICI0
—
ICOV
ICBNE
ICM0
0000
—
—
—
—
IC32
ICTRIG TRIGSTAT
IC1BUF
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
IC1BUF
IC1TMR
0144
0146
0000
xxxx
IC1TMR
IC2CON1 0148
IC2CON2 014A
—
—
—
—
ICSIDL IC2TSEL2 IC2TSEL1 IC2TSEL0
—
—
—
—
ICI1
ICI0
—
ICOV
ICBNE
ICM2
ICM1
ICM0
0000
—
—
—
—
IC32
ICTRIG TRIGSTAT
IC2BUF
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
IC2BUF
IC2TMR
014C
014E
0000
xxxx
IC2TMR
IC3CON1 0150
IC3CON2 0152
—
—
—
—
ICSIDL IC3TSEL2 IC3TSEL1 IC3TSEL0
—
—
—
—
ICI1
ICI0
—
ICOV
ICBNE
ICM2
ICM1
ICM0
0000
—
—
—
—
IC32
ICTRIG TRIGSTAT
IC3BUF
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
IC3BUF
IC3TMR
0154
0156
0000
xxxx
IC3TMR
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-8:
OUTPUT COMPARE REGISTER MAP
All
Resets
File Name Addr Bit 15
OC1CON1 0190
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 ENFLT0 OCFLT2 OCFLT1 OCFLT0 TRIGMODE
OCM2
OCM1
OCM0
0000
OC1CON2 0192 FLTMD FLTOUT FLTTRIEN OCINV
—
DCB1 DCB0 OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C
OC1RS
OC1R
0194
0196
OC1RS
OC1R
0000
0000
xxxx
0000
OC1TMR 0198
OC2CON1 019A
OC1TMR
—
—
OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 ENFLT0 OCFLT2 OCFLT1 OCFLT0 TRIGMODE
DCB1 DCB0
OCM2
OCM1
OCM0
OC2CON2 019C FLTMD FLTOUT FLTTRIEN OCINV
—
OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C
OC2RS
OC2R
019E
01A0
OC2RS
OC2R
0000
0000
xxxx
0000
OC2TMR 01A2
OC3CON1 01A4
OC2TMR
—
—
OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 ENFLT0 OCFLT2 OCFLT1 OCFLT0 TRIGMODE
DCB1 DCB0
OCM2
OCM1
OCM0
OC3CON2 01A6 FLTMD FLTOUT FLTTRIEN OCINV
—
OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C
OC3RS
OC3R
01A8
01AA
OC3RS
OC3R
0000
0000
xxxx
OC3TMR 01AC
OC3TMR
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-9:
I2Cx REGISTER MAP
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I2C1RCV
I2C1TRN
I2C1BRG
I2C1CON
I2C1STAT
I2C1ADD
I2C1MSK
I2C2RCV
I2C2TRN
I2C2BRG
I2C2CON
I2C2STAT
I2C2ADD
I2C2MSK
0200
0202
0204
0206
0208
020A
020C
0210
0212
0214
0216
0218
021A
021C
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I2CRCV
0000
00FF
0000
1000
0000
0000
I2CTRN
I2CBRG
—
—
—
—
I2CEN
I2CSIDL SCLREL IPMIEN
A10M
BCL
—
DISSLW
GCSTAT
SMEN
ADD10
GCEN
STREN
I2COV
ACKDT
D/A
ACKEN
RCEN
S
PEN
R/W
RSEN
RBF
SEN
TBF
ACKSTAT TRSTAT
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IWCOL
P
—
—
—
—
—
—
—
—
I2CADD
—
AMSK9
—
AMSK8
—
AMSK7
AMSK6
AMSK5
AMSK4
AMSK3
AMSK2
AMSK1 AMSK0 0000
—
—
I2CRCV
0000
00FF
0000
—
—
—
—
I2CTRN
I2CBRG
—
—
—
—
I2CEN
I2CSIDL SCLREL IPMIEN
A10M
BCL
—
DISSLW
GCSTAT
SMEN
ADD10
GCEN
STREN
I2COV
ACKDT
D/A
ACKEN
RCEN
S
PEN
R/W
RSEN
RBF
SEN
TBF
1000
0000
0000
ACKSTAT TRSTAT
—
—
—
—
—
—
—
—
—
IWCOL
P
—
—
—
—
I2CADD
—
AMSK9
AMSK8
AMSK7
AMSK6
AMSK5
AMSK4
AMSK3
AMSK2
AMSK1 AMSK0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-10: UARTx REGISTER MAP
File
Name
All
Resets
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
UEN1
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
U1MODE
U1STA
0220 UARTEN
—
USIDL
IREN RTSMD
—
UEN0
TRMT
WAKE
LPBACK
ABAUD
RXINV
RIDLE
BRGH
PERR
PDSEL1 PDSEL0 STSEL
0000
0222 UTXISEL1 UTXINV UTXISEL0
—
—
—
UTXBRK UTXEN UTXBF
URXISEL1 URXISEL0 ADDEN
FERR
OERR URXDA 0110
U1TXREG
U1RXREG
U1BRG
0224
0226
0228
—
—
—
—
—
—
—
—
—
—
—
—
U1TXREG
U1RXREG
xxxx
0000
0000
BRG
WAKE
URXISEL1 URXISEL0 ADDEN
U2MODE
U2STA
0230 UARTEN
—
USIDL
IREN RTSMD
—
UEN1
UEN0
TRMT
LPBACK
ABAUD
RXINV
RIDLE
BRGH
PERR
PDSEL1 PDSEL0 STSEL
0000
0232 UTXISEL1 UTXINV UTXISEL0
—
—
—
UTXBRK UTXEN UTXBF
FERR
OERR URXDA 0110
U2TXREG
U2RXREG
U2BRG
0234
0236
0238
—
—
—
—
—
—
—
—
—
—
—
—
U2TXREG
U2RXREG
xxxx
0000
0000
BRG
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-11: SPIx REGISTER MAP
File
Name
All
Resets
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPI1STAT
SPI1CON1
SPI1CON2
SPI1BUF
0240
0242
0244
0248
0260
0262
0264
0268
SPIEN
—
—
—
SPISIDL
—
—
—
SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SR1MPT SISEL2
SISEL1
SPRE1
—
SISEL0 SPITBF SPIRBF
0000
0000
0000
0000
0000
0000
0000
0000
DISSCK DISSDO MODE16
SMP
—
CKE
—
SSEN
—
CKP
—
MSTEN
—
SPRE2
—
SPRE0
—
PPRE1
SPIFE
PPRE0
FRMEN SPIFSD SPIFPOL
—
—
—
—
—
SPIBEN
SPI1BUF
SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT SISEL2
SPI2STAT
SPI2CON1
SPI2CON2
SPI2BUF
SPIEN
—
—
—
SPISIDL
—
SISEL1
SPRE1
—
SISEL0 SPITBF SPIRBF
DISSCK DISSDO MODE16
SMP
—
CKE
—
SSEN
—
CKP
—
MSTEN
—
SPRE2
—
SPRE0
—
PPRE1
SPIFE
PPRE0
FRMEN SPIFSD SPIFPOL
—
—
—
SPIBEN
SPI2BUF
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-12: PORTA REGISTER MAP
File
Name
All
Resets
Addr
Bit 15
Bit 14
Bit 13
Bit 12 Bit 11(2,3) Bit 10(2,3) Bit 9(2,3) Bit 8(2,3)
Bit 7(2)
Bit 6(4)
Bit 5(1)
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISA
PORTA
LATA
02C0
02C2
02C4
02C6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISA11 TRISA10 TRISA9 TRISA8 TRISA7
TRISA6
RA6
—
RA5
—
TRISA4
RA4
TRISA3
RA3
TRISA2 TRISA1 TRISA0 00DF
RA11
LATA11
ODA11
RA10
LATA10
ODA10
RA9
RA8
RA7
RA2
RA1
RA0
xxxx
xxxx
0000
LATA9
ODA9
LATA8
ODA8
LATA7
ODA7
LATA6
ODA6
LATA4
ODA4
LATA3
ODA3
LATA2
ODA2
LATA1
ODA1
LATA0
ODA0
ODCA
—
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This bit is available only when MCLRE = 1.
2: These bits are not implemented in 20-pin devices.
3: These bits are not implemented in 28-pin devices.
4: These bits are not implemented in FV devices.
TABLE 4-13: PORTB REGISTER MAP
File
Name
All
Resets
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11(1)
Bit 10(1)
Bit 9
Bit 8
Bit 7
Bit 6(1)
Bit 5(1)
Bit 4
Bit 3(1)
Bit 2
Bit 1
Bit 0
TRISB
02C8 TRISB15
TRISB14
RB14
TRISB13 TRISB12 TRISB11 TRISB10
TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF
PORTB 02CA
RB15
LATB15
ODB15
RB13
LATB13
ODB13
RB12
LATB12
ODB12
RB11
LATB11
ODB11
RB10
LATB10
ODB10
RB9
RB8
RB7
LATB7
ODB7
RB6
RB5
RB4
RB3
RB2
LATB2
ODB2
RB1
RB0
xxxx
xxxx
0000
LATB
02CC
02CE
LATB14
ODB14
LATB9
ODB9
LATB8
ODB8
LATB6
ODB6
LATB5
ODB5
LATB4
ODB4
LATB3
ODB3
LATB1
ODB1
LATB0
ODB0
ODCB
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: These bits are not implemented in 20-pin devices.
TABLE 4-14: PORTC REGISTER MAP(1)
File
Name
All
Resets
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISC 02D0
PORTC 02D2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISC9 TRISC8 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2
TRISC1
RC1
TRISC0
RC0
03FF
xxxx
xxxx
0000
RC9
RC8
RC7
RC6
RC5
RC4
RC3
RC2
LATC
02D4
LATC9
ODC9
LATC8
ODC8
LATC7
ODC7
LATC6
ODC6
LATC5
ODC5
LATC4
ODC4
LATC3
ODC3
LATC2
ODC2
LATC1
ODC1
LATC0
ODC0
ODCC 02D6
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: PORTC is not implemented in 20-pin devices or 28-pin devices.
TABLE 4-15: PAD CONFIGURATION REGISTER MAP
File
Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
PADCFG1
02FC
—
—
—
—
—
—
—
—
—
—
SMBUSDEL2 SMBUSDEL1
—
—
—
—
0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-16: A/D REGISTER MAP
File
Name
All
Resets
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADC1BUF0 0300
ADC1BUF1 0302
ADC1BUF2 0304
ADC1BUF3 0306
ADC1BUF4 0308
ADC1BUF5 030A
ADC1BUF6 030C
ADC1BUF7 030E
ADC1BUF8 0310
ADC1BUF9 0312
ADC1BUF10 0314
ADC1BUF11 0316
ADC1BUF12 0318
ADC1BUF13 031A
ADC1BUF14 031C
ADC1BUF15 031E
ADC1BUF16 0320
ADC1BUF17 0322
ADC1BUF0
ADC1BUF1
ADC1BUF2
ADC1BUF3
ADC1BUF4
ADC1BUF5
ADC1BUF6
ADC1BUF7
ADC1BUF8
ADC1BUF9
ADC1BUF10
ADC1BUF11
ADC1BUF12
ADC1BUF13
ADC1BUF14
ADC1BUF15
ADC1BUF16
ADC1BUF17
FORM0
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
0000
0000
AD1CON1
AD1CON2
AD1CON3
AD1CHS
0340 ADON
—
ADSIDL
—
—
MODE12
FORM1
—
SSRC3 SSRC2 SSRC1 SSRC0
BUFS SMPI4 SMPI3 SMPI2
ADCS7 ADCS6 ADCS5 ADCS4
—
ASAM
SMPI0
SAMP
BUFM
DONE
ALTS
0342 PVCFG1 PVCFG0 NVCFG0 OFFCAL BUFREGEN CSCNA
—
SMPI1
ADCS3
0344
ADRC
EXTSAM
—
SAMC4
SAMC3
CH0SB3
CSSL27
CSSL11
r
SAMC2
CH0SB2
CSSL26
CSSL10
—
SAMC1
CH0SB1
—
SAMC0
ADCS2 ADCS1 ADCS0 0000
0348 CH0NB2 CH0NB1 CH0NB0 CH0SB4
CH0SB0 CH0NA2 CH0NA1 CH0NA0 CH0SA4 CH0SA3 CH0SA2 CH0SA1 CH0SA0 0000
AD1CSSH
AD1CSSL
AD1CON5
AD1CHITH
AD1CHITL
034E
—
CSSL30
CSSL29
CSSL13
CSSL28
CSSL12
—
—
CSSL7
—
—
CSSL6
—
—
—
—
CSSL3
WM1
—
—
CSSL2
WM0
—
CSSL17 CSSL16 0000
0350 CSSL15 CSSL14
CSSL9
ASINT1
—
CSSL8
ASINT0
—
CSSL5 CSSL4
CSSL1 CSSL0
CM1 CM0
0000
0000
0354
0356
ASEN
—
LPEN
—
CTMUREQ BGREQ
—
—
—
—
—
—
—
—
—
—
CHH17 CHH16 0000
CHH1 CHH0 0000
0358 CHH15
CHH14
CHH13
CHH12
CHH11
CHH10
CHH9
CHH8
CHH7
CHH6
CHH5
CHH4
CHH3
CHH2
Legend: — = unimplemented, read as ‘0’; r = reserved. Reset values are shown in hexadecimal.
TABLE 4-17: CTMU REGISTER MAP
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CTMUCON1
CTMUCON2
CTMUICON
035A CTMUEN
—
CTMUSIDL
TGEN
EDGEN EDGSEQEN IDISSEN
CTTRIG
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
035C EDG1MOD EDG1POL EDG1SEL3 EDG1SEL2 EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT EDG2EMOD EDG2POL EDG2SEL3 EDG2SEL2 EDG2SEL1 EDG2SEL0
035E
ITRIM5
—
ITRIM4
—
ITRIM3
—
ITRIM2
—
ITRIM1
—
ITRIM0
—
IRNG1
—
IRNG0
—
—
—
—
—
—
—
—
—
—
—
—
—
AD1CTMUENH 0360
CTMEN17 CTMEN16 0000
CTMEN1 CTMEN0 0000
AD1CTMUENL 0362 CTMEN15 CTMEN14 CTMEN13 CTMEN12 CTMEN11 CTMEN10
Legend: — = unimplemented, read as ‘ ’. Reset values are shown in hexadecimal.
CTMEN9
CTMEN8
CTMEN7
CTMEN6
CTMEN5
CTMEN4
CTMEN3
CTMEN2
0
TABLE 4-18: ANALOG SELECT REGISTER MAP
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSA
ANSB
ANSC
04E0
—
—
—
—
ANSB12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ANSA3
ANSA2
ANSB2
ANSA1
ANSB1
ANSA0
ANSB0
000F
F01F
04E2 ANSB15 ANSB14 ANSB13
04E4
ANSB4 ANSB3(1)
—
—
—
—
—
ANSC2(1,2) ANSC1(1,2) ANSC0(1,2) 0007
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: These bits are not implemented in 20-pin devices.
2: These bits are not implemented in 28-pin devices.
TABLE 4-19: REAL-TIME CLOCK AND CALENDAR REGISTER MAP
All
Resets
File Name Addr
0620
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ALRMVAL
ALCFGRPT 0622 ALRMEN CHIME
RTCVAL 0624
RCFGCAL 0626 RTCEN
RTCPWC 0628 PWCEN PWCPOL PWCCPRE PWCSPRE RTCCLK1
ALRMVAL
xxxx
AMASK3
AMASK2
AMASK1
AMASK0
ALRMPTR1 ALRMPTR0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 0000
RTCVAL
xxxx
0000
xxxx
—
RTCWREN RTCSYNC HALFSEC
RTCOE
RTCPTR1
RTCPTR0
RTCOUT0
CAL7
—
CAL6
—
CAL5
—
CAL4
—
CAL3
—
CAL2
—
CAL1
—
CAL0
—
RTCCLK0
RTCOUT1
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-20: TRIPLE COMPARATOR REGISTER MAP
File
Name
All
Resets
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CMSTAT
CVRCON
CM1CON
CM2CON
CM3CON
0630
0632
0634
0636
0638
CMIDL
—
—
—
—
—
—
—
—
—
C3EVT
—
C2EVT
—
C1EVT
—
—
—
—
—
—
CVR3
—
C3OUT C2OUT C1OUT
xxxx
0000
xxxx
0000
0000
—
—
—
CVREN CVROE CVRSS CVR4
CVR2
—
CVR1
CCH1
CCH1
CCH1
CVR0
CCH0
CCH0
CCH0
CON
CON
CON
COE
COE
COE
CPOL
CPOL
CPOL
CLPWR
CLPWR
CLPWR
—
CEVT
CEVT
CEVT
COUT
COUT
COUT
EVPOL1 EVPOL0
EVPOL1 EVPOL0
EVPOL1 EVPOL0
—
—
—
CREF
CREF
CREF
—
—
—
—
—
—
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-21: CRC REGISTER MAP
File
Name
All
Resets
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CRCCON1
CRCCON2
CRCXORL
CRCXORH
CRCDATL
CRCDATH
CRCWDATL
CRCWDATH
0640
0642
0644
0646
0648
064A
064C
064E
CRCEN
—
—
—
CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT CRCISEL CRCGO LENDIAN
—
—
—
0000
—
DWIDTH4 DWIDTH3 DWIDTH2 DWIDTH1 DWIDTH0
—
X7
—
X6
—
X5
PLEN4
X4
PLEN3
X3
PLEN2 PLEN1 PLEN0 0000
X15
X14
X30
X13
X29
X12
X28
X11
X27
X10
X26
X9
X8
X2
X1
—
0000
0000
xxxx
xxxx
xxxx
xxxx
X31
X25
X24
X23
X22
X21
X20
X19
X18
X17
X16
CRCDATL
CRCDATH
CRCWDATL
CRCWDATH
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-22: CLOCK CONTROL REGISTER MAP
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
DPSLP
Bit 9
Bit 8
PMSLP
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
BOR
Bit 0
RCON
0740
0742
0744
0748
074E
TRAPR IOPUWR SBOREN RETEN
—
—
CM
EXTR
SWR
—
SWDTEN
LOCK
—
WDTO
—
SLEEP
CF
IDLE
POR
(Note 1)
OSCCON
CLKDIV
—
ROI
—
COSC2
DOZE2
—
COSC1
DOZE1
—
COSC0
DOZE0
—
NOSC2 NOSC1 NOSC0 CLKLOCK
SOSCDRV SOSCEN OSWEN (Note 2)
DOZEN RCDIV2 RCDIV1 RCDIV0
—
—
—
—
—
—
TUN2
—
—
TUN1
—
—
TUN0
—
3140
0000
0000
0000
OSCTUN
REFOCON
HLVDCON
—
—
—
—
—
TUN5
—
TUN4
—
TUN3
—
ROEN
—
ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0
HLSIDL
—
—
0756 HLVDEN
—
—
—
—
—
—
VDIR
BGVST
IRVST
—
HLVDL3 HLVDL2
HLVDL1 HLVDL0
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: RCON register Reset values are dependent on the type of Reset.
2: OSCCON register Reset values are dependent on the Configuration Fuses and by type of Reset.
TABLE 4-23: DEEP SLEEP REGISTER MAP
All
Resets
File Name
Addr
Bit 15 Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DSCON
0758
075A
075C
075E
DSEN
—
—
—
—
—
—
—
—
—
—
—
—
—
RTCCWDIS
DSINT0
—
—
—
—
—
ULPWDIS
DSBOR RELEASE
DSPOR
0000
0000
0000
0000
DSWAKE
DSGPR0(1)
DSGPR1(1)
DSFLT
—
DSWDT DSRTCC DSMCLR
—
DSGPR0
DSGPR1
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: The Deep Sleep registers, DSGPR0 and DSGPR1, are only reset on a VDD POR event.
TABLE 4-24: NVM REGISTER MAP
All
File Name
Addr Bit 15 Bit 14
Bit 13
Bit 12
Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Resets(1)
NVMCON
NVMKEY
0760
0766
WR
—
WREN WRERR PGMONLY
—
—
—
—
—
—
—
—
—
ERASE
NVMOP5 NVMOP4 NVMOP3 NVMOP2 NVMOP1 NVMOP0
NVMKEY
0000
0000
—
—
—
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Reset value shown is for POR only. The value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
TABLE 4-25: ULTRA LOW-POWER WAKE-UP REGISTER MAP
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ULPWCON
0768 ULPEN
—
ULPSIDL
—
—
—
—
ULPSINK
—
—
—
—
—
—
—
—
0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-26: PMD REGISTER MAP
All
Resets
File Name Addr Bit 15 Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PMD1
PMD2
PMD3
PMD4
0770 T5MD T4MD
T3MD
—
T2MD
—
T1MD
—
—
—
—
I2C1MD
—
U2MD
—
U1MD
—
SPI2MD
—
SPI1MD
—
OC3MD
—
—
ADC1MD 0000
0772
0774
0776
—
—
—
—
—
—
IC3MD
IC2MD
IC1MD
—
—
—
OC2MD
I2C2MD
OC1MD
0000
0000
0000
—
—
—
CMPMD RTCCMD
CRCPMD
ULPWUMD
—
—
—
—
—
—
—
—
—
—
—
—
—
EEMD
REFOMD CTMUMD HLVDMD
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
PIC24FV32KA304 FAMILY
4.2.5
SOFTWARE STACK
4.3
Interfacing Program and Data
Memory Spaces
In addition to its use as a working register, the W15
register in PIC24F devices is also used as a Software
Stack Pointer. The pointer always points to the first
available free word and grows from lower to higher
addresses. It predecrements for stack pops and
post-increments for stack pushes, as shown in
Figure 4-4.
The PIC24F architecture uses a 24-bit wide program
space and 16-bit wide data space. The architecture is
also a modified Harvard scheme, meaning that data
can also be present in the program space. To use this
data successfully, it must be accessed in a way that
preserves the alignment of information in both spaces.
Note that for a PC push during any CALL instruction,
the MSB of the PC is zero-extended before the push,
ensuring that the MSB is always clear.
Apart from the normal execution, the PIC24F
architecture provides two methods by which the
program space can be accessed during operation:
Note:
A PC push during exception processing
will concatenate the SRL register to the
MSB of the PC prior to the push.
• Using table instructions to access individual bytes
or words anywhere in the program space
• Remapping a portion of the program space into
the data space, PSV
The Stack Pointer Limit Value (SPLIM) register,
associated with the Stack Pointer, sets an upper
address boundary for the stack. SPLIM is uninitialized
at Reset. As is the case for the Stack Pointer,
SPLIM<0> is forced to ‘0’ as all stack operations must
be word-aligned. Whenever an EA is generated, using
W15 as a source or destination pointer, the resulting
address is compared with the value in SPLIM. If the
contents of the Stack Pointer (W15) and the SPLIM
register are equal, and a push operation is performed,
a stack error trap will not occur. The stack error trap will
occur on a subsequent push operation.
Table instructions allow an application to read or write
small areas of the program memory. This makes the
method ideal for accessing data tables that need to be
updated from time to time. It also allows access to all
bytes of the program word. The remapping method
allows an application to access a large block of data on
a read-only basis, which is ideal for look-ups from a
large table of static data. It can only access the least
significant word (lsw) of the program word.
4.3.1
ADDRESSING PROGRAM SPACE
Thus, for example, if it is desirable to cause a stack
error trap when the stack grows beyond address, 0DF6
in RAM, initialize the SPLIM with the value, 0DF4.
Since the address ranges for the data and program
spaces are 16 and 24 bits, respectively, a method is
needed to create a 23-bit or 24-bit program address
from 16-bit data registers. The solution depends on the
interface method to be used.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0800h. This prevents the stack from
interfering with the Special Function Register (SFR)
space.
For table operations, the 8-bit Table Memory Page
Address register (TBLPAG) is used to define a 32K word
region within the program space. This is concatenated
with a 16-bit EA to arrive at a full 24-bit program space
address. In this format, the Most Significant bit (MSb) of
TBLPAG is used to determine if the operation occurs in
the user memory (TBLPAG<7> = 0) or the configuration
memory (TBLPAG<7> = 1).
Note:
A write to the SPLIM register should not
be immediately followed by an indirect
read operation using W15.
FIGURE 4-4:
CALL STACK FRAME
For remapping operations, the 8-bit Program Space
Visibility Page Address register (PSVPAG) is used to
define a 16K word page in the program space. When
the MSb of the EA is ‘1’, PSVPAG is concatenated with
the lower 15 bits of the EA to form a 23-bit program
space address. Unlike the table operations, this limits
remapping operations strictly to the user memory area.
0000h
15
0
PC<15:0>
000000000
W15 (before CALL)
W15 (after CALL)
Table 4-27 and Figure 4-5 show how the program EA is
created for table operations and remapping accesses
from the data EA. Here, the P<23:0> bits refer to a pro-
gram space word, whereas the D<15:0> bits refer to a
data space word.
PC<22:16>
<Free Word>
POP : [--W15]
PUSH: [W15++]
DS39995D-page 51
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
TABLE 4-27: PROGRAM SPACE ADDRESS CONSTRUCTION
Program Space Address
Access
Space
Access Type
<23>
<22:16>
<15>
PC<22:1>
<14:1>
<0>
Instruction Access
(Code Execution)
User
User
0
0
0xx xxxx xxxx xxxx xxxx xxx0
TBLRD/TBLWT
(Byte/Word Read/Write)
TBLPAG<7:0>
0xxx xxxx
Data EA<15:0>
xxxx xxxx xxxx xxxx
Data EA<15:0>
Configuration
TBLPAG<7:0>
1xxx xxxx
xxxx xxxx xxxx xxxx
Data EA<14:0>(1)
Program Space Visibility User
(Block Remap/Read)
0
0
PSVPAG<7:0>(2)
xxxx xxxx
xxx xxxx xxxx xxxx
Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of
the address is PSVPAG<0>.
2: PSVPAG can have only two values (‘00’ to access program memory and FF to access data EEPROM) in
the PIC24FV32KA304 family.
FIGURE 4-5:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1)
Program Counter
23 Bits
0
0
1/0
EA
Table Operations(2)
1/0
TBLPAG
8 Bits
16 Bits
24 Bits
Select
1
EA
0
Program Space Visibility(1)
(Remapping)
0
PSVPAG
8 Bits
15 Bits
23 Bits
User/Configuration
Space Select
Byte Select
Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word alignment of data in the
program and data spaces.
2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration
memory space.
2011-2013 Microchip Technology Inc.
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PIC24FV32KA304 FAMILY
Two table instructions are provided to move byte or
word-sized (16-bit) data to and from program space.
Both function as either byte or word operations.
4.3.2
DATA ACCESS FROM PROGRAM
MEMORY AND DATA EEPROM
MEMORY USING TABLE
INSTRUCTIONS
1. TBLRDL (Table Read Low): In Word mode, it
maps the lower word of the program space
location (P<15:0>) to a data address (D<15:0>).
The TBLRDL and TBLWTL instructions offer a direct
method of reading or writing the lower word of any
address within the program memory without going
through data space. It also offers a direct method of
reading or writing a word of any address within data
EEPROM memory. The TBLRDH and TBLWTH
instructions are the only method to read or write the
upper 8 bits of a program space word as data.
In Byte mode, either the upper or lower byte of
the lower program word is mapped to the lower
byte of a data address. The upper byte is
selected when byte select is ‘1’; the lower byte
is selected when it is ‘0’.
2. TBLRDH (Table Read High): In Word mode, it
maps the entire upper word of a program address
Note:
The TBLRDHand TBLWTHinstructions are
not used while accessing data EEPROM
memory.
(P<23:16>) to
a data address. Note that
D<15:8>, the ‘phantom’ byte, will always be ‘0’.
In Byte mode, it maps the upper or lower byte of
the program word to D<7:0> of the data
address, as above. Note that the data will
always be ‘0’ when the upper ‘phantom’ byte is
selected (Byte Select = 1).
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bit
word-wide address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space which contains the least significant
data word, and TBLRDHand TBLWTHaccess the space
which contains the upper data byte.
DS39995D-page 53
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
In a similar fashion, two table instructions, TBLWTH
TBLPAG<7> = 0, the table page is located in the user
memory space. When TBLPAG<7> = 1, the page is
located in configuration space.
and TBLWTL, are used to write individual bytes or
words to a program space address. The details of
their operation are explained in Section 5.0 “Flash
Program Memory”.
Note:
Only Table Read operations will execute
in the configuration memory space, and
only then, in implemented areas, such as
the Device ID. Table write operations are
not allowed.
For all table operations, the area of program memory
space to be accessed is determined by the Table
Memory Page Address register (TBLPAG). TBLPAG
covers the entire program memory space of the
device, including user and configuration spaces. When
FIGURE 4-6:
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space
Data EA<15:0>
TBLPAG
23
16
8
0
00
00000000
00000000
00000000
00000000
000000h
002BFEh
23
15
0
‘Phantom’ Byte
TBLRDH.B(Wn<0> = 0)
TBLRDL.B(Wn<0> = 1)
TBLRDL.B(Wn<0> = 0)
TBLRDL.W
The address for the table operation is determined by the data EA
within the page defined by the TBLPAG register. Only read
operations are provided; write operations are also valid in the
user memory area.
800000h
2011-2013 Microchip Technology Inc.
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PIC24FV32KA304 FAMILY
Although each data space address, 8000h and higher,
maps directly into a corresponding program memory
address (see Figure 4-7), only the lower 16 bits of the
24-bit program word are used to contain the data. The
upper 8 bits of any program space location used as data
should be programmed with ‘1111 1111’ or ‘0000
0000’ to force a NOP. This prevents possible issues
should the area of code ever be accidentally executed.
4.3.3
READING DATA FROM PROGRAM
MEMORY USING PROGRAM SPACE
VISIBILITY
The upper 32 Kbytes of data space may optionally be
mapped into a 16K word page (in PIC24FV16KA3XX
devices) and a 32K word page (in PIC24FV32KA3XX
devices) of the program space. This provides
transparent access of stored constant data from the
data space without the need to use special instructions
(i.e., TBLRDL/H).
Note:
PSV access is temporarily disabled during
table reads/writes.
Program space access through the data space occurs
if the MSb of the data space EA is ‘1’ and PSV is
enabled by setting the PSV bit in the CPU Control
(CORCON<2>) register. The location of the program
memory space to be mapped into the data space is
determined by the Program Space Visibility Page
Address (PSVPAG) register. This 8-bit register defines
any one of 256 possible pages of 16K words in program
space. In effect, PSVPAG functions as the upper 8 bits
of the program memory address, with the 15 bits of the
EA functioning as the lower bits.
For operations that use PSV and are executed outside a
REPEATloop, the MOVand MOV.Dinstructions will require
one instruction cycle in addition to the specified execution
time. All other instructions will require two instruction
cycles in addition to the specified execution time.
For operations that use PSV, which are executed inside
a REPEAT loop, there will be some instances that
require two instruction cycles in addition to the
specified execution time of the instruction:
• Execution in the first iteration
• Execution in the last iteration
• Execution prior to exiting the loop due to an
interrupt
• Execution upon re-entering the loop after an
interrupt is serviced
By incrementing the PC by 2 for each program memory
word, the lower 15 bits of data space addresses directly
map to the lower 15 bits in the corresponding program
space addresses.
Data reads from this area add an additional cycle to the
instruction being executed, since two program memory
fetches are required.
Any other iteration of the REPEAT loop will allow the
instruction accessing data, using PSV, to execute in a
single cycle.
FIGURE 4-7:
PROGRAM SPACE VISIBILITY OPERATION
When CORCON<2> = 1and EA<15> = 1:
Program Space
15
Data Space
PSVPAG
23
0
000000h
002BFEh
0000h
00
Data EA<14:0>
The data in the page
designated by
PSVPAG is mapped
into the upper half
of the data memory
space....
8000h
PSV Area
...while the lower 15 bits of
the EA specify an exact
address within the PSV
area. This corresponds
exactly to the same lower
15 bits of the actual
FFFFh
program space address.
800000h
2011-2013 Microchip Technology Inc.
DS39995D-page 55
PIC24FV32KA304 FAMILY
NOTES:
DS39995D-page 56
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
Run-Time Self Programming (RTSP) is accomplished
using TBLRD (Table Read) and TBLWT (Table Write)
5.0
FLASH PROGRAM MEMORY
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on Flash pro-
gramming, refer to the “PIC24F Family
Reference Manual”, Section 4. “Program
Memory” (DS39715).
instructions. With RTSP, the user may write program
memory data in blocks of 32 instructions (96 bytes) at
a time, and erase program memory in blocks of 32, 64
and 128 instructions (96,192 and 384 bytes) at a time.
The NVMOP<1:0> (NVMCON<1:0>) bits decide the
erase block size.
5.1
Table Instructions and Flash
Programming
The PIC24FV32KA304 family of devices contains
internal Flash program memory for storing and executing
application code. The memory is readable, writable and
erasable when operating with VDD over 1.8V.
Regardless of the method used, Flash memory
programming is done with the table read and write
instructions. These allow direct read and write access to
the program memory space from the data memory while
the device is in normal operating mode. The 24-bit target
address in the program memory is formed using the
TBLPAG<7:0> bits and the Effective Address (EA) from
a W register, specified in the table instruction, as
depicted in Figure 5-1.
Flash memory can be programmed in three ways:
• In-Circuit Serial Programming™ (ICSP™)
• Run-Time Self Programming (RTSP)
• Enhanced In-Circuit Serial Programming
(Enhanced ICSP)
ICSP allows a PIC24FV32KA304 device to be serially
programmed while in the end application circuit. This is
simply done with two lines for the programming clock
and programming data (which are named PGECx and
PGEDx, respectively), and three other lines for power
(VDD), ground (VSS) and Master Clear/Program mode
Entry Voltage (MCLR/VPP). This allows customers to
manufacture boards with unprogrammed devices and
then program the microcontroller just before shipping
the product. This also allows the most recent firmware
or custom firmware to be programmed.
The TBLRDLand the TBLWTLinstructions are used to
read or write to bits<15:0> of program memory.
TBLRDLand TBLWTLcan access program memory in
both Word and Byte modes.
The TBLRDHand TBLWTHinstructions are used to read
or write to bits<23:16> of program memory. TBLRDH
and TBLWTHcan also access program memory in Word
or Byte mode.
FIGURE 5-1:
ADDRESSING FOR TABLE REGISTERS
24 Bits
Using
Program
Counter
0
0
Program Counter
Working Reg EA
Using
Table
Instruction
1/0
TBLPAG Reg
8 Bits
16 Bits
User/Configuration
Space Select
Byte
Select
24-Bit EA
2011-2013 Microchip Technology Inc.
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PIC24FV32KA304 FAMILY
5.2
RTSP Operation
5.3
Enhanced In-Circuit Serial
Programming
The PIC24F Flash program memory array is organized
into rows of 32 instructions or 96 bytes. RTSP allows
the user to erase blocks of 1 row, 2 rows and 4 rows
(32, 64 and 128 instructions) at a time, and to program
one row at a time. It is also possible to program single
words.
Enhanced ICSP uses an on-board bootloader, known as
the Programming Executive (PE), to manage the pro-
gramming process. Using an SPI data frame format, the
Programming Executive can erase, program and verify
program memory. For more information on Enhanced
ICSP, see the device programming specification.
The 1-row (96 bytes), 2-row (192 bytes) and 4-row
(384 bytes) erase blocks, and single row write block
(96 bytes) are edge-aligned from the beginning of
program memory.
5.4
Control Registers
There are two SFRs used to read and write the
program Flash memory: NVMCON and NVMKEY.
When data is written to program memory using TBLWT
instructions, the data is not written directly to memory.
Instead, data written using table writes is stored in holding
latches until the programming sequence is executed.
The NVMCON register (Register 5-1) controls the blocks
that need to be erased, which memory type is to be
programmed and when the programming cycle starts.
Any number of TBLWT instructions can be executed
and a write will be successfully performed. However,
32 TBLWTinstructions are required to write the full row
of memory.
NVMKEY is a write-only register that is used for write
protection. To start a programming or erase sequence,
the user must consecutively write 55h and AAh to the
NVMKEY register. For more information, refer to
Section 5.5 “Programming Operations”.
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWTinstructions to
load the buffers. Programming is performed by setting
the control bits in the NVMCON register.
5.5
Programming Operations
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. During a program or erase operation, the
processor stalls (Waits) until the operation is finished.
Setting the WR bit (NVMCON<15>) starts the opera-
tion and the WR bit is automatically cleared when the
operation is finished.
Data can be loaded in any order and the holding registers
can be written to multiple times before performing a write
operation. Subsequent writes, however, will wipe out any
previous writes.
Note:
Writing to a location multiple times without
erasing it is not recommended.
All of the table write operations are single-word writes
(two instruction cycles), because only the buffers are
written.
A
programming cycle is required for
programming each row.
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REGISTER 5-1:
NVMCON: FLASH MEMORY CONTROL REGISTER
R/SO-0, HC
WR
R/W-0
R/W-0
R/W-0
PGMONLY(4)
U-0
—
U-0
—
U-0
—
U-0
—
WREN
WRERR
bit 15
bit 8
U-0
—
R/W-0
R/W-0
NVMOP5(1)
R/W-0
NVMOP4(1)
R/W-0
R/W-0
R/W-0
NVMOP1(1)
R/W-0
NVMOP0(1)
bit 0
ERASE
NVMOP3(1) NVMOP2(1)
bit 7
Legend:
SO = Settable Only bit
‘1’ = Bit is set
HC = Hardware Clearable bit
R = Readable bit
-n = Value at POR
‘0’ = Bit is cleared
W = Writable bit
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
bit 15
WR: Write Control bit
1= Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is
cleared by hardware once the operation is complete.
0= Program or erase operation is complete and inactive
bit 14
bit 13
WREN: Write Enable bit
1= Enables Flash program/erase operations
0= Inhibits Flash program/erase operations
WRERR: Write Sequence Error Flag bit
1= An improper program or erase sequence attempt, or termination, has occurred (bit is set automatically
on any set attempt of the WR bit)
0= The program or erase operation completed normally
bit 12
bit 11-7
bit 6
PGMONLY: Program Only Enable bit(4)
Unimplemented: Read as ‘0’
ERASE: Erase/Program Enable bit
1= Performs the erase operation specified by NVMOP<5:0> on the next WR command
0= Performs the program operation specified by NVMOP<5:0> on the next WR command
bit 5-0
NVMOP<5:0>: Programming Operation Command Byte bits(1)
Erase Operations (when ERASE bit is ‘1’):
1010xx= Erases entire boot block (including code-protected boot block)(2)
1001xx= Erases entire memory (including boot block, configuration block, general block)(2)
011010= Erases 4 rows of Flash memory(3)
011001= Erases 2 rows of Flash memory(3)
011000= Erases 1 row of Flash memory(3)
0101xx= Erases entire configuration block (except code protection bits)
0100xx= Erases entire data EEPROM(4)
0011xx= Erases entire general memory block programming operations
0001xx= Writes 1 row of Flash memory (when ERASE bit is ‘0’)(3)
Note 1: All other combinations of NVMOP<5:0> are no operation.
2: These values are available in ICSP™ mode only. Refer to the device programming specification.
3: The address in the Table Pointer decides which rows will be erased.
4: This bit is used only while accessing data EEPROM.
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4. Write the first 32 instructions from data RAM into
the program memory buffers (see Example 5-1).
5.5.1
PROGRAMMING ALGORITHM FOR
FLASH PROGRAM MEMORY
5. Write the program block to Flash memory:
The user can program one row of Flash program
memory at a time by erasing the programmable row.
The general process is as follows:
a) Set the NVMOPx bits to ‘011000’ to
configure for row programming. Clear the
ERASE bit and set the WREN bit.
1. Read a row of program memory (32 instructions)
and store in data RAM.
b) Write 55h to NVMKEY.
c) Write AAh to NVMKEY.
2. Update the program data in RAM with the
desired new data.
d) Set the WR bit. The programming cycle
begins and the CPU stalls for the duration of
the write cycle. When the write to Flash
memory is done, the WR bit is cleared
automatically.
3. Erase a row (see Example 5-1):
a) Set the NVMOPx bits (NVMCON<5:0>) to
‘011000’ to configure for row erase. Set the
ERASE (NVMCON<6>) and WREN
(NVMCON<14>) bits.
For protection against accidental operations, the write
initiate sequence for NVMKEY must be used to allow
any erase or program operation to proceed. After the
programming command has been executed, the user
must wait for the programming time until programming
is complete. The two instructions following the start of
the programming sequence should be NOPs, as shown
in Example 5-5.
b) Write the starting address of the block to be
erased into the TBLPAG and W registers.
c) Write 55h to NVMKEY.
d) Write AAh to NVMKEY.
e) Set the WR bit (NVMCON<15>). The erase
cycle begins and the CPU stalls for the
duration of the erase cycle. When the erase is
done, the WR bit is cleared automatically.
EXAMPLE 5-1:
ERASING A PROGRAM MEMORY ROW – ASSEMBLY LANGUAGE CODE
; Set up NVMCON for row erase operation
MOV
MOV
#0x4058, W0
W0, NVMCON
;
; Initialize NVMCON
; Init pointer to row to be ERASED
MOV
MOV
MOV
#tblpage(PROG_ADDR), W0
W0, TBLPAG
#tbloffset(PROG_ADDR), W0
;
; Initialize PM Page Boundary SFR
; Initialize in-page EA[15:0] pointer
; Set base address of erase block
; Block all interrupts
TBLWTL W0, [W0]
DISI
#5
for next 5 instructions
MOV
MOV
MOV
MOV
BSET
NOP
NOP
#0x55, W0
W0, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
; Write the 55 key
;
; Write the AA key
; Start the erase sequence
; Insert two NOPs after the erase
; command is asserted
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EXAMPLE 5-2:
ERASING A PROGRAM MEMORY ROW – ‘C’ LANGUAGE CODE
// C example using MPLAB C30
int __attribute__ ((space(auto_psv))) progAddr = 0x1234;// Global variable located in Pgm Memory
unsigned int offset;
//Set up pointer to the first memory location to be written
TBLPAG = __builtin_tblpage(&progAddr);
offset = __builtin_tbloffset(&progAddr);
// Initialize PM Page Boundary SFR
// Initialize lower word of address
__builtin_tblwtl(offset, 0x0000);
// Set base address of erase block
// with dummy latch write
NVMCON = 0x4058;
// Initialize NVMCON
asm("DISI #5");
// Block all interrupts for next 5
// instructions
// C30 function to perform unlock
// sequence and set WR
__builtin_write_NVM();
EXAMPLE 5-3:
LOADING THE WRITE BUFFERS – ASSEMBLY LANGUAGE CODE
; Set up NVMCON for row programming operations
MOV
MOV
#0x4004, W0
W0, NVMCON
;
; Initialize NVMCON
; Set up a pointer to the first program memory location to be written
; program memory selected, and writes enabled
MOV
MOV
MOV
#0x0000, W0
W0, TBLPAG
#0x6000, W0
;
; Initialize PM Page Boundary SFR
; An example program memory address
; Perform the TBLWT instructions to write the latches
; 0th_program_word
MOV
MOV
#LOW_WORD_0, W2
#HIGH_BYTE_0, W3
;
;
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
; Write PM low word into program latch
; Write PM high byte into program latch
; 1st_program_word
MOV
MOV
#LOW_WORD_1, W2
#HIGH_BYTE_1, W3
;
;
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
; Write PM low word into program latch
; Write PM high byte into program latch
; 2nd_program_word
MOV
MOV
#LOW_WORD_2, W2
#HIGH_BYTE_2, W3
;
;
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
; Write PM low word into program latch
; Write PM high byte into program latch
•
•
•
; 32nd_program_word
MOV
MOV
#LOW_WORD_31, W2
#HIGH_BYTE_31, W3
;
;
TBLWTL W2, [W0]
TBLWTH W3, [W0]
; Write PM low word into program latch
; Write PM high byte into program latch
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EXAMPLE 5-4:
LOADING THE WRITE BUFFERS – ‘C’ LANGUAGE CODE
// C example using MPLAB C30
#define NUM_INSTRUCTION_PER_ROW 64
int __attribute__ ((space(auto_psv))) progAddr = 0x1234; // Global variable located in Pgm Memory
unsigned int offset;
unsigned int i;
unsigned int progData[2*NUM_INSTRUCTION_PER_ROW];
// Buffer of data to write
// Initialize NVMCON
//Set up NVMCON for row programming
NVMCON = 0x4001;
//Set up pointer to the first memory location to be written
TBLPAG = __builtin_tblpage(&progAddr);
offset = __builtin_tbloffset(&progAddr);
// Initialize PM Page Boundary SFR
// Initialize lower word of address
//Perform TBLWT instructions to write necessary number of latches
for(i=0; i < 2*NUM_INSTRUCTION_PER_ROW; i++)
{
__builtin_tblwtl(offset, progData[i++]);
__builtin_tblwth(offset, progData[i]);
offset = offset + 2;
// Write to address low word
// Write to upper byte
// Increment address
}
EXAMPLE 5-5:
INITIATING A PROGRAMMING SEQUENCE – ASSEMBLY LANGUAGE CODE
DISI
#5
; Block all interrupts
for next 5 instructions
MOV
MOV
MOV
MOV
BSET
NOP
NOP
BTSC
BRA
#0x55, W0
W0, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
; Write the 55 key
;
; Write the AA key
; Start the erase sequence
; 2 NOPs required after setting WR
;
; Wait for the sequence to be completed
;
NVMCON, #15
$-2
EXAMPLE 5-6:
INITIATING A PROGRAMMING SEQUENCE – ‘C’ LANGUAGE CODE
// C example using MPLAB C30
asm("DISI #5");
// Block all interrupts for next 5 instructions
// Perform unlock sequence and set WR
__builtin_write_NVM();
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6.1
NVMCON Register
6.0
DATA EEPROM MEMORY
The NVMCON register (Register 6-1) is also the primary
control register for data EEPROM program/erase
operations. The upper byte contains the control bits
used to start the program or erase cycle, and the flag bit
to indicate if the operation was successfully performed.
The lower byte of NVMCOM configures the type of NVM
operation that will be performed.
Note:
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive refer-
ence source. For more information on
Data EEPROM, refer to the “PIC24F
Family Reference Manual”, Section 5.
“Data EEPROM” (DS39720).
The data EEPROM memory is a Nonvolatile Memory
(NVM), separate from the program and volatile data
RAM. Data EEPROM memory is based on the same
Flash technology as program memory, and is optimized
for both long retention and a higher number of
erase/write cycles.
6.2
NVMKEY Register
The NVMKEY is a write-only register that is used to
prevent accidental writes or erasures of data EEPROM
locations.
To start any programming or erase sequence, the
following instructions must be executed first, in the
exact order provided:
The data EEPROM is mapped to the top of the user
program memory space, with the top address at pro-
gram memory address, 7FFE00h to 7FFFFFh. The
size of the data EEPROM is 256 words in the
PIC24FV32KA304 family devices.
1. Write 55h to NVMKEY.
2. Write AAh to NVMKEY.
After this sequence, a write will be allowed to the
NVMCON register for one instruction cycle. In most
cases, the user will simply need to set the WR bit in the
NVMCON register to start the program or erase cycle.
Interrupts should be disabled during the unlock
sequence.
The MPLAB® C30 C compiler provides a defined library
procedure (builtin_write_NVM) to perform the
unlock sequence. Example 6-1 illustrates how the
unlock sequence can be performed with in-line
assembly.
The data EEPROM is organized as 16-bit wide
memory. Each word is directly addressable, and is
readable and writable during normal operation over the
entire VDD range.
Unlike the Flash program memory, normal program
execution is not stopped during a data EEPROM
program or erase operation.
The data EEPROM programming operations are
controlled using the three NVM Control registers:
• NVMCON: Nonvolatile Memory Control Register
• NVMKEY: Nonvolatile Memory Key Register
• NVMADR: Nonvolatile Memory Address Register
EXAMPLE 6-1:
DATA EEPROM UNLOCK SEQUENCE
//Disable Interrupts For 5 instructions
asm volatile
//Issue Unlock Sequence
asm volatile ("mov #0x55, W0
("disi #5");
\n"
"mov W0, NVMKEY
"mov #0xAA, W1
"mov W1, NVMKEY
\n"
\n"
\n");
// Perform Write/Erase operations
asm volatile ("bset NVMCON, #WR \n"
"nop
"nop
\n"
\n");
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REGISTER 6-1:
NVMCON: NONVOLATILE MEMORY CONTROL REGISTER
R/S-0, HC
WR
R/W-0
WREN
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
WRERR
PGMONLY
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ERASE
NVMOP5
NVMOP4
NVMOP3
NVMOP2
NVMOP1
NVMOP0
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
S = Settable bit
R = Readable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
WR: Write Control bit (program or erase)
1= Initiates a data EEPROM erase or write cycle (can be set, but not cleared in software)
0= Write cycle is complete (cleared automatically by hardware)
WREN: Write Enable bit (erase or program)
1= Enables an erase or program operation
0= No operation allowed (device clears this bit on completion of the write/erase operation)
WRERR: Write Flash Error Flag bit
1= A write operation is prematurely terminated (any MCLR or WDT Reset during programming
operation)
0= The write operation completed successfully
bit 12
PGMONLY: Program Only Enable bit
1= Write operation is executed without erasing target address(es) first
0= Automatic erase-before-write
Write operations are preceded automatically by an erase of the target address(es).
bit 11-7
bit 6
Unimplemented: Read as ‘0’
ERASE: Erase Operation Select bit
1= Performs an erase operation when WR is set
0= Performs a write operation when WR is set
bit 5-0
NVMOP<5:0>: Programming Operation Command Byte bits
Erase Operations (when ERASE bit is ‘1’):
011010= Erases 8 words
011001= Erases 4 words
011000= Erases 1 word
0100xx= Erases entire data EEPROM
Programming Operations (when ERASE bit is ‘0’):
0010xx= Writes 1 word
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6.3
NVM Address Register
6.4
Data EEPROM Operations
As with Flash program memory, the NVM Address
registers, NVMADRU and NVMADR, form the 24-bit
Effective Address (EA) of the selected row or word for
data EEPROM operations. The NVMADRU register is
used to hold the upper 8 bits of the EA, while the
NVMADR register is used to hold the lower 16 bits of
the EA. These registers are not mapped into the
Special Function Register (SFR) space. Instead, they
directly capture the EA<23:0> of the last table write
instruction that has been executed and selects the data
EEPROM row to erase. Figure 6-1 depicts the program
memory EA that is formed for programming and erase
operations.
The EEPROM block is accessed using table read and
write operations similar to those used for program
memory. The TBLWTHand TBLRDHinstructions are not
required for data EEPROM operations since the
memory is only 16 bits wide (data on the lower address
is valid only). The following programming operations
can be performed on the data EEPROM:
• Erase one, four or eight words
• Bulk erase the entire data EEPROM
• Write one word
• Read one word
Note 1: Unexpected results will be obtained if the
user attempts to read the EEPROM while
a programming or erase operation is
underway.
Like program memory operations, the Least Significant
bit (LSb) of NVMADR is restricted to even addresses.
This is because any given address in the data EEPROM
space consists of only the lower word of the program
memory width; the upper word, including the uppermost
“phantom byte”, are unavailable. This means that the
LSb of a data EEPROM address will always be ‘0’.
2: The C30 C compiler includes library pro-
cedures to automatically perform the
table read and table write operations,
manage the Table Pointer and write buf-
fers, and unlock and initiate memory
write sequences. This eliminates the
need to create assembler macros or time
critical routines in C for each application.
Similarly, the Most Significant bit (MSb) of NVMADRU
is always ‘0’, since all addresses lie in the user program
space.
FIGURE 6-1:
DATA EEPROM
The library procedures are used in the code examples
detailed in the following sections. General descriptions
of each process are provided for users who are not
using the C30 compiler libraries.
ADDRESSING WITH
TBLPAG AND NVM
ADDRESS REGISTERS
24-Bit PM Address
xxxxh
7Fh
0
0
W Register EA
TBLPAG
NVMADRU
NVMADR
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A typical erase sequence is provided in Example 6-2.
This example shows how to do a one-word erase.
Similarly, a four-word erase and an eight-word erase
can be done. This example uses C library procedures to
manage the Table Pointer (builtin_tblpage and
builtin_tbloffset) and the Erase Page Pointer
(builtin_tblwtl). The memory unlock sequence
(builtin_write_NVM) also sets the WR bit to initiate
the operation and returns control when complete.
6.4.1
ERASE DATA EEPROM
The data EEPROM can be fully erased, or can be
partially erased, at three different sizes: one word, four
words or eight words. The bits, NVMOP<1:0>
(NVMCON<1:0>), decide the number of words to be
erased. To erase partially from the data EEPROM, the
following sequence must be followed:
1. Configure NVMCON to erase the required
number of words: one, four or eight.
2. Load TBLPAG and WREG with the EEPROM
address to be erased.
3. Clear the NVMIF status bit and enable the NVM
interrupt (optional).
4. Write the key sequence to NVMKEY.
5. Set the WR bit to begin the erase cycle.
6. Either poll the WR bit or wait for the NVM
interrupt (NVMIF is set).
EXAMPLE 6-2:
SINGLE-WORD ERASE
int __attribute__ ((space(eedata))) eeData = 0x1234;
/*--------------------------------------------------------------------------------------------
The variable eeData must be a Global variable declared outside of any method
the code following this comment can be written inside the method that will execute the erase
----------------------------------------------------------------------------------------------
*/
unsigned int offset;
// Set up NVMCON to erase one word of data EEPROM
NVMCON = 0x4058;
// Set up a pointer to the EEPROM location to be erased
TBLPAG = __builtin_tblpage(&eeData);
offset = __builtin_tbloffset(&eeData);
__builtin_tblwtl(offset, 0);
// Initialize EE Data page pointer
// Initizlize lower word of address
// Write EEPROM data to write latch
asm volatile ("disi #5");
__builtin_write_NVM();
while(NVMCONbits.WR=1);
// Disable Interrupts For 5 Instructions
// Issue Unlock Sequence & Start Write Cycle
// Optional: Poll WR bit to wait for
// write sequence to complete
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6.4.1.1
Data EEPROM Bulk Erase
6.4.2
SINGLE-WORD WRITE
To erase the entire data EEPROM (bulk erase), the
address registers do not need to be configured
because this operation affects the entire data
EEPROM. The following sequence helps in performing
a bulk erase:
To write a single word in the data EEPROM, the
following sequence must be followed:
1. Erase one data EEPROM word (as mentioned in
the previous section) if the PGMONLY bit
(NVMCON<12>) is set to ‘1’.
1. Configure NVMCON to Bulk Erase mode.
2. Write the data word into the data EEPROM
latch.
2. Clear the NVMIF status bit and enable the NVM
interrupt (optional).
3. Program the data word into the EEPROM:
3. Write the key sequence to NVMKEY.
4. Set the WR bit to begin the erase cycle.
- Configure the NVMCON register to program one
EEPROM word (NVMCON<5:0> = 0001xx).
- Clear the NVMIF status bit and enable the NVM
interrupt (optional).
5. Either poll the WR bit or wait for the NVM
interrupt (NVMIF is set).
- Write the key sequence to NVMKEY.
- Set the WR bit to begin the erase cycle.
- Either poll the WR bit or wait for the NVM
interrupt (NVMIF is set).
A
typical bulk erase sequence is provided in
Example 6-3.
- To get cleared, wait until NVMIF is set.
A typical single-word write sequence is provided in
Example 6-4.
EXAMPLE 6-3:
DATA EEPROM BULK ERASE
// Set up NVMCON to bulk erase the data EEPROM
NVMCON = 0x4050;
// Disable Interrupts For 5 Instructions
asm volatile ("disi #5");
// Issue Unlock Sequence and Start Erase Cycle
__builtin_write_NVM();
EXAMPLE 6-4:
SINGLE-WORD WRITE TO DATA EEPROM
int __attribute__ ((space(eedata))) eeData = 0x1234;
int newData;
// New data to write to EEPROM
/*---------------------------------------------------------------------------------------------
The variable eeData must be a Global variable declared outside of any method
the code following this comment can be written inside the method that will execute the write
-----------------------------------------------------------------------------------------------
*/
unsigned int offset;
// Set up NVMCON to erase one word of data EEPROM
NVMCON = 0x4004;
// Set up a pointer to the EEPROM location to be erased
TBLPAG = __builtin_tblpage(&eeData);
offset = __builtin_tbloffset(&eeData);
__builtin_tblwtl(offset, newData);
// Initialize EE Data page pointer
// Initizlize lower word of address
// Write EEPROM data to write latch
asm volatile ("disi #5");
__builtin_write_NVM();
while(NVMCONbits.WR=1);
// Disable Interrupts For 5 Instructions
// Issue Unlock Sequence & Start Write Cycle
// Optional: Poll WR bit to wait for
// write sequence to complete
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A typical read sequence, using the Table Pointer
management (builtin_tblpage and
builtin_tbloffset) and table read procedures
(builtin_tblrdl) from the C30 compiler library, is
provided in Example 6-5.
6.4.3
READING THE DATA EEPROM
To read a word from data EEPROM, the table read
instruction is used. Since the EEPROM array is only
16 bits wide, only the TBLRDL instruction is needed.
The read operation is performed by loading TBLPAG
and WREG with the address of the EEPROM location,
followed by a TBLRDLinstruction.
Program Space Visibility (PSV) can also be used to
read locations in the data EEPROM.
EXAMPLE 6-5:
READING THE DATA EEPROM USING THE TBLRD COMMAND
int __attribute__ ((space(eedata))) eeData = 0x1234;
int data;
// Data read from EEPROM
/*--------------------------------------------------------------------------------------------
The variable eeData must be a Global variable declared outside of any method
the code following this comment can be written inside the method that will execute the read
----------------------------------------------------------------------------------------------
*/
unsigned int offset;
// Set up a pointer to the EEPROM location to be erased
TBLPAG = __builtin_tblpage(&eeData);
offset = __builtin_tbloffset(&eeData);
data = __builtin_tblrdl(offset);
// Initialize EE Data page pointer
// Initizlize lower word of address
// Write EEPROM data to write latch
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Any active source of Reset will make the SYSRST
signal active. Many registers associated with the CPU
7.0
RESETS
Note:
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive refer-
ence source. For more information on
Resets, refer to the “PIC24F Family
Reference Manual”, Section 40. “Reset
with Programmable Brown-out Reset”
(DS39728).
and peripherals are forced to a known Reset state.
Most registers are unaffected by a Reset; their status is
unknown on Power-on Reset (POR) and unchanged by
all other Resets.
Note:
Refer to the specific peripheral or
Section 3.0 “CPU” of this data sheet for
register Reset states.
All types of device Reset will set a corresponding status
bit in the RCON register to indicate the type of Reset
(see Register 7-1). A Power-on Reset will clear all bits
except for the BOR and POR bits (RCON<1:0>) which
are set. The user may set or clear any bit at any time
during code execution. The RCON bits only serve as
status bits. Setting a particular Reset status bit in
software will not cause a device Reset to occur.
The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
• POR: Power-on Reset
• MCLR: Pin Reset
• SWR: RESETInstruction
• WDTR: Watchdog Timer Reset
• BOR: Brown-out Reset
• Low-Power BOR/Deep Sleep BOR
• TRAPR: Trap Conflict Reset
• IOPUWR: Illegal Opcode Reset
• UWR: Uninitialized W Register Reset
The RCON register also has other bits associated with
the Watchdog Timer (WDT) and device power-saving
states. The function of these bits is discussed in other
sections of this manual.
Note:
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
A simplified block diagram of the Reset module is
shown in Figure 7-1.
FIGURE 7-1:
RESET SYSTEM BLOCK DIAGRAM
RESET
Instruction
Glitch Filter
MCLR
WDT
Module
Sleep or Idle
POR
BOR
VDD Rise
Detect
SYSRST
VDD
BOREN<1:0>
0
00
01
10
Brown-out
Reset
SBOREN
(RCON<13>)
SLEEP
Enable Voltage Regulator
(PIC24FV32KA3XX only)
11
1
Configuration Mismatch
Trap Conflict
Illegal Opcode
Uninitialized W Register
2011-2013 Microchip Technology Inc.
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PIC24FV32KA304 FAMILY
REGISTER 7-1:
R/W-0, HS R/W-0, HS
TRAPR IOPUWR
bit 15
RCON: RESET CONTROL REGISTER(1)
R/W-0
R/W-0
U-0
—
R/C-0, HS
DPSLP
R/W-0
CM
R/W-0
SBOREN
RETEN(3)
PMSLP
bit 8
R/W-0, HS R/W-0, HS
EXTR SWR
bit 7
R/W-0, HS
SWDTEN(2)
R/W-0, HS
WDTO
R/W-0, HS
SLEEP
R/W-0, HS
IDLE
R/W-1, HS
BOR
R/W-1, HS
POR
bit 0
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
HS = Hardware Settable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
R = Readable bit
-n = Value at POR
bit 15
bit 14
TRAPR: Trap Reset Flag bit
1= A Trap Conflict Reset has occurred
0= A Trap Conflict Reset has not occurred
IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit
1= An illegal opcode detection, an illegal address mode or Uninitialized W register used as an Address
Pointer caused a Reset
0= An illegal opcode or Uninitialized W Reset has not occurred
bit 13
bit 12
SBOREN: Software Enable/Disable of BOR bit
1= BOR is turned on in software
0= BOR is turned off in software
RETEN: Retention Sleep Mode control bit(3)
1= Regulated voltage supply provided solely by the Retention Regulator (RETEN) during Sleep
0= Regulated voltage supply provided by the main Voltage Regulator (VREG) during Sleep
bit 11
bit 10
Unimplemented: Read as ‘0’
DPSLP: Deep Sleep Mode Flag bit
1= Deep Sleep has occurred
0= Deep Sleep has not occurred
bit 9
bit 8
CM: Configuration Word Mismatch Reset Flag bit
1= A Configuration Word Mismatch Reset has occurred
0= A Configuration Word Mismatch Reset has not occurred
PMSLP: Program Memory Power During Sleep bit
1= Program memory bias voltage remains powered during Sleep
0= Program memory bias voltage is powered down during Sleep and the Voltage Regulator enters
Standby mode
EXTR: External Reset (MCLR) Pin bit
bit 7
bit 6
1= A Master Clear (pin) Reset has occurred
0= A Master Clear (pin) Reset has not occurred
SWR: Software Reset (Instruction) Flag bit
1= A RESETinstruction has been executed
0= A RESETinstruction has not been executed
Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTENx Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled regardless of the
SWDTEN bit setting.
3: This is implemented on PIC24FV32KA3XX parts only; not used on PIC24F32KA3XX devices.
DS39995D-page 70
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
REGISTER 7-1:
RCON: RESET CONTROL REGISTER(1) (CONTINUED)
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SWDTEN: Software Enable/Disable of WDT bit(2)
1= WDT is enabled
0= WDT is disabled
WDTO: Watchdog Timer Time-out Flag bit
1= WDT time-out has occurred
0= WDT time-out has not occurred
SLEEP: Wake-up from Sleep Flag bit
1= Device has been in Sleep mode
0= Device has not been in Sleep mode
IDLE: Wake-up from Idle Flag bit
1= Device has been in Idle mode
0= Device has not been in Idle mode
BOR: Brown-out Reset Flag bit
1= A Brown-out Reset has occurred (the BOR is also set after a POR)
0= A Brown-out Reset has not occurred
POR: Power-on Reset Flag bit
1= A Power-up Reset has occurred
0= A Power-up Reset has not occurred
Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTENx Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled regardless of the
SWDTEN bit setting.
3: This is implemented on PIC24FV32KA3XX parts only; not used on PIC24F32KA3XX devices.
TABLE 7-1:
RESET FLAG BIT OPERATION
Setting Event
Flag Bit
Clearing Event
TRAPR (RCON<15>)
IOPUWR (RCON<14>)
CM (RCON<9>)
Trap Conflict Event
POR
Illegal Opcode or Uninitialized W Register Access
Configuration Mismatch Reset
MCLR Reset
POR
POR
EXTR (RCON<7>)
SWR (RCON<6>)
WDTO (RCON<4>)
SLEEP (RCON<3>)
IDLE (RCON<2>)
BOR (RCON<1>)
POR (RCON<0>)
DPSLP (RCON<10>)
POR
RESETInstruction
POR
WDT Time-out
PWRSAVInstruction, POR
PWRSAV#SLEEPInstruction
PWRSAV#IDLEInstruction
POR, BOR
POR
POR
—
POR
—
PWRSAV#SLEEPInstruction with DSEN (DSCON<15>) Set
POR
Note: All Reset flag bits may be set or cleared by the user software.
2011-2013 Microchip Technology Inc.
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7.1
Clock Source Selection at Reset
7.2
Device Reset Times
If clock switching is enabled, the system clock source at
device Reset is chosen, as shown in Table 7-2. If clock
switching is disabled, the system clock source is always
selected according to the Oscillator Configuration bits.
For more information, see Section 9.0 “Oscillator
Configuration”.
The Reset times for various types of device Reset are
summarized in Table 7-3. Note that the System Reset
Signal, SYSRST, is released after the POR and PWRT
delay times expire.
The time at which the device actually begins to execute
code will also depend on the system oscillator delays,
which include the Oscillator Start-up Timer (OST) and
the PLL lock time. The OST and PLL lock times occur
in parallel with the applicable SYSRST delay times.
TABLE 7-2:
OSCILLATOR SELECTION vs.
TYPE OF RESET (CLOCK
SWITCHING ENABLED)
The FSCM delay determines the time at which the
FSCM begins to monitor the system clock source after
the SYSRST signal is released.
Reset Type
Clock Source Determinant
POR
BOR
FNOSCx Configuration bits
(FNOSC<10:8>)
MCLR
WDTO
SWR
COSCx Control bits
(OSCCON<14:12>)
TABLE 7-3:
Reset Type
POR(6)
DELAY TIMES FOR VARIOUS DEVICE RESETS
System Clock
Delay
Clock Source
SYSRST Delay
Notes
EC
TPOR + TPWRT
TPOR + TPWRT
TPOR + TPWRT
TPOR + TPWRT
TPOR + TPWRT
TPOR+ TPWRT
TPOR + TPWRT
TPWRT
—
1, 2
FRC, FRCDIV
LPRC
TFRC
TLPRC
TLOCK
1, 2, 3
1, 2, 3
1, 2, 4
ECPLL
FRCPLL
TFRC + TLOCK 1, 2, 3, 4
TOST 1, 2, 5
TOST + TLOCK 1, 2, 4, 5
XT, HS, SOSC
XTPLL, HSPLL
EC
BOR
—
2
FRC, FRCDIV
LPRC
TPWRT
TFRC
TLPRC
TLOCK
2, 3
2, 3
2, 4
TPWRT
ECPLL
TPWRT
FRCPLL
TPWRT
TFRC + TLOCK 2, 3, 4
TOST 2, 5
TFRC + TLOCK 2, 3, 4
None
XT, HS, SOSC
XTPLL, HSPLL
Any Clock
TPWRT
TPWRT
All Others
—
—
Note 1: TPOR = Power-on Reset delay.
2: TPWRT = 64 ms nominal if the Power-up Timer (PWRT) is enabled; otherwise, it is zero.
3: TFRC and TLPRC = RC oscillator start-up times.
4: TLOCK = PLL lock time.
5: TOST = Oscillator Start-up Timer (OST). A 10-bit counter waits 1024 oscillator periods before releasing the
oscillator clock to the system.
6: If Two-Speed Start-up is enabled, regardless of the primary oscillator selected, the device starts with
FRC, and in such cases, FRC start-up time is valid.
Note: For detailed operating frequency and timing specifications, see Section 29.0 “Electrical Characteristics”.
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PIC24FV32KA304 FAMILY
7.2.1
POR AND LONG OSCILLATOR
START-UP TIMES
7.5
Brown-out Reset (BOR)
The PIC24FV32KA304 family devices implement a
BOR circuit, which provides the user several
configuration and power-saving options. The BOR is
controlled by the BORV<1:0> and BOREN<1:0>
Configuration bits (FPOR<6:5,1:0>). There are a total
of four BOR configurations, which are provided in
Table 7-3.
The oscillator start-up circuitry and its associated delay
timers are not linked to the device Reset delays that
occur at power-up. Some crystal circuits (especially
low-frequency crystals) will have a relatively long
start-up time. Therefore, one or more of the following
conditions is possible after SYSRST is released:
• The oscillator circuit has not begun to oscillate.
The BOR threshold is set by the BORV<1:0> bits. If
BOR is enabled (any values of BOREN<1:0>, except
‘00’), any drop of VDD below the set threshold point will
reset the device. The chip will remain in BOR until VDD
rises above the threshold.
• The Oscillator Start-up Timer (OST) has not
expired (if a crystal oscillator is used).
• The PLL has not achieved a lock (if PLL is used).
The device will not begin to execute code until a valid
clock source has been released to the system.
Therefore, the oscillator and PLL start-up delays must
be considered when the Reset delay time must be
known.
If the Power-up Timer is enabled, it will be invoked after
VDD rises above the threshold. Then, it will keep the chip
in Reset for an additional time delay, TPWRT, if VDD
drops below the threshold while the Power-up Timer is
running. The chip goes back into a BOR and the
Power-up Timer will be initialized. Once VDD rises above
the threshold, the Power-up Timer will execute the
additional time delay.
7.2.2
FAIL-SAFE CLOCK MONITOR
(FSCM) AND DEVICE RESETS
If the FSCM is enabled, it will begin to monitor the
system clock source when SYSRST is released. If a
valid clock source is not available at this time, the
device will automatically switch to the FRC oscillator
and the user can switch to the desired crystal oscillator
in the Trap Service Routine (TSR).
BOR and the Power-up Timer (PWRT) are indepen-
dently configured. Enabling the Brown-out Reset does
not automatically enable the PWRT.
7.5.1
SOFTWARE ENABLED BOR
When BOREN<1:0> = 01, the BOR can be enabled or
disabled by the user in software. This is done with the
control bit, SBOREN (RCON<13>). Setting SBOREN
enables the BOR to function as previously described.
Clearing the SBOREN disables the BOR entirely. The
SBOREN bit operates only in this mode; otherwise, it is
read as ‘0’.
7.3
Special Function Register Reset
States
Most of the Special Function Registers (SFRs)
associated with the PIC24F CPU and peripherals are
reset to a particular value at a device Reset. The SFRs
are grouped by their peripheral or CPU function and their
Reset values are specified in each section of this manual.
Placing BOR under software control gives the user the
additional flexibility of tailoring the application to its
environment without having to reprogram the device to
change the BOR configuration. It also allows the user
to tailor the incremental current that the BOR
consumes. While the BOR current is typically very
small, it may have some impact in low-power
applications.
The Reset value for each SFR does not depend on the
type of Reset with the exception of four registers. The
Reset value for the Reset Control register, RCON, will
depend on the type of device Reset. The Reset value for
the Oscillator Control register, OSCCON, will depend on
the type of Reset and the programmed values of the
FNOSCx bits in the Flash Configuration Word
(FOSCSEL<2:0>); see Table 7-2. The RCFGCAL and
NVMCON registers are only affected by a POR.
Note:
Even when the BOR is under software con-
trol, the Brown-out Reset voltage level is
still set by the BORV<1:0> Configuration
bits; it cannot be changed in software.
7.4
Deep Sleep BOR (DSBOR)
Deep Sleep BOR is a very low-power BOR circuitry,
used when the device is in Deep Sleep mode. Due to
low current consumption, accuracy may vary.
The DSBOR trip point is around 2.0V. DSBOR is
enabled by configuring DSLPBOR (FDS<6>) = 1.
DSLPBOR will re-arm the POR to ensure the device will
reset if VDD drops below the POR threshold.
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7.5.2
DETECTING BOR
7.5.3
DISABLING BOR IN SLEEP MODE
When BOR is enabled, the BOR bit (RCON<1>) is
always reset to ‘1’ on any BOR or POR event. This
makes it difficult to determine if a BOR event has
occurred just by reading the state of BOR alone. A
more reliable method is to simultaneously check the
state of both POR and BOR. This assumes that the
POR and BOR bits are reset to ‘0’ in the software
immediately after any POR event. If the BOR bit is ‘1’
while POR is ‘0’, it can be reliably assumed that a BOR
event has occurred.
When BOREN<1:0> = 10, BOR remains under
hardware control and operates as previously
described. However, whenever the device enters Sleep
mode, BOR is automatically disabled. When the device
returns to any other operating mode, BOR is
automatically re-enabled.
This mode allows for applications to recover from
brown-out situations, while actively executing code
when the device requires BOR protection the most. At
the same time, it saves additional power in Sleep mode
by eliminating the small incremental BOR current.
Note:
Even when the device exits from Deep
Sleep mode, both the POR and BOR bits
are set.
Note:
BOR levels differ depending on device type;
PIC24FV32KA3XX devices are at different
levels than those of PIC24F32KA3XX
devices. See Section 29.0 “Electrical
Characteristics” for BOR voltage levels.
DS39995D-page 74
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PIC24FV32KA304 FAMILY
8.1.1
ALTERNATE INTERRUPT VECTOR
TABLE (AIVT)
8.0
INTERRUPT CONTROLLER
Note:
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive refer-
ence source. For more information on the
Interrupt Controller, refer to the “PIC24F
Family Reference Manual”, Section 8.
“Interrupts” (DS39707).
The Alternate Interrupt Vector Table (AIVT) is located
after the IVT, as shown in Figure 8-1. Access to the
AIVT is provided by the ALTIVT control bit
(INTCON2<15>). If the ALTIVT bit is set, all interrupt
and exception processes will use the alternate vectors
instead of the default vectors. The alternate vectors are
organized in the same manner as the default vectors.
The PIC24F interrupt controller reduces the numerous
peripheral interrupt request signals to a single interrupt
request signal to the CPU. It has the following features:
The AIVT supports emulation and debugging efforts by
providing a means to switch between an application
and a support environment without requiring the inter-
rupt vectors to be reprogrammed. This feature also
enables switching between applications for evaluation
of different software algorithms at run time. If the AIVT
is not needed, the AIVT should be programmed with
the same addresses used in the IVT.
• Up to Eight Processor Exceptions and
Software Traps
• Seven User-Selectable Priority Levels
• Interrupt Vector Table (IVT) with up to 118 Vectors
• Unique Vector for each Interrupt or Exception
Source
• Fixed Priority within a Specified User Priority Level
• Alternate Interrupt Vector Table (AIVT) for Debug
Support
8.2
Reset Sequence
A device Reset is not a true exception, because the
interrupt controller is not involved in the Reset process.
The PIC24F devices clear their registers in response to
a Reset, which forces the Program Counter (PC) to
zero. The microcontroller then begins program
execution at location, 000000h. The user programs a
GOTOinstruction at the Reset address, which redirects
the program execution to the appropriate start-up
routine.
• Fixed Interrupt Entry and Return Latencies
8.1
Interrupt Vector Table (IVT)
The IVT is shown in Figure 8-1. The IVT resides in the
program memory, starting at location, 000004h. The IVT
contains 126 vectors, consisting of eight non-maskable
trap vectors, plus up to 118 sources of interrupt. In
general, each interrupt source has its own vector. Each
interrupt vector contains a 24-bit wide address. The
value programmed into each interrupt vector location is
the starting address of the associated Interrupt Service
Routine (ISR).
Note:
Any unimplemented or unused vector
locations in the IVT and AIVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESETinstruction.
Interrupt vectors are prioritized in terms of their natural
priority; this is linked to their position in the vector table.
All other things being equal, lower addresses have a
higher natural priority. For example, the interrupt
associated with Vector 0 will take priority over interrupts
at any other vector address.
PIC24FV32KA304 family devices implement
non-maskable traps and unique interrupts; these are
summarized in Table 8-1 and Table 8-2.
2011-2013 Microchip Technology Inc.
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PIC24FV32KA304 FAMILY
FIGURE 8-1:
PIC24F INTERRUPT VECTOR TABLE
Reset – GOTOInstruction
Reset – GOTOAddress
Reserved
000000h
000002h
000004h
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved
Reserved
Reserved
Interrupt Vector 0
Interrupt Vector 1
—
000014h
—
—
Interrupt Vector 52
Interrupt Vector 53
Interrupt Vector 54
—
00007Ch
00007Eh
000080h
(1)
Interrupt Vector Table (IVT)
—
—
Interrupt Vector 116
Interrupt Vector 117
Reserved
0000FCh
0000FEh
000100h
000102h
Reserved
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved
Reserved
Reserved
Interrupt Vector 0
Interrupt Vector 1
—
000114h
—
—
(1)
Alternate Interrupt Vector Table (AIVT)
Interrupt Vector 52
Interrupt Vector 53
Interrupt Vector 54
—
00017Ch
00017Eh
000180h
—
—
Interrupt Vector 116
Interrupt Vector 117
Start of Code
0001FEh
000200h
Note 1: See Table 8-2 for the interrupt vector list.
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PIC24FV32KA304 FAMILY
TABLE 8-1:
TRAP VECTOR DETAILS
IVT Address
Vector Number
AIVT Address
Trap Source
0
1
2
3
4
5
6
7
000004h
000006h
000008h
00000Ah
00000Ch
00000Eh
000010h
000012h
000104h
000106h
000108h
00010Ah
00010Ch
00010Eh
000110h
000112h
Reserved
Oscillator Failure
Address Error
Stack Error
Math Error
Reserved
Reserved
Reserved
TABLE 8-2:
IMPLEMENTED INTERRUPT VECTORS
Interrupt Bit Locations
AIVT
Address
Interrupt Source
Vector Number IVT Address
Flag
Enable
Priority
ADC1 Conversion Done
Comparator Event
CRC Generator
CTMU
13
18
67
77
0
00002Eh
000038h
00009Ah
0000AEh
000014h
00003Ch
00004Eh
000036h
000034h
000078h
000076h
000016h
00001Eh
00005Eh
00003Ah
0000A4h
000032h
000018h
000020h
000046h
000090h
000026h
000028h
000054h
000056h
00001Ah
000022h
000024h
00004Ah
00004Ch
000096h
00002Ah
00002Ch
000098h
000050h
000052h
0000B4h
00012Eh
000138h
00019Ah
0001AEh
000114h
00013Ch
00014Eh
000136h
000134h
000178h
000176h
000116h
00011Eh
00015Eh
00013Ah
0001A4h
000132h
000118h
000120h
000146h
000190h
000126h
000128h
000154h
000156h
00011Ah
000122h
000124h
00014Ah
00015Ch
000196h
00012Ah
00012Ch
000198h
000150h
000152h
0001B4h
IFS0<13>
IFS1<2>
IFS4<3>
IFS4<13>
IFS0<0>
IFS1<4>
IFS1<13>
IFS1<1>
IFS1<0>
IFS3<2>
IFS3<1>
IFS0<1>
IFS0<5>
IFS2<5>
IFS1<3>
IFS4<8>
IFS0<15>
IFS0<2>
IFS0<6>
IFS1<9>
IFS3<14>
IFS0<9>
IFS0<10>
IFS2<0>
IFS2<1>
IFS0<3>
IFS0<7>
IFS0<8>
IFS1<11>
IFS1<12>
IFS4<1>
IFS0<11>
IFS0<12>
IFS4<2>
IFS1<14>
IFS1<15>
IFS5<0>
IEC0<13>
IEC1<2>
IEC4<3>
IEC4<13>
IEC0<0>
IEC1<4>
IEC1<13>
IEC1<1>
IEC1<0>
IEC3<2>
IEC3<1>
IEC0<1>
IEC0<5>
IEC2<5>
IEC1<3>
IEC4<8>
IEC0<15>
IEC0<2>
IEC0<6>
IEC1<9>
IEC3<14>
IEC0<9>
IEC0<10>
IEC2<2>
IEC2<1>
IEC0<3>
IEC0<7>
IEC0<8>
IEC1<11>
IEC1<12>
IEC4<1>
IEC0<11>
IEC0<12>
IEC4<2>
IEC1<14>
IEC1<15>
IEC5<0>
IPC3<6:4>
IPC4<10:8>
IPC16<14:12>
IPC19<6:4>
IPC0<2:0>
External Interrupt 0
External Interrupt 1
External Interrupt 2
I2C1 Master Event
I2C1 Slave Event
I2C2 Master Event
I2C2 Slave Event
Input Capture 1
Input Capture 2
Input Capture 3
Input Change Notification
HLVD (High/Low-Voltage Detect)
NVM – NVM Write Complete
Output Compare 1
Output Compare 2
Output Compare 3
Real-Time Clock/Calendar
SPI1 Error
20
29
17
16
50
49
1
IPC5<2:0>
IPC7<6:4>
IPC4<6:4>
IPC4<2:0>
IPC12<10:8>
IPC12<6:4>
IPC0<6:4>
5
IPC1<6:4>
37
19
72
15
2
IPC9<6:4>
IPC4<14:12>
IPC17<2:0>
IPC3<14:12>
IPC0<10:8>
IPC1<10:8>
IPC6<6:4>
6
25
62
9
IPC15<10:8>
IPC2<6:4>
SPI1 Event
10
32
33
3
IPC2<10:8>
IPC8<2:0>
SPI2 Error
SPI2 Event
IPC8<6:4>
Timer1
IPC0<14:12>
IPC1<14:12>
IPC2<2:0>
Timer2
7
Timer3
8
Timer4
27
28
65
11
12
66
30
31
80
IPC6<14:12>
IPC7<2:0>
Timer5
UART1 Error
IPC16<6:4>
IPC2<14:12>
IPC3<2:0>
UART1 Receiver
UART1 Transmitter
UART2 Error
IPC16<10:8>
IPC7<10:8>
IPC7<14:12>
IPC20<2:0>
UART2 Receiver
UART2 Transmitter
Ultra Low-Power Wake-up
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The INTTREG register contains the associated
interrupt vector number and the new CPU Interrupt
Priority Level, which are latched into the Vector
Number (VECNUM<6:0>) and the Interrupt Level
(ILR<3:0>) bit fields in the INTTREG register. The new
Interrupt Priority Level is the priority of the pending
interrupt.
8.3
Interrupt Control and Status
Registers
The PIC24FV32KA304 family of devices implements a
total of 23 registers for the interrupt controller:
• INTCON1
• INTCON2
The interrupt sources are assigned to the IFSx, IECx
and IPCx registers in the same sequence listed in
Table 8-2. For example, the INT0 (External Interrupt 0)
is depicted as having a vector number and a natural
order priority of 0. The INT0IF status bit is found in
IFS0<0>, the INT0IE enable bit in IEC0<0> and the
INT0IP<2:0> priority bits are in the first position of IPC0
(IPC0<2:0>).
• IFS0, IFS1, IFS3 and IFS4
• IEC0, IEC1, IEC3 and IEC4
• IPC0 through IPC5, IPC7 and IPC15 through
IPC19
• INTTREG
Global Interrupt Enable (GIE) control functions are
controlled from INTCON1 and INTCON2. INTCON1
contains the Interrupt Nesting Disable (NSTDIS) bit, as
well as the control and status flags for the processor
trap sources. The INTCON2 register controls the
external interrupt request signal behavior and the use
of the AIVT.
Although they are not specifically part of the interrupt
control hardware, two of the CPU Control registers con-
tain bits that control interrupt functionality. The ALU
STATUS Register (SR) contains the IPL<2:0> bits
(SR<7:5>). These indicate the current CPU Interrupt
Priority Level. The user may change the current CPU
Interrupt Priority Level by writing to the IPLx bits.
The IFSx registers maintain all of the interrupt request
flags. Each source of interrupt has a status bit, which is
set by the respective peripherals, or external signal,
and is cleared via software.
The CORCON register contains the IPL3 bit, which
together with IPL<2:0>, also indicates the current CPU
Interrupt Priority Level. IPL3 is a read-only bit so that the
trap events cannot be masked by the user’s software.
The IECx registers maintain all of the interrupt enable
bits. These control bits are used to individually enable
interrupts from the peripherals or external signals.
All Interrupt registers are described in Register 8-1
through Register 8-33, in the following sections.
The IPCx registers are used to set the Interrupt Priority
Level (IPL) for each source of interrupt. Each user
interrupt source can be assigned to one of eight priority
levels.
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REGISTER 8-1:
SR: ALU STATUS REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R-0, HSC
DC(1)
bit 15
bit 8
R/W-0, HSC R/W-0, HSC R/W-0, HSC
IPL2(2,3) IPL1(2,3) IPL0(2,3)
bit 7
R-0, HSC
RA(1)
R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC
N(1) OV(1) Z(1) C(1)
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-9
bit 7-5
Unimplemented: Read as ‘0’
IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3)
111= CPU Interrupt Priority Level is 7 (15); user interrupts are disabled
110= CPU Interrupt Priority Level is 6 (14)
101= CPU Interrupt Priority Level is 5 (13)
100= CPU Interrupt Priority Level is 4 (12)
011= CPU Interrupt Priority Level is 3 (11)
010= CPU Interrupt Priority Level is 2 (10)
001= CPU Interrupt Priority Level is 1 (9)
000= CPU Interrupt Priority Level is 0 (8)
Note 1: See Register 3-1 for the description of these bits, which are not dedicated to interrupt control functions.
2: The IPL<2:0> bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the Interrupt Priority Level if IPL3 = 1.
3: The IPLx Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
Note:
Bit 8 and bits 4 through 0 are described in Section 3.0 “CPU”.
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REGISTER 8-2:
CORCON: CPU CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
R/C-0, HSC
IPL3(2)
R/W-0
PSV(1)
U-0
—
U-0
—
bit 7
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
HSC = Hardware Settable/Clearable bit
U = Unimplemented bit, read as ‘0’
R = Readable bit
-n = Value at POR
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-4
bit 3
Unimplemented: Read as ‘0’
IPL3: CPU Interrupt Priority Level Status bit(2)
1= CPU Interrupt Priority Level is greater than 7
0= CPU Interrupt Priority Level is 7 or less
bit 1-0
Unimplemented: Read as ‘0’
Note 1: See Register 3-2 for the description of this bit, which is not dedicated to interrupt control functions.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
Note:
Bit 2 is described in Section 3.0 “CPU”.
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REGISTER 8-3:
INTCON1: INTERRUPT CONTROL REGISTER 1
R/W-0
NSTDIS
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 8
bit 0
U-0
—
U-0
—
U-0
—
R/W-0, HS
MATHERR
R/W-0, HS
ADDRERR
R/W-0, HS
STKERR
R/W-0, HS
OSCFAIL
U-0
—
bit 7
Legend:
HS = Hardware Settable bit
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 15
NSTDIS: Interrupt Nesting Disable bit
1= Interrupt nesting is disabled
0= Interrupt nesting is enabled
bit 14-5
bit 4
Unimplemented: Read as ‘0’
MATHERR: Arithmetic Error Trap Status bit
1= Overflow trap has occurred
0= Overflow trap has not occurred
bit 3
bit 2
bit 1
bit 0
ADDRERR: Address Error Trap Status bit
1= Address error trap has occurred
0= Address error trap has not occurred
STKERR: Stack Error Trap Status bit
1= Stack error trap has occurred
0= Stack error trap has not occurred
OSCFAIL: Oscillator Failure Trap Status bit
1= Oscillator failure trap has occurred
0= Oscillator failure trap has not occurred
Unimplemented: Read as ‘0’
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REGISTER 8-4:
INTCON2: INTERRUPT CONTROL REGISTER2
R/W-0
R-0, HSC
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
ALTIVT
DISI
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
INT2EP
INT1EP
INT0EP
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
ALTIVT: Enable Alternate Interrupt Vector Table bit
1= Uses Alternate Interrupt Vector Table (AIVT)
0= Uses standard (default) Interrupt Vector Table (IVT)
DISI: DISIInstruction Status bit
1= DISIinstruction is active
0= DISIinstruction is not active
bit 13-3
bit 2
Unimplemented: Read as ‘0’
INT2EP: External Interrupt 2 Edge Detect Polarity Select bit
1= Interrupt is on the negative edge
0= Interrupt is on the positive edge
bit 1
bit 0
INT1EP: External Interrupt 1 Edge Detect Polarity Select bit
1= Interrupt is on the negative edge
0= Interrupt is on the positive edge
INT0EP: External Interrupt 0 Edge Detect Polarity Select bit
1= Interrupt is on the negative edge
0= Interrupt is on the positive edge
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REGISTER 8-5:
IFS0: INTERRUPT FLAG STATUS REGISTER 0
R/W-0, HS
NVMIF
U-0
—
R/W-0, HS
AD1IF
R/W-0, HS
U1TXIF
R/W-0, HS
U1RXIF
R/W-0, HS
SPI1IF
R/W-0, HS
SPF1IF
R/W-0, HS
T3IF
bit 15
bit 8
R/W-0, HS
T2IF
R/W-0, HS
OC2IF
R/W-0, HS
IC2IF
U-0
—
R/W-0, HS
T1IF
R/W-0, HS
OC1IF
R/W-0, HS
IC1IF
R/W-0, HS
INT0IF
bit 7
bit 0
Legend:
HS = Hardware Settable bit
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 15
NVMIF: NVM Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 14
bit 13
Unimplemented: Read as ‘0’
AD1IF: A/D Conversion Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 12
bit 11
bit 10
bit 9
U1TXIF: UART1 Transmitter Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
U1RXIF: UART1 Receiver Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
SPI1IF: SPI1 Event Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
SPF1IF: SPI1 Fault Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 8
T3IF: Timer3 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 7
T2IF: Timer2 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 6
OC2IF: Output Compare Channel 2 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
IC2IF: Input Capture Channel 2 Interrupt Flag Status bit
1= Interrupt request has occurred
bit 5
0= Interrupt request has not occurred
Unimplemented: Read as ‘0’
bit 4
bit 3
T1IF: Timer1 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
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REGISTER 8-5:
IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED)
bit 2
bit 1
bit 0
OC1IF: Output Compare Channel 1 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
IC1IF: Input Capture Channel 1 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
INT0IF: External Interrupt 0 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
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REGISTER 8-6:
IFS1: INTERRUPT FLAG STATUS REGISTER 1
R/W-0, HS
U2TXIF
bit 15
R/W-0, HS
R/W-0, HS
INT2IF
R/W-0, HS
T5IF
R/W-0, HS
T4IF
U-0
—
R/W-0, HS
OC3IF
U-0
—
U2RXIF
bit 8
U-0
—
U-0
—
U-0
—
R/W-0, HS
INT1IF
R/W-0, HS
CNIF
R/W-0, HS
CMIF
R/W-0
R/W-0
MI2C1IF
SI2C1IF
bit 7
bit 0
Legend:
HS = Hardware Settable bit
W = Writable bit
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
‘1’ = Bit is set
bit 15
bit 14
bit 13
bit 12
U2TXIF: UART2 Transmitter Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
U2RXIF: UART2 Receiver Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
INT2IF: External Interrupt 2 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
T5IF: Timer5 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
T4IF: Timer4 Interrupt Flag Status bit
1= Interrupt request has occurred
bit 11
0= Interrupt request has not occurred
Unimplemented: Read as ‘0’
bit 10
bit 9
OC3IF: Output Compare Channel 3 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
Unimplemented: Read as ‘0’
bit 8-5
bit 4
INT1IF: External Interrupt 1 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 3
bit 2
bit 1
bit 0
CNIF: Input Change Notification Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
CMIF: Comparator Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
MI2C1IF: Master I2C1 Event Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
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REGISTER 8-7:
IFS2: INTERRUPT FLAG STATUS REGISTER 2
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
R/W-0, HS
IC3IF
U-0
—
U-0
—
U-0
—
R/W-0, HS
SPI2IF
R/W-0, HS
SPF2IF
bit 7
bit 0
Legend:
HS = Hardware Settable bit
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 15-6
bit 5
Unimplemented: Read as ‘0’
IC3IF: Input Capture Channel 3 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 4-2
bit 1
Unimplemented: Read as ‘0’
SPI2IF: SPI2 Event Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 0
SPF2IF: SPI2 Fault Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
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REGISTER 8-8:
IFS3: INTERRUPT FLAG STATUS REGISTER 3
U-0
—
R/W-0, HS
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
RTCIF
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0, HS
MI2C2IF
R/W-0, HS
SI2C2IF
U-0
—
bit 7
Legend:
HS = Hardware Settable bit
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 15
bit 14
Unimplemented: Read as ‘0’
RTCIF: Real-Time Clock and Calendar Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 13-3
bit 2
Unimplemented: Read as ‘0’
MI2C2IF: Master I2C2 Event Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 1
bit 0
SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
Unimplemented: Read as ‘0’
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REGISTER 8-9:
IFS4: INTERRUPT FLAG STATUS REGISTER 4
U-0
—
U-0
—
R/W-0, HS
CTMUIF
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0, HS
HLVDIF
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0, HS
CRCIF
R/W-0, HS
U2ERIF
R/W-0, HS
U1ERIF
U-0
—
bit 7
bit 0
Legend:
HS = Hardware Settable bit
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 15-14
bit 13
Unimplemented: Read as ‘0’
CTMUIF: CTMU Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 12-9
bit 8
Unimplemented: Read as ‘0’
HLVDIF: High/Low-Voltage Detect Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 7-4
bit 3
Unimplemented: Read as ‘0’
CRCIF: CRC Generator Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 2
bit 1
bit 0
U2ERIF: UART2 Error Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
U1ERIF: UART1 Error Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
Unimplemented: Read as ‘0’
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REGISTER 8-10: IFS5: INTERRUPT FLAG STATUS REGISTER 5
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0, HS
ULPWUIF
bit 7
bit 0
Legend:
HS = Hardware Settable bit
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 15-1
bit 0
Unimplemented: Read as ‘0’
ULPWUIF: Ultra Low-Power Wake-up Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
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REGISTER 8-11: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0
R/W-0
U-0
—
R/W-0
AD1IE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T3IE
NVMIE
U1TXIE
U1RXIE
SPI1IE
SPF1IE
bit 15
bit 8
R/W-0
T2IE
R/W-0
OC2IE
R/W-0
IC2IE
U-0
—
R/W-0
T1IE
R/W-0
OC1IE
R/W-0
IC1IE
R/W-0
INT0IE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
NVMIE: NVM Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 14
bit 13
Unimplemented: Read as ‘0’
AD1IE: A/D Conversion Complete Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 12
bit 11
bit 10
bit 9
U1TXIE: UART1 Transmitter Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
U1RXIE: UART1 Receiver Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
SPI1IE: SPI1 Transfer Complete Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
SPF1IE: SPI1 Fault Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 8
T3IE: Timer3 Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 7
T2IE: Timer2 Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 6
bit 5
OC2IE: Output Compare Channel 2 Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
IC2IE: Input Capture Channel 2 Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 4
bit 3
Unimplemented: Read as ‘0’
T1IE: Timer1 Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 2
OC1IE: Output Compare Channel 1 Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
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REGISTER 8-11: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0
bit 1
IC1IE: Input Capture Channel 1 Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 0
INT0IE: External Interrupt 0 Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
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REGISTER 8-12: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
T5IE
R/W-0
T4IE
U-0
—
R/W-0
OC3IE
U-0
—
U2TXIE
U2RXIE
INT2IE
bit 15
bit 8
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
CNIE
R/W-0
CMIE
R/W-0
R/W-0
INT1IE
MI2C1IE
SI2C1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
U2TXIE: UART2 Transmitter Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
U2RXIE: UART2 Receiver Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
INT2IE: External Interrupt 2 Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
T5IE: Timer5 Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
T4IE: Timer4 Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 10
bit 9
Unimplemented: Read as ‘0’
OC3IE: Output Compare 3 Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 8-5
bit 4
Unimplemented: Read as ‘0’
INT1IE: External Interrupt 1 Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 3
bit 2
bit 1
bit 0
CNIE: Input Change Notification Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
CMIE: Comparator Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
MI2C1IE: Master I2C1 Event Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
SI2C1IE: Slave I2C1 Event Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
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REGISTER 8-13: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
R/W-0
IC3IE
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
SPI2IE
SPF2IE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5
Unimplemented: Read as ‘0’
IC3IE: Input Capture Channel 3 Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 4-2
bit 1
Unimplemented: Read as ‘0’
SPI2IE: SPI2 Event Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 0
SPF2IE: SPI2 Fault Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
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REGISTER 8-14: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3
U-0
—
R/W-0
RTCIE
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
U-0
—
MI2C2IE
SI2C2IE
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
Unimplemented: Read as ‘0’
RTCIE: Real-Time Clock and Calendar Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 13-3
bit 2
Unimplemented: Read as ‘0’
MI2C2IE: Master I2C2 Event Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 1
bit 0
SI2C2IE: Slave I2C2 Event Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
Unimplemented: Read as ‘0’
DS39995D-page 94
2011-2013 Microchip Technology Inc.
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REGISTER 8-15: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
CTMUIE
HLVDIE
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
U-0
—
CRCIE
U2ERIE
U1ERIE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13
Unimplemented: Read as ‘0’
CTMUIE: CTMU Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 12-9
bit 8
Unimplemented: Read as ‘0’
HLVDIE: High/Low-Voltage Detect Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 7-4
bit 3
Unimplemented: Read as ‘0’
CRCIE: CRC Generator Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 2
bit 1
bit 0
U2ERIE: UART2 Error Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
U1ERIE: UART1 Error Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
Unimplemented: Read as ‘0’
2011-2013 Microchip Technology Inc.
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REGISTER 8-16: IEC5: INTERRUPT ENABLE CONTROL REGISTER 5
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
ULPWUIE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-1
bit 0
Unimplemented: Read as ‘0’
ULPWUIE: Ultra Low-Power Wake-up Interrupt Enable Bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
DS39995D-page 96
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REGISTER 8-17: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0
U-0
—
R/W-1
T1IP2
R/W-0
T1IP1
R/W-0
T1IP0
U-0
—
R/W-1
R/W-0
R/W-0
OC1IP2
OC1IP1
OC1IP0
bit 15
bit 8
U-0
—
R/W-1
IC1IP2
R/W-0
IC1IP1
R/W-0
IC1IP0
U-0
—
R/W-1
R/W-0
R/W-0
INT0IP2
INT0IP1
INT0IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
Unimplemented: Read as ‘0’
T1IP<2:0>: Timer1 Interrupt Priority bits
bit 14-12
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
INT0IP<2:0>: External Interrupt 0 Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
2011-2013 Microchip Technology Inc.
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REGISTER 8-18: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1
U-0
—
R/W-1
T2IP2
R/W-0
T2IP1
R/W-0
T2IP0
U-0
—
R/W-1
R/W-0
R/W-0
OC2IP2
OC2IP1
OC2IP0
bit 15
bit 8
U-0
—
R/W-1
IC2IP2
R/W-0
IC2IP1
R/W-0
IC2IP0
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
Unimplemented: Read as ‘0’
T2IP<2:0>: Timer2 Interrupt Priority bits
bit 14-12
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
DS39995D-page 98
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REGISTER 8-19: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
U1RXIP2
U1RXIP1
U1RXIP0
SPI1IP2
SPI1IP1
SPI1IP0
bit 15
bit 8
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
T3IP2
R/W-0
T3IP1
R/W-0
T3IP0
SPF1IP2
SPF1IP1
SPF1IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
Unimplemented: Read as ‘0’
bit 14-12
U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
SPI1IP<2:0>: SPI1 Event Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SPF1IP<2:0>: SPI1 Fault Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
T3IP<2:0>: Timer3 Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
2011-2013 Microchip Technology Inc.
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REGISTER 8-20: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
NVMIP2
NVMIP1
NVMIP0
bit 15
bit 8
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
AD1IP2
AD1IP1
AD1IP0
U1TXIP2
U1TXIP1
U1TXIP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
Unimplemented: Read as ‘0’
NVMIP<2:0>: NVM Interrupt Priority bits
bit 14-12
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 11-7
bit 6-4
Unimplemented: Read as ‘0’
AD1IP<2:0>: A/D Conversion Complete Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
DS39995D-page 100
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REGISTER 8-21: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4
U-0
—
R/W-1
CNIP2
R/W-0
CNIP1
R/W-0
CNIP0
U-0
—
R/W-1
CMIP2
R/W-0
CMIP1
R/W-0
CMIP0
bit 15
bit 8
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
MI2C1P2
MI2C1P1
MI2C1P0
SI2C1P2
SI2C1P1
SI2C1P0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
Unimplemented: Read as ‘0’
bit 14-12
CNIP<2:0>: Input Change Notification Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
CMIP<2:0>: Comparator Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
MI2C1P<2:0>: Master I2C1 Event Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
SI2C1P<2:0>: Slave I2C1 Event Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
2011-2013 Microchip Technology Inc.
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REGISTER 8-22: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
R/W-0
INT1IP2
INT1IP1
INT1IP0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-3
bit 2-0
Unimplemented: Read as ‘0’
INT1IP<2:0>: External Interrupt 1 Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
DS39995D-page 102
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REGISTER 8-23: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6
U-0
—
R/W-1
T4IP2
R/W-0
T4IP1
R/W-0
T4IP0
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
OC3IP2
OC3IP1
OC3IP0
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
Unimplemented: Read as ‘0’
T4IP<2:0>: Timer4 Interrupt Priority bits
bit 14-12
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 11-7
bit 6-4
Unimplemented: Read as ‘0’
OC3IP<2:0>: Output Compare Channel 3 Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
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REGISTER 8-24: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
U2TXIP2
U2TXIP1
U2TXIP0
U2RXIP2
U2RXIP1
U2RXIP0
bit 15
bit 8
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
T5IP2
R/W-0
T5IP1
R/W-0
T5IP0
INT2IP2
INT2IP1
INT2IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
Unimplemented: Read as ‘0’
bit 14-12
U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
U2RXIP<2:0>: UART2 Receiver Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
INT2IP<2:0>: External Interrupt 2 Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
T5IP<2:0>: Timer5 Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
DS39995D-page 104
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REGISTER 8-25: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
SPI2IP2
SPI2IP1
SPI2IP0
SPF2IP2
SPF2IP1
SPF2IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-7
bit 6-4
Unimplemented: Read as ‘0’
SPI2IP<2:0>: SPI2 Event Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
SPF2IP<2:0>: SPI2 Fault Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
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REGISTER 8-26: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-1
IC3IP2
R/W-0
IC3IP1
R/W-0
IC3IP0
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-7
bit 6-4
Unimplemented: Read as ‘0’
IC3IP<2:0>: Input Capture Channel 3 Event Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
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REGISTER 8-27: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
R/W-0
MI2C2IP2
MI2C2IP1
MI2C2IP0
bit 15
bit 8
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
SI2C2IP2
SI2C2IP1
SI2C2IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-11
bit 10-8
Unimplemented: Read as ‘0’
MI2C2IP <2:0>: Master I2C2 Event Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SI2C2IP<2:0>: Slave I2C2 Event Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
2011-2013 Microchip Technology Inc.
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REGISTER 8-28: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
R/W-0
RTCIP2
RTCIP1
RTCIP0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-11
bit 10-8
Unimplemented: Read as ‘0’
RTCIP<2:0>: Real-Time Clock and Calendar Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 7-0
Unimplemented: Read as ‘0’
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REGISTER 8-29: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
CRCIP2
CRCIP1
CRCIP0
U2ERIP2
U2ERIP1
U2ERIP0
bit 15
bit 8
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U1ERIP2
U1ERIP1
U1ERIP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
Unimplemented: Read as ‘0’
bit 14-12
CRCIP<2:0>: CRC Generator Error Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
U2ERIP<2:0>: UART2 Error Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
U1ERIP<2:0>: UART1 Error Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
2011-2013 Microchip Technology Inc.
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REGISTER 8-30: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
R/W-0
HLVDIP2
HLVDIP1
HLVDIP0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-3
bit 2-0
Unimplemented: Read as ‘0’
HLVDIP<2:0>: High/Low-Voltage Detect Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
REGISTER 8-31: IPC19: INTERRUPT PRIORITY CONTROL REGISTER 19
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
CTMUIP2
CTMUIP1
CTMUIP0
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-7
bit 6-4
Unimplemented: Read as ‘0’
CTMUIP<2:0>: CTMU Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
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REGISTER 8-32: IPC20: INTERRUPT PRIORITY CONTROL REGISTER 20
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
R/W-0
ULPWUIP2 ULPWUIP1 ULPWUIP0
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-3
bit 6-4
Unimplemented: Read as ‘0’
ULPWUIP<2:0>: Ultra Low-Power Wake-up Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
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REGISTER 8-33: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER
R-0
U-0
—
R/W-0
U-0
—
R-0
R-0
R-0
R-0
CPUIRQ
VHOLD
ILR3
ILR2
ILR1
ILR0
bit 15
bit 8
U-0
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
VECNUM6
VECNUM5 VECNUM4 VECNUM3
VECNUM2
VECNUM1
VECNUM0
bit 0
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
CPUIRQ: Interrupt Request from Interrupt Controller CPU bit
1= An interrupt request has occurred but has not yet been Acknowledged by the CPU (this will
happen when the CPU priority is higher than the interrupt priority)
0= No interrupt request is left unacknowledged
bit 14
bit 13
Unimplemented: Read as ‘0’
VHOLD: Vector Hold bit
Allows Vector Number Capture and Changes which Interrupt is Stored in the VECNUM bit:
1= VECNUM will contain the value of the highest priority pending interrupt, instead of the current
interrupt
0= VECNUM will contain the value of the last Acknowledged interrupt (last interrupt that has occurred
with higher priority than the CPU, even if other interrupts are pending)
bit 12
Unimplemented: Read as ‘0’
bit 11-8
ILR<3:0>: New CPU Interrupt Priority Level bits
1111= CPU Interrupt Priority Level is 15
•
•
•
0001= CPU Interrupt Priority Level is 1
0000= CPU Interrupt Priority Level is 0
bit 7
Unimplemented: Read as ‘0’
bit 6-0
VECNUM<6:0>: Vector Number of Pending Interrupt bits
0111111= Interrupt vector pending is Number 135
•
•
•
0000001= Interrupt vector pending is Number 9
0000000= Interrupt vector pending is Number 8
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8.4.3
TRAP SERVICE ROUTINE (TSR)
8.4
Interrupt Setup Procedures
A Trap Service Routine (TSR) is coded like an ISR,
except that the appropriate trap status flag in the
INTCON1 register must be cleared to avoid re-entry
into the TSR.
8.4.1
INITIALIZATION
To configure an interrupt source:
1. Set the NSTDIS control bit (INTCON1<15>) if
nested interrupts are not desired.
8.4.4
INTERRUPT DISABLE
2. Select the user-assigned priority level for the
interrupt source by writing the control bits in the
appropriate IPCx register. The priority level will
depend on the specific application and type of
interrupt source. If multiple priority levels are not
desired, the IPCx register control bits for all
enabled interrupt sources may be programmed
to the same non-zero value.
All user interrupts can be disabled using the following
procedure:
1. Push the current SR value onto the software
stack using the PUSHinstruction.
2. Force the CPU to Priority Level 7 by inclusive
ORing the value, OEh with SRL.
To enable user interrupts, the POPinstruction may be
used to restore the previous SR value.
Note:
At a device Reset, the IPCx registers are
initialized, such that all user interrupt
sources are assigned to Priority Level 4.
Only user interrupts with a priority level of 7 or less can
be disabled. Trap sources (Level 8-15) cannot be
disabled.
3. Clear the interrupt flag status bit associated with
the peripheral in the associated IFSx register.
The DISI instruction provides a convenient way to
disable interrupts of Priority Levels 1-6 for a fixed
period. Level 7 interrupt sources are not disabled by
the DISIinstruction.
4. Enable the interrupt source by setting the
interrupt enable control bit associated with the
source in the appropriate IECx register.
8.4.2
INTERRUPT SERVICE ROUTINE
The method that is used to declare an ISR (Interrupt
Service Routine) and initialize the IVT with the correct
vector address depends on the programming language
(i.e., C or assembly) and the language development
toolsuite that is used to develop the application. In
general, the user must clear the interrupt flag in the
appropriate IFSx register for the source of the interrupt
that the ISR handles. Otherwise, the ISR will be
re-entered immediately after exiting the routine. If the
ISR is coded in assembly language, it must be termi-
nated using a RETFIEinstruction to unstack the saved
PC value, SRL value and old CPU priority level.
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NOTES:
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• Software-controllable switching between various
clock sources.
9.0
OSCILLATOR
CONFIGURATION
• Software-controllable postscaler for selective
clocking of CPU for system power savings.
Note:
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive refer-
ence source. For more information on
Oscillator Configuration, refer to the
“PIC24F Family Reference Manual”,
Section 38. “Oscillator with 500 kHz
Low-Power FRC” (DS39726).
• System frequency range declaration bits for EC
mode. When using an external clock source, the
current consumption is reduced by setting the
declaration bits to the expected frequency range.
• A Fail-Safe Clock Monitor (FSCM) that detects clock
failure and permits safe application recovery or
shutdown.
A simplified diagram of the oscillator system is shown in
Figure 9-1.
The oscillator system for the PIC24FV32KA304 family
of devices has the following features:
• A total of five external and internal oscillator options
as clock sources, providing 11 different clock
modes.
• On-chip 4x Phase Locked Loop (PLL) to boost
internal operating frequency on select internal and
external oscillator sources.
FIGURE 9-1:
PIC24FV32KA304 FAMILY CLOCK DIAGRAM
Primary Oscillator
REFOCON<15:8>
XT, HS, EC
OSCO
OSCI
Reference Clock
Generator
XTPLL, HSPLL
ECPLL,FRCPLL
4 x PLL
REFO
8 MHz
4 MHz
8 MHz
FRC
Oscillator
FRCDIV
Peripherals
500 kHz
LPFRC
Oscillator
CLKDIV<10:8>
FRC
CLKO
CPU
LPRC
LPRC
Oscillator
31 kHz (nominal)
Secondary Oscillator
SOSC
SOSCO
SOSCI
CLKDIV<14:12>
SOSCEN
Enable
Oscillator
Clock Control Logic
Fail-Safe
Clock
Monitor
WDT, PWRT, DSWDT
Clock Source Option
for Other Modules
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9.1
CPU Clocking Scheme
9.2
Initial Configuration on POR
The system clock source can be provided by one of
four sources:
The oscillator source (and operating mode) that is used
at a device Power-on Reset (POR) event is selected
using Configuration bit settings. The Oscillator Configu-
ration bit settings are located in the Configuration
registers in the program memory (for more information,
see Section 26.1 “Configuration Bits”). The Primary
• Primary Oscillator (POSC) on the OSCI and OSCO
pins
• Secondary Oscillator (SOSC) on the SOSCI and
SOSCO pins
Oscillator
Configuration
bits,
POSCMD<1:0>
The PIC24FV32KA304 family devices consist of
two types of secondary oscillator:
(FOSC<1:0>), and the Initial Oscillator Select Configura-
tion bits, FNOSC<2:0> (FOSCSEL<2:0>), select the
oscillator source that is used at a POR. The FRC Primary
Oscillator with Postscaler (FRCDIV) is the default (unpro-
grammed) selection. The secondary oscillator, or one of
the internal oscillators, may be chosen by programming
these bit locations. The EC mode Frequency Range
Configuration bits, POSCFREQ<1:0> (FOSC<4:3>),
optimize power consumption when running in EC mode.
The default configuration is “frequency range is greater
than 8 MHz”.
- High-Power Secondary Oscillator
- Low-Power Secondary Oscillator
These can be selected by using the SOSCSEL
(FOSC<5>) bit.
• Fast Internal RC (FRC) Oscillator
- 8 MHz FRC Oscillator
- 500 kHz Lower Power FRC Oscillator
• Low-Power Internal RC (LPRC) Oscillator with two
modes:
- High-Power/High Accuracy mode
- Low-Power/Low Accuracy mode
The Configuration bits allow users to choose between
the various clock modes, shown in Table 9-1.
The primary oscillator and 8 MHz FRC sources have the
option of using the internal 4x PLL. The frequency of the
FRC clock source can optionally be reduced by the pro-
grammable clock divider. The selected clock source
generates the processor and peripheral clock sources.
9.2.1
CLOCK SWITCHING MODE
CONFIGURATION BITS
The FCKSMx Configuration bits (FOSC<7:6>) are
used jointly to configure device clock switching and the
FSCM. Clock switching is enabled only when FCKSM1
is programmed (‘0’). The FSCM is enabled only when
FCKSM<1:0> are both programmed (‘00’).
The processor clock source is divided by two to produce
the internal instruction cycle clock, FCY. In this
document, the instruction cycle clock is also denoted by
FOSC/2. The internal instruction cycle clock, FOSC/2, can
be provided on the OSCO I/O pin for some operating
modes of the primary oscillator.
TABLE 9-1:
CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator Mode Oscillator Source POSCMD<1:0>
FNOSC<2:0>
Notes
1, 2
8 MHz FRC Oscillator with Postscaler
(FRCDIV)
Internal
11
111
500 kHz FRC Oscillator with Postscaler
(LPFRCDIV)
Internal
11
110
1
Low-Power RC Oscillator (LPRC)
Internal
Secondary
Primary
11
00
10
101
100
011
1
1
Secondary (Timer1) Oscillator (SOSC)
Primary Oscillator (HS) with PLL Module
(HSPLL)
Primary Oscillator (EC) with PLL Module
(ECPLL)
Primary
00
011
Primary Oscillator (HS)
Primary Oscillator (XT)
Primary Oscillator (EC)
Primary
Primary
Primary
Internal
10
01
00
11
010
010
010
001
8 MHz FRC Oscillator with PLL Module
(FRCPLL)
1
1
8 MHz FRC Oscillator (FRC)
Internal
11
000
Note 1: The OSCO pin function is determined by the OSCIOFNC Configuration bit.
2: This is the default oscillator mode for an unprogrammed (erased) device.
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The Clock Divider register (Register 9-2) controls the
features associated with Doze mode, as well as the
postscaler for the FRC oscillator.
9.3
Control Registers
The operation of the oscillator is controlled by three
Special Function Registers (SFRs):
The FRC Oscillator Tune register (Register 9-3) allows
the user to fine tune the FRC oscillator over a range of
approximately ±5.25%. Each bit increment or decre-
ment changes the factory calibrated frequency of the
FRC oscillator by a fixed amount.
• OSCCON
• CLKDIV
• OSCTUN
The OSCCON register (Register 9-1) is the main
control register for the oscillator. It controls clock
source switching and allows the monitoring of clock
sources.
REGISTER 9-1:
OSCCON: OSCILLATOR CONTROL REGISTER
U-0
—
R-0, HSC
COSC2
R-0, HSC
COSC1
R-0, HSC
COSC0
U-0
—
R/W-x(1)
NOSC2
R/W-x(1)
NOSC1
R/W-x(1)
NOSC0
bit 15
bit 8
R/SO-0, HSC
CLKLOCK
bit 7
U-0
—
R-0, HSC(2)
LOCK
U-0
—
R/CO-0, HS R/W-0(3)
R/W-0
R/W-0
CF
SOSCDRV SOSCEN
OSWEN
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
HS = Hardware Settable bit
R = Readable bit
CO = Clearable Only bit
W = Writable bit
SO = Settable Only bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
COSC<2:0>: Current Oscillator Selection bits
111= 8 MHz Fast RC Oscillator with Postscaler (FRCDIV)
110= 500 kHz Low-Power Fast RC Oscillator (FRC) with Postscaler (LPFRCDIV)
101= Low-Power RC Oscillator (LPRC)
100= Secondary Oscillator (SOSC)
011= Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)
010= Primary Oscillator (XT, HS, EC)
001= 8 MHz FRC Oscillator with Postscaler and PLL module (FRCPLL)
000= 8 MHz FRC Oscillator (FRC)
bit 11
Unimplemented: Read as ‘0’
bit 10-8
NOSC<2:0>: New Oscillator Selection bits(1)
111= 8 MHz Fast RC Oscillator with Postscaler (FRCDIV)
110= 500 kHz Low-Power Fast RC Oscillator (FRC) with Postscaler (LPFRCDIV)
101= Low-Power RC Oscillator (LPRC)
100= Secondary Oscillator (SOSC)
011= Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)
010= Primary Oscillator (XT, HS, EC)
001= 8 MHz FRC Oscillator with Postscaler and PLL module (FRCPLL)
000= 8 MHz FRC Oscillator (FRC)
Note 1: Reset values for these bits are determined by the FNOSCx Configuration bits.
2: This bit also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected.
3: When SOSC is selected to run from a digital clock input, rather than an external crystal (SOSCSRC = 0),
this bit has no effect.
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REGISTER 9-1:
OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
bit 7
CLKLOCK: Clock Selection Lock Enabled bit
If FSCM is enabled (FCKSM1 = 1):
1= Clock and PLL selections are locked
0= Clock and PLL selections are not locked and may be modified by setting the OSWEN bit
If FSCM is disabled (FCKSM1 = 0):
Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.
bit 6
bit 5
Unimplemented: Read as ‘0’
LOCK: PLL Lock Status bit(2)
1= PLL module is in lock or PLL module start-up timer is satisfied
0= PLL module is out of lock, PLL start-up timer is running or PLL is disabled
bit 4
bit 3
Unimplemented: Read as ‘0’
CF: Clock Fail Detect bit
1= FSCM has detected a clock failure
0= No clock failure has been detected
bit 2
bit 1
bit 0
SOSCDRV: Secondary Oscillator Drive Strength bit(3)
1= High-power SOSC circuit is selected
0= Low/high-power select is done via the SOSCSRC Configuration bit
SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit
1= Enables the secondary oscillator
0= Disables the secondary oscillator
OSWEN: Oscillator Switch Enable bit
1= Initiates an oscillator switch to the clock source specified by the NOSC<2:0> bits
0= Oscillator switch is complete
Note 1: Reset values for these bits are determined by the FNOSCx Configuration bits.
2: This bit also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected.
3: When SOSC is selected to run from a digital clock input, rather than an external crystal (SOSCSRC = 0),
this bit has no effect.
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REGISTER 9-2:
CLKDIV: CLOCK DIVIDER REGISTER
R/W-0
ROI
R/W-0
R/W-1
R/W-1
R/W-0
DOZEN(1)
R/W-0
R/W-0
R/W-1
DOZE2
DOZE1
DOZE0
RCDIV2
RCDIV1
RCDIV0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
ROI: Recover on Interrupt bit
1= Interrupts clear the DOZEN bit, and reset the CPU and peripheral clock ratio to 1:1
0= Interrupts have no effect on the DOZEN bit
bit 14-12
DOZE<2:0>: CPU and Peripheral Clock Ratio Select bits
111= 1:128
110= 1:64
101= 1:32
100= 1:16
011= 1:8
010= 1:4
001= 1:2
000= 1:1
bit 11
DOZEN: Doze Enable bit(1)
1= DOZE<2:0> bits specify the CPU and peripheral clock ratio
0= CPU and peripheral clock ratio are set to 1:1
bit 10-8
RCDIV<2:0>: FRC Postscaler Select bits
When COSC<2:0> (OSCCON<14:12>) = 111:
111= 31.25 kHz (divide-by-256)
110= 125 kHz (divide-by-64)
101= 250 kHz (divide-by-32)
100= 500 kHz (divide-by-16)
011= 1 MHz (divide-by-8)
010= 2 MHz (divide-by-4)
001= 4 MHz (divide-by-2) (default)
000= 8 MHz (divide-by-1)
When COSC<2:0> (OSCCON<14:12>) = 110:
111= 1.95 kHz (divide-by-256)
110= 7.81 kHz (divide-by-64)
101= 15.62 kHz (divide-by-32)
100= 31.25 kHz (divide-by-16)
011= 62.5 kHz (divide-by-8)
010= 125 kHz (divide-by-4)
001= 250 kHz (divide-by-2) (default)
000= 500 kHz (divide-by-1)
bit 7-0
Unimplemented: Read as ‘0’
Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs.
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REGISTER 9-3:
OSCTUN: FRC OSCILLATOR TUNE REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
R/W-0
TUN5(1)
R/W-0
TUN4(1)
R/W-0
TUN3(1)
R/W-0
TUN2(1)
R/W-0
TUN1(1)
R/W-0
TUN0(1)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5-0
Unimplemented: Read as ‘0’
TUN<5:0>: FRC Oscillator Tuning bits(1)
011111= Maximum frequency deviation
011110
•
•
•
000001
000000= Center frequency, oscillator is running at factory calibrated frequency
111111
•
•
•
100001
100000= Minimum frequency deviation
Note 1: Increments or decrements of TUN<5:0> may not change the FRC frequency in equal steps over the FRC
tuning range and may not be monotonic.
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Once the basic sequence is completed, the system
clock hardware responds automatically, as follows:
9.4
Clock Switching Operation
With few limitations, applications are free to switch
between any of the four clock sources (POSC, SOSC,
FRC and LPRC) under software control and at any
time. To limit the possible side effects that could result
from this flexibility, PIC24F devices have a safeguard
lock built into the switching process.
1. The clock switching hardware compares the
COSCx bits with the new value of the NOSCx
bits. If they are the same, then the clock switch
is a redundant operation. In this case, the
OSWEN bit is cleared automatically and the
clock switch is aborted.
Note:
The Primary Oscillator mode has three
different submodes (XT, HS and EC),
which are determined by the POSCMDx
Configuration bits. While an application
can switch to and from Primary Oscillator
mode in software, it cannot switch
between the different primary submodes
without reprogramming the device.
2. If a valid clock switch has been initiated, the
LOCK (OSCCON<5>) and CF (OSCCON<3>)
bits are cleared.
3. The new oscillator is turned on by the hardware
if it is not currently running. If a crystal oscillator
must be turned on, the hardware will wait until
the OST expires. If the new source is using the
PLL, then the hardware waits until a PLL lock is
detected (LOCK = 1).
9.4.1
ENABLING CLOCK SWITCHING
4. The hardware waits for 10 clock cycles from the
new clock source and then performs the clock
switch.
To enable clock switching, the FCKSM1 Configuration bit
in the FOSC Configuration register must be programmed
to ‘0’. (Refer to Section 26.0 “Special Features” for
further details.) If the FCKSM1 Configuration bit is
unprogrammed (‘1’), the clock switching function and
FSCM function are disabled. This is the default setting.
5. The hardware clears the OSWEN bit to indicate a
successful clock transition. In addition, the
NOSCx bits value is transferred to the COSCx
bits.
The NOSCx control bits (OSCCON<10:8>) do not
control the clock selection when clock switching is
disabled. However, the COSCx bits (OSCCON<14:12>)
will reflect the clock source selected by the FNOSCx
Configuration bits.
6. The old clock source is turned off at this time,
with the exception of LPRC (if WDT, FSCM or
RTCC with LPRC as a clock source is enabled)
or SOSC (if SOSCEN remains enabled).
Note 1: The processor will continue to execute
code throughout the clock switching
sequence. Timing-sensitive code should
not be executed during this time.
The OSWEN control bit (OSCCON<0>) has no effect
when clock switching is disabled; it is held at ‘0’ at all
times.
2: Direct clock switches between any
Primary Oscillator mode with PLL and
FRCPLL mode are not permitted. This
applies to clock switches in either direc-
tion. In these instances, the application
must switch to FRC mode as a transition
clock source between the two PLL
modes.
9.4.2
OSCILLATOR SWITCHING
SEQUENCE
At a minimum, performing a clock switch requires this
basic sequence:
1. If
desired,
read
the
COSCx
bits
(OSCCON<14:12>) to determine the current
oscillator source.
2. Perform the unlock sequence to allow a write to
the OSCCON register high byte.
3. Write the appropriate value to the NOSCx bits
(OSCCON<10:8>) for the new oscillator source.
4. Perform the unlock sequence to allow a write to
the OSCCON register low byte.
5. Set the OSWEN bit to initiate the oscillator
switch.
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The following code sequence for a clock switch is
recommended:
9.5
Reference Clock Output
In addition to the CLKO output (FOSC/2) available in
certain oscillator modes, the device clock in the
PIC24FV32KA304 family devices can also be
configured to provide a reference clock output signal to
a port pin. This feature is available in all oscillator
configurations and allows the user to select a greater
range of clock submultiples to drive external devices in
the application.
1. Disable interrupts during the OSCCON register
unlock and write sequence.
2. Execute the unlock sequence for the OSCCON
high byte by writing 78h and 9Ah to
OSCCON<15:8>,
instructions.
in
two
back-to-back
3. Write new oscillator source to the NOSCx bits in
the instruction immediately following the unlock
sequence.
This reference clock output is controlled by the
REFOCON register (Register 9-4). Setting the ROEN
bit (REFOCON<15>) makes the clock signal available
on the REFO pin. The RODIVx bits (REFOCON<11:8>)
enable the selection of 16 different clock divider
options.
4. Execute the unlock sequence for the OSCCON
low byte by writing 46h and 57h to
OSCCON<7:0>, in two back-to-back instructions.
5. Set the OSWEN bit in the instruction immediately
following the unlock sequence.
The ROSSLP and ROSEL bits (REFOCON<13:12>)
control the availability of the reference output during
Sleep mode. The ROSEL bit determines if the oscillator
on OSC1 and OSC2, or the current system clock
source, is used for the reference clock output. The
ROSSLP bit determines if the reference source is
available on REFO when the device is in Sleep mode.
6. Continue to execute code that is not
clock-sensitive (optional).
7. Invoke an appropriate amount of software delay
(cycle counting) to allow the selected oscillator
and/or PLL to start and stabilize.
8. Check to see if OSWEN is ‘0’. If it is, the switch
was successful. If OSWEN is still set, then check
the LOCK bit to determine the cause of failure.
To use the reference clock output in Sleep mode, both
the ROSSLP and ROSEL bits must be set. The device
clock must also be configured for one of the primary
modes (EC, HS or XT); otherwise, if the ROSEL bit is
not also set, the oscillator on OSC1 and OSC2 will be
powered down when the device enters Sleep mode.
Clearing the ROSEL bit allows the reference output
frequency to change as the system clock changes
during any clock switches.
The core sequence for unlocking the OSCCON register
and initiating a clock switch is shown in Example 9-1.
EXAMPLE 9-1:
BASIC CODE SEQUENCE
FOR CLOCK SWITCHING
;Place the new oscillator selection in W0
;OSCCONH (high byte) Unlock Sequence
MOV
MOV
MOV
MOV.b
MOV.b
#OSCCONH, w1
#0x78, w2
#0x9A, w3
w2, [w1]
w3, [w1]
;Set new oscillator selection
MOV.b WREG, OSCCONH
;OSCCONL (low byte) unlock sequence
MOV
MOV
MOV
MOV.b
MOV.b
#OSCCONL, w1
#0x46, w2
#0x57, w3
w2, [w1]
w3, [w1]
;Start oscillator switch operation
BSET OSCCON,#0
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2011-2013 Microchip Technology Inc.
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REGISTER 9-4:
REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER
R/W-0
ROEN
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ROSSLP
ROSEL
RODIV3
RODIV2
RODIV1
RODIV0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
ROEN: Reference Oscillator Output Enable bit
1= Reference oscillator is enabled on REFO pin
0= Reference oscillator is disabled
bit 14
bit 13
Unimplemented: Read as ‘0’
ROSSLP: Reference Oscillator Output Stop in Sleep bit
1= Reference oscillator continues to run in Sleep
0= Reference oscillator is disabled in Sleep
bit 12
ROSEL: Reference Oscillator Source Select bit
1= Primary oscillator is used as the base clock(1)
0= System clock is used as the base clock; base clock reflects any clock switching of the device
bit 11-8
RODIV<3:0>: Reference Oscillator Divisor Select bits
1111= Base clock value divided by 32,768
1110= Base clock value divided by 16,384
1101= Base clock value divided by 8,192
1100= Base clock value divided by 4,096
1011= Base clock value divided by 2,048
1010= Base clock value divided by 1,024
1001= Base clock value divided by 512
1000= Base clock value divided by 256
0111= Base clock value divided by 128
0110= Base clock value divided by 64
0101= Base clock value divided by 32
0100= Base clock value divided by 16
0011= Base clock value divided by 8
0010= Base clock value divided by 4
0001= Base clock value divided by 2
0000= Base clock value
bit 7-0
Unimplemented: Read as ‘0’
Note 1: The crystal oscillator must be enabled using the FOSC<2:0> bits; the crystal maintains the operation in
Sleep mode.
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NOTES:
DS39995D-page 124
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
The assembly syntax of the PWRSAV instruction is
shown in Example 10-1.
10.0 POWER-SAVING FEATURES
Note:
This data sheet summarizes the features
Note: SLEEP_MODE and IDLE_MODE are
constants defined in the assembler
include file for the selected device.
of this group of PIC24F devices. It is not
intended to be a comprehensive refer-
ence source. For more information, refer
to the “PIC24F Family Reference
Manual”, ”Section 39. Power-Saving
Features with Deep Sleep” (DS39727).
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset.
When the device exits these modes, it is said to
“wake-up”.
The PIC24FV32KA304 family of devices provides the
ability to manage power consumption by selectively
managing clocking to the CPU and the peripherals. In
general, a lower clock frequency and a reduction in the
number of circuits being clocked constitutes lower
consumed power. All PIC24F devices manage power
consumption in four different ways:
10.2.1
SLEEP MODE
Sleep mode includes these features:
• The system clock source is shut down. If an
on-chip oscillator is used, it is turned off.
• The device current consumption will be reduced
to a minimum provided that no I/O pin is sourcing
current.
• Clock Frequency
• Instruction-Based Sleep, Idle and Deep Sleep
modes
• The I/O pin directions and states are frozen.
• The Fail-Safe Clock Monitor does not operate
during Sleep mode since the system clock source
is disabled.
• Software Controlled Doze mode
• Selective Peripheral Control in Software
Combinations of these methods can be used to
selectively tailor an application’s power consumption,
while still maintaining critical application features, such
as timing-sensitive communications.
• The LPRC clock will continue to run in Sleep
mode if the WDT or RTCC with LPRC as the clock
source is enabled.
• The WDT, if enabled, is automatically cleared
prior to entering Sleep mode.
10.1 Clock Frequency and Clock
Switching
• Some device features or peripherals may
continue to operate in Sleep mode. This includes
items, such as the Input Change Notification on
the I/O ports, or peripherals that use an external
clock input. Any peripheral that requires the
system clock source for its operation will be
disabled in Sleep mode.
PIC24F devices allow for a wide range of clock
frequencies to be selected under application control. If
the system clock configuration is not locked, users can
choose low-power or high-precision oscillators by simply
changing the NOSCx bits. The process of changing a
system clock during operation, as well as limitations to
the process, are discussed in more detail in Section 9.0
“Oscillator Configuration”.
The device will wake-up from Sleep mode on any of
these events:
• On any interrupt source that is individually
enabled
10.2 Instruction-Based Power-Saving
Modes
• On any form of device Reset
• On a WDT time-out
PIC24F devices have two special power-saving modes
that are entered through the execution of a special
PWRSAVinstruction. Sleep mode stops clock operation
and halts all code execution; Idle mode halts the CPU
and code execution, but allows peripheral modules to
continue operation. Deep Sleep mode stops clock
operation, code execution and all peripherals, except
RTCC and DSWDT. It also freezes I/O states and
removes power to SRAM and Flash memory.
On wake-up from Sleep, the processor will restart with
the same clock source that was active when Sleep
mode was entered.
EXAMPLE 10-1:
PWRSAV INSTRUCTION SYNTAX
PWRSAV
PWRSAV
BSET
#SLEEP_MODE
#IDLE_MODE
DSCON, #DSEN
#SLEEP_MODE
; Put the device into SLEEP mode
; Put the device into IDLE mode
; Enable Deep Sleep
PWRSAV
; Put the device into Deep SLEEP mode
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10.2.2
IDLE MODE
10.2.4.1
Entering Deep Sleep Mode
Idle mode has these features:
Deep Sleep mode is entered by setting the DSEN bit in
the DSCON register and then executing a Sleep com-
mand (PWRSAV #SLEEP_MODE). An unlock sequence
is required to set the DSEN bit. Once the DSEN bit has
been set, there is no time limit before the SLEEPcom-
mand can be executed. The DSEN bit is automatically
cleared when exiting the Deep Sleep mode.
• The CPU will stop executing instructions.
• The WDT is automatically cleared.
• The system clock source remains active. By
default, all peripheral modules continue to operate
normally from the system clock source, but can
also be selectively disabled (see Section 10.6
“Selective Peripheral Module Control”).
Note: To re-enter Deep Sleep after a Deep Sleep
wake-up, allow a delay of at least 3 TCY
after clearing the RELEASE bit.
• If the WDT or FSCM is enabled, the LPRC will
also remain active.
The device will wake from Idle mode on any of these
events:
The sequence to enter Deep Sleep mode is:
1. If the application requires the Deep Sleep WDT,
enable it and configure its clock source. For
more information on Deep Sleep WDT, see
Section 10.2.4.5 “Deep Sleep WDT”.
• Any interrupt that is individually enabled
• Any device Reset
• A WDT time-out
2. If the application requires Deep Sleep BOR,
enable it by programming the DSLPBOR
Configuration bit (FDS<6>).
On wake-up from Idle, the clock is re-applied to the
CPU and instruction execution begins immediately,
starting with the instruction following the PWRSAV
instruction or the first instruction in the ISR.
3. If the application requires wake-up from Deep
Sleep on RTCC alarm, enable and configure the
RTCC module For more information on RTCC,
see Section 19.0 “Real-Time Clock and
Calendar (RTCC)”.
10.2.3
INTERRUPTS COINCIDENT WITH
POWER SAVE INSTRUCTIONS
Any interrupt that coincides with the execution of a
PWRSAVinstruction will be held off until entry into Sleep
or Idle mode has completed. The device will then
wake-up from Sleep or Idle mode.
4. If needed, save any critical application context
data by writing it to the DSGPR0 and DSGPR1
registers (optional).
5. Enable Deep Sleep mode by setting the DSEN
bit (DSCON<15>).
10.2.4
DEEP SLEEP MODE
In PIC24FV32KA304 family devices, Deep Sleep mode
is intended to provide the lowest levels of power
consumption available without requiring the use of
external switches to completely remove all power from
the device. Entry into Deep Sleep mode is completely
under software control. Exit from Deep Sleep mode can
be triggered from any of the following events:
Note: An unlock sequence is required to set the
DSEN bit.
6. Enter Deep Sleep mode by issuing a PWRSAV#0
instruction.
Any time the DSEN bit is set, all bits in the DSWAKE
register will be automatically cleared.
• POR Event
To set the DSEN bit, the unlock sequence in
Example 10-2 is required:
• MCLR Event
• RTCC Alarm (if the RTCC is present)
• External Interrupt 0
EXAMPLE 10-2:
THE UNLOCK SEQUENCE
• Deep Sleep Watchdog Timer (DSWDT) Time-out
• Ultra Low-Power Wake-up (ULPWU) Event
//Disable Interrupts For 5 instructions
asm volatile(“disi #5”);
//Issue Unlock Sequence
In Deep Sleep mode, it is possible to keep the device
Real-Time Clock and Calendar (RTCC) running without
the loss of clock cycles.
asm
mov
mov
mov
mov
volatile
#0x55, W0;
W0, NVMKEY;
#0xAA, W1;
W1, NVMKEY;
The device has a dedicated Deep Sleep Brown-out
Reset (DSBOR) and a Deep Sleep Watchdog Timer
Reset (DSWDT) for monitoring voltage and time-out
events. The DSBOR and DSWDT are independent of
the standard BOR and WDT used with other
power-managed modes (Sleep, Idle and Doze).
bset DSCON, #DSEN
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Applications which require critical data to be saved
prior to Deep Sleep may use the Deep Sleep General
10.2.4.2
Exiting Deep Sleep Mode
Deep Sleep mode exits on any one of the following events:
Purpose registers, DSGPR0 and DSGPR1 or data
EEPROM (if available). Unlike other SFRs, the con-
tents of these registers are preserved while the device
is in Deep Sleep mode. After exiting Deep Sleep, soft-
ware can restore the data by reading the registers and
clearing the RELEASE bit (DSCON<0>).
• A POR event on VDD supply. If there is no
DSBOR circuit to re-arm the VDD supply POR cir-
cuit, the external VDD supply must be lowered to
the natural arming voltage of the POR circuit.
• A DSWDT time-out. When the DSWDT timer
times out, the device exits Deep Sleep.
10.2.4.4
I/O Pins During Deep Sleep
• An RTCC alarm (if RTCEN = 1).
• An assertion (‘0’) of the MCLR pin.
During Deep Sleep, the general purpose I/O pins retain
their previous states and the Secondary Oscillator
(SOSC) will remain running, if enabled. Pins that are
configured as inputs (TRISx bit is set), prior to entry into
Deep Sleep, remain high-impedance during Deep
Sleep. Pins that are configured as outputs (TRISx bit is
clear), prior to entry into Deep Sleep, remain as output
pins during Deep Sleep. While in this mode, they
continue to drive the output level determined by their
corresponding LATx bit at the time of entry into Deep
Sleep.
• An assertion of the INT0 pin (if the interrupt was
enabled before Deep Sleep mode was entered).
The polarity configuration is used to determine the
assertion level (‘0’ or ‘1’) of the pin that will cause
an exit from Deep Sleep mode. Exiting from Deep
Sleep mode requires a change on the INT0 pin
while in Deep Sleep mode.
Note:
Any interrupt pending when entering
Deep Sleep mode is cleared.
Exiting Deep Sleep mode generally does not retain the
state of the device and is equivalent to a Power-on
Reset (POR) of the device. Exceptions to this include
the RTCC (if present), which remains operational
through the wake-up, the DSGPRx registers and
DSWDT.
Once the device wakes back up, all I/O pins continue to
maintain their previous states, even after the device
has finished the POR sequence and is executing
application code again. Pins configured as inputs
during Deep Sleep remain high-impedance and pins
configured as outputs continue to drive their previous
value. After waking up, the TRIS and LAT registers,
and the SOSCEN bit (OSCCON<1>) are reset. If
firmware modifies any of these bits or registers, the I/O
will not immediately go to the newly configured states.
Once the firmware clears the RELEASE bit
(DSCON<0>), the I/O pins are “released”. This causes
the I/O pins to take the states configured by their
respective TRISx and LATx bit values.
Wake-up events that occur after Deep Sleep exits, but
before the POR sequence completes, are ignored and
are not be captured in the DSWAKE register.
The sequence for exiting Deep Sleep mode is:
1. After a wake-up event, the device exits Deep
Sleep and performs a POR. The DSEN bit is
cleared automatically. Code execution resumes
at the Reset vector.
This means that keeping the SOSC running after
waking up requires the SOSCEN bit to be set before
clearing RELEASE.
2. To determine if the device exited Deep Sleep,
read the Deep Sleep bit, DPSLP (RCON<10>).
This bit will be set if there was an exit from Deep
Sleep mode; if the bit is set, clear it.
If the Deep Sleep BOR (DSBOR) is enabled, and a
DSBOR or a true POR event occurs during Deep
Sleep, the I/O pins will be immediately released, similar
to clearing the RELEASE bit. All previous state
information will be lost, including the general purpose
DSGPR0 and DSGPR1 contents.
3. Determine the wake-up source by reading the
DSWAKE register.
4. Determine if a DSBOR event occurred during
Deep Sleep mode by reading the DSBOR bit
(DSCON<1>).
If a MCLR Reset event occurs during Deep Sleep, the
DSGPRx, DSCON and DSWAKE registers will remain
valid, and the RELEASE bit will remain set. The state
of the SOSC will also be retained. The I/O pins,
however, will be reset to their MCLR Reset state. Since
RELEASE is still set, changes to the SOSCEN bit
(OSCCON<1>) cannot take effect until the RELEASE
bit is cleared.
5. If application context data has been saved, read
it back from the DSGPR0 and DSGPR1 registers.
6. Clear the RELEASE bit (DSCON<0>).
10.2.4.3
Saving Context Data with the
DSGPR0/DSGPR1 Registers
As exiting Deep Sleep mode causes a POR, most
Special Function Registers reset to their default POR
values. In addition, because VCORE power is not sup-
plied in Deep Sleep mode, information in data RAM
may be lost when exiting this mode.
In all other Deep Sleep wake-up cases, application
firmware must clear the RELEASE bit in order to
reconfigure the I/O pins.
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10.2.4.5
Deep Sleep WDT
10.2.4.8
Power-on Resets (PORs)
To enable the DSWDT in Deep Sleep mode, program
the Configuration bit, DSWDTEN (FDS<7>). The
device Watchdog Timer (WDT) need not be enabled for
the DSWDT to function. Entry into Deep Sleep mode
automatically resets the DSWDT.
VDD voltage is monitored to produce PORs. Since
exiting from Deep Sleep functionally looks like a POR,
the technique described in Section 10.2.4.7 “Checking
and Clearing the Status of Deep Sleep” should be
used to distinguish between Deep Sleep and a true POR
event.
The DSWDT clock source is selected by the
DSWDTOSC Configuration bit (FDS<4>). The post-
scaler options are programmed by the DSWDTPS<3:0>
Configuration bits (FDS<3:0>). The minimum time-out
period that can be achieved is 2.1 ms and the maximum
is 25.7 days. For more details on the FDS Configuration
register and DSWDT configuration options, refer to
Section 26.0 “Special Features”.
When a true POR occurs, the entire device, including
all Deep Sleep logic (Deep Sleep registers: RTCC,
DSWDT, etc.) is reset.
10.2.4.9
Summary of Deep Sleep Sequence
To review, these are the necessary steps involved in
invoking and exiting Deep Sleep mode:
1. The device exits Reset and begins to execute its
application code.
10.2.4.6
Switching Clocks in Deep Sleep Mode
Both the RTCC and the DSWDT may run from either
SOSC or the LPRC clock source. This allows both the
RTCC and DSWDT to run without requiring both the
LPRC and SOSC to be enabled together, reducing
power consumption.
2. If DSWDT functionality is required, program the
appropriate Configuration bit.
3. Select the appropriate clock(s) for the DSWDT
and RTCC (optional).
4. Enable and configure the DSWDT (optional).
5. Enable and configure the RTCC (optional).
Running the RTCC from LPRC will result in a loss of
accuracy in the RTCC of approximately 5 to 10%. If a
more accurate RTCC is required, it must be run from
the SOSC clock source. The RTCC clock source is
selected with the RTCOSC Configuration bit (FDS<5>).
6. Write context data to the DSGPRx registers
(optional).
7. Enable the INT0 interrupt (optional).
8. Set the DSEN bit in the DSCON register.
Under certain circumstances, it is possible for the
DSWDT clock source to be off when entering Deep
Sleep mode. In this case, the clock source is turned on
automatically (if DSWDT is enabled), without the need
for software intervention; however, this can cause a
delay in the start of the DSWDT counters. In order to
avoid this delay when using SOSC as a clock source,
the application can activate SOSC prior to entering
Deep Sleep mode.
9. Enter Deep Sleep by issuing
a
PWRSV
#SLEEP_MODEcommand.
10. The device exits Deep Sleep when a wake-up
event occurs.
11. The DSEN bit is automatically cleared.
12. Read and clear the DPSLP status bit in RCON,
and the DSWAKE status bits.
13. Read the DSGPRx registers (optional).
10.2.4.7
Checking and Clearing the Status of
Deep Sleep
14. Once all state related configurations are
complete, clear the RELEASE bit.
15. The application resumes normal operation.
Upon entry into Deep Sleep mode, the status bit,
DPSLP (RCON<10>), becomes set and must be
cleared by the software.
On power-up, the software should read this status bit to
determine if the Reset was due to an exit from Deep
Sleep mode and clear the bit if it is set. Of the four
possible combinations of DPSLP and POR bit states,
three cases can be considered:
• Both the DPSLP and POR bits are cleared. In this
case, the Reset was due to some event other
than a Deep Sleep mode exit.
• The DPSLP bit is clear, but the POR bit is set; this
is a normal POR.
• Both the DPSLP and POR bits are set. This
means that Deep Sleep mode was entered, the
device was powered down and Deep Sleep mode
was exited.
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REGISTER 10-1: DSCON: DEEP SLEEP CONTROL REGISTER(1)
R/W-0
DSEN
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
RTCCWDIS
bit 8
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
DSBOR(2)
R/C-0, HS
RELEASE
bit 0
ULPWUDIS
bit 7
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
HS = Hardware Settable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
R = Readable bit
-n = Value at POR
bit 15
DSEN: Deep Sleep Enable bit
1= Enters Deep Sleep on execution of PWRSAV #0
0= Enters normal Sleep on execution of PWRSAV #0
bit 14-9
bit 8
Unimplemented: Read as ‘0’
RTCCWDIS: RTCC Wake-up Disable bit
1= Wake-up from Deep Sleep with RTCC disabled
0= Wake-up from Deep Sleep with RTCC enabled
bit 7-3
bit 2
Unimplemented: Read as ‘0’
ULPWUDIS: ULPWU Wake-up Disable bit
1= Wake-up from Deep Sleep with ULPWU disabled
0= Wake-up from Deep Sleep with ULPWU enabled
bit 1
bit 0
DSBOR: Deep Sleep BOR Event bit(2)
1= The DSBOR was active and a BOR event was detected during Deep Sleep
0= The DSBOR was not active or was active but did not detect a BOR event during Deep Sleep
RELEASE: I/O Pin State Release bit
1= Upon waking from Deep Sleep, I/O pins maintain their previous states to Deep Sleep entry
0= Release I/O pins from their state previous to Deep Sleep entry, and allow their respective TRISx and
LATx bits to control their states
Note 1: All register bits are only reset in the case of a POR event outside of Deep Sleep mode.
2: Unlike all other events, a Deep Sleep BOR event will NOT cause a wake-up from Deep Sleep; this
re-arms POR.
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REGISTER 10-2: DSWAKE: DEEP SLEEP WAKE-UP SOURCE REGISTER(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0, HS
DSINT0
bit 15
bit 8
R/W-0, HS
DSFLT
bit 7
U-0
—
U-0
—
R/W-0, HS
DSWDT
R/W-0, HS
DSRTCC
R/W-0, HS
DSMCLR
U-0
—
R/W-0, HS
DSPOR(2,3)
bit 0
Legend:
HS = Hardware Settable bit
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 15-9
bit 8
Unimplemented: Read as ‘0’
DSINT0: Deep Sleep Interrupt-on-Change bit
1= Interrupt-on-change was asserted during Deep Sleep
0= Interrupt-on-change was not asserted during Deep Sleep
bit 7
DSFLT: Deep Sleep Fault Detect bit
1= A Fault occurred during Deep Sleep and some Deep Sleep configuration settings may have been
corrupted
0= No Fault was detected during Deep Sleep
bit 6-5
bit 4
Unimplemented: Read as ‘0’
DSWDT: Deep Sleep Watchdog Timer Time-out bit
1= The Deep Sleep Watchdog Timer timed out during Deep Sleep
0= The Deep Sleep Watchdog Timer did not time out during Deep Sleep
bit 3
bit 2
DSRTCC: Deep Sleep Real-Time Clock and Calendar (RTCC) Alarm bit
1= The Real-Time Clock and Calendar triggered an alarm during Deep Sleep
0= The Real-Time Clock and Calendar did not trigger an alarm during Deep Sleep
DSMCLR: Deep Sleep MCLR Event bit
1= The MCLR pin was active and was asserted during Deep Sleep
0= The MCLR pin was not active, or was active, but not asserted during Deep Sleep
bit 1
bit 0
Unimplemented: Read as ‘0’
DSPOR: Deep Sleep Power-on Reset Event bit(2,3)
1= The VDD supply POR circuit was active and a POR event was detected
0= The VDD supply POR circuit was not active, or was active, but did not detect a POR event
Note 1: All register bits are cleared when the DSEN (DSCON<15>) bit is set.
2: All register bits are reset only in the case of a POR event outside of Deep Sleep mode, except bit,
DSPOR, which does not reset on a POR event that is caused due to a Deep Sleep exit.
3: Unlike the other bits in this register, this bit can be set outside of Deep Sleep.
DS39995D-page 130
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EXAMPLE 10-3:
ULTRA LOW-POWER
WAKE-UP INITIALIZATION
10.3 Ultra Low-Power Wake-up
The Ultra Low-Power Wake-up (ULPWU) on pin, RB0,
allows a slow falling voltage to generate an interrupt
without excess current consumption.
//*******************************
// 1. Charge the capacitor on RB0
//*******************************
TRISBbits.TRISB0 = 0;
To use this feature:
LATBbits.LATB0 = 1;
1. Charge the capacitor on RB0 by configuring the
for(i = 0; i < 10000; i++) Nop();
//*****************************
//2. Stop Charging the capacitor
RB0 pin to an output and setting it to ‘1’.
2. Stop charging the capacitor by configuring RB0
as an input.
//
on RB0
//*****************************
TRISBbits.TRISB0 = 1;
//*****************************
//3. Enable ULPWU Interrupt
//*****************************
IFS5bits.ULPWUIF = 0;
3. Discharge the capacitor by setting the ULPEN
and ULPSINK bits in the ULPWCON register.
4. Configure Sleep mode.
5. Enter Sleep mode.
When the voltage on RB0 drops below VIL, the device
wakes up and executes the next instruction.
IEC5bits.ULPWUIE = 1;
IPC21bits.ULPWUIP = 0x7;
//*****************************
//4. Enable the Ultra Low Power
This feature provides a low-power technique for
periodically waking up the device from Sleep mode.
//
//
Wakeup module and allow
capacitor discharge
The time-out is dependent on the discharge time of the
RC circuit on RB0.
//*****************************
ULPWCONbits.ULPEN = 1;
ULPWCONbit.ULPSINK = 1;
//*****************************
//5. Enter Sleep Mode
//*****************************
Sleep();
When the ULPWU module wakes the device from
Sleep mode, the ULPWUIF bit (IFS5<0>) is set. Soft-
ware can check this bit upon wake-up to determine the
wake-up source. See Example 10-3 for initializing the
ULPWU module.
//for sleep, execution will
//resume here
A series resistor, between RB0 and the external
capacitor, provides overcurrent protection for the
RB0/AN0/ULPWU pin and enables software calibration
of the time-out (see Figure 10-1).
FIGURE 10-1:
SERIES RESISTOR
R
1
RB0
C
1
A timer can be used to measure the charge time and
discharge time of the capacitor. The charge time can
then be adjusted to provide the desired delay in Sleep.
This technique compensates for the affects of temper-
ature, voltage and component accuracy. The peripheral
can also be configured as a simple, programmable
Low-Voltage Detect (LVD) or temperature sensor.
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REGISTER 10-3: ULPWCON: ULPWU CONTROL REGISTER
R/W-0
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
ULPEN
ULPSIDL
ULPSINK
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
ULPEN: ULPWU Module Enable bit
1= Module is enabled
0= Module is disabled
bit 14
bit 13
Unimplemented: Read as ‘0’
ULPSIDL: ULPWU Stop in Idle Select bit
1= Discontinues module operation when the device enters Idle mode
0= Continues module operation in Idle mode
bit 12-9
bit 8
Unimplemented: Read as ‘0’
ULPSINK: ULPWU Current Sink Enable bit
1= Current sink is enabled
0= Current sink is disabled
bit 7-0
Unimplemented: Read as ‘0’
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10.4.3
RETENTION SLEEP MODE
10.4 Voltage Regulator-Based
Power-Saving Features
In Retention Sleep mode, the device is in Sleep and all
regulated voltage is provided solely by the Retention
Regulator. Consequently, this mode has lower power
consumption than regular Sleep mode, but is also
limited in terms of how much functionality can be
enabled. Retention Sleep wake-up time is longer than
Sleep mode due to the extra time required to raise the
VCORE supply rail back to normal regulated levels.
The PIC24FV32KA304 series devices have a Voltage
Regulator that has the ability to alter functionality to
provide power savings. The on-board regulator is made
up of two basic modules: the Voltage Regulator
(VREG) and the Retention Regulator (RETREG). With
the combination of VREG and RETREG, the following
power modes are available:
Note: PIC24F32KA30X family devices do not
use an On-Chip Voltage Regulator, so
they do not support Retention Sleep
mode.
10.4.1
RUN MODE
In Run mode, the main VREG is providing a regulated
voltage with enough current to supply a device running
at full speed, and the device is not in Sleep or Deep
Sleep Mode. The Retention Regulator may or may not
be running, but is unused.
10.4.4
DEEP SLEEP MODE
In Deep Sleep mode, both the main Voltage Regulator
and Retention Regulator are shut down, providing the
lowest possible device power consumption. However,
this mode provides no retention or functionality of the
device and has the longest wake-up time.
10.4.2
SLEEP (STANDBY) MODE
In Sleep mode, the device is in Sleep and the main
VREG is providing a regulated voltage at a reduced
(standby) supply current. This mode provides for
limited functionality due to the reduced supply current.
It requires a longer time to wake-up from Sleep.
TABLE 10-1: VOLTAGE REGULATION CONFIGURATION SETTINGS FOR PIC24FV32KA304
FAMILY DEVICES
RETCGF Bit
(FPOR<2>)
RETEN Bit
(RCON<12> (RCON<8>) During Sleep
PMSLP Bit
Power Mode
Description
VREG mode (normal) is unchanged during Sleep.
RETREG is unused.
0
0
0
1
1
0
0
1
X
X
1
0
0
1
0
Sleep
Sleep
(Standby)
VREG goes to Low-Power Standby mode during
Sleep. RETREG is unused.
Retention
Sleep
VREG is off during Sleep. RETREG is enabled and
provides Sleep voltage regulation.
VREG mode (normal) is unchanged during Sleep.
RETREG is disabled at all times.
Sleep
Sleep
(Standby)
VREG goes to Low-Power Standby mode during
Sleep. RETREG is disabled at all times
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10.5 Doze Mode
10.6 Selective Peripheral Module
Control
Generally, changing clock speed and invoking one of
the power-saving modes are the preferred strategies
for reducing power consumption. There may be circum-
stances, however, where this is not practical. For
example, it may be necessary for an application to
maintain uninterrupted synchronous communication,
even while it is doing nothing else. Reducing system
clock speed may introduce communication errors,
Idle and Doze modes allow users to substantially
reduce power consumption by slowing or stopping the
CPU clock. Even so, peripheral modules still remain
clocked, and thus, consume power. There may be
cases where the application needs what these modes
do not provide: the allocation of power resources to
CPU processing, with minimal power consumption
from the peripherals.
while using
a
power-saving mode may stop
communications completely.
PIC24F devices address this requirement by allowing
peripheral modules to be selectively disabled, reducing
or eliminating their power consumption. This can be
done with two control bits:
Doze mode is a simple and effective alternative method
to reduce power consumption while the device is still
executing code. In this mode, the system clock
continues to operate from the same source and at the
same speed. Peripheral modules continue to be
clocked at the same speed, while the CPU clock speed
is reduced. Synchronization between the two clock
domains is maintained, allowing the peripherals to
access the SFRs while the CPU executes code at a
slower rate.
• The Peripheral Enable bit, generically named,
“XXXEN”, located in the module’s main control
SFR.
• The Peripheral Module Disable (PMD) bit,
generically named, “XXXMD”, located in one of
the PMD Control registers.
Both bits have similar functions in enabling or disabling its
associated module. Setting the PMDx bits for a module
disables all clock sources to that module, reducing its
power consumption to an absolute minimum. In this
state, the control and status registers associated with the
peripheral will also be disabled, so writes to those
registers will have no effect, and read values will be
invalid. Many peripheral modules have a corresponding
PMDx bit.
Doze mode is enabled by setting the DOZEN bit
(CLKDIV<11>). The ratio between peripheral and core
clock speed is determined by the DOZE<2:0> bits
(CLKDIV<14:12>). There are eight possible
configurations, from 1:1 to 1:128, with 1:1 being the
default.
It is also possible to use Doze mode to selectively reduce
power consumption in event driven applications. This
allows clock-sensitive functions, such as synchronous
communications, to continue without interruption. Mean-
while, the CPU Idles, waiting for something to invoke an
interrupt routine. Enabling the automatic return to
full-speed CPU operation on interrupts is enabled by
setting the ROI bit (CLKDIV<15>). By default, interrupt
events have no effect on Doze mode operation.
In contrast, disabling a module by clearing its XXXEN
bit, disables its functionality, but leaves its registers
available to be read and written to. Power consumption
is reduced, but not by as much as the PMDx bits are
used. Most peripheral modules have an enable bit;
exceptions include capture, compare and RTCC.
To achieve more selective power savings, peripheral
modules can also be selectively disabled when the
device enters Idle mode. This is done through the control
bit of the generic name format, “XXXIDL”. By default, all
modules that can operate during Idle mode will do so.
Using the disable on Idle feature disables the module
while in Idle mode, allowing further reduction of power
consumption during Idle mode, enhancing power
savings for extremely critical power applications.
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When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as
11.0 I/O PORTS
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
a general purpose output pin is disabled. The I/O pin
may be read, but the output driver for the parallel port
bit will be disabled. If a peripheral is enabled, but the
peripheral is not actively driving a pin, that pin may be
driven by a port.
intended to be a comprehensive reference
source. For more information on the I/O
Ports, refer to the “PIC24F Family
Reference Manual”, Section 12. “I/O
Ports with Peripheral Pin Select
(PPS)” (DS39711). Note that the
PIC24FV32KA304 family devices do not
support Peripheral Pin Select features.
All port pins have three registers directly associated
with their operation as digital I/O. The Data Direction
register (TRISx) determines whether the pin is an input
or an output. If the data direction bit is a ‘1’, then the pin
is an input. All port pins are defined as inputs after a
Reset. Reads from the Data Latch register (LAT), read
the latch. Writes to the latch, write the latch. Reads
from the port (PORT), read the port pins; writes to the
port pins, write the latch.
All of the device pins (except VDD and VSS) are shared
between the peripherals and the parallel I/O ports. All
I/O input ports feature Schmitt Trigger inputs for
improved noise immunity.
Any bit and its associated data and control registers
that are not valid for a particular device will be
disabled. That means the corresponding LATx and
TRISx registers, and the port pin will read as zeros.
11.1 Parallel I/O (PIO) Ports
A parallel I/O port that shares a pin with a peripheral is,
in general, subservient to the peripheral. The
peripheral’s output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
the I/O pin. The logic also prevents “loop through”, in
which a port’s digital output can drive the input of a
peripheral that shares the same pin. Figure 11-1
illustrates how ports are shared with other peripherals
and the associated I/O pin to which they are connected.
When a pin is shared with another peripheral or
function that is defined as an input only, it is
nevertheless regarded as a dedicated port because
there is no other competing source of outputs.
Note:
The I/O pins retain their state during Deep
Sleep. They will retain this state at
wake-up until the software restore bit
(RELEASE) is cleared.
FIGURE 11-1:
BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
Peripheral Module
Output Multiplexers
Peripheral Input Data
Peripheral Module Enable
Peripheral Output Enable
Peripheral Output Data
I/O
1
Output Enable
0
1
0
PIO Module
Output Data
Read TRIS
Data Bus
WR TRIS
D
Q
I/O Pin
CK
TRIS Latch
D
Q
WR LAT +
WR PORT
CK
Data Latch
Read LAT
Input Data
Read PORT
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When reading the PORT register, all pins configured as
analog input channels will read as cleared (a low level).
Analog levels on any pin that is defined as a digital
input (including the ANx pins) may cause the input
buffer to consume current that exceeds the device
specifications.
11.1.1
OPEN-DRAIN CONFIGURATION
In addition to the PORT, LAT and TRIS registers for
data control, each port pin can also be individually
configured for either digital or open-drain output. This is
controlled by the Open-Drain Control register, ODCx,
associated with each port. Setting any of the bits
configures the corresponding pin to act as an
open-drain output.
11.2.1
ANALOG SELECTION REGISTERS
I/O pins with shared analog functionality, such as A/D
inputs and comparator inputs, must have their digital
inputs shut off when analog functionality is used. Note
that analog functionality includes an analog voltage
being applied to the pin externally.
The maximum open-drain voltage allowed is the same
as the maximum VIH specification.
11.2 Configuring Analog Port Pins
The use of the ANS and TRIS registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their correspond-
ing TRISx bit set (input). If the TRISx bit is cleared
(output), the digital output level (VOH or VOL) will be
converted.
To allow for analog control, the ANSx registers are
provided. There is one ANS register for each port
(ANSA, ANSB and ANSC). Within each ANSx register,
there is a bit for each pin that shares analog
functionality with the digital I/O functionality.
If a particular pin does not have an analog function, that
bit is unimplemented. See Register 11-1 to Register 11-3
for implementation.
REGISTER 11-1: ANSA: ANALOG SELECTION (PORTA)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
ANSA3
ANSA2
ANSA1
ANSA0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-4
bit 3-0
Unimplemented: Read as ‘0’
ANSA<3:0>: Analog Select Control bits
1= Digital input buffer is not active (use for analog input)
0= Digital input buffer is active
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REGISTER 11-2: ANSB: ANALOG SELECTION (PORTB)
R/W-1
R/W-1
R/W-1
R/W-1
U-0
—
U-0
—
U-0
—
U-0
—
ANSB15
ANSB14
ANSB13
ANSB12
bit 15
bit 8
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
ANSB3(1)
R/W-1
R/W-1
R/W-1
ANSB4
ANSB2
ANSB1
ANSB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-12
ANSB<15:12>: Analog Select Control bits
1= Digital input buffer is not active (use for analog input)
0= Digital input buffer is active
bit 11-5
bit 4-0
Unimplemented: Read as ‘0’
ANSB<4:0>: Analog Select Control bits(1)
1= Digital input buffer is not active (use for analog input)
0= Digital input buffer is active
Note 1: The ANSB3 bit is not available on 20-pin devices.
REGISTER 11-3: ANSC ANALOG SELECTION (PORTC)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
ANSC2(1)
R/W-1
ANSC1(1)
R/W-1
ANSC0(1)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-3
bit 2-0
Unimplemented: Read as ‘0’
ANSC<2:0>: Analog Select Control bits(1)
1= Digital input buffer is not active (use for analog input)
0= Digital input buffer is active
Note 1: These bits are not available on 20-pin or 28-pin devices.
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On any pin, only the pull-up resistor or the pull-down
resistor should be enabled, but not both of them. If the
push button or the keypad is connected to VDD, enable
the pull-down, or if they are connected to VSS, enable
the pull-up resistors. The pull-ups are enabled
separately, using the CNPU1 and CNPU2 registers,
which contain the control bits for each of the CN pins.
11.2.2
I/O PORT WRITE/READ TIMING
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically, this instruction
would be a NOP.
11.3 Input Change Notification (ICN)
Setting any of the control bits enables the weak
pull-ups for the corresponding pins. The pull-downs are
enabled separately, using the CNPD1 and CNPD2 reg-
isters, which contain the control bits for each of the CN
pins. Setting any of the control bits enables the weak
pull-downs for the corresponding pins.
The Input Change Notification function of the I/O ports
allows the PIC24FV32KA304 family of devices to
generate interrupt requests to the processor in
response to a Change-of-State (COS) on selected
input pins. This feature is capable of detecting input
Change-of-States, even in Sleep mode, when the
clocks are disabled. Depending on the device pin
count, there are up to 23 external signals (CN0 through
CN22) that may be selected (enabled) for generating
an interrupt request on a Change-of-State.
When the internal pull-up is selected, the pin uses VDD
as the pull-up source voltage. When the internal
pull-down is selected, the pins are pulled down to VSS
by an internal resistor. Make sure that there is no
external pull-up source/pull-down sink when the
internal pull-ups/pull-downs are enabled.
There are six control registers associated with the ICN
module. The CNEN1 and CNEN2 registers contain the
interrupt enable control bits for each of the CN input
pins. Setting any of these bits enables a CN interrupt
for the corresponding pins.
Note:
Pull-ups and pull-downs on Change Notifi-
cation pins should always be disabled
whenever the port pin is configured as a
digital output.
Each CN pin also has a weak pull-up/pull-down
connected to it. The pull-ups act as a current source
that is connected to the pin. The pull-downs act as a
current sink to eliminate the need for external resistors
when push button or keypad devices are connected.
EXAMPLE 11-1:
PORT WRITE/READ EXAMPLE
MOV
MOV
0xFF00, W0;
W0, TRISB;
//Configure PORTB<15:8> as inputs and PORTB<7:0> as outputs
NOP;
//Delay 1 cycle
BTSS PORTB, #13;
//Next Instruction
Equivalent ‘C’ Code
TRISB = 0xFF00;
NOP();
//Configure PORTB<15:8> as inputs and PORTB<7:0> as outputs
//Delay 1 cycle
if(PORTBbits.RB13 == 1)
// execute following code if PORTB pin 13 is set.
{
}
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Figure 12-1 illustrates a block diagram of the 16-bit
Timer1 module.
12.0 TIMER1
Note:
This data sheet summarizes the features
of this group of PIC24F devices. It is not
To configure Timer1 for operation:
1. Set the TON bit (= 1).
intended to be a comprehensive refer-
ence source. For more information on
Timers, refer to the “PIC24F Family Refer-
ence Manual”, Section 14. “Timers”
(DS39704).
2. Select the timer prescaler ratio using the
TCKPS<1:0> bits.
3. Set the Clock and Gating modes using the TCS
and TGATE bits.
4. Set or clear the TSYNC bit to configure
synchronous or asynchronous operation.
The Timer1 module is a 16-bit timer which can serve as
the time counter for the Real-Time Clock (RTC) or
operate as a free-running, interval timer/counter. Timer1
can operate in three modes:
5. Load the timer period value into the PR1
register.
6. If interrupts are required, set the Timer1 Interrupt
Enable bit, T1IE. Use the Timer1 Interrupt Priority
bits, T1IP<2:0>, to set the interrupt priority.
• 16-Bit Timer
• 16-Bit Synchronous Counter
• 16-Bit Asynchronous Counter
Timer1 also supports these features:
• Timer Gate Operation
• Selectable Prescaler Settings
• Timer Operation During CPU Idle and Sleep
modes
• Interrupt on 16-Bit Period Register Match or
Falling Edge of External Gate Signal
FIGURE 12-1:
16-BIT TIMER1 MODULE BLOCK DIAGRAM
T1ECS<1:0>
LPRC
TCKPS<1:0>
TON
2
SOSCO
Prescaler
1, 8, 64, 256
Gate
Sync
SOSCI
T1CK
SOSCEN
TGATE
TCS
FOSC/2
TGATE
Q
Q
D
Set T1IF
CK
Reset
TMR1
Sync
TSYNC
Comparator
PR1
Equal
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REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0
TON
U-0
—
R/W-0
TSIDL
U-0
—
U-0
—
U-0
—
R/W-0
T1ECS1(1)
R/W-0
T1ECS0(1)
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
TCS
U-0
—
TGATE
TCKPS1
TCKPS0
TSYNC
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
TON: Timer1 On bit
1= Starts 16-bit Timer1
0= Stops 16-bit Timer1
bit 14
bit 13
Unimplemented: Read as ‘0’
TSIDL: Timer1 Stop in Idle Mode bit
1= Discontinues module operation when device enters Idle mode
0= Continues module operation in Idle mode
bit 12-10
bit 9-8
Unimplemented: Read as ‘0’
T1ECS<1:0>: Timer1 Extended Clock Select bits(1)
11= Reserved; do not use
10= Timer1 uses the LPRC as the clock source
01= Timer1 uses the external clock from T1CK
00= Timer1 uses the Secondary Oscillator (SOSC) as the clock source
bit 7
bit 6
Unimplemented: Read as ‘0’
TGATE: Timer1 Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1= Gated time accumulation is enabled
0= Gated time accumulation is disabled
bit 5-4
TCKPS<1:0>: Timer1 Input Clock Prescale Select bits
11= 1:256
10= 1:64
01= 1:8
00= 1:1
bit 3
bit 2
Unimplemented: Read as ‘0’
TSYNC: Timer1 External Clock Input Synchronization Select bit
When TCS = 1:
1= Synchronizes external clock input
0= Does not synchronize external clock input
When TCS = 0:
This bit is ignored.
bit 1
bit 0
TCS: Timer1 Clock Source Select bit
1= Timer1 clock source is selected by T1ECS<1:0>
0= Internal clock (FOSC/2)
Unimplemented: Read as ‘0’
Note 1: The T1ECSx bits are valid only when TCS = 1.
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To configure Timer2/3 or Timer4/5 for 32-bit operation:
13.0 TIMER2/3 AND TIMER4/5
1. Set the T32 bit (T2CON<3> or T4CON<3> = 1).
Note:
This data sheet summarizes the features of
2. Select the prescaler ratio for Timer2 or Timer4
using the TCKPS<1:0> bits.
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on Timers,
refer to the “PIC24F Family Reference
Manual”, Section 14. “Timers” (DS39704).
3. Set the Clock and Gating modes using the TCS
and TGATE bits.
4. Load the timer period value. PR3 (or PR5) will
contain the most significant word of the value,
while PR2 (or PR4) contains the least significant
word.
The Timer2/3 and Timer4/5 modules are 32-bit timers,
which can also be configured as four independent,16-bit
timers with selectable operating modes.
5. If interrupts are required, set the Timerx Interrupt
Enable bit, TxIE. Use the Timerx Interrupt Priority
bits, TxIP<2:0>, to set the interrupt priority.
As a 32-bit timer, Timer2/3 or Timer4/5 operate in three
modes:
• Two Independent 16-Bit Timers (Timer2 and
Timer3) with all 16-Bit Operating modes (except
Asynchronous Counter mode)
6. Set the TON bit (TxCON<15> = 1).
The timer value, at any point, is stored in the register
pair, TMR3:TMR2 (or TMR5:TMR4). TMR3 (TMR5)
always contains the most significant word of the count,
while TMR2 (TMR4) contains the least significant word.
• Single 32-Bit Timer
• Single 32-Bit Synchronous Counter
To configure any of the timers for individual 16-bit
operation:
They also support these features:
• Timer Gate Operation
1. Clear the T32 bit corresponding to that timer
(T2CON<3> for Timer2 and Timer3 or
T4CON<3> for Timer4 and Timer5).
• Selectable Prescaler Settings
• Timer Operation during Idle mode
• Interrupt on a 32-Bit Period Register Match
• A/D Event Trigger
2. Select the timer prescaler ratio using the
TCKPS<1:0> bits.
Individually, all four of the 16-bit timers can function as
synchronous timers or counters. They also offer the
features listed above, except for the A/D event trigger
(this is implemented only with Timer3). The operating
modes and enabled features are determined by setting
the appropriate bit(s) in the T2CON, T3CON, T4CON
and T5CON registers. The T2CON,T3CON, T4CON
and T5CON registers are provided in generic form in
Register 13-1 and Register 13-2, respectively.
3. Set the Clock and Gating modes using the TCS
and TGATE bits.
4. Load the timer period value into the PRx
register.
5. If interrupts are required, set the Timerx Interrupt
Enable bit, TxIE; use the Timerx Interrupt Priority
bits, TxIP<2:0>, to set the interrupt priority.
6. Set the TON bit (TxCON<15> = 1).
For 32-bit timer/counter operation, Timer2/Timer4 is
the least significant word (lsw) and Timer3/Timer5 is
the most significant word (msw) of the 32-bit timer.
Note:
For 32-bit operation, T3CON or T5CON
control bits are ignored. Only T2CON or
T4CON control bits are used for setup and
control. Timer2 or Timer4 clock and gate
inputs are utilized for the 32-bit timer
modules, but an interrupt is generated with
the Timer3 or Timer5 interrupt flags.
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FIGURE 13-1:
TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM
TCKPS<1:0>
2
TON
T2CK
(T4CK)
Prescaler
1, 8, 64, 256
Gate
Sync
TCY
TGATE
TGATE
TCS
1
0
Q
D
Set T3IF (T5IF)
Q
CK
PR3
PR2
(PR5)
(PR4)
(2)
A/D Event Trigger
Equal
Reset
Comparator
MSB
LSB
TMR2
(TMR4)
TMR3
(TMR5)
Sync
16
(1)
(1)
Read TMR2 (TMR4)
Write TMR2 (TMR4)
16
16
TMR3HLD
(TMR5HLD)
Data Bus<15:0>
Note 1: The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are
respective to the T2CON and T4CON registers.
2: The A/D event trigger is available only on Timer2/3 and Timer4/5 in 32-bit mode, and Timer3 and Timer5 in
16-bit mode.
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FIGURE 13-2:
TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM
TCKPS<1:0>
2
TON
T2CK
(T4CK)
Gate
Sync
Prescaler
1, 8, 64, 256
TGATE
TCS
TGATE
TCY
Q
D
1
0
Set T2IF (T4IF)
Q
CK
Reset
Equal
Sync
TMR2 (TMR4)
Comparator
PR2 (PR4)
FIGURE 13-3:
TIMER3 AND TIMER5 (16-BIT ASYNCHRONOUS) BLOCK DIAGRAM
TCKPS<1:0>
2
TON
T3CK
(T5CK)
Sync
Prescaler
1, 8, 64, 256
TGATE
TCS
TGATE
TCY
Q
Q
D
1
0
Set T3IF (T5IF)
CK
Reset
Equal
TMR3 (TMR5)
A/D Event Trigger
Comparator
PR3 (PR5)
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REGISTER 13-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER
R/W-0
TON
U-0
—
R/W-0
TSIDL
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
T32(1)
U-0
—
R/W-0
TCS
U-0
—
TGATE
TCKPS1
TCKPS0
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
TON: Timerx On bit
When TxCON<3> = 1:
1= Starts 32-bit Timerx/y
0= Stops 32-bit Timerx/y
When TxCON<3> = 0:
1= Starts 16-bit Timerx
0= Stops 16-bit Timerx
bit 14
bit 13
Unimplemented: Read as ‘0’
TSIDL: Timerx Stop in Idle Mode bit
1= Discontinues module operation when device enters Idle mode
0= Continues module operation in Idle mode
bit 12-7
bit 6
Unimplemented: Read as ‘0’
TGATE: Timerx Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1= Gated time accumulation is enabled
0= Gated time accumulation is disabled
bit 5-4
bit 3
TCKPS<1:0>: Timerx Input Clock Prescale Select bits
11= 1:256
10= 1:64
01= 1:8
00= 1:1
T32: 32-Bit Timer Mode Select bit(1)
1= Timer2 and Timer3 or Timer4 and Timer5 form a single 32-bit timer
0= Timer2 and Timer3 or Timer4 and Timer5 act as two 16-bit timers
bit 2
bit 1
Unimplemented: Read as ‘0’
TCS: Timerx Clock Source Select bit
1= External clock from pin, TxCK (on the rising edge)
0= Internal clock (FOSC/2)
bit 0
Unimplemented: Read as ‘0’
Note 1: In 32-bit mode, the T3CON or T5CON control bits do not affect 32-bit timer operation.
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REGISTER 13-2: TyCON: TIMER3 AND TIMER5 CONTROL REGISTER
R/W-0
TON(1)
U-0
—
R/W-0
TSIDL(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-0
TGATE(1)
R/W-0
TCKPS1(1)
R/W-0
TCKPS0(1)
U-0
—
U-0
—
R/W-0
TCS(1)
U-0
—
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
TON: Timery On bit(1)
1= Starts 16-bit Timery
0= Stops 16-bit Timery
bit 14
bit 13
Unimplemented: Read as ‘0’
TSIDL: Timery Stop in Idle Mode bit(1)
1= Discontinues module operation when device enters Idle mode
0= Continues module operation in Idle mode
bit 12-7
bit 6
Unimplemented: Read as ‘0’
TGATE: Timery Gated Time Accumulation Enable bit(1)
When TCS = 1:
This bit is ignored.
When TCS = 0:
1= Gated time accumulation is enabled
0= Gated time accumulation is disabled
bit 5-4
TCKPS<1:0>: Timery Input Clock Prescale Select bits(1)
11= 1:256
10= 1:64
01= 1:8
00= 1:1
bit 3-2
bit 1
Unimplemented: Read as ‘0’
TCS: Timery Clock Source Select bit(1)
1= External clock is from the T3CK pin (on the rising edge)
0= Internal clock (FOSC/2)
bit 0
Unimplemented: Read as ‘0’
Note 1: When 32-bit operation is enabled (TxCON<3> = 1), these bits have no effect on Timery operation. All timer
functions are set through the TxCON register.
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NOTES:
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14.1 General Operating Modes
14.0 INPUT CAPTURE WITH
DEDICATED TIMERS
14.1.1
SYNCHRONOUS AND TRIGGER
MODES
Note:
This data sheet summarizes the features
of this group of PIC24F devices. It is
not intended to be a comprehensive
reference source. For more information,
refer to the “PIC24F Family Reference
Manual”, Section 34. “Input Capture
with Dedicated Timer” (DS39722).
By default, the input capture module operates in a
Free-Running mode. The internal 16-bit counter,
ICxTMR, counts up continuously, wrapping around
from FFFFh to 0000h on each overflow, with its period
synchronized to the selected external clock source.
When a capture event occurs, the current 16-bit value
of the internal counter is written to the FIFO buffer.
All devices in the PIC24FV32KA304 family feature
three independent input capture modules. Each of the
modules offers a wide range of configuration and
operating options for capturing external pulse events,
and generating interrupts.
In Synchronous mode, the module begins capturing
events on the ICx pin as soon as its selected clock
source is enabled. Whenever an event occurs on the
selected Sync source, the internal counter is reset. In
Trigger mode, the module waits for a Sync event from
another internal module to occur before allowing the
internal counter to run.
Key features of the input capture module include:
• Hardware-configurable for 32-bit operation in all
modes by cascading two adjacent modules
Standard, free-running operation is selected by setting
the SYNCSELx bits to ‘00000’ and clearing the ICTRIG
bit (ICxCON2<7>). Synchronous and Trigger modes
are selected any time the SYNCSELx bits are set to
any value except ‘00000’. The ICTRIG bit selects
either Synchronous or Trigger mode; setting the bit
selects Trigger mode operation. In both modes, the
SYNCSELx bits determine the Sync/trigger source.
• Synchronous and Trigger modes of output
compare operation, with up to 20 user-selectable
Sync/trigger sources available
• A 4-level FIFO buffer for capturing and holding
timer values for several events
• Configurable interrupt generation
• Up to 6 clock sources available for each module,
driving a separate internal 16-bit counter
When the SYNCSELx bits are set to ‘00000’ and
ICTRIG is set, the module operates in Software Trigger
mode. In this case, capture operations are started by
manually setting the TRIGSTAT bit (ICxCON2<6>).
The module is controlled through two registers: ICxCON1
(Register 14-1) and ICxCON2 (Register 14-2). A general
block diagram of the module is shown in Figure 14-1.
FIGURE 14-1:
INPUT CAPTURE x BLOCK DIAGRAM
ICM<2:0>
ICI<1:0>
Edge Detect Logic
Set ICxIF
Prescaler
Counter
1:1/4/16
Event and
Interrupt
Logic
and
Clock Synchronizer
ICx Pin
ICTSEL<2:0>
Increment
16
Clock
Select
IC Clock
Sources
ICxTMR
4-Level FIFO Buffer
16
16
Reset
Trigger and
Sync Logic
Trigger and
Sync Sources
ICxBUF
SYNCSEL<4:0>
Trigger
System Bus
ICOV, ICBNE
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For 32-bit cascaded operations, the setup procedure is
slightly different:
14.1.2
CASCADED (32-BIT) MODE
By default, each module operates independently with
its own 16-bit timer. To increase resolution, adjacent
even and odd modules can be configured to function as
a single 32-bit module. (For example, Modules 1 and 2
are paired, as are Modules 3 and 4, and so on.) The
odd numbered module (ICx) provides the Least Signif-
icant 16 bits of the 32-bit register pairs, and the even
numbered module (ICy) provides the Most Significant
16 bits. Wraparounds of the ICx registers cause an
increment of their corresponding ICy registers.
1. Set the IC32 bits for both modules
(ICyCON2<8> and (ICxCON2<8>), enabling the
even numbered module first. This ensures the
modules will start functioning in unison.
2. Set the ICTSELx and SYNCSELx bits for both
modules to select the same Sync/trigger and
time base source. Set the even module first,
then the odd module. Both modules must use
the same ICTSELx and SYNCSELx bit settings.
3. Clear the ICTRIG bit of the even module
(ICyCON2<7>). This forces the module to run in
Synchronous mode with the odd module,
regardless of its trigger setting.
Cascaded operation is configured in hardware by
setting the IC32 bit (ICxCON2<8>) for both modules.
14.2 Capture Operations
4. Use the odd module’s ICIx bits (ICxCON1<6:5>)
to the desired interrupt frequency.
The input capture module can be configured to capture
timer values and generate interrupts on rising edges on
ICx or all transitions on ICx. Captures can be configured
to occur on all rising edges or just some (every 4th or
16th). Interrupts can be independently configured to
generate on each event or a subset of events.
5. Use the ICTRIG bit of the odd module
(ICxCON2<7>) to configure Trigger or
Synchronous mode operation.
Note:
For Synchronous mode operation, enable
the Sync source as the last step. Both
input capture modules are held in Reset
until the Sync source is enabled.
To set up the module for capture operations:
1. If Synchronous mode is to be used, disable the
Sync source before proceeding.
2. Make sure that any previous data has been
removed from the FIFO by reading ICxBUF until
the ICBNE bit (ICxCON1<3>) is cleared.
6. Use the ICMx bits of the odd module
(ICxCON1<2:0>) to set the desired capture
mode.
3. Set the SYNCSELx bits (ICxCON2<4:0>) to the
desired Sync/trigger source.
The module is ready to capture events when the time
base and the Sync/trigger source are enabled. When
the ICBNE bit (ICxCON1<3>) becomes set, at least
one capture value is available in the FIFO. Read input
capture values from the FIFO until the ICBNE clears
to ‘0’.
4. Set the ICTSELx bits (ICxCON1<12:10>) for
the desired clock source. If the desired clock
source is running, set the ICTSELx bits before
the input capture module is enabled, for proper
synchronization with the desired clock source.
For 32-bit operation, read both the ICxBUF and
ICyBUF for the full 32-bit timer value (ICxBUF for the
lsw, ICyBUF for the msw). At least one capture value is
available in the FIFO buffer when the odd module’s
ICBNE bit (ICxCON1<3>) becomes set. Continue to
read the buffer registers until ICBNE is cleared
(performed automatically by hardware).
5. Set the ICIx bits (ICxCON1<6:5>) to the desired
interrupt frequency.
6. Select Synchronous or Trigger mode operation:
a) Check that the SYNCSELx bits are not set
to ‘00000’.
b) For Synchronous mode, clear the ICTRIG
bit (ICxCON2<7>).
c) For Trigger mode, set ICTRIG and clear the
TRIGSTAT bit (ICxCON2<6>).
7. Set the ICMx bits (ICxCON1<2:0>) to the
desired operational mode.
8. Enable the selected Sync/trigger source.
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REGISTER 14-1: ICxCON1: INPUT CAPTURE x CONTROL REGISTER 1
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
ICSIDL
ICTSEL2
ICTSEL1
ICTSEL0
bit 15
bit 8
U-0
—
R/W-0
ICI1
R/W-0
ICI0
R-0, HSC
ICOV
R-0, HSC
ICBNE
R/W-0
ICM2
R/W-0
ICM1
R/W-0
ICM0
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13
Unimplemented: Read as ‘0’
ICSIDL: Input Capture x Module Stop in Idle Control bit
1= Input capture module halts in CPU Idle mode
0= Input capture module continues to operate in CPU Idle mode
bit 12-10
ICTSEL<2:0>: Input Capture x Timer Select bits
111= System clock (FOSC/2)
110= Reserved
101= Reserved
100= Timer1
011= Timer5
010= Timer4
001= Timer2
000= Timer3
bit 9-7
bit 6-5
Unimplemented: Read as ‘0’
ICI<1:0>: Select Number of Captures per Interrupt bits
11= Interrupt on every fourth capture event
10= Interrupt on every third capture event
01= Interrupt on every second capture event
00= Interrupt on every capture event
bit 4
ICOV: Input Capture x Overflow Status Flag bit (read-only)
1= Input capture overflow occurred
0= No input capture overflow occurred
bit 3
ICBNE: Input Capture x Buffer Empty Status bit (read-only)
1= Input capture buffer is not empty, at least one more capture value can be read
0= Input capture buffer is empty
bit 2-0
ICM<2:0>: Input Capture Mode Select bits
111= Interrupt mode: Input capture functions as an interrupt pin only when the device is in Sleep or
Idle mode (rising edge detect only, all other control bits are not applicable)
110= Unused (module disabled)
101= Prescaler Capture mode: Capture on every 16th rising edge
100= Prescaler Capture mode: Capture on every 4th rising edge
011= Simple Capture mode: Capture on every rising edge
010= Simple Capture mode: Capture on every falling edge
001= Edge Detect Capture mode: Capture on every edge (rising and falling); ICI<1:0 bits do not
control interrupt generation for this mode
000= Input capture module is turned off
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REGISTER 14-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
IC32
bit 15
bit 8
R/W-0
R/W-0, HS
TRIGSTAT
U-0
—
R/W-0
R/W-1
R/W-1
R/W-0
R/W-1
ICTRIG
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
bit 0
bit 7
Legend:
HS = Hardware Settable bit
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 15-9
bit 8
Unimplemented: Read as ‘0’
IC32: Cascade Two IC Modules Enable bit (32-bit operation)
1= ICx and ICy operate in cascade as a 32-bit module (this bit must be set in both modules)
0= ICx functions independently as a 16-bit module
bit 7
bit 6
ICTRIG: Input Capture x Sync/Trigger Select bit
1= Triggers ICx from source designated by the SYNCSELx bits
0= Synchronizes ICx with source designated by the SYNCSELx bits
TRIGSTAT: Timer Trigger Status bit
1= Timer source has been triggered and is running (set in hardware, can be set in software)
0= Timer source has not been triggered and is being held clear
bit 5
Unimplemented: Read as ‘0’
bit 4-0
SYNCSEL<4:0>: Trigger/Synchronization Source Selection bits
11111= Reserved
11110= Reserved
11101= Reserved
11100= CTMU(1)
11011= A/D(1)
11010= Comparator 3(1)
11001= Comparator 2(1)
11000= Comparator 1(1)
10111= Input Capture 4
10110= Input Capture 3
10101= Input Capture 2
10100= Input Capture 1
10011= Reserved
10010= Reserved
1000x= Reserved
01111= Timer5
01110= Timer4
01101= Timer3
01100= Timer2
01011= Timer1
01010= Input Capture 5
01001= Reserved
01000= Reserved
00111= Reserved
00110= Reserved
00101= Output Compare 5
00100= Output Compare 4
00011= Output Compare 3
00010= Output Compare 2
00001= Output Compare 1
00000= Not synchronized to any other module
Note 1: Use these inputs as trigger sources only and never as Sync sources.
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In Synchronous mode, the module begins performing
its compare or PWM operation as soon as its selected
clock source is enabled. Whenever an event occurs on
15.0 OUTPUT COMPARE WITH
DEDICATED TIMERS
the selected Sync source, the module’s internal
counter is reset. In Trigger mode, the module waits for
a Sync event from another internal module to occur
before allowing the counter to run.
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
Section 35. “Output Compare with
Dedicated Timer” (DS39723).
Free-Running mode is selected by default or any time
that the SYNCSELx bits (OCxCON2<4:0>) are set to
‘00000’. Synchronous or Trigger modes are selected
any time the SYNCSELx bits are set to any value
except ‘00000’. The OCTRIG bit (OCxCON2<7>)
selects either Synchronous or Trigger mode. Setting
this bit selects Trigger mode operation. In both modes,
the SYNCSELx bits determine the Sync/trigger source.
All devices in the PIC24FV32KA304 family feature
3 independent output compare modules. Each of these
modules offers a wide range of configuration and
operating options for generating pulse trains on internal
device events. Also, the modules can produce
Pulse-Width Modulated (PWM) waveforms for driving
power applications.
15.1.2
CASCADED (32-BIT) MODE
By default, each module operates independently with
its own set of 16-bit Timer and Duty Cycle registers. To
increase the range, adjacent even and odd numbered
modules can be configured to function as a single
32-bit module. (For example, Modules 1 and 2 are
paired, as are Modules 3 and 4, and so on.) The odd
numbered module (OCx) provides the Least Significant
16 bits of the 32-bit register pairs, and the even
numbered module (OCy) provides the Most Significant
16 bits. Wraparounds of the OCx registers cause an
increment of their corresponding OCy registers.
Key features of the output compare module include:
• Hardware-configurable for 32-bit operation in all
modes by cascading two adjacent modules
• Synchronous and Trigger modes of output
compare operation, with up to 21 user-selectable
Sync/trigger sources available
• Two separate Period registers (a main register,
OCxR, and a secondary register, OCxRS) for
greater flexibility in generating pulses of varying
widths
Cascaded operation is configured in hardware by setting
the OC32 bit (OCxCON2<8>) for both modules.
• Configurable for single pulse or continuous pulse
generation on an output event, or continuous
PWM waveform generation
• Up to 6 clock sources available for each module,
driving a separate internal 16-bit counter
15.1 General Operating Modes
15.1.1
SYNCHRONOUS AND TRIGGER
MODES
By default, the output compare module operates in a
Free-Running mode. The internal 16-bit counter,
OCxTMR, counts up continuously, wrapping around
from FFFFh to 0000h on each overflow, with its period
synchronized to the selected external clock source.
Compare or PWM events are generated each time a
match between the internal counter and one of the
Period registers occurs.
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FIGURE 15-1:
OUTPUT COMPARE x BLOCK DIAGRAM (16-BIT MODE)
DCBx
OCMx
OCINV
OCxCON1
OCxCON2
OCTRIS
FLTOUT
FLTTRIEN
FLTMD
ENFLTx
OCFLTx
OCTSELx
SYNCSELx
TRIGSTAT
TRIGMODE
OCTRIG
OCxR
OCx Pin
Match Event
Match Event
Comparator
Increment
Clock
Select
OC Clock
Sources
OC Output and
OCxTMR
Comparator
OCxRS
Fault Logic
Reset
OCFA/
OCFB/
CxOUT
Match Event
Trigger and
Sync Logic
Trigger and
Sync Sources
Reset
OCx Interrupt
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For 32-bit cascaded operation, these steps are also
necessary:
15.2 Compare Operations
In Compare mode (Figure 15-1), the output compare
module can be configured for single-shot or continuous
pulse generation. It can also repeatedly toggle an
output pin on each timer event.
1. Set the OC32 bits for both registers
(OCyCON2<8> and (OCxCON2<8>). Enable
the even numbered module first to ensure the
modules will start functioning in unison.
To set up the module for compare operations:
2. Clear the OCTRIG bit of the even module
(OCyCON2), so the module will run in
Synchronous mode.
1. Calculate the required values for the OCxR and
(for Double Compare modes) OCxRS Duty
Cycle registers:
3. Configure the desired output and Fault settings
for OCy.
a) Determine the instruction clock cycle time.
Take into account the frequency of the
external clock to the timer source (if one is
used) and the timer prescaler settings.
4. Force the output pin for OCx to the output state
by clearing the OCTRIS bit.
5. If Trigger mode operation is required, configure
the trigger options in OCx by using the OCTRIG
(OCxCON2<7>), TRIGSTAT (OCxCON2<6>)
and SYNCSELx (OCxCON2<4:0>) bits.
b) Calculate the time to the rising edge of the
output pulse relative to the timer start value
(0000h).
c) Calculate the time to the falling edge of the
pulse, based on the desired pulse width and
the time to the rising edge of the pulse.
6. Configure the desired Compare or PWM mode
of operation (OCM<2:0>) for OCy first, then for
OCx.
2. Write the rising edge value to OCxR and the
falling edge value to OCxRS.
Depending on the output mode selected, the module
holds the OCx pin in its default state and forces a
transition to the opposite state when OCxR matches
the timer. In Double Compare modes, OCx is forced
back to its default state when a match with OCxRS
occurs. The OCxIF interrupt flag is set after an OCxR
match in Single Compare modes and after each
OCxRS match in Double Compare modes.
3. For Trigger mode operations, set OCTRIG to
enable Trigger mode. Set or clear TRIGMODE
to configure the trigger operation and
TRIGSTAT to select a hardware or software
trigger. For Synchronous mode, clear OCTRIG.
4. Set the SYNCSEL<4:0> bits to configure the
trigger or synchronization source. If free-running
timer operation is required, set the SYNCSELx
bits to ‘00000’ (no Sync/trigger source).
Single-shot pulse events only occur once, but may be
repeated by simply rewriting the value of the
OCxCON1 register. Continuous pulse events continue
indefinitely until terminated.
5. Select the time base source with the
OCTSEL<2:0> bits. If the desired clock source is
running, set the OCTSEL<2:0> bits before the
output compare module is enabled for proper
synchronization with the desired clock source. If
necessary, set the TON bit for the selected timer
which enables the compare time base to count.
Synchronous mode operation starts as soon as
the synchronization source is enabled; Trigger
mode operation starts after a trigger source event
occurs.
6. Set the OCM<2:0> bits for the appropriate
compare operation (‘0xx’).
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4. Select
a
clock source by writing the
15.3 Pulse-Width Modulation (PWM)
Mode
OCTSEL2<2:0> (OCxCON<12:10>) bits.
5. Enable interrupts, if required, for the timer and
output compare modules. The output compare
interrupt is required for PWM Fault pin utilization.
In PWM mode, the output compare module can be
configured for edge-aligned or center-aligned pulse
waveform generation. All PWM operations are
double-buffered (buffer registers are internal to the
module and are not mapped into SFR space).
6. Select the desired PWM mode in the OCM<2:0>
(OCxCON1<2:0>) bits.
7. If a timer is selected as a clock source, set the
TMRy prescale value and enable the time base by
setting the TON (TxCON<15>) bit.
To configure the output compare module for
edge-aligned PWM operation:
1. Calculate the desired ON time and load it into
the OCxR register.
2. Calculate the desired period and load it into the
OCxRS register.
3. Select the current OCx as the synchronization
source by writing 0x1F to SYNCSEL<4:0>
(OCxCON2<4:0>) and ‘0’ to OCTRIG
(OCxCON2<7>).
FIGURE 15-2:
OUTPUT COMPARE x BLOCK DIAGRAM (DOUBLE-BUFFERED,
16-BIT PWM MODE)
OCxCON1
OCxCON2
OCMx
OCINV
OCTSELx
OCTRIS
FLTOUT
FLTTRIEN
FLTMD
SYNCSELx
TRIGSTAT
TRIGMODE
OCTRIG
OCxR and DCB<1:0>
Rollover/Reset
ENFLTx
OCFLTx
DCB<1:0>
OCxR and DCB<1:0> Buffers
OCx Pin
Comparator
Match
Event
Increment
Clock
Select
OC Clock
Sources
OC Output Timing
and Fault Logic
OCxTMR
Comparator
OCxRS Buffer
Rollover
Reset
OCFA/OCFB/CxOUT
Match
Event
Match Event
Trigger and
Sync Logic
Trigger and
Sync Sources
Rollover/Reset
OCxRS
OCx Interrupt
Reset
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15.3.1
PWM PERIOD
15.3.2
PWM DUTY CYCLE
In Edge-Aligned PWM mode, the period is specified by
the value of the OCxRS register. In Center-Aligned
PWM mode, the period of the synchronization source,
such as the Timers’ PRy, specifies the period. The
period in both cases can be calculated using
Equation 15-1.
The PWM duty cycle is specified by writing to the
OCxRS and OCxR registers. The OCxRS and OCxR
registers can be written to at any time, but the duty
cycle value is not latched until a period is complete.
This provides a double buffer for the PWM duty cycle
and is essential for glitchless PWM operation.
Some important boundary parameters of the PWM duty
cycle include:
EQUATION 15-1: CALCULATING THE PWM
PERIOD(1)
• Edge-Aligned PWM:
PWM Period = [Value + 1] x TCY x (Prescaler Value)
- If OCxR and OCxRS are loaded with 0000h,
the OCx pin will remain low (0% duty cycle).
Where:
- If OCxRS is greater than OCxR, the pin will
remain high (100% duty cycle).
Value = OCxRS in Edge-Aligned PWM mode
and can be PRy in Center-Aligned PWM mode
(if TMRy is the Sync source).
• Center-Aligned PWM (with TMRy as the
Sync source):
Note 1: Based on TCY = TOSC * 2; Doze mode and
- If OCxR, OCxRS and PRy are all loaded with
0000h, the OCx pin will remain low
(0% duty cycle).
PLL are disabled.
- If OCxRS is greater than PRy, the pin will go
high (100% duty cycle).
See Example 15-3 for PWM mode timing details.
Table 15-1 and Table 15-2 show example PWM
frequencies and resolutions for a device operating at
4 MIPS and 10 MIPS, respectively.
EQUATION 15-2: CALCULATION FOR MAXIMUM PWM RESOLUTION(1)
FCY
log10
(
)
FPWM • (Prescale Value)
bits
Maximum PWM Resolution (bits) =
log10(2)
Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
EQUATION 15-3: PWM PERIOD AND DUTY CYCLE CALCULATIONS(1)
1. Find the OCxRS register value for a desired PWM frequency of 52.08 kHz, where FOSC = 8 MHz with PLL (32 MHz device
clock rate) and a prescaler setting of 1:1 using Edge-Aligned PWM mode:
TCY = 2 • TOSC = 62.5 ns
PWM Period
PWM Period
19.2 s
= 1/PWM Frequency = 1/52.08 kHz = 19.2 s
= (OCxRS + 1) • TCY • (OCx Prescale Value)
= (OCxRS + 1) • 62.5 ns • 1
OCxRS
= 306
2. Find the maximum resolution of the duty cycle that can be used with a 52.08 kHz frequency and a 32 MHz device clock rate:
PWM Resolution = log10(FCY/FPWM)/log102) bits
= (log10(16 MHz/52.08 kHz)/log102) bits
= 8.3 bits
Note 1: Based on TCY = 2 * TOSC; Doze mode and PLL are disabled.
2011-2013 Microchip Technology Inc.
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The DCBx bits are intended for use with a clock source
15.4 Subcycle Resolution
identical to the system clock. When an OCx module
with enabled prescaler is used, the falling edge delay
caused by the DCBx bits will be referenced to the
system clock period, rather than the OCx module’s
period.
The DCBx bits (OCxCON2<10:9>) provide for resolu-
tion better than one instruction cycle. When used, they
delay the falling edge generated from a match event by
a portion of an instruction cycle.
For example, setting DCB<1:0> = 10causes the falling
edge to occur halfway through the instruction cycle in
which the match event occurs, instead of at the
beginning. These bits cannot be used when
OCM<2:0> = 001. When operating the module in PWM
mode (OCM<2:0> = 110or 111), the DCBx bits will be
double-buffered.
TABLE 15-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (FCY = 4 MHz)(1)
PWM Frequency
Prescaler Ratio
7.6 Hz
61 Hz
122 Hz
977 Hz
3.9 kHz
31.3 kHz
125 kHz
8
1
FFFFh
16
1
1
1
1
007Fh
7
1
001Fh
5
Period Value
FFFFh
16
7FFFh
15
0FFFh
12
03FFh
10
Resolution (bits)
Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
TABLE 15-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (FCY = 16 MHz)(1)
PWM Frequency
Prescaler Ratio
30.5 Hz
244 Hz
488 Hz
3.9 kHz
15.6 kHz
125 kHz
500 kHz
8
1
FFFFh
16
1
1
1
1
007Fh
7
1
001Fh
5
Period Value
FFFFh
16
7FFFh
15
0FFFh
12
03FFh
10
Resolution (bits)
Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
DS39995D-page 156
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REGISTER 15-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
OCSIDL
OCTSEL2
OCTSEL1
OCTSEL0
ENFLT2
ENFLT1
bit 15
bit 8
R/W-0
R/W-0, HSC R/W-0, HSC R/W-0, HSC
OCFLT2 OCFLT1 OCFLT0
R/W-0
R/W-0
OCM2(1)
R/W-0
OCM1(1)
R/W-0
OCM0(1)
ENFLT0
TRIGMODE
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-14
bit 13
Unimplemented: Read as ‘0’
OCSIDL: Output Compare x Stop in Idle Mode Control bit
1= Output Compare x halts in CPU Idle mode
0= Output Compare x continues to operate in CPU Idle mode
bit 12-10
OCTSEL<2:0>: Output Compare x Timer Select bits
111= System clock
110= Reserved
101= Reserved
100= Timer1
011= Timer5
010= Timer4
001= Timer3
000= Timer2
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
ENFLT2: Comparator Fault Input Enable bit
1= Comparator Fault input is enabled
0= Comparator Fault input is disabled
ENFLT1: OCFB Fault Input Enable bit
1= OCFB Fault input is enabled
0= OCFB Fault input is disabled
ENFLT0: OCFA Fault Input Enable bit
1= OCFA Fault input is enabled
0= OCFA Fault input is disabled
OCFLT2: PWM Comparator Fault Condition Status bit
1= PWM comparator Fault condition has occurred (this is cleared in hardware only)
0= PWM comparator Fault condition has not occurred (this bit is used only when OCM<2:0> = 111)
OCFLT1: PWM OCFB Fault Input Enable bit
1= PWM OCFB Fault condition has occurred (this is cleared in hardware only)
0= PWM OCFB Fault condition has not occurred (this bit is used only when OCM<2:0> = 111)
OCFLT0: PWM OCFA Fault Condition Status bit
1= PWM OCFA Fault condition has occurred (this is cleared in hardware only)
0= PWM OCFA Fault condition has not occurred (this bit is used only when OCM<2:0> = 111)
TRIGMODE: Trigger Status Mode Select bit
1= TRIGSTAT (OCxCON2<6>) is cleared when OCxRS = OCxTMR or in software
0= TRIGSTAT is only cleared by software
Note 1: The comparator module used for Fault input varies with the OCx module. OC1 and OC2 use
Comparator 1; OC3 and OC4 use Comparator 2; OC5 uses Comparator 3.
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REGISTER 15-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 (CONTINUED)
bit 2-0
OCM<2:0>: Output Compare x Mode Select bits(1)
111= Center-Aligned PWM mode on OCx
110= Edge-Aligned PWM mode on OCx
101= Double Compare Continuous Pulse mode: Initialize OCx pin low; toggle OCx state continuously
on alternate matches of OCxR and OCxRS
100= Double Compare Single-Shot mode: Initialize OCx pin low; toggle OCx state on matches of
OCxR and OCxRS for one cycle
011= Single Compare Continuous Pulse mode: Compare events continuously toggle the OCx pin
010= Single Compare Single-Shot mode: Initialize OCx pin high; compare event forces the OCx pin low
001= Single Compare Single-Shot mode: Initialize OCx pin low, compare event forces the OCx pin high
000= Output compare channel is disabled
Note 1: The comparator module used for Fault input varies with the OCx module. OC1 and OC2 use
Comparator 1; OC3 and OC4 use Comparator 2; OC5 uses Comparator 3.
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REGISTER 15-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
DCB1(3)
R/W-0
DCB0(3)
R/W-0
OC32
FLTMD
FLTOUT
FLTTRIEN
OCINV
bit 15
bit 8
R/W-0
R/W-0, HS
TRIGSTAT
R/W-0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
OCTRIG
OCTRIS
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
bit 0
bit 7
Legend:
HS = Hardware Settable bit
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 15
FLTMD: Fault Mode Select bit
1= Fault mode is maintained until the Fault source is removed and the corresponding OCFLTx bit is
cleared in software
0= Fault mode is maintained until the Fault source is removed and a new PWM period starts
bit 14
bit 13
bit 12
FLTOUT: Fault Out bit
1= PWM output is driven high on a Fault
0= PWM output is driven low on a Fault
FLTTRIEN: Fault Output State Select bit
1= Pin is forced to an output on a Fault condition
0= Pin I/O condition is unaffected by a Fault
OCINV: Output Compare x Invert bit
1= OCx output is inverted
0= OCx output is not inverted
bit 11
Unimplemented: Read as ‘0’
bit 10-9
DCB<1:0>: Output Compare x Pulse-Width Least Significant bits(3)
11= Delays OCx falling edge by 3/4 of the instruction cycle
10= Delays OCx falling edge by 1/2 of the instruction cycle
01= Delays OCx falling edge by 1/4 of the instruction cycle
00= OCx falling edge occurs at the start of the instruction cycle
bit 8
bit 7
bit 6
bit 5
OC32: Cascade Two Output Compare Modules Enable bit (32-bit operation)
1= Cascade module operation is enabled
0= Cascade module operation is disabled
OCTRIG: Output Compare x Sync/Trigger Select bit
1= Triggers OCx from source designated by the SYNCSELx bits
0= Synchronizes OCx with source designated by the SYNCSELx bits
TRIGSTAT: Timer Trigger Status bit
1= Timer source has been triggered and is running
0= Timer source has not been triggered and is being held clear
OCTRIS: Output Compare x Output Pin Direction Select bit
1= OCx pin is tri-stated
0= Output Compare x peripheral is connected to the OCx pin
Note 1: Do not use an output compare module as its own trigger source, either by selecting this mode or another
equivalent SYNCSELx setting.
2: Use these inputs as trigger sources only and never as Sync sources.
3: These bits affect the rising edge when OCINV = 1. The bits have no effect when the OCMx bits
(OCxCON1<2:0>) = 001.
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REGISTER 15-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 (CONTINUED)
bit 4-0
SYNCSEL<4:0>: Trigger/Synchronization Source Selection bits
11111= This output compare module(1)
11110= Reserved
11101= Reserved
11100= CTMU(2)
11011= A/D(2)
11010= Comparator 3(2)
11001= Comparator 2(2)
11000= Comparator 1(2)
10111= Input Capture 4(2)
10110= Input Capture 3(2)
10101= Input Capture 2(2)
10100= Input Capture 1(2)
100xx= Reserved
01111= Timer5
01110= Timer4
01101= Timer3
01100= Timer2
01011= Timer1
01010= Input Capture 5(2)
01001= Reserved
01000= Reserved
00111= Reserved
00110= Reserved
00101= Output Compare 5(1)
00100= Output Compare 4(1)
00011= Output Compare 3(1)
00010= Output Compare 2(1)
00001= Output Compare 1(1)
00000= Not synchronized to any other module
Note 1: Do not use an output compare module as its own trigger source, either by selecting this mode or another
equivalent SYNCSELx setting.
2: Use these inputs as trigger sources only and never as Sync sources.
3: These bits affect the rising edge when OCINV = 1. The bits have no effect when the OCMx bits
(OCxCON1<2:0>) = 001.
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To set up the SPI1 module for the Standard Master
mode of operation:
16.0 SERIAL PERIPHERAL
INTERFACE (SPI)
1. If using interrupts:
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
a) Clear the SPI1IF bit in the IFS0 register.
b) Set the SPI1IE bit in the IEC0 register.
intended to be a comprehensive reference
source. For more information on the Serial
Peripheral Interface, refer to the “PIC24F
Family Reference Manual”, Section 23.
“Serial Peripheral Interface (SPI)”
(DS39699).
c) Write the respective SPI1IPx bits in the
IPC2 register to set the interrupt priority.
2. Write the desired settings to the SPI1CON1 and
SPI1CON2 registers with the MSTEN bit
(SPI1CON1<5>) = 1.
3. Clear the SPIROV bit (SPI1STAT<6>).
The Serial Peripheral Interface (SPI) module is a
synchronous serial interface useful for communicating
with other peripheral or microcontroller devices. These
peripheral devices may be serial data EEPROMs, shift
registers, display drivers, A/D Converters, etc. The SPI
module is compatible with Motorola® SPI and SIOP
interfaces.
4. Enable SPI operation by setting the SPIEN bit
(SPI1STAT<15>).
5. Write the data to be transmitted to the SPI1BUF
register. Transmission (and reception) will start
as soon as data is written to the SPI1BUF
register.
To set up the SPI1 module for the Standard Slave mode
of operation:
The module supports operation in two buffer modes. In
Standard mode, data is shifted through a single serial
buffer. In Enhanced Buffer mode, data is shifted
through an 8-level FIFO buffer.
1. Clear the SPI1BUF register.
2. If using interrupts:
a) Clear the SPI1IF bit in the IFS0 register.
b) Set the SPI1IE bit in the IEC0 register.
Note:
Do not perform read-modify-write opera-
tions (such as bit-oriented instructions) on
the SPI1BUF register in either Standard or
Enhanced Buffer mode.
c) Write the respective SPI1IPx bits in the
IPC2 register to set the interrupt priority.
3. Write the desired settings to the SPI1CON1
and SPI1CON2 registers with the MSTEN bit
(SPI1CON1<5>) = 0.
The module also supports a basic framed SPI protocol
while operating in either Master or Slave mode. A total
of four framed SPI configurations are supported.
4. Clear the SMP bit.
The SPI serial interface consists of four pins:
5. If the CKE bit is set, then the SSEN bit
(SPI1CON1<7>) must be set to enable the SS1
pin.
• SDI1: Serial Data Input
• SDO1: Serial Data Output
• SCK1: Shift Clock Input or Output
• SS1: Active-Low Slave Select or Frame
Synchronization I/O Pulse
6. Clear the SPIROV bit (SPI1STAT<6>).
7. Enable SPI operation by setting the SPIEN bit
(SPI1STAT<15>).
The SPI module can be configured to operate using 2,
3 or 4 pins. In the 3-pin mode, SS1 is not used. In the
2-pin mode, both SDO1 and SS1 are not used.
Block diagrams of the module, in Standard and
Enhanced Buffer modes, are shown in Figure 16-1 and
Figure 16-2.
The devices of the PIC24FV32KA304 family offer two
SPI modules on a device.
Note:
In this section, the SPI modules are
referred to as SPIx. Special Function
Registers (SFRs) will follow a similar
notation. For example, SPI1CON1 or
SPI1CON2 refers to the control register
for the SPI1 module.
2011-2013 Microchip Technology Inc.
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FIGURE 16-1:
SPI1 MODULE BLOCK DIAGRAM (STANDARD BUFFER MODE)
SCK1
1:1 to 1:8
Secondary
Prescaler
1:1/4/16/64
Primary
Prescaler
FCY
SS1/FSYNC1
Sync
Control
Select
Edge
Control
Clock
SPI1CON1<1:0>
SPI1CON1<4:2>
Shift Control
SDO1
SDI1
Enable
Master Clock
bit 0
SPI1SR
Transfer
Transfer
SPI1BUF
Read SPI1BUF
Write SPI1BUF
16
Internal Data Bus
DS39995D-page 162
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To set up the SPI1 module for the Enhanced Buffer
Master (EBM) mode of operation:
To set up the SPI1 module for the Enhanced Buffer
Slave mode of operation:
1. If using interrupts:
1. Clear the SPI1BUF register.
2. If using interrupts:
a) Clear the SPI1IF bit in the IFS0 register.
b) Set the SPI1IE bit in the IEC0 register.
a) Clear the SPI1IF bit in the IFS0 register.
b) Set the SPI1IE bit in the IEC0 register.
c) Write the respective SPI1IPx bits in the
IPC2 register.
c) Write the respective SPI1IPx bits in the
IPC2 register to set the interrupt priority.
2. Write the desired settings to the SPI1CON1
and SPI1CON2 registers with the MSTEN bit
(SPI1CON1<5>) = 1.
3. Write the desired settings to the SPI1CON1 and
SPI1CON2 registers with the MSTEN bit
(SPI1CON1<5>) = 0.
3. Clear the SPIROV bit (SPI1STAT<6>).
4. Select Enhanced Buffer mode by setting the
SPIBEN bit (SPI1CON2<0>).
4. Clear the SMP bit.
5. If the CKE bit is set, then the SSEN bit must be
set, thus enabling the SS1 pin.
5. Enable SPI operation by setting the SPIEN bit
(SPI1STAT<15>).
6. Clear the SPIROV bit (SPI1STAT<6>).
6. Write the data to be transmitted to the SPI1BUF
register. Transmission (and reception) will start
as soon as data is written to the SPI1BUF
register.
7. Select Enhanced Buffer mode by setting the
SPIBEN bit (SPI1CON2<0>).
8. Enable SPI operation by setting the SPIEN bit
(SPI1STAT<15>).
FIGURE 16-2:
SPI1 MODULE BLOCK DIAGRAM (ENHANCED BUFFER MODE)
SCK1
1:1 to 1:8
Secondary
Prescaler
1:1/4/16/64
Primary
Prescaler
FCY
SS1/FSYNC1
Sync
Control
Control
Clock
Select
Edge
SPI1CON1<1:0>
SPI1CON1<4:2>
Shift Control
SDO1
SDI1
Enable
Master Clock
bit 0
SPI1SR
Transfer
Transfer
8-Level FIFO
Transmit Buffer
8-Level FIFO
Receive Buffer
SPI1BUF
Read SPI1BUF
Write SPI1BUF
16
Internal Data Bus
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REGISTER 16-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER
R/W-0
SPIEN
U-0
—
R/W-0
U-0
—
U-0
—
R-0, HSC
SPIBEC2
R-0, HSC
SPIBEC1
R-0, HSC
SPIBEC0
SPISIDL
bit 15
bit 8
bit 0
R-0, HSC R/C-0, HS R/W-0, HSC
SRMPT SPIROV SRXMPT
bit 7
R/W-0
R/W-0
R/W-0
R-0, HSC
SPITBF
R-0, HSC
SPIRBF
SISEL2
SISEL1
SISEL0
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit
U = Unimplemented bit, read as ‘0’
R = Readable bit
-n = Value at POR
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
SPIEN: SPIx Enable bit
1= Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins
0= Disables module
bit 14
bit 13
Unimplemented: Read as ‘0’
SPISIDL: SPIx Stop in Idle Mode bit
1= Discontinues module operation when device enters Idle mode
0= Continues module operation in Idle mode
bit 12-11
bit 10-8
Unimplemented: Read as ‘0’
SPIBEC<2:0>: SPIx Buffer Element Count bits (valid in Enhanced Buffer mode)
Master mode:
Number of SPI transfers pending.
Slave mode:
Number of SPI transfers unread.
bit 7
bit 6
SRMPT: SPIx Shift Register (SPIxSR) Empty bit (valid in Enhanced Buffer mode)
1= SPIx Shift register is empty and ready to send or receive
0= SPIx Shift register is not empty
SPIROV: SPIx Receive Overflow Flag bit
1= A new byte/word is completely received and discarded (the user software has not read the previous
data in the SPI1BUF register)
0= No overflow has occurred
bit 5
SRXMPT: SPIx Receive FIFO Empty bit (valid in Enhanced Buffer mode)
1= Receive FIFO is empty
0= Receive FIFO is not empty
bit 4-2
SISEL<2:0>: SPIx Buffer Interrupt Mode bits (valid in Enhanced Buffer mode)
111= Interrupt when SPIx transmit buffer is full (SPITBF bit is set)
110= Interrupt when last bit is shifted into SPIxSR; as a result, the TX FIFO is empty
101= Interrupt when the last bit is shifted out of SPIxSR; now the transmit is complete
100= Interrupt when one data byte is shifted into the SPIxSR; as a result, the TX FIFO has one open spot
011= Interrupt when SPIx receive buffer is full (SPIRBF bit is set)
010= Interrupt when SPIx receive buffer is 3/4 or more full
001= Interrupt when data is available in receive buffer (SRMPT bit is set)
000= Interrupt when the last data in the receive buffer is read; as a result, the buffer is empty (SRXMPT
bit is set)
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REGISTER 16-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED)
bit 1
SPITBF: SPIx Transmit Buffer Full Status bit
1= Transmit has not yet started, SPIxTXB is full
0= Transmit has started, SPIxTXB is empty
In Standard Buffer mode:
Automatically set in hardware when the CPU writes the SPIxBUF location, loading SPIxTXB. Automatically
cleared in hardware when the SPIx module transfers data from SPIxTXB to SPIxSR.
In Enhanced Buffer mode:
Automatically set in hardware when the CPU writes the SPIxBUF location, loading the last available buffer
location. Automatically cleared in hardware when a buffer location is available for a CPU write.
bit 0
SPIRBF: SPIx Receive Buffer Full Status bit
1= Receive is complete, SPIxRXB is full
0= Receive is not complete, SPIxRXB is empty
In Standard Buffer mode:
Automatically set in hardware when the SPIx transfers data from the SPIxSR to SPIxRXB. Automatically
cleared in hardware when the core reads the SPIxBUF location, reading SPIxRXB.
In Enhanced Buffer mode:
Automatically set in hardware when SPIx transfers data from SPIxSR to buffer, filling the last unread buffer
location. Automatically cleared in hardware when a buffer location is available for a transfer from SPIxSR.
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REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
SMP
R/W-0
CKE(1)
DISSCK
DISSDO
MODE16
bit 15
bit 8
R/W-0
SSEN
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MSTEN
SPRE2
SPRE1
SPRE0
PPRE1
PPRE0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12
Unimplemented: Read as ‘0’
DISSCK: Disable SCKx pin bit (SPIx Master modes only)
1= Internal SPIx clock is disabled, pin functions as an I/O
0= Internal SPIx clock is enabled
bit 11
bit 10
bit 9
DISSDO: Disables SDOx pin bit
1= SDOx pin is not used by the module; pin functions as an I/O
0= SDOx pin is controlled by the module
MODE16: Word/Byte Communication Select bit
1= Communication is word-wide (16 bits)
0= Communication is byte-wide (8 bits)
SMP: SPIx Data Input Sample Phase bit
Master mode:
1= Input data is sampled at the end of data output time
0= Input data is sampled at the middle of data output time
Slave mode:
SMP must be cleared when SPIx is used in Slave mode.
bit 8
bit 7
bit 6
bit 5
bit 4-2
CKE: Clock Edge Select bit(1)
1= Serial output data changes on transition from active clock state to Idle clock state (see bit 6)
0= Serial output data changes on transition from Idle clock state to active clock state (see bit 6)
SSEN: Slave Select Enable bit (Slave mode)
1= SSx pin is used for Slave mode
0= SSx pin is not used by the module; pin is controlled by port function
CKP: Clock Polarity Select bit
1= Idle state for clock is a high level; active state is a low level
0= Idle state for clock is a low level; active state is a high level
MSTEN: Master Mode Enable bit
1= Master mode
0= Slave mode
SPRE<2:0>: Secondary Prescale bits (Master mode)
111= Secondary prescale 1:1
110= Secondary prescale 2:1
.
.
.
000= Secondary prescale 8:1
Note 1: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed
SPI modes (FRMEN = 1).
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REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED)
bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode)
11= Primary prescale 1:1
10= Primary prescale 4:1
01= Primary prescale 16:1
00= Primary prescale 64:1
Note 1: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed
SPI modes (FRMEN = 1).
REGISTER 16-3: SPIxCON2: SPIx CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
FRMEN
SPIFSD
SPIFPOL
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
SPIFE
R/W-0
SPIBEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
bit 13
FRMEN: Framed SPIx Support bit
1= Framed SPIx support is enabled
0= Framed SPIx support is disabled
SPIFSD: SPIx Frame Sync Pulse Direction Control on SSx Pin bit
1= Frame Sync pulse input (slave)
0= Frame Sync pulse output (master)
SPIFPOL: SPIx Frame Sync Pulse Polarity bit (Frame mode only)
1= Frame Sync pulse is active-high
0= Frame Sync pulse is active-low
bit 12-2
bit 1
Unimplemented: Read as ‘0’
SPIFE: SPIx Frame Sync Pulse Edge Select bit
1= Frame Sync pulse coincides with the first bit clock
0= Frame Sync pulse precedes the first bit clock
bit 0
SPIBEN: SPIx Enhanced Buffer Enable bit
1= Enhanced buffer is enabled
0= Enhanced buffer is disabled (Legacy mode)
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EQUATION 16-1: RELATIONSHIP BETWEEN DEVICE AND SPIx CLOCK SPEED(1)
FCY
FSCK =
Primary Prescaler * Secondary Prescaler
Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
TABLE 16-1: SAMPLE SCKx FREQUENCIES(1,2)
Secondary Prescaler Settings
FCY = 16 MHz
1:1
2:1
4:1
6:1
8:1
Primary Prescaler Settings
1:1
4:1
Invalid
4000
1000
250
8000
2000
500
4000
1000
250
63
2667
667
167
42
2000
500
125
31
16:1
64:1
125
FCY = 5 MHz
Primary Prescaler Settings
1:1
4:1
5000
1250
313
78
2500
625
156
39
1250
313
78
833
208
52
625
156
39
16:1
64:1
20
13
10
Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
2: SCKx frequencies are indicated in kHz.
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17.2 Communicating as a Master in a
Single Master Environment
17.0 INTER-INTEGRATED
2
CIRCUIT™ (I C™)
The details of sending a message in Master mode
depends on the communication protocols for the device
being communicated with. Typically, the sequence of
events is as follows:
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on the
Inter-Integrated Circuit, refer to the
“PIC24F Family Reference Manual”,
Section 24. “Inter-Integrated Circuit™
(I2C™)” (DS39702).
1. Assert a Start condition on SDAx and SCLx.
2. Send the I2C device address byte to the slave
with a write indication.
3. Wait for and verify an Acknowledge from the
slave.
The Inter-Integrated Circuit (I2C™) module is a serial
interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial data EEPROMs, display drivers,
A/D Converters, etc.
4. Send the first data byte (sometimes known as
the command) to the slave.
5. Wait for and verify an Acknowledge from the
slave.
The I2C modules support these features:
6. Send the serial memory address low byte to the
slave.
• Independent master and slave logic
• 7-bit and 10-bit device addresses
• General call address, as defined in the I2C protocol
• Clock stretching to provide delays for the
processor to respond to a slave data request
• Both 100 kHz and 400 kHz bus specifications
• Configurable address masking
7. Repeat Steps 4 and 5, until all data bytes are
sent.
8. Assert a Repeated Start condition on SDAx and
SCLx.
9. Send the device address byte to the slave with
a read indication.
10. Wait for and verify an Acknowledge from the
slave.
• Multi-Master modes to prevent loss of messages
in arbitration
11. Enable master reception to receive serial
memory data.
• Bus Repeater mode, allowing the acceptance of
all messages as a slave, regardless of the
address
12. Generate an ACK or NACK condition at the end
of a received byte of data.
• Automatic SCL
13. Generate a Stop condition on SDAx and SCLx.
A block diagram of the module is shown in Figure 17-1.
17.1 Pin Remapping Options
The I2C modules are tied to a fixed pin. To allow flexi-
bility with peripheral multiplexing, the I2C1 module in
28-pin devices, can be reassigned to the alternate pins.
These alternate pins are designated as SCL1 and
SDA1 during device configuration.
Pin assignment is controlled by the I2CxSEL
Configuration bit. Programming this bit (= 0) multiplexes
the module to the SCL1 and SDA1 pins.
Note:
Throughout this section, references to
register and bit names that may be
associated with a specific I2C module are
referred to generically by the use of ‘x’ in
place of the specific module number. Thus,
“I2CxSTAT” might refer to the Receive
Status register for either I2C1 or I2C2.
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FIGURE 17-1:
I2C™ BLOCK DIAGRAM (I2C1 MODULE IS SHOWN)
Internal
Data Bus
I2C1RCV
Read
Shift
Clock
SCL1
SDA1
I2C1RSR
LSB
Address Match
Write
Read
Match Detect
I2C1MSK
Write
Read
I2C1ADD
Start and Stop
Bit Detect
Write
Start and Stop
Bit Generation
I2C1STAT
I2C1CON
Read
Write
Collision
Detect
Acknowledge
Generation
Read
Clock
Stretching
Write
Read
I2C1TRN
LSB
Shift Clock
Reload
Control
Write
Read
BRG Down Counter
TCY/2
I2C1BRG
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17.3 Setting Baud Rate When
Operating as a Bus Master
17.4 Slave Address Masking
The I2CxMSK register (Register 17-3) designates
address bit positions as “don’t care” for both 7-Bit and
10-Bit Addressing modes. Setting a particular bit
location (= 1) in the I2CxMSK register causes the slave
module to respond, whether the corresponding
address bit value is ‘0’ or ‘1’. For example, when
I2CxMSK is set to ‘00100000’, the slave module will
detect both addresses: ‘0000000’ and ‘00100000’.
To compute the Baud Rate Generator (BRG) reload
value, use Equation 17-1.
EQUATION 17-1: COMPUTING BAUD RATE
RELOAD VALUE(1)
FCY
FSCL = ---------------------------------------------------------------------
To enable address masking, the Intelligent Peripheral
Management Interface (IPMI) must be disabled by
clearing the IPMIEN bit (I2C1CON<11>).
FCY
I2CxBRG + 1 + -----------------------------
10 000 000
or
Note:
As a result of changes in the I2C protocol,
the addresses in Table 17-2 are reserved
and will not be Acknowledged in Slave
mode. This includes any address mask
settings that include any of these
addresses.
FCY
FCY
I2CxBRG = ----------- – ----------------------------- – 1
FSCL 10 000 000
Note 1: Based on FCY = FOSC/2; Doze mode and PLL
are disabled.
TABLE 17-1: I2C™ CLOCK RATES(1)
Required
I2CxBRG Value
Actual
FSCL
System
FSCL
FCY
(Decimal)
(Hexadecimal)
100 kHz
100 kHz
100 kHz
400 kHz
400 kHz
400 kHz
400 kHz
1 MHz
16 MHz
8 MHz
4 MHz
16 MHz
8 MHz
4 MHz
2 MHz
16 MHz
8 MHz
4 MHz
157
78
39
37
18
9
9D
4E
27
25
12
9
100 kHz
100 kHz
99 kHz
404 kHz
404 kHz
385 kHz
385 kHz
1.026 MHz
1.026 MHz
0.909 MHz
4
4
13
6
D
1 MHz
6
1 MHz
3
3
Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
TABLE 17-2: I2C™ RESERVED ADDRESSES(1)
Slave
Address
R/W
Bit
Description
0000 000
0000 000
0000 001
0000 010
0000 011
0000 1xx
1111 1xx
1111 0xx
0
1
x
x
x
x
x
x
General Call Address(2)
Start Byte
CBus Address
Reserved
Reserved
HS Mode Master Code
Reserved
10-Bit Slave Upper Byte(3)
Note 1: The address bits listed here will never cause an address match, independent of the address mask settings.
2: This address will be Acknowledged only if GCEN = 1.
3: A match on this address can only occur on the upper byte in 10-Bit Addressing mode.
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REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER
R/W-0
I2CEN
U-0
—
R/W-0
R/W-1, HC
SCLREL
R/W-0
R/W-0
A10M
R/W-0
R/W-0
SMEN
I2CSIDL
IPMIEN
DISSLW
bit 15
bit 8
R/W-0
GCEN
R/W-0
R/W-0
R/W-0, HC
ACKEN
R/W-0, HC
RCEN
R/W-0, HC
PEN
R/W-0, HC
RSEN
R/W-0, HC
SEN
STREN
ACKDT
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 15
I2CEN: I2Cx Enable bit
1= Enables the I2Cx module, and configures the SDAx and SCLx pins as serial port pins
0= Disables the I2Cx module; all I2C™ pins are controlled by port functions
bit 14
bit 13
Unimplemented: Read as ‘0’
I2CSIDL: I2Cx Stop in Idle Mode bit
1= Discontinues module operation when the device enters an Idle mode
0= Continues module operation in Idle mode
bit 12
SCLREL: SCLx Release Control bit (when operating as I2C slave)
1= Releases SCLx clock
0= Holds SCLx clock low (clock stretch)
If STREN = 1:
The bit is R/W (i.e., software may write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware is
clear at the beginning of the slave transmission. Hardware is clear at the end of slave reception.
If STREN = 0:
The bit is R/S (i.e., software may only write ‘1’ to release clock). Hardware is clear at the beginning of
slave transmission.
bit 11
bit 10
bit 9
IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit
1= IPMI Support mode is enabled; all addresses are Acknowledged
0= IPMI Support mode is disabled
A10M: 10-Bit Slave Addressing bit
1= I2CxADD is a 10-bit slave address
0= I2CxADD is a 7-bit slave address
DISSLW: Disable Slew Rate Control bit
1= Slew rate control is disabled
0= Slew rate control is enabled
bit 8
SMEN: SMBus Input Levels bit
1= Enables I/O pin thresholds compliant with the SMBus specification
0= Disables the SMBus input thresholds
bit 7
GCEN: General Call Enable bit (when operating as I2C slave)
1= Enables interrupt when a general call address is received in the I2CxRSR (module is enabled for
reception)
0= General call address is disabled
bit 6
STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave)
Used in conjunction with the SCLREL bit.
1= Enables software or receives clock stretching
0= Disables software or receives clock stretching
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REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)
bit 5
ACKDT: Acknowledge Data bit (when operating as I2C master; applicable during master receive)
Value that will be transmitted when the software initiates an Acknowledge sequence.
1= Sends NACK during Acknowledge
0= Sends ACK during Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit
(when operating as I2C master; applicable during master receive)
1= Initiates the Acknowledge sequence on the SDAx and SCLx pins, and transmits the ACKDT data bit;
hardware is clear at the end of the master Acknowledge sequence
0= Acknowledge sequence is not in progress
bit 3
RCEN: Receive Enable bit (when operating as I2C master)
1= Enables Receive mode for I2C; hardware is clear at the end of the eighth bit of the master receive
data byte
0= Receive sequence is not in progress
bit 2
bit 1
PEN: Stop Condition Enable bit (when operating as I2C master)
1= Initiates Stop condition on SDAx and SCLx pins; hardware is clear at end of master Stop sequence
0= Stop condition is not in progress
RSEN: Repeated Start Condition Enable bit (when operating as I2C master)
1= Initiates Repeated Start condition on SDAx and SCLx pins; hardware is clear at the end of the
master Repeated Start sequence
0= Repeated Start condition is not in progress
bit 0
SEN: Start Condition Enable bit (when operating as I2C master)
1= Initiates Start condition on SDAx and SCLx pins; hardware is clear at the end of the
master Start sequence
0= Start condition is not in progress
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REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER
R-0, HSC R-0, HSC
ACKSTAT TRSTAT
bit 15
U-0
—
U-0
—
U-0
—
R/C-0, HS
BCL
R-0, HSC
GCSTAT
R-0, HSC
ADD10
bit 8
bit 0
R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC
R-0, HSC
R/W
R-0, HSC
RBF
R-0, HSC
TBF
IWCOL
bit 7
I2COV
D/A
P
S
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit
U = Unimplemented bit, read as ‘0’
R = Readable bit
-n = Value at POR
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
ACKSTAT: Acknowledge Status bit
1= NACK was detected last
0= ACK was detected last
Hardware is set or clear at the end of Acknowledge.
bit 14
TRSTAT: Transmit Status bit
(when operating as I2C master; applicable to master transmit operation)
1= Master transmit is in progress (8 bits + ACK)
0= Master transmit is not in progress
Hardware is set at the beginning of the master transmission; hardware is clear at the end of slave Acknowledge.
bit 13-11
bit 10
Unimplemented: Read as ‘0’
BCL: Master Bus Collision Detect bit
1= A bus collision has been detected during a master operation
0= No collision
Hardware is set at the detection of a bus collision.
bit 9
bit 8
bit 7
bit 6
bit 5
GCSTAT: General Call Status bit
1= General call address was received
0= General call address was not received
Hardware is set when an address matches the general call address; hardware is clear at Stop detection.
ADD10: 10-Bit Address Status bit
1= 10-bit address was matched
0= 10-bit address was not matched
Hardware is set at a match of the 2nd byte of the matched 10-bit address; hardware is clear at Stop detection.
IWCOL: I2Cx Write Collision Detect bit
1= An attempt to write to the I2CxTRN register failed because the I2C module is busy
0= No collision
Hardware is set at an occurrence of a write to I2CxTRN while busy (cleared by software).
I2COV: I2Cx Receive Overflow Flag bit
1= A byte was received while the I2CxRCV register is still holding the previous byte
0= No overflow
Hardware is set at an attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
D/A: Data/Address bit (when operating as I2C slave)
1= Indicates that the last byte received was data
0= Indicates that the last byte received was the device address
Hardware is clear at a device address match; hardware is set by a write to I2CxTRN or by reception of a
slave byte.
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REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)
bit 4
bit 3
bit 2
bit 1
P: Stop bit
1= Indicates that a Stop bit has been detected last
0= Stop bit was not detected last
Hardware is set or cleared when a Start, Repeated Start or Stop is detected.
S: Start bit
1= Indicates that a Start (or Repeated Start) bit has been detected last
0= Start bit was not detected last
Hardware is set or clear when a Start, Repeated Start or Stop is detected.
R/W: Read/Write Information bit (when operating as I2C slave)
1= Read – indicates data transfer is output from the slave
0= Write – indicates data transfer is input to the slave
Hardware is set or clear after the reception of an I2C device address byte.
RBF: Receive Buffer Full Status bit
1= Receive is complete, I2CxRCV is full
0= Receive is not complete, I2CxRCV is empty
Hardware is set when I2CxRCV is written with a received byte; hardware is clear when the software reads
I2CxRCV.
bit 0
TBF: Transmit Buffer Full Status bit
1= Transmit is in progress, I2CxTRN is full
0= Transmit is complete, I2CxTRN is empty
Hardware is set when the software writes to I2CxTRN; hardware is clear at the completion of data
transmission.
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REGISTER 17-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
AMSK9
AMSK8
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
AMSK7
AMSK6
AMSK5
AMSK4
AMSK3
AMSK2
AMSK1
AMSK0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-10
bit 9-0
Unimplemented: Read as ‘0’
AMSK<9:0>: Mask for Address Bit x Select bits
1= Enables masking for bit x of an incoming message address; bit match is not required in this position
0= Disables masking for bit x; bit match is required in this position
REGISTER 17-4: PADCFG1: PAD CONFIGURATION CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
SMBUSDEL2 SMBUSDEL1
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5
Unimplemented: Read as ‘0’
SMBUSDEL2: SMBus SDA2 Input Delay Select bit
1= The I2C2 module is configured for a longer SMBus input delay (nominal 300 ns delay)
0= The I2C2 module is configured for a legacy input delay (nominal 150 ns delay)
bit 4
SMBUSDEL1: SMBus SDA1 Input Delay Select bit
1= The I2C1 module is configured for a longer SMBus input delay (nominal 300 ns delay)
0= The I2C1 module is configured for a legacy input delay (nominal 150 ns delay)
bit 3-0
Unimplemented: Read as ‘0’
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• Baud Rates Ranging from 1 Mbps to 15 bps at
16 MIPS
18.0 UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
• 4-Deep, First-In-First-Out (FIFO) Transmit Data
Buffer
• 4-Deep FIFO Receive Data Buffer
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on the Univer-
sal Asynchronous Receiver Transmitter,
refer to the “PIC24F Family Reference
Manual”, Section 21. “UART” (DS39708).
• Parity, Framing and Buffer Overrun Error
Detection
• Support for 9-Bit mode with Address Detect
(9th bit = 1)
• Transmit and Receive Interrupts
• Loopback mode for Diagnostic Support
• Support for Sync and Break Characters
• Supports Automatic Baud Rate Detection
• IrDA® Encoder and Decoder Logic
• 16x Baud Clock Output for IrDA Support
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules
available in this PIC24F device family. The UART is a
full-duplex, asynchronous system that can communicate
with peripheral devices, such as personal computers,
LIN/J2602, RS-232 and RS-485 interfaces. This module
also supports a hardware flow control option with the
UxCTS and UxRTS pins, and also includes an IrDA®
encoder and decoder.
A simplified block diagram of the UARTx is shown in
Figure 18-1. The UARTx module consists of these
important hardware elements:
• Baud Rate Generator
The primary features of the UART module are:
• Asynchronous Transmitter
• Asynchronous Receiver
• Full-Duplex, 8-Bit or 9-Bit Data Transmission
through the UxTX and UxRX Pins
Note:
Throughout this section, references to
register and bit names that may be asso-
ciated with a specific USART module are
referred to generically by the use of ‘x’ in
place of the specific module number.
Thus, “UxSTA” might refer to the USART
Status register for either USART1 or
USART2.
• Even, Odd or No Parity Options (for 8-bit data)
• One or Two Stop bits
• Hardware Flow Control Option with UxCTS and
UxRTS pins
• Fully Integrated Baud Rate Generator (IBRG) with
16-Bit Prescaler
FIGURE 18-1:
UARTx SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA®
UxBCLK
Hardware Flow Control
UARTx Receiver
UxRTS
UxCTS
UxRX
UARTx Transmitter
UxTX
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The maximum baud rate (BRGH = 0) possible is
FCY/16 (for UxBRG = 0) and the minimum baud rate
possible is FCY/(16 * 65536).
18.1 UARTx Baud Rate Generator
(BRG)
The UARTx module includes a dedicated 16-bit Baud
Rate Generator (BRG). The UxBRG register controls
the period of a free-running, 16-bit timer. Equation 18-1
provides the formula for computation of the baud rate
with BRGH = 0.
Equation 18-2 shows the formula for computation of
the baud rate with BRGH = 1.
EQUATION 18-2: UARTx BAUD RATE WITH
BRGH = 1(1)
EQUATION 18-1: UARTx BAUD RATE WITH
FCY
Baud Rate =
BRGH = 0(1)
4 • (UxBRG + 1)
FCY
FCY
4 • Baud Rate
Baud Rate =
– 1
UxBRG =
16 • (UxBRG + 1)
FCY
16 • Baud Rate
Note 1: Based on FCY = FOSC/2; Doze mode
– 1
UxBRG =
and PLL are disabled.
Note 1: Based on FCY = FOSC/2; Doze mode
The maximum baud rate (BRGH = 1) possible is FCY/4
(for UxBRG = 0) and the minimum baud rate possible
is FCY/(4 * 65536).
and PLL are disabled.
Example 18-1 provides the calculation of the baud rate
error for the following conditions:
Writing a new value to the UxBRG register causes the
BRG timer to be reset (cleared). This ensures the BRG
does not wait for a timer overflow before generating the
new baud rate.
• FCY = 4 MHz
• Desired Baud Rate = 9600
EXAMPLE 18-1:
BAUD RATE ERROR CALCULATION (BRGH = 0)(1)
Desired Baud Rate
= FCY/(16 (UxBRG + 1))
Solving for UxBRG value:
UxBRG
UxBRG
UxBRG
= ((FCY/Desired Baud Rate)/16) – 1
= ((4000000/9600)/16) – 1
= 25
Calculated Baud Rate = 4000000/(16 (25 + 1))
= 9615
Error
= (Calculated Baud Rate – Desired Baud Rate)
Desired Baud Rate
= (9615 – 9600)/9600
= 0.16%
Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
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18.2 Transmitting in 8-Bit Data Mode
18.5 Receiving in 8-Bit or 9-Bit Data
Mode
1. Set up the UARTx:
a) Write appropriate values for data, parity and
Stop bits.
1. Set up the UARTx (as described in Section 18.2
“Transmitting in 8-Bit Data Mode”).
b) Write appropriate baud rate value to the
UxBRG register.
2. Enable the UARTx.
3. A receive interrupt will be generated when one
or more data characters have been received, as
per interrupt control bit, URXISELx.
c) Set up transmit and receive interrupt enable
and priority bits.
2. Enable the UARTx.
4. Read the OERR bit to determine if an overrun
error has occurred. The OERR bit must be reset
in software.
3. Set the UTXEN bit (causes a transmit interrupt,
two cycles after being set).
5. Read UxRXREG.
4. Write the data byte to the lower byte of the
UxTXREG word. The value will be immediately
transferred to the Transmit Shift Register (TSR)
and the serial bit stream will start shifting out
with the next rising edge of the baud clock.
The act of reading the UxRXREG character will move
the next character to the top of the receive FIFO,
including a new set of PERR and FERR values.
5. Alternately, the data byte may be transferred
while UTXEN = 0 and then, the user may set
UTXEN. This will cause the serial bit stream to
begin immediately, because the baud clock will
start from a cleared state.
18.6 Operation of UxCTS and UxRTS
Control Pins
UARTx Clear-to-Send (UxCTS) and Request-to-Send
(UxRTS) are the two hardware-controlled pins that are
associated with the UARTx module. These two pins
allow the UARTx to operate in Simplex and Flow Con-
trol modes. They are implemented to control the
transmission and reception between the Data Terminal
Equipment (DTE). The UEN<1:0> bits in the UxMODE
register configure these pins.
6. A transmit interrupt will be generated as per
interrupt control bit, UTXISELx.
18.3 Transmitting in 9-Bit Data Mode
1. Set up the UARTx (as described in Section 18.2
“Transmitting in 8-Bit Data Mode”).
2. Enable the UARTx.
18.7 Infrared Support
3. Set the UTXEN bit (causes a transmit interrupt,
two cycles after being set).
The UARTx module provides two types of infrared
UARTx support: one is the IrDA clock output to support
an external IrDA encoder and decoder device (legacy
module support), and the other is the full implementation
of the IrDA encoder and decoder.
4. Write UxTXREG as a 16-bit value only.
5. A word write to UxTXREG triggers the transfer
of the 9-bit data to the TSR. The serial bit stream
will start shifting out with the first rising edge of
the baud clock.
As the IrDA modes require a 16x baud clock, they will
only work when the BRGH bit (UxMODE<3>) is ‘0’.
6. A transmit interrupt will be generated as per the
setting of control bit, UTXISELx.
18.7.1
EXTERNAL IrDA SUPPORT – IrDA
CLOCK OUTPUT
18.4 Break and Sync Transmit
Sequence
To support external IrDA encoder and decoder devices,
the UxBCLK pin (same as the UxRTS pin) can be
configured to generate the 16x baud clock. When
UEN<1:0> = 11, the UxBCLK pin will output the 16x
baud clock if the UARTx module is enabled; it can be
used to support the IrDA codec chip.
The following sequence will send a message frame
header made up of a Break, followed by an auto-baud
Sync byte.
1. Configure the UARTx for the desired mode.
18.7.2
BUILT-IN IrDA ENCODER AND
DECODER
2. Set UTXEN and UTXBRK – this sets up the
Break character.
3. Load the UxTXREG with a dummy character to
initiate transmission (value is ignored).
The UARTx has full implementation of the IrDA
encoder and decoder as part of the UARTx module.
The built-in IrDA encoder and decoder functionality is
enabled using the IREN bit (UxMODE<12>). When
enabled (IREN = 1), the receive pin (UxRX) acts as the
input from the infrared receiver. The transmit pin
(UxTX) acts as the output to the infrared transmitter.
4. Write ‘55h’ to UxTXREG – loads the Sync
character into the transmit FIFO.
5. After the Break has been sent, the UTXBRK bit
is reset by hardware. The Sync character now
transmits.
2011-2013 Microchip Technology Inc.
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REGISTER 18-1: UxMODE: UARTx MODE REGISTER
R/W-0
U-0
—
R/W-0
USIDL
R/W-0
IREN(1)
R/W-0
U-0
—
R/W-0(2)
UEN1
R/W-0(2)
UEN0
UARTEN
RTSMD
bit 15
bit 8
R/C-0, HC
WAKE
R/W-0
R/W-0, HC
ABAUD
R/W-0
RXINV
R/W-0
BRGH
R/W-0
R/W-0
R/W-0
LPBACK
PDSEL1
PDSEL0
STSEL
bit 7
bit 0
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
HC = Hardware Clearable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
R = Readable bit
-n = Value at POR
bit 15
UARTEN: UARTx Enable bit
1= UARTx is enabled: All UARTx pins are controlled by UARTx, as defined by UEN<1:0>
0= UARTx is disabled: All UARTx pins are controlled by port latches; UARTx power consumption is
minimal
bit 14
bit 13
Unimplemented: Read as ‘0’
USIDL: UARTx Stop in Idle Mode bit
1= Discontinues module operation when the device enters Idle mode
0= Continues module operation in Idle mode
bit 12
bit 11
IREN: IrDA® Encoder and Decoder Enable bit(1)
1= IrDA encoder and decoder are enabled
0= IrDA encoder and decoder are disabled
RTSMD: Mode Selection for UxRTS Pin bit
1= UxRTS pin is in Simplex mode
0= UxRTS pin is in Flow Control mode
bit 10
Unimplemented: Read as ‘0’
bit 9-8
UEN<1:0>: UARTx Enable bits(2)
11= UxTX, UxRX and UxBCLK pins are enabled and used; UxCTS pin is controlled by port latches
10= UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01= UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by port latches
00= UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by
port latches
bit 7
WAKE: Wake-up on Start Bit Detect During Sleep Mode Enable bit
1= UARTx will continue to sample the UxRX pin; interrupt is generated on the falling edge, bit is
cleared in hardware on the following rising edge
0= No wake-up is enabled
bit 6
bit 5
LPBACK: UARTx Loopback Mode Select bit
1= Enables Loopback mode
0= Loopback mode is disabled
ABAUD: Auto-Baud Enable bit
1= Enables baud rate measurement on the next character – requires reception of a Sync field (55h);
cleared in hardware upon completion
0= Baud rate measurement is disabled or completed
bit 4
RXINV: Receive Polarity Inversion bit
1= UxRX Idle state is ‘0’
0= UxRX Idle state is ‘1’
Note 1: This feature is is only available for the 16x BRG mode (BRGH = 0).
2: The bit availability depends on the pin availability.
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REGISTER 18-1: UxMODE: UARTx MODE REGISTER (CONTINUED)
bit 3
BRGH: High Baud Rate Enable bit
1= BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)
0= BRG generates 16 clocks per bit period (16x baud clock, Standard mode)
bit 2-1
PDSEL<1:0>: Parity and Data Selection bits
11= 9-bit data, no parity
10= 8-bit data, odd parity
01= 8-bit data, even parity
00= 8-bit data, no parity
bit 0
STSEL: Stop Bit Selection bit
1= Two Stop bits
0= One Stop bit
Note 1: This feature is is only available for the 16x BRG mode (BRGH = 0).
2: The bit availability depends on the pin availability.
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REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER
R/W-0
UTXISEL1
bit 15
R/W-0
R/W-0
U-0
—
R/W-0, HC
UTXBRK
R/W-0
R-0, HSC
UTXBF
R-1, HSC
TRMT
UTXINV
UTXISEL0
UTXEN
bit 8
R/W-0
URXISEL1
bit 7
R/W-0
R/W-0
R-1, HSC
RIDLE
R-0, HSC
PERR
R-0, HSC
FERR
R/C-0, HS
OERR
R-0, HSC
URXDA
URXISEL0
ADDEN
bit 0
Legend:
HC = Hardware Clearable bit
HS = Hardware Settable bit C = Clearable bit
HSC = Hardware Settable/Clearable bit
U = Unimplemented bit, read as ‘0’
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15,13
UTXISEL<1:0>: UARTx Transmission Interrupt Mode Selection bits
11= Reserved; do not use
10= Interrupt when a character is transferred to the Transmit Shift Register (TSR) and as a result, the
transmit buffer becomes empty
01= Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations
are completed
00= Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at
least one character open in the transmit buffer)
bit 14
UTXINV: IrDA® Encoder Transmit Polarity Inversion bit
If IREN = 0:
1= UxTX Idle ‘0’
0= UxTX Idle ‘1’
If IREN = 1:
1= UxTX Idle ‘1’
0= UxTX Idle ‘0’
bit 12
bit 11
Unimplemented: Read as ‘0’
UTXBRK: UARTx Transmit Break bit
1= Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
cleared by hardware upon completion
0= Sync Break transmission is disabled or completed
bit 10
UTXEN: UARTx Transmit Enable bit
1= Transmit is enabled; UxTX pin is controlled by UARTx
0= Transmit is disabled; any pending transmission is aborted and the buffer is reset. UxTX pin is
controlled by the PORT register.
bit 9
bit 8
UTXBF: UARTx Transmit Buffer Full Status bit (read-only)
1= Transmit buffer is full
0= Transmit buffer is not full, at least one more character can be written
TRMT: Transmit Shift Register Empty bit (read-only)
1= Transmit Shift Register is empty and the transmit buffer is empty (the last transmission has
completed)
0= Transmit Shift Register is not empty; a transmission is in progress or queued
bit 7-6
URXISEL<1:0>: UARTx Receive Interrupt Mode Selection bits
11= Interrupt is set on a RSR transfer, making the receive buffer full (i.e., has 4 data characters)
10= Interrupt is set on a RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters)
0x= Interrupt is set when any character is received and transferred from the RSR to the receive buffer;
receive buffer has one or more characters.
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REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
bit 5
bit 4
bit 3
bit 2
bit 1
ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1= Address Detect mode is enabled; if 9-bit mode is not selected, this does not take effect
0= Address Detect mode is disabled
RIDLE: Receiver Idle bit (read-only)
1= Receiver is Idle
0= Receiver is active
PERR: Parity Error Status bit (read-only)
1= Parity error has been detected for the current character (character at the top of the receive FIFO)
0= Parity error has not been detected
FERR: Framing Error Status bit (read-only)
1= Framing error has been detected for the current character (character at the top of the receive FIFO)
0= Framing error has not been detected
OERR: Receive Buffer Overrun Error Status bit (clear/read-only)
1= Receive buffer has overflowed
0= Receive buffer has not overflowed (clearing a previously set OERR bit (1 0transition) will reset
the receiver buffer and the RSR to the empty state)
bit 0
URXDA: UARTx Receive Buffer Data Available bit (read-only)
1= Receive buffer has data; at least one more characters can be read
0= Receive buffer is empty
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REGISTER 18-3: UxTXREG: UARTx TRANSMIT REGISTER
U-x
—
U-x
—
U-x
—
U-x
—
U-x
—
U-x
—
U-x
—
W-x
UTX8
bit 15
bit 8
W-x
W-x
W-x
W-x
W-x
W-x
W-x
W-x
UTX7
UTX6
UTX5
UTX4
UTX3
UTX2
UTX1
UTX0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-9
bit 8
Unimplemented: Read as ‘0’
UTX8: UARTx Data of the Transmitted Character bit (in 9-bit mode)
UTX<7:0>: UARTx Data of the Transmitted Character bits
bit 7-0
REGISTER 18-4: UxRXREG: UARTx RECEIVE REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R-0, HSC
URX8
bit 15
bit 8
R-0, HSC
URX7
R-0, HSC
URX6
R-0, HSC
URX5
R-0, HSC
URX4
R-0, HSC
URX3
R-0, HSC
URX2
R-0, HSC
URX1
R-0, HSC
URX0
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-9
bit 8
Unimplemented: Read as ‘0’
URX8: UARTx Data of the Received Character bit (in 9-bit mode)
URX<7:0>: UARTx Data of the Received Character bits
bit 7-0
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• BCD format for smaller software overhead
• Optimized for long-term battery operation
• User calibration of the 32.768 kHz clock
crystal/32K INTRC frequency with periodic
auto-adjust
19.0 REAL-TIME CLOCK AND
CALENDAR (RTCC)
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on the
Real-Time Clock and Calendar, refer to the
“PIC24F Family Reference Manual”,
Section 29. “Real-Time Clock and
Calendar (RTCC)” (DS39696).
• Optimized for long-term battery operation
• Fractional second synchronization
• Calibration to within ±2.64 seconds error per
month
• Calibrates up to 260 ppm of crystal error
• Ability to periodically wake-up external devices
without CPU intervention (external power control)
The RTCC provides the user with a Real-Time Clock
and Calendar (RTCC) function that can be calibrated.
• Power control output for external circuit control
• Calibration takes effect every 15 seconds
• Runs from any one of the following:
- External Real-Time Clock of 32.768 kHz
- Internal 31.25 kHz LPRC Clock
Key features of the RTCC module are:
• Operates in Deep Sleep mode
• Selectable clock source
• Provides hours, minutes and seconds using
24-hour format
- 50 Hz or 60 Hz External Input
• Visibility of one half second period
19.1 RTCC Source Clock
• Provides calendar – weekday, date, month
and year
The user can select between the SOSC crystal
oscillator, LPRC internal oscillator or an external
50 Hz/60 Hz power line input as the clock reference for
the RTCC module. This gives the user an option to trade
off system cost, accuracy and power consumption,
based on the overall system needs.
• Alarm-configurable for half a second, one second,
10 seconds, one minute, 10 minutes, one hour,
one day, one week, one month or one year
• Alarm repeat with decrementing counter
• Alarm with indefinite repeat chime
• Year 2000 to 2099 leap year correction
FIGURE 19-1:
RTCC BLOCK DIAGRAM
RTCC Clock Domain
CPU Clock Domain
RCFGCAL
Input from
SOSC/LPRC
Oscillator or
External Source
RTCC Prescalers
0.5 Sec
ALCFGRPT
YEAR
MTHDY
WKDYHR
RTCC Timer
RTCVAL
MINSEC
Alarm
Event
Comparator
Alarm Registers with Masks
Repeat Counter
ALMTHDY
ALWDHR
ALMINSEC
ALRMVAL
RTCOUT<1:0>
1s
RTCC
Interrupt
RTCC Interrupt Logic
Alarm Pulse
RTCC
Pin
Clock Source
RTCOE
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TABLE 19-2: ALRMVAL REGISTER
19.2 RTCC Module Registers
MAPPING
The RTCC module registers are organized into three
categories:
Alarm Value Register Window
ALRMPTR
<1:0>
• RTCC Control Registers
• RTCC Value Registers
• Alarm Value Registers
ALRMVAL<15:8> ALRMVAL<7:0>
00
01
10
11
ALRMMIN
ALRMWD
ALRMSEC
ALRMHR
19.2.1
REGISTER MAPPING
ALRMMNTH
PWCSTAB
ALRMDAY
PWCSAMP
To limit the register interface, the RTCC Timer and
Alarm Time registers are accessed through corre-
sponding register pointers. The RTCC Value Register
Window (RTCVALH and RTCVALL) uses the RTCPTR
bits (RCFGCAL<9:8>) to select the desired Timer
register pair (see Table 19-1).
Considering that the 16-bit core does not distinguish
between 8-bit and 16-bit read operations, the user must
be aware that when reading either the ALRMVALH or
ALRMVALL bytes, the ALRMPTR<1:0> value will be
decremented. The same applies to the RTCVALH or
RTCVALL bytes with the RTCPTR<1:0> being
decremented.
By writing the RTCVALH byte, the RTCC Pointer value,
the RTCPTR<1:0> bits decrement by one until they
reach ‘00’. Once they reach ‘00’, the MINUTES and
SECONDS value will be accessible through RTCVALH
and RTCVALL until the pointer value is manually
changed.
Note:
This only applies to read operations and
not write operations.
19.2.2
WRITE LOCK
TABLE 19-1: RTCVAL REGISTER MAPPING
In order to perform a write to any of the RTCC Timer
registers, the RTCWREN bit (RTCPWC<13>) must be
set (see Example 19-1).
RTCC Value Register Window
RTCPTR<1:0>
RTCVAL<15:8> RTCVAL<7:0>
Note:
To avoid accidental writes to the timer, it is
recommended that the RTCWREN bit
(RCFGCAL<13>) is kept clear at any
other time. For the RTCWREN bit to be
set, there is only one instruction cycle time
window allowed between the 55h/AA
sequence and the setting of RTCWREN.
Therefore, it is recommended that code
follow the procedure in Example 19-1.
00
01
10
11
MINUTES
WEEKDAY
MONTH
—
SECONDS
HOURS
DAY
YEAR
The Alarm Value Register Window (ALRMVALH
and ALRMVALL) uses the ALRMPTRx bits
(ALCFGRPT<9:8>) to select the desired Alarm
register pair (see Table 19-2).
19.2.3
SELECTING RTCC CLOCK SOURCE
By writing the ALRMVALH byte, the Alarm Pointer
value (ALRMPTR<1:0> bits) decrements by one until
they reach ‘00’. Once they reach ‘00’, the ALRMMIN
and ALRMSEC value will be accessible through
ALRMVALH and ALRMVALL, until the pointer value is
manually changed.
There are four reference source clock options that can
be selected for the RTCC using the RTCCSEL<1:0>
bits: 00= Secondary Oscillator, 01= LPRC, 10= 50 Hz
External Clock and 11= 60 Hz External Clock.
EXAMPLE 19-1:
SETTING THE RTCWREN BIT
asm volatile
asm volatile
asm volatile
asm volatile
asm volatile
asm volatile
asm volatile
asm volatile
asm volatile
asm volatile
(“push w7”);
(“push w8”);
(“disi #5”);
(“mov #0x55, w7”);
(“mov w7, _NVMKEY”);
(“mov #0xAA, w8”);
(“mov w8, _NVMKEY”);
(“bset _RCFGCAL, #13”);
(“pop w8”);
//set the RTCWREN bit
(“pop w7”);
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19.2.4
RTCC CONTROL REGISTERS
REGISTER 19-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1)
R/W-0
RTCEN(2)
U-0
—
R/W-0
R-0, HSC
RTCSYNC HALFSEC(3)
R-0, HSC
R/W-0
R/W-0
R/W-0
RTCWREN
RTCOE
RTCPTR1
RTCPTR0
bit 15
bit 8
R/W-0
CAL7
R/W-0
CAL6
R/W-0
CAL5
R/W-0
CAL4
R/W-0
CAL3
R/W-0
CAL2
R/W-0
CAL1
R/W-0
CAL0
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
RTCEN: RTCC Enable bit(2)
1= RTCC module is enabled
0= RTCC module is disabled
bit 14
bit 13
Unimplemented: Read as ‘0’
RTCWREN: RTCC Value Registers Write Enable bit
1= RTCVALH and RTCVALL registers can be written to by the user
0= RTCVALH and RTCVALL registers are locked out from being written to by the user
bit 12
RTCSYNC: RTCC Value Registers Read Synchronization bit
1= RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple
resulting in an invalid data read. If the register is read twice and results in the same data, the data
can be assumed to be valid.
0= RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple
bit 11
bit 10
bit 9-8
HALFSEC: Half Second Status bit(3)
1= Second half period of a second
0= First half period of a second
RTCOE: RTCC Output Enable bit
1= RTCC output is enabled
0= RTCC output is disabled
RTCPTR<1:0>: RTCC Value Register Window Pointer bits
Points to the corresponding RTCC Value registers when reading the RTCVALH and RTCVALL registers.
The RTCPTR<1:0> value decrements on every read or write of RTCVALH until it reaches ‘00’.
RTCVAL<15:8>:
00= MINUTES
01= WEEKDAY
10= MONTH
11= Reserved
RTCVAL<7:0>:
00= SECONDS
01= HOURS
10= DAY
11= YEAR
Note 1: The RCFGCAL register is only affected by a POR.
2: A write to the RTCEN bit is only allowed when RTCWREN = 1.
3: This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register.
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REGISTER 19-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) (CONTINUED)
bit 7-0
CAL<7:0>: RTC Drift Calibration bits
01111111= Maximum positive adjustment; adds 508 RTC clock pulses every one minute
.
.
.
00000001= Minimum positive adjustment; adds 4 RTC clock pulses every one minute
00000000= No adjustment
11111111= Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute
.
.
.
10000000= Maximum negative adjustment; subtracts 512 RTC clock pulses every one minute
Note 1: The RCFGCAL register is only affected by a POR.
2: A write to the RTCEN bit is only allowed when RTCWREN = 1.
3: This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register.
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REGISTER 19-2: RTCPWC: RTCC CONFIGURATION REGISTER 2(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PWCEN
PWCPOL
PWCCPRE PWCSPRE
RTCCLK1(2)
RTCCLK0(2)
RTCOUT1
RTCOUT0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11-10
PWCEN: Power Control Enable bit
1= Power control is enabled
0= Power control is disabled
PWCPOL: Power Control Polarity bit
1= Power control output is active-high
0= Power control output is active-low
PWCCPRE: Power Control Control/Stability Prescaler bits
1= PWC stability window clock is divide-by-2 of source RTCC clock
0= PWC stability window clock is divide-by-1 of source RTCC clock
PWCSPRE: Power Control Sample Prescaler bits
1= PWC sample window clock is divide-by-2 of source RTCC clock
0= PWC sample window clock is divide-by-1 of source RTCC clock
RTCCLK<1:0>: RTCC Clock Select bits(2)
Determines the source of the internal RTCC clock, which is used for all RTCC timer operations.
00= External Secondary Oscillator (SOSC)
01= Internal LPRC Oscillator
10= External power line source – 50 Hz
11= External power line source – 60 Hz
bit 9-8
bit 7-0
RTCOUT<1:0>: RTCC Output Select bits
Determines the source of the RTCC pin output.
00= RTCC alarm pulse
01= RTCC seconds clock
10= RTCC clock
11= Power control
Unimplemented: Read as ‘0’
Note 1: The RTCPWC register is only affected by a POR.
2: When a new value is written to these register bits, the Seconds Value register should also be written to
properly reset the clock prescalers in the RTCC.
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REGISTER 19-3: ALCFGRPT: ALARM CONFIGURATION REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ALRMEN
CHIME
AMASK3
AMASK2
AMASK1
AMASK0
ALRMPTR1 ALRMPTR0
bit 8
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ARPT7
ARPT6
ARPT5
ARPT4
ARPT3
ARPT2
ARPT1
ARPT0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
ALRMEN: Alarm Enable bit
1= Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0> = 00h and
CHIME = 0)
0= Alarm is disabled
bit 14
CHIME: Chime Enable bit
1= Chime is enabled; ARPT<7:0> bits are allowed to roll over from 00h to FFh
0= Chime is disabled; ARPT<7:0> bits stop once they reach 00h
bit 13-10
AMASK<3:0>: Alarm Mask Configuration bits
0000= Every half second
0001= Every second
0010= Every 10 seconds
0011= Every minute
0100= Every 10 minutes
0101= Every hour
0110= Once a day
0111= Once a week
1000= Once a month
1001= Once a year (except when configured for February 29th, once every 4 years)
101x= Reserved – do not use
11xx= Reserved – do not use
bit 9-8
ALRMPTR<1:0>: Alarm Value Register Window Pointer bits
Points to the corresponding Alarm Value registers when reading the ALRMVALH and ALRMVALL registers.
The ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches ‘00’.
ALRMVAL<15:8>:
00= ALRMMIN
01= ALRMWD
10= ALRMMNTH
11= Unimplemented
ALRMVAL<7:0>:
00= ALRMSEC
01= ALRMHR
10= ALRMDAY
11= Unimplemented
bit 7-0
ARPT<7:0>: Alarm Repeat Counter Value bits
11111111= Alarm will repeat 255 more times
.
.
.
00000000= Alarm will not repeat
The counter decrements on any alarm event; it is prevented from rolling over from 00h to FFh unless
CHIME = 1.
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19.2.5
RTCVAL REGISTER MAPPINGS
REGISTER 19-4: YEAR: YEAR VALUE REGISTER(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
YRTEN3
YRTEN2
YRTEN2
YRTEN1
YRONE3
YRONE2
YRONE1
YRONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-8
bit 7-4
Unimplemented: Read as ‘0’
YRTEN<3:0>: Binary Coded Decimal Value of Year’s Tens Digit bits
Contains a value from 0 to 9.
bit 3-0
YRONE<3:0>: Binary Coded Decimal Value of Year’s Ones Digit bits
Contains a value from 0 to 9.
Note 1: A write to the YEAR register is only allowed when RTCWREN = 1.
REGISTER 19-5: MTHDY: MONTH AND DAY VALUE REGISTER(1)
U-0
—
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
bit 15
bit 8
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
DAYTEN1
DAYTEN0
DAYONE3
DAYONE2
DAYONE1
DAYONE0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12
Unimplemented: Read as ‘0’
MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit
Contains a value of ‘0’ or ‘1’.
bit 11-8
MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits
Contains a value from 0 to 9.
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit bits
Contains a value from 0 to 3.
bit 3-0
DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits
Contains a value from 0 to 9.
Note 1: A write to this register is only allowed when RTCWREN = 1.
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REGISTER 19-6: WKDYHR: WEEKDAY AND HOURS VALUE REGISTER(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
WDAY2
WDAY1
WDAY0
bit 15
bit 8
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-11
bit 10-8
Unimplemented: Read as ‘0’
WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits
Contains a value from 0 to 6.
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits
Contains a value from 0 to 2.
bit 3-0
HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits
Contains a value from 0 to 9.
Note 1: A write to this register is only allowed when RTCWREN = 1.
REGISTER 19-7: MINSEC: MINUTES AND SECONDS VALUE REGISTER
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
bit 15
bit 8
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits
Contains a value from 0 to 5.
bit 11-8
MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits
Contains a value from 0 to 9.
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits
Contains a value from 0 to 5.
bit 3-0
SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits
Contains a value from 0 to 9.
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19.2.6
ALRMVAL REGISTER MAPPINGS
REGISTER 19-8: ALMTHDY: ALARM MONTH AND DAY VALUE REGISTER(1)
U-0
—
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
bit 15
bit 8
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
DAYTEN1
DAYTEN0
DAYONE3
DAYONE2
DAYONE1
DAYONE0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12
Unimplemented: Read as ‘0’
MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit
Contains a value of ‘0’ or ‘1’.
bit 11-8
MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits
Contains a value from 0 to 9.
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit bits
Contains a value from 0 to 3.
bit 3-0
DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits
Contains a value from 0 to 9.
Note 1: A write to this register is only allowed when RTCWREN = 1.
REGISTER 19-9: ALWDHR: ALARM WEEKDAY AND HOURS VALUE REGISTER(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
WDAY2
WDAY1
WDAY0
bit 15
bit 8
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-11
bit 10-8
Unimplemented: Read as ‘0’
WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits
Contains a value from 0 to 6.
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits
Contains a value from 0 to 2.
bit 3-0
HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits
Contains a value from 0 to 9.
Note 1: A write to this register is only allowed when RTCWREN = 1.
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REGISTER 19-10: ALMINSEC: ALARM MINUTES AND SECONDS VALUE REGISTER
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
bit 15
bit 8
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits
Contains a value from 0 to 5.
bit 11-8
MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits
Contains a value from 0 to 9.
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits
Contains a value from 0 to 5.
bit 3-0
SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits
Contains a value from 0 to 9.
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REGISTER 19-11: RTCCSWT: CONTROL/SAMPLE WINDOW TIMER REGISTER(1)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
PWCSTAB7 PWCSTAB6 PWCSTAB5 PWCSTAB4 PWCSTAB3 PWCSTAB2 PWCSTAB1 PWCSTAB0
bit 15 bit 8
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
PWCSAMP7 PWCSAMP6 PWCSAMP5 PWCSAMP4 PWCSAMP3 PWCSAMP2 PWCSAMP1 PWCSAMP0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
PWCSTAB<7:0>: PWM Stability Window Timer bits
11111111= Stability window is 255 TPWCCLK clock periods
.
.
.
00000000= Stability window is 0 TPWCCLK clock periods
The sample window starts when the alarm event triggers. The stability window timer starts counting
from every alarm event when PWCEN = 1.
bit 7-0
PWCSAMP<7:0>: PWM Sample Window Timer bits
11111111= Sample window is always enabled, even when PWCEN = 0
11111110= Sample window is 254 TPWCCLK clock periods
.
.
.
00000000= Sample window is 0 TPWCCLK clock periods
The sample window timer starts counting at the end of the stability window when PWCEN = 1. If
PWCSTAB<7:0> = 00000000, the sample window timer starts counting from every alarm event when
PWCEN = 1.
Note 1: A write to this register is only allowed when RTCWREN = 1.
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19.3 Calibration
19.4 Alarm
The real-time crystal input can be calibrated using the
periodic auto-adjust feature. When properly calibrated,
the RTCC can provide an error of less than 3 seconds
per month. This is accomplished by finding the number
of error clock pulses and storing the value into the
lower half of the RCFGCAL register. The 8-bit signed
value, loaded into the lower half of RCFGCAL, is multi-
plied by four and will be either added or subtracted from
the RTCC timer, once every minute. Refer to the steps
below for RTCC calibration:
• Configurable from half second to one year
• Enabled using the ALRMEN bit
(ALCFGRPT<15>)
• One-time alarm and repeat alarm options are
available
19.4.1
CONFIGURING THE ALARM
The alarm feature is enabled using the ALRMEN bit.
This bit is cleared when an alarm is issued. Writes to
ALRMVAL should only take place when ALRMEN = 0.
1. Using another timer resource on the device, the
user must find the error of the 32.768 kHz crystal.
As shown in Figure 19-2, the interval selection of the
alarm is configured through the AMASKx bits
(ALCFGRPT<13:10>). These bits determine which and
how many digits of the alarm must match the clock
value for the alarm to occur.
2. Once the error is known, it must be converted to
the number of error clock pulses per minute.
3. a) If the oscillator is faster than ideal (negative
result from Step 2), the RCFGCAL register value
must be negative. This causes the specified
number of clock pulses to be subtracted from
the timer counter, once every minute.
The alarm can also be configured to repeat based on a
preconfigured interval. The amount of times this
occurs, once the alarm is enabled, is stored in the
ARPT<7:0> bits (ALCFGRPT<7:0>). When the value
of the ARPTx bits equals 00h and the CHIME bit
(ALCFGRPT<14>) is cleared, the repeat function is
disabled, and only a single alarm will occur. The alarm
can be repeated up to 255 times by loading
ARPT<7:0> with FFh.
b) If the oscillator is slower than ideal (positive
result from Step 2), the RCFGCAL register value
must be positive. This causes the specified
number of clock pulses to be subtracted from
the timer counter, once every minute.
After each alarm is issued, the value of the ARPTx bits
is decremented by one. Once the value has reached
00h, the alarm will be issued one last time, after which,
the ALRMEN bit will be cleared automatically and the
alarm will turn off.
EQUATION 19-1:
(Ideal Frequency† – Measured Frequency) *
60 = Clocks per Minute
†
Ideal Frequency = 32,768 Hz
Writes to the lower half of the RCFGCAL register
should only occur when the timer is turned off, or
immediately after the rising edge of the seconds pulse,
except when SECONDS = 00, 15, 30 or 45. This is due
to the auto-adjust of the RTCC at 15 second intervals.
Indefinite repetition of the alarm can occur if the CHIME
bit = 1. Instead of the alarm being disabled when the value
of the ARPTx bits reaches 00h, it rolls over to FFh and
continues counting indefinitely while CHIME is set.
19.4.2
ALARM INTERRUPT
Note:
It is up to the user to include, in the error
value, the initial error of the crystal: drift
due to temperature and drift due to crystal
aging.
At every alarm event, an interrupt is generated. In
addition, an alarm pulse output is provided that
operates at half the frequency of the alarm. This output
is completely synchronous to the RTCC clock and can
be used as a trigger clock to other peripherals.
Note:
Changing any of the registers, other than
the RCFGCAL and ALCFGRPT registers,
and the CHIME bit while the alarm is
enabled (ALRMEN = 1), can result in a
false alarm event leading to a false alarm
interrupt. To avoid a false alarm event, the
timer and alarm values should only be
changed while the alarm is disabled
(ALRMEN = 0). It is recommended that
the ALCFGRPT register and CHIME bit be
changed when RTCSYNC = 0.
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FIGURE 19-2:
ALARM MASK SETTINGS
Day of
the
Week
Alarm Mask Setting
(AMASK<3:0>)
Month
Day
Hours
Minutes
Seconds
0000- Every half second
0001- Every second
0010- Every 10 seconds
0011- Every minute
0100- Every 10 minutes
0101- Every hour
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
m
m
m
m
m
m
m
m
m
m
m
0110- Every day
h
h
h
h
h
h
h
h
0111- Every week
1000- Every month
d
d
d
d
(1)
1001- Every year
m
m
d
Note 1: Annually, except when configured for February 29.
The polarity of the PWC control signal may be chosen
using the PWCPOL register bit. Active-low or
active-high may be used with the appropriate external
switch to turn on or off the power to one or more exter-
nal devices. The active-low setting may also be used in
conjunction with an open-drain setting on the RTCC
pin. This setting is able to drive the GND pin(s) of the
external device directly (with the appropriate external
VDD pull-up device), without the need for external
switches. Finally, the CHIME bit should be set to enable
the PWC periodicity.
19.5 POWER CONTROL
The RTCC includes a power control feature that allows
the device to periodically wake-up an external device,
wait for the device to be stable before sampling wake-up
events from that device and then shut down the external
device. This can be done completely autonomously by
the RTCC, without the need to wake from the current
low-power mode (Sleep, Deep Sleep, etc.).
To enable this feature, the RTCC must be enabled
(RTCEN = 1), the PWCEN register bit must be set and
the RTCC pin must be driving the PWC control signal
(RTCOE = 1and RTCOUT<1:0> = 11).
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NOTES:
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The programmable CRC generator provides
a
20.0 32-BIT PROGRAMMABLE
CYCLIC REDUNDANCY CHECK
(CRC) GENERATOR
hardware implemented method of quickly generating
checksums for various networking and security
applications. It offers the following features:
• User-programmable CRC polynomial equation,
up to 32 bits
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
Section 41. “32-Bit Programmable Cyclic
Redundancy Check (CRC)” (DS39729).
• Programmable shift direction (little or big-endian)
• Independent data and polynomial lengths
• Configurable interrupt output
• Data FIFO
A simplified block diagram of the CRC generator is
shown in Figure 20-1. A simple version of the CRC shift
engine is shown in Figure 20-2.
FIGURE 20-1:
CRC BLOCK DIAGRAM
CRCDATH
CRCDATL
FIFO Empty Event
Variable FIFO
(4x32, 8x16 or 16x8)
CRCISEL
2 * FCY Shift Clock
1
0
Shift Buffer
Set CRCIF
0 1
LENDIAN
Shift Complete Event
CRC Shift Engine
CRCWDATH
CRCWDATL
FIGURE 20-2:
CRC SHIFT ENGINE DETAIL
CRCWDATH
CRCWDATL
Read/Write Bus
(1)
(1)
(1)
X(1)
X(2)
X(n)
Shift Buffer
Data
(2)
Bit 0
Bit 1
Bit 2
Bit n
Note 1: Each XOR stage of the shift engine is programmable; see text for details.
2: Polynomial Length n is determined by ([PLEN<4:0>] + 1).
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The data for which the CRC is to be calculated must
20.1 User Interface
first be written into the FIFO. Even if the data width is
less than 8, the smallest data element that can be
written into the FIFO is one byte. For example, if the
DWIDTHx value is 5, then the size of the data is
DWIDTHx + 1 or 6. The data is written as a whole byte;
the two unused upper bits are ignored by the module.
20.1.1
POLYNOMIAL INTERFACE
The CRC module can be programmed for CRC
polynomials of up to the 32nd order, using up to 32 bits.
Polynomial length, which reflects the highest exponent
in the equation, is selected by the PLEN<4:0> bits
(CRCCON2<4:0>).
Once data is written into the MSb of the CRCDAT
registers (that is, MSb as defined by the data width),
the value of the VWORD<4:0> bits (CRCCON1<12:8>)
increments by one. For example, if the DWIDTHx value
is 24, the VWORDx bits will increment when bit 7 of
CRCDATH is written. Therefore, CRCDATL must
always be written before CRCDATH.
The CRCXORL and CRCXORH registers control which
exponent terms are included in the equation. Setting a
particular bit includes that exponent term in the
equation. Functionally, this includes an XOR operation
on the corresponding bit in the CRC engine. Clearing
this bit disables the XOR.
The CRC engine starts shifting data when the CRCGO
bit is set and the value of the VWORDx bits is greater
than zero. Each word is copied out of the FIFO into a
buffer register, which decrements VWORDx. The data
is then shifted out of the buffer. The CRC engine
continues shifting at a rate of two bits per instruction
cycle until the VWORDx value reaches zero. This
means that for a given data width, it takes half that
number of instructions for each word to complete the
calculation. For example, it takes 16 cycles to calculate
the CRC for a single word of 32-bit data.
For example, consider two CRC polynomials, one is a
16-bit equation and the other is a 32-bit equation:
x16 + x12 + x5 + 1
and
x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 +
x8 + x7 + x5 + x4 + x2 + x + 1
To program these polynomials into the CRC generator,
set the register bits, as shown in Table 20-1.
Note that the appropriate positions are set to ‘1’ to
indicate that they are used in the equation (for example,
X26 and X23). The 0 bit required by the equation is
always XORed; thus, X0 is a don’t care. For a
polynomial of length, N, it is assumed that the Nth bit will
always be used, regardless of the bit setting. Therefore,
for a polynomial length of 32, there is no 32nd bit in the
CRCXOR register.
When the VWORDx value reaches the maximum value
for the configured value of DWIDTHx (4, 8 or 16), the
CRCFUL bit becomes set. When the VWORDx value
reaches zero, the CRCMPT bit becomes set. The FIFO
is emptied and the VWORD<4:0> bits are set to
‘00000’ whenever CRCEN is ‘0’.
At least one instruction cycle must pass, after a write to
CRCDAT, before a read of the VWORDx bits is done.
20.1.2
DATA INTERFACE
The module incorporates a FIFO that works with a
variable data width. Input data width can be configured
to any value, between 1 and 32 bits, using the
DWIDTH<4:0> bits (CRCCON2<12:8>). When the
data width is greater than 15, the FIFO is 4 words deep.
When the DWIDTHx value is between 15 and 8, the
FIFO is 8 words deep. When the DWIDTHx value is
less than 8, the FIFO is 16 words deep.
TABLE 20-1:
CRC SETUP EXAMPLES FOR 16 AND 32-BIT POLYNOMIAL
Bit Values
CRC Control
Bits
16-Bit Polynomial
32-Bit Polynomial
PLEN<4:0>
X<31:16>
X<15:0>
01111
11111
0000 0000 0000 000x
0001 0000 0010 000x
0000 0100 1100 0001
0001 1101 1011 011x
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20.1.3
DATA SHIFT DIRECTION
20.2 Registers
The LENDIAN bit (CRCCON1<3>) is used to control
the shift direction. By default, the CRC will shift data
through the engine, MSb first. Setting LENDIAN (= 1)
causes the CRC to shift data, LSb first. This setting
allows better integration with various communication
schemes and removes the overhead of reversing the
bit order in software. Note that this only changes the
direction of the data that is shifted into the engine. The
result of the CRC calculation will still be a normal CRC
result, not a reverse CRC result.
There are eight registers associated with the module:
• CRCCON1
• CRCCON2
• CRCXORL
• CRCXORH
• CRCDATL
• CRCDATH
• CRCWDATL
• CRCWDATH
20.1.4
INTERRUPT OPERATION
The CRCCON1 and CRCCON2 registers (Register 20-1
and Register 20-2) control the operation of the module,
and configure the various settings. The CRCXOR
registers (Register 20-3 and Register 20-4) select the
polynomial terms to be used in the CRC equation. The
CRCDAT and CRCWDAT registers are each register
pairs that serve as buffers for the double-word, input
data and CRC processed output, respectively.
The module generates an interrupt that is configurable
by the user for either of two conditions. If CRCISEL is
‘0’, an interrupt is generated when the VWORD<4:0>
bits make a transition from a value of ‘1’ to ‘0’. If
CRCISEL is ‘1’, an interrupt will be generated after the
CRC operation finishes and the module sets the
CRCGO bit to ‘0’. Manually setting CRCGO to ‘0’ will
not generate an interrupt.
20.1.5
TYPICAL OPERATION
To use the module for a typical CRC calculation:
1. Set the CRCEN bit to enable the module.
2. Configure the module for the desired operation:
a) Program the desired polynomial using the
CRCXORL and CRCXORH registers, and
the PLEN<4:0> bits.
b) Configure the data width and shift direction
using the DWIDTHx and LENDIAN bits.
c) Select the desired interrupt mode using the
CRCISEL bit.
3. Preload the FIFO by writing to the CRCDATL
and CRCDATH registers until the CRCFUL bit is
set or no data is left.
4. Clear old results by writing 00h to CRCWDATL
and CRCWDATH. CRCWDAT can also be left
unchanged to resume a previously halted
calculation.
5. Set the CRCGO bit to start calculation.
6. Write the remaining data into the FIFO as space
becomes available.
7. When the calculation completes, CRCGO is
automatically cleared. An interrupt will be
generated if CRCISEL = 1.
8. Read CRCWDATL and CRCWDATH for the
result of the calculation.
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REGISTER 20-1: CRCCON1: CRC CONTROL REGISTER 1
R/W-0
U-0
—
R/W-0
CSIDL
R-0
R-0
R-0
R-0
R-0
CRCEN
VWORD4
VWORD3
VWORD2
VWORD1
VWORD0
bit 15
bit 8
R-0, HSC
CRCFUL
R-1, HSC
CRCMPT
R/W-0
R/W-0, HC
CRCGO
R/W-0
U-0
—
U-0
—
U-0
—
CRCISEL
LENDIAN
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
W = Writable bit
HSC = Hardware Settable/Clearable bit
U = Unimplemented bit, read as ‘0’
R = Readable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CRCEN: CRC Enable bit
1= Module is enabled
0= Module is enabled
All state machines, pointers and CRCWDAT/CRCDAT registers are reset; other SFRs are NOT reset.
bit 14
bit 13
Unimplemented: Read as ‘0’
CSIDL: CRC Stop in Idle Mode bit
1= Discontinues module operation when device enters Idle mode
0= Continues module operation in Idle mode
bit 12-8
bit 7
VWORD<4:0>: Pointer Value bits
Indicates the number of valid words in the FIFO, which has a maximum value of 8 when PLEN<4:0> > 7
or 16 when PLEN<4:0> 7.
CRCFUL: CRC FIFO Full bit
1= FIFO is full
0= FIFO is not full
bit 6
CRCMPT: CRC FIFO Empty Bit
1= FIFO is empty
0= FIFO is not empty
bit 5
CRCISEL: CRC interrupt Selection bit
1= Interrupt on FIFO is empty; CRC calculation is not complete
0= Interrupt on shift is complete and CRCWDAT result is ready
bit 4
CRCGO: Start CRC bit
1= Starts CRC serial shifter
0= CRC serial shifter is turned off
bit 3
LENDIAN: Data Shift Direction Select bit
1= Data word is shifted into the CRC, starting with the LSb (little endian)
0= Data word is shifted into the CRC, starting with the MSb (big endian)
bit 2-0
Unimplemented: Read as ‘0’
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REGISTER 20-2: CRCCON2: CRC CONTROL REGISTER 2
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DWIDTH4
DWIDTH3
DWIDTH2
DWIDTH1
DWIDTH0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PLEN4
PLEN3
PLEN2
PLEN1
PLEN0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
DWIDTH<4:0>: Data Width Select bits
Defines the width of the data word (Data Word Width = (DWIDTH<4:0>) + 1).
Unimplemented: Read as ‘0’
bit 7-5
bit 4-0
PLEN<4:0>: Polynomial Length Select bits
Defines the length of the CRC polynomial (Polynomial Length = (PLEN<4:0>) + 1).
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REGISTER 20-3: CRCXORL: CRC XOR POLYNOMIAL REGISTER, LOW BYTE
R/W-0
X15
R/W-0
X14
R/W-0
X13
R/W-0
X12
R/W-0
X11
R/W-0
X10
R/W-0
X9
R/W-0
X8
bit 15
bit 8
R/W-0
X7
R/W-0
X6
R/W-0
X5
R/W-0
X4
R/W-0
X3
R/W-0
X2
R/W-0
X1
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-1
bit 0
X<15:1>: XOR of Polynomial Term Xn Enable bits
Unimplemented: Read as ‘0’
REGISTER 20-4: CRCXORH: CRC XOR POLYNOMIAL REGISTER, HIGH BYTE
R/W-0
X31
R/W-0
X30
R/W-0
X29
R/W-0
X28
R/W-0
X27
R/W-0
X26
R/W-0
X25
R/W-0
X24
bit 15
bit 8
R/W-0
X23
R/W-0
X22
R/W-0
X21
R/W-0
X20
R/W-0
X19
R/W-0
X18
R/W-0
X17
R/W-0
X16
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
X<31:16>: XOR of Polynomial Term Xn Enable bits
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An interrupt flag is set if the device experiences an
21.0 HIGH/LOW-VOLTAGE DETECT
(HLVD)
excursion past the trip point in the direction of change.
If the interrupt is enabled, the program execution will
branch to the interrupt vector address and the software
can then respond to the interrupt.
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on the
High/Low-Voltage Detect, refer to the
“PIC24F Family Reference Manual”,
Section 36. “High-Level Integration
with Programmable High/Low-Voltage
Detect (HLVD)” (DS39725).
The HLVD Control register (see Register 21-1)
completely controls the operation of the HLVD module.
This allows the circuitry to be “turned off” by the user
under software control, which minimizes the current
consumption for the device.
The High/Low-Voltage Detect module (HLVD) is a
programmable circuit that allows the user to specify
both the device voltage trip point and the direction of
change.
FIGURE 21-1:
HIGH/LOW-VOLTAGE DETECT (HLVD) MODULE BLOCK DIAGRAM
Externally Generated
Trip Point
VDD
VDD
HLVDL<3:0>
HLVDIN
HLVDEN
VDIR
Set
HLVDIF
-
Internal Voltage
Reference
1.024V Typical
HLVDEN
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REGISTER 21-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER
R/W-0
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
HLVDEN
HLSIDL
bit 15
bit 8
R/W-0
VDIR
R/W-0
R/W-0
IRVST
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
BGVST
HLVDL3
HLVDL2
HLVDL1
HLVDL0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
HLVDEN: High/Low-Voltage Detect Power Enable bit
1= HLVD is enabled
0= HLVD is disabled
bit 14
bit 13
Unimplemented: Read as ‘0’
HLSIDL: HLVD Stop in Idle Mode bit
1= Discontinues module operation when device enters Idle mode
0= Continues module operation in Idle mode
bit 12-8
bit 7
Unimplemented: Read as ‘0’
VDIR: Voltage Change Direction Select bit
1= Event occurs when voltage equals or exceeds trip point (HLVDL<3:0>)
0= Event occurs when voltage equals or falls below trip point (HLVDL<3:0>)
bit 6
bit 5
BGVST: Band Gap Voltage Stable Flag bit
1= Indicates that the band gap voltage is stable
0= Indicates that the band gap voltage is unstable
IRVST: Internal Reference Voltage Stable Flag bit
1= Indicates that the internal reference voltage is stable and the high-voltage detect logic generates
the interrupt flag at the specified voltage range
0= Indicates that the internal reference voltage is unstable and the high-voltage detect logic will not
generate the interrupt flag at the specified voltage range, and the HLVD interrupt should not be
enabled
bit 4
Unimplemented: Read as ‘0’
bit 3-0
HLVDL<3:0>: High/Low-Voltage Detection Limit bits
1111= External analog input is used (input comes from the HLVDIN pin)
1110= Trip Point 1(1)
1101= Trip Point 2(1)
1100= Trip Point 3(1)
.
.
.
0000= Trip Point 15(1)
Note 1: For the actual trip point, see Section 29.0 “Electrical Characteristics”.
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The 12-bit A/D Converter module is an enhanced
22.0 12-BIT A/D CONVERTER WITH
version of the 10-bit module offered in some PIC24
devices. Both modules are Successive Approximation
Register (SAR) converters at their cores, surrounded
THRESHOLD DETECT
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on the 12-Bit
A/D Converter with Threshold Detect, refer
to the “PIC24F Family Reference Manual”,
Section 51. “12-Bit A/D Converter with
Threshold Detect” (DS39739).
by
a range of hardware features for flexible
configuration. This version of the module extends
functionality by providing 12-bit resolution, a wider
range of automatic sampling options and tighter
integration with other analog modules, such as the
CTMU and a configurable results buffer. This module
also includes a unique Threshold Detect feature that
allows the module itself to make simple decisions
based on the conversion results.
The PIC24F 12-bit A/D Converter has the following key
features:
A simplified block diagram for the module is illustrated
in Figure 22-1.
• Successive Approximation Register (SAR)
Conversion
• Conversion Speeds of up to 100 ksps
• Up to 32 Analog Input Channels (Internal and
External)
• Multiple Internal Reference Input Channels
• External Voltage Reference Input Pins
• Unipolar Differential Sample-and-Hold (S/H)
Amplifier
• Automated Threshold Scan and Compare
Operation to Pre-Evaluate Conversion Results
• Selectable Conversion Trigger Source
• Fixed-Length (one word per channel),
Configurable Conversion Result Buffer
• Four Options for Results Alignment
• Configurable Interrupt Generation
• Operation During CPU Sleep and Idle modes
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FIGURE 22-1:
12-BIT A/D CONVERTER BLOCK DIAGRAM
Internal
Data Bus
AVDD
AVSS
VREF+
VREF-
VBG
VR+
VR-
16
Comparator
VINH
VR- VR+
S/H
DAC
VINL
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
12-Bit SAR
Conversion Logic
Data Formatting
VINH
ADC1BUF0:
ADC1BUF17
AD1CON1
AD1CON2
AD1CON3
AD1CON5
AD1CHS
VINL
AD1CHITL
AD1CHITH
AD1CSSL
AD1CSSH
AN14
AN15
VINH
CTMU
Temp. Sensor
VINL
CTMU
VBG
Sample Control
Control Logic
Conversion Control
Input MUX Control
Pin Config. Control
0.785 * VDD
0.215 * VDD
AVDD
AVss
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To perform an A/D conversion:
1. Configure the A/D module:
To perform an A/D sample and conversion using
Threshold Detect scanning:
1. Configure the A/D module:
a) Configure the port pins as analog inputs
and/or select band gap reference inputs
(ANS<12:10>, ANS<5:0>).
a) Configure the port pins as analog inputs
(ANS<12:10>, ANS<5,0>).
b) Select voltage reference source to match
the expected range on the analog inputs
(AD1CON2<15:13>).
b) Select the voltage reference source to
match the expected range on the analog
inputs (AD1CON2<15:13>).
c) Select the analog conversion clock to
match the desired data rate with the
processor clock (AD1CON3<7:0>).
c) Select the analog conversion clock to
match the desired data rate with the
processor clock (AD1CON3<7:0>).
d) Select the appropriate sample/conver-
sion sequence (AD1CON1<7:4> and
AD1CON3<12:8>).
d) Select the appropriate sample/conversion
sequence (AD1CON1<7:4>, AD1CON3<12:8>).
e) Select how the conversion results are
presented in the buffer (AD1CON1<9:8>).
e) Select how conversion results are
presented in the buffer (AD1CON1<9:8>).
f) Select the interrupt rate (AD1CON2<6:2>).
2. Configure the threshold compare channels:
a) Enable auto-scan – ASEN bit (AD1CON5<15>).
f) Select the interrupt rate (AD1CON2<6:2>).
g) Turn on the A/D module (AD1CON1<15>).
2. Configure the A/D interrupt (if required):
a) Clear the AD1IF bit.
b) Select the Compare mode, “Greater Than,
Less Than or Windowed” – CMx bits
(AD1CON5<1:0>).
b) Select the A/D interrupt priority.
c) Select the threshold compare channels to
be scanned (ADCSSH, ADCSSL).
d) If the CTMU is required as a current
source for a threshold compare channel,
enable the corresponding CTMU channel
(ADCCTMUENH, ADCCTMUENL).
e) Write the threshold values into the
corresponding ADC1BUFn registers.
f) Turn on the A/D module (AD1CON1<15>).
Note:
If performing an A/D sample and
conversion using Threshold Detect in Sleep
Mode, the RC A/D clock source must be
selected before entering into Sleep mode.
3. Configure the A/D interrupt (OPTIONAL):
a) Clear the AD1IF bit.
b) Select the A/D interrupt priority.
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indicate if a match condition has occurred. AD1CHITL
is always implemented, whereas AD1CHITH may not
be implemented in devices with 16 or fewer channels.
22.1 A/D Control Registers
The 12-bit A/D Converter module uses up to
43 registers for its operation. All registers are mapped
in the data memory space.
The AD1CSSH/L registers (Register 22-8 and
Register 22-9) select the channels to be included for
sequential scanning.
22.1.1
CONTROL REGISTERS
The AD1CTMUENH/L registers (Register 22-10 and
Register 22-11) select the channel(s) to be used by the
CTMU during conversions. Selecting a particular
channel allows the A/D Converter to control the CTMU
(particularly, its current source) and read its data
through that channel. AD1CTMUENL is always
implemented, whereas AD1CTMUENH may not be
implemented in devices with 16 or fewer channels.
Depending on the specific device, the module has up to
eleven control and status registers:
• AD1CON1: A/D Control Register 1
• AD1CON2: A/D Control Register 2
• AD1CON3: A/D Control Register 3
• AD1CON5: A/D Control Register 5
• AD1CHS: A/D Sample Select Register
• AD1CHITH and AD1CHITL: A/D Scan Compare
Hit Registers
22.1.2
A/D RESULT BUFFERS
The module incorporates a multi-word, dual port RAM,
called ADC1BUF. The buffer is composed of at least
the same number of word locations as there are
external analog channels for a particular device, with a
maximum number of 32. The number of buffer
addresses is always even. Each of the locations is
mapped into the data memory space and is separately
addressable. The buffer locations are referred to as
ADC1BUF0 through ADC1BUFn (up to 31).
• AD1CSSL and AD1CSSH: A/D Input Scan Select
Registers
• AD1CTMUENH and AD1CTMUENL: CTMU
Enable Registers
The AD1CON1, AD1CON2 and AD1CON3 registers
(Register 22-1, Register 22-2 and Register 22-3)
control the overall operation of the A/D module. This
includes enabling the module, configuring the
conversion clock and voltage reference sources,
selecting the sampling and conversion triggers, and
manually controlling the sample/convert sequences.
The AD1CON5 register (Register 22-4) specifically
controls features of the Threshold Detect operation,
including its function in power-saving modes.
The A/D result buffers are both readable and writable.
When the module is active (AD1CON<15> = 1), the
buffers are read-only, and store the results of A/D
conversions. When the module is inactive
(AD1CON<15> = 0), the buffers are both readable and
writable. In this state, writing to a buffer location
programs a conversion threshold for Threshold Detect
operations.
The AD1CHS register (Register 22-5) selects the input
channels to be connected to the S/H amplifier. It also
allows the choice of input multiplexers and the
Buffer contents are not cleared when the module is
deactivated with the ADON bit (AD1CON1<15>).
Conversion results and any programmed threshold
values are maintained when ADON is set or cleared.
selection of
a
reference source for differential
sampling.
The
AD1CHITH and AD1CHITL registers
(Register 22-6 and Register 22-7) are semaphore
registers used with Threshold Detect operations. The
status of individual bits, or bit pairs in some cases,
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REGISTER 22-1: AD1CON1: A/D CONTROL REGISTER 1
R/W-0
ADON
U-0
—
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
ADSIDL
MODE12
FORM1
FORM0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
ASAM
R/W-0, HSC R/C-0, HSC
SAMP DONE
bit 0
SSRC3
SSRC2
SSRC1
SSRC0
bit 7
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
R = Readable bit
HSC = Hardware Settable/Clearable bit
-n = Value at POR
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
ADON: A/D Operating Mode bit
1= A/D Converter module is operating
0= A/D Converter is off
bit 14
bit 13
Unimplemented: Read as ‘0’
ADSIDL: A/D Stop in Idle Mode bit
1= Discontinues module operation when device enters Idle mode
0= Continues module operation in Idle mode
bit 12-11
bit 10
Unimplemented: Read as ‘0’
MODE12: 12-Bit Operation Mode bit
1= 12-bit A/D operation
0= 10-bit A/D operation
bit 9-8
bit 7-4
FORM<1:0>: Data Output Format bits (see the following formats)
11= Fractional result, signed, left-justified
10= Absolute fractional result, unsigned, left-justified
01= Decimal result, signed, right-justified
00= Absolute decimal result, unsigned, right-justified
SSRC<3:0>: Sample Clock Source Select bits
1111= Not available; do not use
1000= Not available; do not use
0111= Internal counter ends sampling and starts conversion (auto-convert)
0110= Not available; do not use
0101= Timer1 event ends sampling and starts conversion
0100= CTMU event ends sampling and starts conversion
0011= Timer5 event ends sampling and starts conversion
0010= Timer3 event ends sampling and starts conversion
0001= INT0 event ends sampling and starts conversion
0000= Clearing the SAMP bit in software ends sampling and begins conversion
bit 3
bit 2
Unimplemented: Read as ‘0’
ASAM: A/D Sample Auto-Start bit
1= Sampling begins immediately after the last conversion; SAMP bit is auto-set
0= Sampling begins when the SAMP bit is manually set
bit 1
bit 0
SAMP: A/D Sample Enable bit
1= A/D Sample-and-Hold amplifiers are sampling
0= A/D Sample-and-Hold amplifiers are holding
DONE: A/D Conversion Status bit
1= A/D conversion cycle has completed
0= A/D conversion cycle has not started or is in progress
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REGISTER 22-2: AD1CON2: A/D CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
PVCFG1
PVCFG0
NVCFG0
OFFCAL
BUFREGEN
CSCNA
bit 15
bit 8
R/W-0
BUFS(1)
R/W-0
SMPI4
R/W-0
SMPI3
R/W-0
SMPI2
R/W-0
SMPI1
R/W-0
SMPI0
R/W-0
BUFM(1)
R/W-0
ALTS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-14
PVCFG<1:0>: Converter Positive Voltage Reference Configuration bits
(2)
11= 4 * Internal VBG
(3)
10= 2 * Internal VBG
01= External VREF+
00= AVDD
bit 13
bit 12
bit 11
bit 10
NVCFG0: Converter Negative Voltage Reference Configuration bits
1= External VREF-
0= AVSS
OFFCAL: Offset Calibration Mode Select bit
1= Inverting and non-inverting inputs of channel Sample-and-Hold are connected to AVSS
0= Inverting and non-inverting inputs of channel Sample-and-Hold are connected to normal inputs
BUFREGEN: A/D Buffer Register Enable bit
1= Conversion result is loaded into a buffer location determined by the converted channel
0= A/D result buffer is treated as a FIFO
CSCNA: Scan Input Selections for CH0+ S/H Input for MUX A Setting bit
1= Scans inputs
0= Does not scan inputs
bit 9-8
bit 7
Unimplemented: Read as ‘0’
BUFS: Buffer Fill Status bit(1)
1= A/D is filling the upper half of the buffer; user should access data in the lower half
0= A/D is filling the lower half of the buffer; user should access data in the upper half
bit 6-2
SMPI<4:0>: Sample Rate Interrupt Select bits
11111= Interrupts at the completion of the conversion for each 32nd sample
11110= Interrupts at the completion of the conversion for each 31st sample
00001= Interrupts at the completion of the conversion for every other sample
00000= Interrupts at the completion of the conversion for each sample
bit 1
BUFM: Buffer Fill Mode Select bit(1)
1= Starts filling the buffer at address, AD1BUF0, on the first interrupt and AD1BUF(n/2) on the next
interrupt (Split Buffer mode)
0= Starts filling the buffer at address, ADCBUF0, and each sequential address on successive
interrupts (FIFO mode)
Note 1: This is only applicable when the buffer is used in FIFO mode (BUFREGEN = 0). In addition, BUFS is only
used when BUFM = 1.
2: The voltage reference setting will not be within the specification with VDD below 4.5V.
3: The voltage reference setting will not be within the specification with VDD below 2.3V.
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REGISTER 22-2: AD1CON2: A/D CONTROL REGISTER 2 (CONTINUED)
bit 0 ALTS: Alternate Input Sample Mode Select bit
1= Uses channel input selects for Sample A on the first sample and Sample B on the next sample
0= Always uses channel input selects for Sample A
Note 1: This is only applicable when the buffer is used in FIFO mode (BUFREGEN = 0). In addition, BUFS is only
used when BUFM = 1.
2: The voltage reference setting will not be within the specification with VDD below 4.5V.
3: The voltage reference setting will not be within the specification with VDD below 2.3V.
REGISTER 22-3: AD1CON3: A/D CONTROL REGISTER 3
R/W-0
ADRC
R-0
r-0
r
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EXTSAM
SAMC4
SAMC3
SAMC2
SAMC1
SAMC0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADCS7
ADCS6
ADCS5
ADCS4
ADCS3
ADCS2
ADCS1
ADCS0
bit 7
bit 0
Legend:
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
ADRC: A/D Conversion Clock Source bit
1= RC clock
0= Clock is derived from the system clock
EXTSAM: Extended Sampling Time bit
1= A/D is still sampling after SAMP = 0
0= A/D is finished sampling
bit 13
Reserved: Maintain as ‘0’
bit 12-8
SAMC<4:0>: Auto-Sample Time Select bits
11111= 31 TAD
00001= 1 TAD
00000= 0 TAD
bit 7-0
ADCS<7:0>: A/D Conversion Clock Select bits
11111111-01000000= Reserved
00111111= 64·TCY = TAD
00000001= 2·TCY = TAD
00000000= TCY = TAD
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REGISTER 22-4: AD1CON5: A/D CONTROL REGISTER 5
R/W-0
ASEN(1)
R/W-0
LPEN
R/W-0
R/W-0
r-0
r
U-0
—
R/W-0
R/W-0
CTMREQ
BGREQ
ASINT1
ASINT0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
WM1
R/W-0
WM0
R/W-0
CM1
R/W-0
CM0
bit 7
bit 0
Legend:
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
ASEN: Auto-Scan Enable bit(1)
1= Auto-scan is enabled
0= Auto-scan is disabled
LPEN: Low-Power Enable bit
1= Returns to Low-Power mode after scan
0= Remains in Full-Power mode after scan
CTMREQ: CTMU Request bit
1= CTMU is enabled when the A/D is enabled and active
0= CTMU is not enabled by the A/D
BGREQ: Band Gap Request bit
1= Band gap is enabled when the A/D is enabled and active
0= Band gap is not enabled by the A/D
bit 11
bit 10
bit 9-8
Reserved: Maintain as ‘0’
Unimplemented: Read as ‘0’
ASINT<1:0>: Auto-Scan (Threshold Detect) Interrupt Mode bits
11= Interrupt after a Threshold Detect sequence completed and a valid compare has occurred
10= Interrupt after a valid compare has occurred
01= Interrupt after a Threshold Detect sequence completed
00= No interrupt
bit 7-4
bit 3-2
Unimplemented: Read as ‘0’
WM<1:0>: Write Mode bits
11= Reserved
10= Auto-compare only (conversion results are not saved, but interrupts are generated when a valid
match, as defined by the CMx and ASINTx bits, occurs)
01= Convert and save (conversion results are saved to locations as determined by the register bits
when a match, as defined by the CMx bits, occurs)
00= Legacy operation (conversion data is saved to a location determined by the buffer register bits)
bit 1-0
CM<1:0>: Compare Mode bits
11= Outside Window mode (valid match occurs if the conversion result is outside of the window defined
by the corresponding buffer pair)
10= Inside Window mode (valid match occurs if the conversion result is inside the window defined by the
corresponding buffer pair)
01= Greater Than mode (valid match occurs if the result is greater than the value in the corresponding
buffer register)
00= Less Than mode (valid match occurs if the result is less than the value in the corresponding buffer
register)
Note 1: When using auto-scan with Threshold Detect (ASEN = 1), do not configure the sample clock source to
Auto-Convert mode (SSRCx = 7). Any other available SSRCx selection is valid. To use auto-convert as
the sample clock source (SSRCx = 7), make sure ASEN is cleared.
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REGISTER 22-5: AD1CHS: A/D SAMPLE SELECT REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH0NB2
CH0NB1
CH0NB0
CH0SB4
CH0SB3
CH0SB2
CH0SB1
CH0SB0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH0NA2
CH0NA1
CH0NA0
CH0SA4
CH0SA3
CH0SA2
CH0SA1
CH0SA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-13
CH0NB<2:0>: Sample B Channel 0 Negative Input Select bits
111= AN6(1)
110= AN5(2)
101= AN4
100= AN3
011= AN2
010= AN1
001= AN0
000= AVSS
bit 12-8
CH0SB<4:0>: S/H Amplifier Positive Input Select for MUX B Multiplexer Setting bits
11111= Unimplemented, do not use
11110= AVDD
11101= AVSS
11100= Upper guardband rail (0.785 * VDD)
11011= Lower guardband rail (0.215 * VDD)
11010= Internal Band Gap Reference (VBG)(3)
11001-10010= Unimplemented, do not use
10001= No channels are connected, all inputs are floating (used for CTMU)
10000= No channels are connected, all inputs are floating (used for CTMU temperature sensor input)
01111= AN15
01110= AN14
01101= AN13
01100= AN12
01011= AN11
01010= AN10
01001= AN9
01000= AN8(1)
00111= AN7(1)
00110= AN6(1)
00101= AN5(2)
00100= AN4
00011= AN3
00010= AN2
00001= AN1
00000= AN0
bit 7-5
bit 4-0
CH0NA<2:0>: Sample A Channel 0 Negative Input Select bits
The same definitions as for CHONB<2:0>.
CH0SA<4:0>: Sample A Channel 0 Positive Input Select bits
The same definitions as for CHONA<4:0>.
Note 1: This is implemented on 44-pin devices only.
2: This is implemented on 28-pin and 44-pin devices only.
3: The band gap value used for this input is 2x or 4x the internal VBG, which is selected when PVCFG<1:0> = 1x.
2011-2013 Microchip Technology Inc.
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REGISTER 22-6: AD1CHITH: A/D SCAN COMPARE HIT REGISTER (HIGH WORD)(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
CHH17
CHH16
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-2
bit 1-0
Unimplemented: Read as ‘0’.
CHH<17:16>: A/D Compare Hit bits
If CM<1:0> = 11:
1= A/D Result Buffer x has been written with data or a match has occurred
0= A/D Result Buffer x has not been written with data
For All Other Values of CM<1:0>:
1= A match has occurred on A/D Result Channel x
0= No match has occurred on A/D Result Channel x
Note 1: Unimplemented channels are read as ‘0’.
REGISTER 22-7: AD1CHITL: A/D SCAN COMPARE HIT REGISTER (LOW WORD)(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHH9
R/W-0
CHH8
CHH15
CHH14
CHH13
CHH12
CHH11
CHH10
bit 15
bit 8
R/W-0
CHH7
R/W-0
CHH6
R/W-0
CHH5
R/W-0
CHH4
R/W-0
CHH3
R/W-0
CHH2
R/W-0
CHH1
R/W-0
CHH0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-0
CHH<15:0>: A/D Compare Hit bits
If CM<1:0> = 11:
1= A/D Result Buffer x has been written with data or a match has occurred
0= A/D Result Buffer x has not been written with data
For all other values of CM<1:0>:
1= A match has occurred on A/D Result Channel x
0= No match has occurred on A/D Result Channel x
Note 1: Unimplemented channels are read as ‘0’.
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REGISTER 22-8: AD1CSSH: A/D INPUT SCAN SELECT REGISTER (HIGH WORD)(1)
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
CSS30
CSS29
CSS28
CSS27
CSS26
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
CSS17
CSS16
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
Unimplemented: Read as ‘0’
CSS<30:26>: A/D Input Scan Selection bits
bit 14-10
1= Includes corresponding channel for input scan
0= Skips channel for input scan
bit 9-2
bit 1-0
Unimplemented: Read as ‘0’
CSS<17:16>: A/D Input Scan Selection bits
1= Includes corresponding channel for input scan
0= Skips channel for input scan
Note 1: Unimplemented channels are read as ‘0’. Do not select unimplemented channels for sampling as
indeterminate results may be produced.
REGISTER 22-9: AD1CSSL: A/D INPUT SCAN SELECT REGISTER (LOW WORD)(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSS9
R/W-0
CSS8
bit 8
CSS15
CSS14
CSS13
CSS12
CSS11
CSS10
bit 15
R/W-0
CSS7
R/W-0
CSS6
R/W-0
CSS5
R/W-0
CSS4
R/W-0
CSS3
R/W-0
CSS2
R/W-0
CSS1
R/W-0
CSS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-0
CSS<15:0>: A/D Input Scan Selection bits
1= Includes corresponding ANx input for scan
0= Skips channel for input scan
Note 1: Unimplemented channels are read as ‘0’. Do not select unimplemented channels for sampling as
indeterminate results may be produced.
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REGISTER 22-10: AD1CTMUENH: A/D CTMU ENABLE REGISTER (HIGH WORD)(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
CTMEN17
CTMEN16
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-2
bit 1-0
Unimplemented: Read as ‘0’.
CTMEN<17:16>: CTMU Enabled During Conversion bits
1= CTMU is enabled and connected to the selected channel during conversion
0= CTMU is not connected to this channel
Note 1: Unimplemented channels are read as ‘0’.
REGISTER 22-11: AD1CTMUENL: A/D CTMU ENABLE REGISTER (LOW WORD)(1)
R/W-0
CTMEN15
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CTMEN14
CTMEN13
CTMEN12
CTMUEN11
CTMEN10
CTMEN9
CTMEN8
bit 8
R/W-0
CTMEN7
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CTMEN6
CTMEN5
CTMEN4
CTMEN3
CTMEN2
CTMEN1
CTMEN0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
CTMEN<15:0>: CTMU Enabled During Conversion bits
1= CTMU is enabled and connected to the selected channel during conversion
0= CTMU is not connected to this channel
Note 1: Unimplemented channels are read as ‘0’.
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sampling function must be completed prior to starting the
conversion. The internal holding capacitor will be in a
discharged state prior to each sample operation.
22.2 A/D Sampling Requirements
The analog input model of the 12-bit A/D Converter is
shown in Figure 22-2. The total sampling time for the
A/D is a function of the holding capacitor charge time.
At least 1 TAD time period should be allowed between
conversions for the sample time. For more details, see
Section 29.0 “Electrical Characteristics”.
For the A/D Converter to meet its specified accuracy, the
Charge Holding Capacitor (CHOLD) must be allowed to
fully charge to the voltage level on the analog input pin.
The Source (RS) impedance, the Interconnect (RIC)
impedance and the internal Sampling Switch (RSS)
impedance combine to directly affect the time required to
charge CHOLD. The combined impedance of the analog
sources must, therefore, be small enough to fully charge
the holding capacitor within the chosen sample time. To
minimize the effects of pin leakage currents on the
accuracy of the A/D Converter, the maximum recom-
mended Source impedance, RS, is 2.5 k. After the
analog input channel is selected (changed), this
EQUATION 22-1: A/D CONVERSION CLOCK
PERIOD
TAD = TCY(ADCS + 1)
TAD
– 1
ADCS =
TCY
Note:
Based on TCY = 2/FOSC; Doze mode
and PLL are disabled.
FIGURE 22-2:
12-BIT A/D CONVERTER ANALOG INPUT MODEL
RIC 250
Sampling
Switch
ANx
RSS
RSS 3 k
Rs
CHOLD
= 32 pF
CPIN
VA
ILEAKAGE
500 nA
VSS
Legend: CPIN
= Input Capacitance
= Threshold Voltage
VT
ILEAKAGE = Leakage Current at the Pin Due to
Various Junctions
= Interconnect Resistance
RIC
RSS
= Sampling Switch Resistance
CHOLD
= Sample-and-Hold Capacitance (from DAC)
Note: The CPIN value depends on the device package and is not tested. The effect of CPIN is negligible if Rs 5 k.
2011-2013 Microchip Technology Inc.
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• The first code transition occurs when the input
voltage is ((VR+) – (VR-))/4096 or 1.0 LSb.
22.3 Transfer Function
The transfer functions of the A/D Converter in 12-bit
resolution are shown in Figure 22-3. The difference of
the input voltages, (VINH – VINL), is compared to the
reference, ((VR+) – (VR-)).
• The 0000 0000 0001code is centered at
VR- + (1.5 * ((VR+) – (VR-))/4096).
• The ‘0010 0000 0000’ code is centered at
VREFL + (2048.5 * ((VR+) – (VR-))/4096).
• An input voltage less than
VR- + (((VR-) – (VR-))/4096)
converts as ‘0000 0000 0000’.
• An input voltage greater than
(VR-) + (4095((VR+) – (VR-))/4096)
converts as ‘1111 1111 1111’.
FIGURE 22-3:
12-BIT A/D TRANSFER FUNCTION
Output Code
(Binary (Decimal))
1111 1111 1111(4095)
1111 1111 1110(4094)
0010 0000 0011(2051)
0010 0000 0010(2050)
0010 0000 0001(2049)
0010 0000 0000(2048)
0001 1111 1111(2047)
0001 1111 1110(2046)
0001 1111 1101(2045)
0000 0000 0001(1)
0000 0000 0000(0)
Voltage Level
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conversions 11 bits wide. The signed decimal format
yields 12-bit and 10-bit values, respectively. The sign bit
22.4 Buffer Data Formats
The A/D conversions are fully differential 12-bit values
when MODE12 = 1(AD1CON1<10>) and 10-bit values
when MODE12 = 0. When absolute fractional or abso-
lute integer formats are used, the results are 12 or
10 bits wide, respectively. When signed decimal format-
ting is used, the conversion also includes a sign bit,
making 12-bit conversions 13 bits wide, and 10-bit
(bit 12 or bit 10) is sign-extended to fill the buffer. The
FORM<1:0> bits (AD1CON1<9:8>) select the format.
Figure 22-4 and Figure 22-5 show the data output
formats that can be selected. Table 22-1 through
Table 22-4 show the numerical equivalents for the
various conversion result codes.
FIGURE 22-4:
A/D OUTPUT DATA FORMATS (12-BIT)
RAM Contents:
Read to Bus:
d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
Integer
0
0
0
0
Signed Integer
Fractional (1.15)
s0 s0 s0 s0 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
0
0
0
0
0
0
0
Signed Fractional (1.15)
s0 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
TABLE 22-1: NUMERICAL EQUIVALENTS OF VARIOUS RESULT CODES:
12-BIT INTEGER FORMATS
12-Bit Differential
Output Code
(13-bit result)
16-Bit Integer Format/
Equivalent Decimal Value
16-Bit Signed Integer Format/
Equivalent Decimal Value
VIN/VREF
+4095/4096 0 1111 1111 1111
+4094/4096 0 1111 1111 1110
0000 1111 1111 1111
0000 1111 1111 1110
+4095
+4094
0000 1111 1111 1111
0000 1111 1111 1110
+4095
+4094
+1/4096
0/4096
0 1000 0000 0001
0 0000 0000 0000
1 0111 1111 1111
0000 0000 0000 0001
0000 0000 0000 0000
0000 0000 0000 0000
+1
0
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
+1
0
-1/4096
0
-1
-4095/4096 1 0000 0000 0001
-4096/4096 1 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0
0
1111 0000 0000 0001
1111 0000 0000 0000
-4095
-4096
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TABLE 22-2: NUMERICAL EQUIVALENTS OF VARIOUS RESULT CODES:
12-BIT FRACTIONAL FORMATS
16-Bit Fractional Format/
Equivalent Decimal Value
16-Bit Signed Fractional Format/
Equivalent Decimal Value
12-Bit
Output Code
VIN/VREF
+4095/4096 0 1111 1111 1111
+4094/4096 0 1111 1111 1110
1111 1111 1111 0000
1111 1111 1110 0000
0.999
0.998
0111 1111 1111 1000
0111 1111 1110 1000
0.999
0.998
+1/4096
0/4096
-1/4096
0 0000 0000 0001
0 0000 0000 0000
1 0111 1111 1111
0000 0000 0001 0000
0000 0000 0000 0000
0000 0000 0000 0000
0.001
0.000
0.000
0000 0000 0000 1000
0000 0000 0000 0000
1111 1111 1111 1000
0.001
0.000
-0.001
-4095/4096 1 0000 0000 0001
-4096/4096 1 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0.000
0.000
1000 0000 0000 1000
1000 0000 0000 0000
-0.999
-1.000
FIGURE 22-5:
A/D OUTPUT DATA FORMATS (10-BIT)
RAM Contents:
Read to Bus:
d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
Integer
0
0
0
0
0
0
Signed Integer
Fractional (1.15)
s0 s0 s0 s0 s0 s0 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
0
0
0
0
0
0
0
0
0
0
0
Signed Fractional (1.15)
s0 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
TABLE 22-3: NUMERICAL EQUIVALENTS OF VARIOUS RESULT CODES:
10-BIT INTEGER FORMATS
10-Bit Differential
Output Code
(11-bit result)
16-Bit Integer Format/
Equivalent Decimal Value
16-Bit Signed Integer Format/
Equivalent Decimal Value
VIN/VREF
+1023/1024
+1022/1024
011 1111 1111
011 1111 1110
0000 0011 1111 1111
0000 0011 1111 1110
1023
1022
0000 0001 1111 1111
0000 0001 1111 1110
1023
1022
+1/1024
0/1024
000 0000 0001
000 0000 0000
101 1111 1111
0000 0000 0000 0001
0000 0000 0000 0000
0000 0000 0000 0000
1
0
0
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1
0
-1/1024
-1
-1023/1024
-1024/1024
100 0000 0001
100 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0
0
1111 1110 0000 0001
1111 1110 0000 0000
-1023
-1024
DS39995D-page 222
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
TABLE 22-4: NUMERICAL EQUIVALENTS OF VARIOUS RESULT CODES:
10-BIT FRACTIONAL FORMATS
10-Bit Differential
Output Code
(11-bit result)
16-Bit Fractional Format/
Equivalent Decimal Value
16-Bit Signed Fractional Format/
Equivalent Decimal Value
VIN/VREF
+1023/1024
+1022/1024
011 1111 1111
011 1111 1110
1111 1111 1100 0000
1111 1111 1000 0000
0.999
0.998
0111 1111 1110 0000
0111 1111 1000 0000
0.999
0.998
+1/1024
0/1024
-1/1024
000 0000 0001
000 0000 0000
101 1111 1111
0000 0000 0100 0000
0000 0000 0000 0000
0000 0000 0000 0000
0.001
0.000
0.000
0000 0000 0010 0000
0000 0000 0000 0000
1111 1111 1110 0000
0.001
0.000
-0.001
-1023/1024
-1024/1024
100 0000 0001
100 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0.000
0.000
1000 0000 0010 0000
1000 0000 0000 0000
-0.999
-1.000
2011-2013 Microchip Technology Inc.
DS39995D-page 223
PIC24FV32KA304 FAMILY
NOTES:
DS39995D-page 224
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
The comparator outputs may be directly connected to
the CxOUT pins. When the respective COE equals ‘1’,
23.0 COMPARATOR MODULE
Note:
This data sheet summarizes the features
the I/O pad logic makes the unsynchronized output of
the comparator available on the pin.
of this group of PIC24F devices. It is not
intended to be a comprehensive refer-
ence source. For more information on the
Comparator module, refer to the “PIC24F
Family Reference Manual”, Section 46.
A simplified block diagram of the module is shown in
Figure 23-1. Diagrams of the possible individual
comparator configurations are shown in Figure 23-2.
Each comparator has its own control register,
CMxCON (Register 23-1), for enabling and configuring
its operation. The output and event status of all three
comparators is provided in the CMSTAT register
(Register 23-2).
“Scalable
(DS39734).
Comparator
Module”
The comparator module provides three dual input
comparators. The inputs to the comparator can be
configured to use any one of four external analog
inputs, as well as a voltage reference input from either
the internal band gap reference, divided by 2 (VBG/2),
or the comparator voltage reference generator.
FIGURE 23-1:
COMPARATOR x MODULE BLOCK DIAGRAM
CCH<1:0>
CREF
EVPOL<1:0>
CEVT
Trigger/Interrupt
Logic
CXINB
CXINC
CXIND
VBG/2
COE
CPOL
Input
Select
Logic
VIN-
C1
VIN+
C1OUT
Pin
COUT
CEVT
EVPOL<1:0>
CPOL
Trigger/Interrupt
Logic
COE
VIN-
C2
VIN+
C2OUT
Pin
COUT
CEVT
COUT
EVPOL<1:0>
CPOL
Trigger/Interrupt
Logic
COE
VIN-
CXINA
CVREF
C3
VIN+
C3OUT
Pin
2011-2013 Microchip Technology Inc.
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PIC24FV32KA304 FAMILY
FIGURE 23-2:
INDIVIDUAL COMPARATOR CONFIGURATIONS
Comparator Off
CON = 0, CREF = x, CCH<1:0> = xx
COE
VIN-
–
Cx
VIN+
Off (Read as ‘0’)
CxOUT
Pin
Comparator CxINB > CxINA Compare
Comparator CxINC > CxINA Compare
CON = 1, CREF = 0, CCH<1:0> = 00
CON = 1, CREF = 0, CCH<1:0> = 01
COE
COE
VIN-
VIN-
–
–
CXINC
CXINA
CXINB
Cx
Cx
VIN+
VIN+
CXINA
CxOUT
Pin
CxOUT
Pin
Comparator VBG > CxINA Compare
Comparator CxIND > CxINA Compare
CON = 1, CREF = 0, CCH<1:0> = 11
CON = 1, CREF = 0, CCH<1:0> = 10
COE
COE
COE
COE
VIN-
VIN-
–
VBG/2
CXINA
–
CXIND
CXINA
Cx
Cx
VIN+
VIN+
CxOUT
Pin
CxOUT
Pin
Comparator CxINB > CVREF Compare
CON = 1, CREF = 1, CCH<1:0> = 00
Comparator CxINC > CVREF Compare
CON = 1, CREF = 1, CCH<1:0> = 01
COE
VIN-
VIN-
–
–
CXINB
CVREF
CXINC
Cx
Cx
VIN+
VIN+
CVREF
CxOUT
Pin
CxOUT
Pin
Comparator CxIND > CVREF Compare
CON = 1, CREF = 1, CCH<1:0> = 10
Comparator VBG > CVREF Compare
CON = 1, CREF = 1, CCH<1:0> = 11
COE
VIN-
VIN-
–
VBG/2
–
CXIND
CVREF
Cx
Cx
VIN+
VIN+
CVREF
CxOUT
Pin
CxOUT
Pin
DS39995D-page 226
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PIC24FV32KA304 FAMILY
REGISTER 23-1: CMxCON: COMPARATOR x CONTROL REGISTERS
R/W-0
CON
R/W-0
COE
R/W-0
CPOL
R/W-0
U-0
—
U-0
—
R/W-0
CEVT
R-0
CLPWR
COUT
bit 15
bit 8
R/W-0
R/W-0
U-0
—
R/W-0
CREF
U-0
—
U-0
—
R/W-0
CCH1
R/W-0
CCH0
EVPOL1
EVPOL0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
CON: Comparator x Enable bit
1= Comparator is enabled
0= Comparator is disabled
COE: Comparator x Output Enable bit
1= Comparator output is present on the CxOUT pin
0= Comparator output is internal only
CPOL: Comparator x Output Polarity Select bit
1= Comparator output is inverted
0= Comparator output is not inverted
CLPWR: Comparator x Low-Power Mode Select bit
1= Comparator operates in Low-Power mode
0= Comparator does not operate in Low-Power mode
bit 11-10
bit 9
Unimplemented: Read as ‘0’
CEVT: Comparator x Event bit
1= Comparator event defined by EVPOL<1:0> has occurred; subsequent triggers and interrupts are
disabled until the bit is cleared
0= Comparator event has not occurred
bit 8
COUT: Comparator x Output bit
When CPOL = 0:
1= VIN+ > VIN-
0= VIN+ < VIN-
When CPOL = 1:
1= VIN+ < VIN-
0= VIN+ > VIN-
bit 7-6
EVPOL<1:0>: Trigger/Event/Interrupt Polarity Select bits
11= Trigger/event/interrupt is generated on any change of the comparator output (while CEVT = 0)
10= Trigger/event/interrupt is generated on the transition of the comparator output:
If CPOL = 0(non-inverted polarity):
High-to-low transition only.
If CPOL = 1(inverted polarity):
Low-to-high transition only.
01= Trigger/event/interrupt is generated on the transition of the comparator output
If CPOL = 0(non-inverted polarity):
Low-to-high transition only.
If CPOL = 1(inverted polarity):
High-to-low transition only.
00= Trigger/event/interrupt generation is disabled
Unimplemented: Read as ‘0’
bit 5
2011-2013 Microchip Technology Inc.
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REGISTER 23-1: CMxCON: COMPARATOR x CONTROL REGISTERS (CONTINUED)
bit 4
CREF: Comparator x Reference Select bits (non-inverting input)
1= Non-inverting input connects to the internal CVREF voltage
0= Non-inverting input connects to the CxINA pin
bit 3-2
bit 1-0
Unimplemented: Read as ‘0’
CCH<1:0>: Comparator x Channel Select bits
11= Inverting input of the comparator connects to VBG
10= Inverting input of the comparator connects to the CxIND pin
01= Inverting input of the comparator connects to the CxINC pin
00= Inverting input of the comparator connects to the CxINB pin
REGISTER 23-2: CMSTAT: COMPARATOR x MODULE STATUS REGISTER
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
R-0, HSC
C3EVT
R-0, HSC
C2EVT
R-0, HSC
C1EVT
CMIDL
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R-0, HSC
C3OUT
R-0, HSC
C2OUT
R-0, HSC
C1OUT
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
CMIDL: Comparator x Stop in Idle Mode bit
1= Comparator interrupts are disabled in Idle mode; enabled comparators remain operational
0= Continues operation of all enabled comparators in Idle mode
bit 14-11
bit 10
Unimplemented: Read as ‘0’
C3EVT: Comparator 3 Event Status bit (read-only)
Shows the current event status of Comparator 3 (CM3CON<9>).
C2EVT: Comparator 2 Event Status bit (read-only)
Shows the current event status of Comparator 2 (CM2CON<9>).
C1EVT: Comparator 1 Event Status bit (read-only)
Shows the current event status of Comparator 1 (CM1CON<9>).
Unimplemented: Read as ‘0’
bit 9
bit 8
bit 7-3
bit 2
C3OUT: Comparator 3 Output Status bit (read-only)
Shows the current output of Comparator 3 (CM3CON<8>).
C2OUT: Comparator 2 Output Status bit (read-only)
Shows the current output of Comparator 2 (CM2CON<8>).
C1OUT: Comparator 1 Output Status bit (read-only)
Shows the current output of Comparator 1 (CM1CON<8>).
bit 1
bit 0
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PIC24FV32KA304 FAMILY
24.1 Configuring the Comparator
Voltage Reference
24.0 COMPARATOR VOLTAGE
REFERENCE
The comparator voltage reference module is controlled
Note:
This data sheet summarizes the features
through the CVRCON register (Register 24-1). The
comparator voltage reference provides a range of
output voltages, with 32 distinct levels.
of this group of PIC24F devices. It is not
intended to be a comprehensive refer-
ence source. For more information on the
Comparator Voltage Reference, refer to
the “PIC24F Family Reference Manual”,
Section 20. “Comparator Module
Voltage Reference Module” (DS39709).
The comparator voltage reference supply voltage can
come from either VDD and VSS or the external VREF+
and VREF-. The voltage source is selected by the
CVRSS bit (CVRCON<5>).
The settling time of the comparator voltage reference
must be considered when changing the CVREF output.
FIGURE 24-1:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
CVRSS = 1
VREF+
AVDD
8R
R
CVRSS = 0
CVR<3:0>
CVREN
R
R
R
32 Steps
CVREF
R
R
R
8R
CVRSS = 1
VREF-
CVRSS = 0
AVSS
2011-2013 Microchip Technology Inc.
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REGISTER 24-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
CVR4
R/W-0
CVR3
R/W-0
CVR2
R/W-0
CVR1
R/W-0
CVR0
CVREN
CVROE
CVRSS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-8
bit 7
Unimplemented: Read as ‘0’
CVREN: Comparator Voltage Reference Enable bit
1= CVREF circuit is powered on
0= CVREF circuit is powered down
bit 6
CVROE: Comparator VREF Output Enable bit
1= CVREF voltage level is output on the CVREF pin
0= CVREF voltage level is disconnected from the CVREF pin
bit 5
CVRSS: Comparator VREF Source Selection bit
1= Comparator reference source, CVRSRC = VREF+ – VREF-
0= Comparator reference source, CVRSRC = AVDD – AVSS
bit 4-0
CVR<4:0>: Comparator VREF Value Selection 0 ≤ CVR<4:0> ≤ 31 bits
When CVRSS = 1:
CVREF = (VREF-) + (CVR<4:0>/32) • (VREF+ – VREF-)
When CVRSS = 0:
CVREF = (AVSS) + (CVR<4:0>/32) • (AVDD – AVSS)
DS39995D-page 230
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
25.1 Measuring Capacitance
25.0 CHARGE TIME
MEASUREMENT UNIT (CTMU)
The CTMU module measures capacitance by
generating an output pulse, with a width equal to the
time between edge events, on two separate input
channels. The pulse edge events to both input
channels can be selected from several internal
peripheral modules (OC1, Timer1, any input capture or
comparator module) and up to 13 external pins
(CTED1 through CTED13). This pulse is used with the
module’s precision current source to calculate
capacitance according to the relationship:
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on the
Charge Measurement Unit, refer to the
“PIC24F Family Reference Manual”,
Section 53. “Charge Time Measurement
Unit (CTMU) with Threshold Detect”
(DS39743).
EQUATION 25-1:
The Charge Time Measurement Unit (CTMU) is a
flexible analog module that provides charge
measurement, accurate differential time measurement
between pulse sources and asynchronous pulse
generation. Its key features include:
dV
dT
------
I = C
For capacitance measurements, the A/D Converter
samples an external capacitor (CAPP) on one of its
input channels after the CTMU output’s pulse. A Preci-
sion Resistor (RPR) provides current source calibration
on a second A/D channel. After the pulse ends, the
converter determines the voltage on the capacitor. The
actual calculation of capacitance is performed in
software by the application.
• Thirteen external edge input trigger sources
• Polarity control for each edge source
• Control of edge sequence
• Control of response to edge levels or edge
transitions
• Time measurement resolution of one nanosecond
• Accurate current source suitable for capacitive
measurement
Figure 25-1 illustrates the external connections used
for capacitance measurements, and how the CTMU
and A/D modules are related in this application. This
example also shows the edge events coming from
Timer1, but other configurations using external edge
sources are possible. A detailed discussion on measur-
ing capacitance and time with the CTMU module is
provided in the “PIC24F Family Reference Manual”.
Together with other on-chip analog modules, the CTMU
can be used to precisely measure time, measure
capacitance, measure relative changes in capacitance
or generate output pulses that are independent of the
system clock. The CTMU module is ideal for interfacing
with capacitive-based touch sensors.
The CTMU is controlled through three registers:
CTMUCON1,
CTMUCON2
and
CTMUICON.
CTMUCON1 enables the module and controls the mode
of operation of the CTMU, as well as controlling edge
sequencing. CTMUCON2 controls edge source selec-
tion and edge source polarity selection. The CTMUICON
register selects the current range of current source and
trims the current.
2011-2013 Microchip Technology Inc.
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PIC24FV32KA304 FAMILY
FIGURE 25-1:
TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR
CAPACITANCE MEASUREMENT
PIC24F Device
Timer1
CTMU
EDG1
EDG2
Current Source
Output Pulse
ANx
ANy
A/D Converter
CAPP
RPR
time measurements, and how the CTMU and A/D
modules are related in this application. This example
also shows both edge events coming from the external
CTEDx pins, but other configurations using internal
edge sources are possible.
25.2 Measuring Time
Time measurements on the pulse width can be similarly
performed using the A/D module’s Internal Capacitor
(CAD) and a precision resistor for current calibration.
Figure 25-2 displays the external connections used for
FIGURE 25-2:
TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME
MEASUREMENT
PIC24F Device
CTMU
CTEDX
CTEDX
EDG1
EDG2
Current Source
Output Pulse
A/D Converter
CAD
ANx
RPR
DS39995D-page 232
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PIC24FV32KA304 FAMILY
When the voltage on CDELAY equals CVREF, CTPLS
goes low. With Comparator 2 configured as the second
edge, this stops the CTMU from charging. In this state
event, the CTMU automatically connects to ground.
The IDISSEN bit doesn’t need to be set and cleared
before the next CTPLS cycle.
25.3 Pulse Generation and Delay
The CTMU module can also generate an output pulse
with edges that are not synchronous with the device’s
system clock. More specifically, it can generate a pulse
with a programmable delay from an edge event input to
the module.
Figure 25-3 illustrates the external connections for
pulse generation, as well as the relationship of the
different analog modules required. While CTED1 is
shown as the input pulse source, other options are
available. A detailed discussion on pulse generation
with the CTMU module is provided in the “PIC24F
Family Reference Manual”.
When the module is configured for pulse generation
delay by setting the TGEN bit (CTMUCON<12>), the
internal current source is connected to the B input of
Comparator 2. A capacitor (CDELAY) is connected to
the Comparator 2 pin, C2INB, and the Comparator
Voltage Reference, CVREF, is connected to C2INA.
CVREF is then configured for a specific trip point. The
module begins to charge CDELAY when an edge event
is detected. While CVREF is greater than the voltage on
CDELAY, CTPLS is high.
FIGURE 25-3:
TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE
DELAY GENERATION
PIC24F Device
CTMU
VDD
D
Q
Q
CTPLS
EDG1 EDG2
EDG1
CK
CTED1
R
Current
Source
Comparator
EDG2
–
C2INB
C2
CDELAY
CVREF
2011-2013 Microchip Technology Inc.
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REGISTER 25-1: CTMUCON1: CTMU CONTROL REGISTER 1
R/W-0
U-0
—
R/W-0
R/W-0
TGEN
R/W-0
R/W-0
R/W-0
R/W-0
CTMUEN
CTMUSIDL
EDGEN
EDGSEQEN
IDISSEN
CTTRIG
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
CTMUEN: CTMU Enable bit
1= Module is enabled
0= Module is disabled
bit 14
bit 13
Unimplemented: Read as ‘0’
CTMUSIDL: CTMU Stop in Idle Mode bit
1= Discontinues module operation when device enters Idle mode
0= Continues module operation in Idle mode
bit 12
bit 11
bit 10
bit 9
TGEN: Time Generation Enable bit
1= Enables edge delay generation
0= Disables edge delay generation
EDGEN: Edge Enable bit
1= Edges are not blocked
0= Edges are blocked
EDGSEQEN: Edge Sequence Enable bit
1= Edge 1 event must occur before Edge 2 event can occur
0= No edge sequence is needed
IDISSEN: Analog Current Source Control bit
1= Analog current source output is grounded
0= Analog current source output is not grounded
bit 8
CTTRIG: CTMU Trigger Control bit
1= Trigger output is enabled
0= Trigger output is disabled
bit 7-0
Unimplemented: Read as ‘0’
DS39995D-page 234
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PIC24FV32KA304 FAMILY
REGISTER 25-2: CTMUCON2: CTMU CONTROL REGISTER 2
R/W-0
EDG1MOD
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EDG1POL
EDG1SEL3 EDG1SEL2 EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT
bit 8
R/W-0
EDG2MOD
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
EDG2POL
EDG2SEL3 EDG2SEL2 EDG2SEL1 EDG2SEL0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
EDG1MOD: Edge 1 Edge-Sensitive Select bit
1= Input is edge-sensitive
0= Input is level-sensitive
bit 14
EDG1POL: Edge 1 Polarity Select bit
1= Edge 1 is programmed for a positive edge response
0= Edge 1 is programmed for a negative edge response
bit 13-10
EDG1SEL<3:0>: Edge 1 Source Select bits
1111= Edge 1 source is Comparator 3 output
1110= Edge 1 source is Comparator 2 output
1101= Edge 1 source is Comparator 1 output
1100= Edge 1 source is IC3
1011= Edge 1 source is IC2
1010= Edge 1 source is IC1
1001= Edge 1 source is CTED8
1000= Edge 1 source is CTED7
0111= Edge 1 source is CTED6
0110= Edge 1 source is CTED5
0101= Edge 1 source is CTED4
0100= Edge 1 source is CTED3(2)
0011= Edge 1 source is CTED1
0010= Edge 1 source is CTED2
0001= Edge 1 source is OC1
0000= Edge 1 source is Timer1
bit 9
bit 8
bit 7
EDG2STAT: Edge 2 Status bit
Indicates the status of Edge 2 and can be written to control the current source.
1= Edge 2 has occurred
0= Edge 2 has not occurred
EDG1STAT: Edge 1 Status bit
Indicates the status of Edge 1 and can be written to control the current source.
1= Edge 1 has occurred
0= Edge 1 has not occurred
EDG2MOD: Edge 2 Edge-Sensitive Select bit
1= Input is edge-sensitive
0= Input is level-sensitive
Note 1: Edge sources, CTED11 and CTED12, are not available on PIC24FV32KA302 devices.
2: Edge sources, CTED3, CTED11, CTED12 and CTED13, are not available on PIC24FV32KA301 devices.
2011-2013 Microchip Technology Inc.
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REGISTER 25-2: CTMUCON2: CTMU CONTROL REGISTER 2 (CONTINUED)
bit 6
EDG2POL: Edge 2 Polarity Select bit
1= Edge 2 is programmed for a positive edge
0= Edge 2 is programmed for a negative edge
bit 5-2
EDG2SEL<3:0>: Edge 2 Source Select bits
1111= Edge 2 source is Comparator 3 output
1110= Edge 2 source is Comparator 2 output
1101= Edge 2 source is Comparator 1 output
1100= Unimplemented; do not use
1011= Edge 2 source is IC3
1010= Edge 2 source is IC2
1001= Edge 2 source is IC1
1000= Edge 2 source is CTED13(2)
0111= Edge 2 source is CTED12(1,2)
0110= Edge 2 source is CTED11(1,2)
0101= Edge 2 source is CTED10
0100= Edge 2 source is CTED9
0011= Edge 2 source is CTED1
0010= Edge 2 source is CTED2
0001= Edge 2 source is OC1
0000= Edge 2 source is Timer1
bit 1-0
Unimplemented: Read as ‘0’
Note 1: Edge sources, CTED11 and CTED12, are not available on PIC24FV32KA302 devices.
2: Edge sources, CTED3, CTED11, CTED12 and CTED13, are not available on PIC24FV32KA301 devices.
DS39995D-page 236
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REGISTER 25-3: CTMUICON: CTMU CURRENT CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IRNG1
R/W-0
IRNG0
ITRIM5
ITRIM4
ITRIM3
ITRIM2
ITRIM1
ITRIM0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-10
ITRIM<5:0>: Current Source Trim bits
011111= Maximum positive change from nominal current
011110
.
.
.
000001= Minimum positive change from nominal current
000000= Nominal current output specified by IRNG<1:0>
111111= Minimum negative change from nominal current
.
.
.
100010
100001= Maximum negative change from nominal current
bit 9-8
bit 7-0
IRNG<1:0>: Current Source Range Select bits
11= 100 × Base Current
10= 10 × Base Current
01= Base Current Level (0.55 µA nominal)
00= 1000 × Base Current
Unimplemented: Read as ‘0’
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PIC24FV32KA304 FAMILY
NOTES:
DS39995D-page 238
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
26.1 Configuration Bits
26.0 SPECIAL FEATURES
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select vari-
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
ous device configurations. These bits are mapped,
starting at program memory location, F80000h. A
complete list of Configuration register locations is
provided in Table 26-1. A detailed explanation of the
various bit functions is provided in Register 26-1
through Register 26-8.
intended to be a comprehensive reference
source. For more information on the Watch-
dog Timer, High-Level Device Integration
and Programming Diagnostics, refer to the
individual sections of the “PIC24F Family
Reference Manual” provided below:
The address, F80000h, is beyond the user program
memory space. In fact, it belongs to the configuration
memory space (800000h-FFFFFFh), which can only be
accessed using table reads and table writes.
• Section 9. “Watchdog Timer (WDT)”
(DS39697)
• Section 36. “High-Level Integration
with Programmable
High/Low-Voltage Detect (HLVD)”
(DS39725)
• Section 33. “Programming and
Diagnostics” (DS39716)
TABLE 26-1: CONFIGURATION REGISTERS
LOCATIONS
Configuration
Address
Register
PIC24FV32KA304 family devices include several
features intended to maximize application flexibility and
reliability, and minimize cost through elimination of
external components. These are:
FBS
F80000
F80004
F80006
F80008
F8000A
F8000C
F8000E
F80010
FGS
FOSCSEL
FOSC
FWDT
FPOR
FICD
• Flexible Configuration
• Watchdog Timer (WDT)
• Code Protection
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Emulation
FDS
REGISTER 26-1: FBS: BOOT SEGMENT CONFIGURATION REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
BSS2
R/W-1
BSS1
R/W-1
BSS0
R/W-1
BWRP
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-4
bit 3-1
Unimplemented: Read as ‘0’
BSS<2:0>: Boot Segment Program Flash Code Protection bits
111= No boot program Flash segment
011= Reserved
110= Standard security, boot program Flash segment starts at 200h, ends at 000AFEh
010= High-security boot program Flash segment starts at 200h, ends at 000AFEh
101= Standard security, boot program Flash segment starts at 200h, ends at 0015FEh(1)
001= High-security, boot program Flash segment starts at 200h, ends at 0015FEh(1)
100= Standard security; boot program Flash segment starts at 200h, ends at 002BFEh(1)
000= High-security; boot program Flash segment starts at 200h, ends at 002BFEh(1)
bit 0
BWRP: Boot Segment Program Flash Write Protection bit
1= Boot segment may be written
0= Boot segment is write-protected
Note 1: This selection should not be used in PIC24FV16KA3XX devices.
2011-2013 Microchip Technology Inc.
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REGISTER 26-2: FGS: GENERAL SEGMENT CONFIGURATION REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/C-1
GSS0
R/C-1
GWRP
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
C = Clearable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-2
bit 1
Unimplemented: Read as ‘0’
GSS0: General Segment Code Flash Code Protection bit
1= No protection
0= Standard security is enabled
bit 0
GWRP: General Segment Code Flash Write Protection bit
1= General segment may be written
0= General segment is write-protected
REGISTER 26-3: FOSCSEL: OSCILLATOR SELECTION CONFIGURATION REGISTER
R/P-1
IESO
R/P-1
R/P-1
U-0
—
U-0
—
R/P-1
R/P-1
R/P-1
LPRCSEL
SOSCSRC
FNOSC2
FNOSC1
FNOSC0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
P = Programmable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
IESO: Internal External Switchover bit
1= Internal External Switchover mode is enabled (Two-Speed Start-up is enabled)
0= Internal External Switchover mode is disabled (Two-Speed Start-up is disabled)
LPRCSEL: Internal LPRC Oscillator Power Select bit
1= High-Power/High-Accuracy mode
0= Low-Power/Low-Accuracy mode
SOSCSRC: Secondary Oscillator Clock Source Configuration bit
1= SOSC analog crystal function is available on the SOSCI/SOSCO pins
0= SOSC crystal is disabled; digital SCLKI function is selected on the SOSCO pin
bit 4-3
bit 2-0
Unimplemented: Read as ‘0’
FNOSC<2:0>: Oscillator Selection bits
000= Fast RC Oscillator (FRC)
001= Fast RC Oscillator with Divide-by-N with PLL module (FRCDIV+PLL)
010= Primary Oscillator (XT, HS, EC)
011= Primary Oscillator with PLL module (HS+PLL, EC+PLL)
100= Secondary Oscillator (SOSC)
101= Low-Power RC Oscillator (LPRC)
110= 500 kHz Low-Power FRC Oscillator with Divide-by-N (LPFRCDIV)
111= 8 MHz FRC Oscillator with Divide-by-N (FRCDIV)
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REGISTER 26-4: FOSC: OSCILLATOR CONFIGURATION REGISTER
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
POSCMD0
bit 0
FCKSM1
FCKSM0
SOSCSEL POSCFREQ1 POSCFREQ0 OSCIOFNC POSCMD1
bit 7
Legend:
R = Readable bit
P = Programmable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7-6
FCKSM<1:0>: Clock Switching and Fail-Safe Clock Monitor Selection Configuration bits
1x= Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01= Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00= Clock switching is enabled, Fail-Safe Clock Monitor is enabled
bit 5
SOSCSEL: Secondary Oscillator Power Selection Configuration bit
1= Secondary oscillator is configured for high-power operation
0= Secondary oscillator is configured for low-power operation
bit 4-3
POSCFREQ<1:0>: Primary Oscillator Frequency Range Configuration bits
11= Primary oscillator/external clock input frequency is greater than 8 MHz
10= Primary oscillator/external clock input frequency is between 100 kHz and 8 MHz
01= Primary oscillator/external clock input frequency is less than 100 kHz
00= Reserved; do not use
bit 2
OSCIOFNC: CLKO Enable Configuration bit
1= CLKO output signal is active on the OSCO pin; primary oscillator must be disabled or configured
for the External Clock mode (EC) for the CLKO to be active (POSCMD<1:0> = 11or 00)
0= CLKO output is disabled
bit 1-0
POSCMD<1:0>: Primary Oscillator Configuration bits
11= Primary Oscillator mode is disabled
10= HS Oscillator mode is selected
01= XT Oscillator mode is selected
00= External Clock mode is selected
2011-2013 Microchip Technology Inc.
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REGISTER 26-5: FWDT: WATCHDOG TIMER CONFIGURATION REGISTER
R/P-1
FWDTEN1
bit 7
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
WINDIS
FWDTEN0
FWPSA
WDTPS3
WDTPS2
WDTPS1
WDTPS0
bit 0
Legend:
R = Readable bit
P = Programmable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7,5
bit 6
FWDTEN<1:0>: Watchdog Timer Enable bits
11= WDT is enabled in hardware
10= WDT is controlled with the SWDTEN bit setting
01= WDT is enabled only while device is active; WDT is disabled in Sleep, SWDTEN bit is disabled
00= WDT is disabled in hardware; SWDTEN bit is disabled
WINDIS: Windowed Watchdog Timer Disable bit
1= Standard WDT is selected; windowed WDT is disabled
0= Windowed WDT is enabled; note that executing a CLRWDTinstruction while the WDT is disabled in
hardware and software (FWDTEN<1:0> = 00 and SWDTEN (RCON<5>) = 0) will not cause a
device Reset
bit 4
FWPSA: WDT Prescaler bit
1= WDT prescaler ratio of 1:128
0= WDT prescaler ratio of 1:32
bit 3-0
WDTPS<3:0>: Watchdog Timer Postscale Select bits
1111= 1:32,768
1110= 1:16,384
1101= 1:8,192
1100= 1:4,096
1011= 1:2,048
1010= 1:1,024
1001= 1:512
1000= 1:256
0111= 1:128
0110= 1:64
0101= 1:32
0100= 1:16
0011= 1:8
0010= 1:4
0001= 1:2
0000= 1:1
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REGISTER 26-6: FPOR: RESET CONFIGURATION REGISTER
R/P-1
MCLRE(2)
bit 7
R/P-1
BORV1(3)
R/P-1
BORV0(3)
R/P-1
I2C1SEL(1)
R/P-1
R/P-1
RETCFG(1)
R/P-1
R/P-1
PWRTEN
BOREN1
BOREN0
bit 0
Legend:
R = Readable bit
-n = Value at POR
P = Programmable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
MCLRE: MCLR Pin Enable bit(2)
1= MCLR pin is enabled; RA5 input pin is disabled
0= RA5 input pin is enabled; MCLR is disabled
bit 6-5
BORV<1:0>: Brown-out Reset Enable bits(3)
11= Brown-out Reset is set to the lowest voltage
10= Brown-out Reset
01= Brown-out Reset is set to the highest voltage
00= Downside protection on POR is enabled – “zero power” is selected
bit 4
I2C1SEL: Alternate I2C1 Pin Mapping bit(1)
1= Default location for SCL1/SDA1 pins
0= Alternate location for SCL1/SDA1 pins
bit 3
PWRTEN: Power-up Timer Enable bit
1= PWRT is enabled
0= PWRT is disabled
bit 2
RETCFG: Retention Regulator Configuration bit(1)
1= Retention Regulator is not available
0= Retention Regulator is available and controlled by the RETEN bit (RCON<12>) during Sleep
BOREN<1:0>: Brown-out Reset Enable bits
bit 1-0
11= Brown-out Reset is enabled in hardware; SBOREN bit is disabled
10= Brown-out Reset is enabled only while device is active and disabled in Sleep; SBOREN bit is disabled
01= Brown-out Reset is controlled with the SBOREN bit setting
00= Brown-out Reset is disabled in hardware; SBOREN bit is disabled
Note 1: This setting only applies to the “FV” devices. This bit is reserved and should be maintained as ‘1’ on “F”
devices.
2: The MCLRE fuse can only be changed when using the VPP-based ICSP™ mode entry. This prevents a
user from accidentally locking out the device from the low-voltage test entry.
3: Refer to Section 29.0 “Electrical Characteristics” for BOR voltages.
2011-2013 Microchip Technology Inc.
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REGISTER 26-7: FICD: IN-CIRCUIT DEBUGGER CONFIGURATION REGISTER
R/P-1
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
R/P-1
DEBUG
FICD1
FICD0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
P = Programmable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
DEBUG: Background Debugger Enable bit
1= Background debugger is disabled
0= Background debugger functions are enabled
bit 6-2
bit 1-0
Unimplemented: Read as ‘0’
FICD<1:0:>: ICD Pin Select bits
11= PGEC1/PGED1 are used for programming and debugging the device
10= PGEC2/PGED2 are used for programming and debugging the device
01= PGEC3/PGED3 are used for programming and debugging the device
00= Reserved; do not use
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REGISTER 26-8: FDS: DEEP SLEEP CONFIGURATION REGISTER
R/P-1
R/P-1
U-0
—
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
DSWDTEN DSBOREN
bit 7
DSWDTOSC DSWDTPS3 DSWDTPS2 DSWDTPS1 DSWDTPS0
bit 0
Legend:
R = Readable bit
-n = Value at POR
P = Programmable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
DSWDTEN: Deep Sleep Watchdog Timer Enable bit
1= DSWDT is enabled
0= DSWDT is disabled
DSBOREN: Deep Sleep/Low-Power BOR Enable bit
(does not affect operation in non Deep Sleep modes)
1= Deep Sleep BOR is enabled in Deep Sleep
0= Deep Sleep BOR is disabled in Deep Sleep
bit 5
bit 4
Unimplemented: Read as ‘0’
DSWDTOSC: DSWDT Reference Clock Select bit
1= DSWDT uses LPRC as the reference clock
0= DSWDT uses SOSC as the reference clock
bit 3-0
DSWDTPS<3:0>: Deep Sleep Watchdog Timer Postscale Select bits
The DSWDT prescaler is 32; this creates an approximate base time unit of 1 ms.
1111= 1:2,147,483,648 (25.7 days) nominal
1110= 1:536,870,912 (6.4 days) nominal
1101= 1:134,217,728 (38.5 hours) nominal
1100= 1:33,554,432 (9.6 hours) nominal
1011= 1:8,388,608 (2.4 hours) nominal
1010= 1:2,097,152 (36 minutes) nominal
1001= 1:524,288 (9 minutes) nominal
1000= 1:131,072 (135 seconds) nominal
0111= 1:32,768 (34 seconds) nominal
0110= 1:8,192 (8.5 seconds) nominal
0101= 1:2,048 (2.1 seconds) nominal
0100= 1:512 (528 ms) nominal
0011= 1:128 (132 ms) nominal
0010= 1:32 (33 ms) nominal
0001= 1:8 (8.3 ms) nominal
0000= 1:2 (2.1 ms) nominal
2011-2013 Microchip Technology Inc.
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REGISTER 26-9: DEVID: DEVICE ID REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 23
bit 16
R
R
R
R
R
R
R
R
FAMID7
FAMID6
FAMID5
FAMID4
FAMID3
FAMID2
FAMID1
FAMID0
bit 15
bit 8
R
R
R
R
R
R
R
R
DEV7
DEV6
DEV5
DEV4
DEV3
DEV2
DEV1
DEV0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 23-16
bit 15-8
Unimplemented: Read as ‘0’
FAMID<7:0>: Device Family Identifier bits
01000101= PIC24FV32KA304 family
DEV<7:0>: Individual Device Identifier bits
bit 7-0
00010111= PIC24FV32KA304
00000111= PIC24FV16KA304
00010011= PIC24FV32KA302
00000011= PIC24FV16KA302
00011001= PIC24FV32KA301
00001001= PIC24FV16KA301
00010110= PIC24F32KA304
00000110= PIC24F16KA304
00010010= PIC24F32KA302
00000010= PIC24F16KA302
00011000= PIC24F32KA301
00001000= PIC24F16KA301
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REGISTER 26-10: DEVREV: DEVICE REVISION REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 23
bit 16
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
R
R
R
R
REV3
REV2
REV1
REV0
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 23-4
bit 3-0
Unimplemented: Read as ‘0’
REV<3:0>: Minor Revision Identifier bits
2011-2013 Microchip Technology Inc.
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PIC24FV32KA304 FAMILY
FIGURE 26-1:
CONNECTIONS FOR THE
ON-CHIP REGULATOR
26.2 On-Chip Voltage Regulator
All of the PIC24FV32KA304 family devices power their
core digital logic at a nominal 3.0V. This may create an
issue for designs that are required to operate at a
higher typical voltage, as high as 5.0V. To simplify sys-
tem design, all devices in the “FV” family incorporate an
on-chip regulator that allows the device to run its core
logic from VDD.
(1)
Regulator Enabled
:
5.0V
PIC24FV32KA304
VDD
The regulator is always enabled and provides power to
the core from the other VDD pins. A low-ESR capacitor
(such as ceramic) must be connected to the VCAP pin
(Figure 26-1). This helps to maintain the stability of the
regulator. The recommended value for the filter capaci-
tor is discussed in Section 2.4 “Voltage Regulator Pin
(VCAP)”, and in Section 29.1 “DC Characteristics”.
VCAP
VSS
CEFC
(10 F typ)
Note 1: These are typical operating voltages. Refer to
Section 29.0 “Electrical Characteristics”
for the full operating ranges of VDD.
For “F” devices, the regulator is disabled. Instead, core
logic is powered directly from VDD. This allows the
devices to operate at an overall lower allowable voltage
range (1.8V-3.6V).
26.3 Watchdog Timer (WDT)
For the PIC24FV32KA304 family of devices, the WDT
is driven by the LPRC oscillator. When the WDT is
enabled, the clock source is also enabled.
26.2.1
VOLTAGE REGULATOR TRACKING
MODE AND LOW-VOLTAGE
DETECTION
The nominal WDT clock source from LPRC is 31 kHz.
This feeds a prescaler that can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the FWPSA Configuration bit.
With a 31 kHz input, the prescaler yields a nominal
WDT time-out period (TWDT) of 1 ms in 5-bit mode or
4 ms in 7-bit mode.
For all PIC24FV32KA304 devices, the on-chip regula-
tor provides a constant voltage of 3.2V nominal to the
digital core logic. The regulator can provide this level
from a VDD of about 3.2V, all the way up to the device’s
VDDMAX. It does not have the capability to boost VDD
levels below 3.2V. In order to prevent “brown-out” con-
ditions when the voltage drops too low for the regulator,
the regulator enters Tracking mode. In Tracking mode,
the regulator output follows VDD with a typical voltage
drop of 150 mV.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the Configuration bits,
WDTPS<3:0> (FWDT<3:0>), which allow the selection
of a total of 16 settings, from 1:1 to 1:32,768. Using the
prescaler and postscaler time-out periods, ranging
from 1 ms to 131 seconds, can be achieved.
When the device enters Tracking mode, it is no longer
possible to operate at full speed. To provide information
about when the device enters Tracking mode, the
on-chip regulator includes a simple, High/Low-Voltage
Detect (HLVD) circuit. When VDD drops below full-speed
operating voltage, the circuit sets the High/Low-Voltage
Detect Interrupt Flag, HLVDIF (IFS4<8>). This can be
used to generate an interrupt and put the application into
a low-power operational mode or trigger an orderly
shutdown. Maximum device speeds as a function of VDD
are shown in Section 29.1 “DC Characteristics”, in
Figure 29-1 and Figure 29-1.
The WDT, prescaler and postscaler are reset:
• On any device Reset
• On the completion of a clock switch, whether
invoked by software (i.e., setting the OSWEN bit
after changing the NOSCx bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
• When a PWRSAVinstruction is executed
(i.e., Sleep or Idle mode is entered)
• When the device exits Sleep or Idle mode to
resume normal operation
• By a CLRWDTinstruction during normal execution
26.2.2
ON-CHIP REGULATOR AND POR
For PIC24FV32KA304 devices, it takes a brief time,
designated as TPM, for the Voltage Regulator to gener-
ate a stable output. During this time, code execution is
disabled. TPM (DC Specification SY71) is applied every
time the device resumes operation after any
power-down, including Sleep mode.
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If the WDT is enabled in hardware (FWDTEN<1:0> = 11),
it will continue to run during Sleep or Idle modes. When
the WDT time-out occurs, the device will wake and code
execution will continue from where the PWRSAV
instruction was executed. The corresponding SLEEP or
IDLE bit (RCON<3:2>) will need to be cleared in software
after the device wakes up.
26.3.2
CONTROL REGISTER
The WDT is enabled or disabled by the FWDTEN<1:0>
Configuration bits. When both the FWDTEN<1:0>
Configuration bits are set, the WDT is always enabled.
The WDT can be optionally controlled in software when
the FWDTEN<1:0> Configuration bits have been pro-
grammed to ‘10’. The WDT is enabled in software by
setting the SWDTEN control bit (RCON<5>). The
SWDTEN control bit is cleared on any device Reset.
The software WDT option allows the user to enable the
WDT for critical code segments, and disable the WDT
during non-critical segments, for maximum power
savings. When the FWTEN<1:0> bits are set to ‘01’,
the WDT is only enabled in Run and Idle modes, and is
disabled in Sleep. Software control of the SWDTEN bit
(RCON<5>) is disabled with this setting.
The WDT Flag bit, WDTO (RCON<4>), is not auto-
matically cleared following a WDT time-out. To detect
subsequent WDT events, the flag must be cleared in
software.
Note:
The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
26.3.1
WINDOWED OPERATION
The Watchdog Timer has an optional Fixed Window
mode of operation. In this Windowed mode, CLRWDT
instructions can only reset the WDT during the last 1/4
of the programmed WDT period. A CLRWDTinstruction
executed before that window causes a WDT Reset,
similar to a WDT time-out.
Windowed WDT mode is enabled by programming the
Configuration bit, WINDIS (FWDT<6>), to ‘0’.
FIGURE 26-2:
WDT BLOCK DIAGRAM
SWDTEN
FWDTEN<1:0>
LPRC Control
Wake from Sleep
FWPSA
WDTPS<3:0>
Prescaler
(5-Bit/7-Bit)
Postscaler
1:1 to 1:32.768
WDT
Counter
WDT Overflow
Reset
LPRC Input
31 kHz
1 ms/4 ms
All Device Resets
Transition to
New Clock Source
Exit Sleep or
Idle Mode
CLRWDTInstr.
PWRSAVInstr.
Sleep or Idle Mode
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26.4 Deep Sleep Watchdog Timer
(DSWDT)
26.6 In-Circuit Serial Programming
PIC24FV32KA304 family microcontrollers can be
serially programmed while in the end application circuit.
This is simply done with two lines for clock (PGECx) and
data (PGEDx), and three other lines for power, ground
and the programming voltage. This allows customers to
manufacture boards with unprogrammed devices and
then program the microcontroller just before shipping the
product. This also allows the most recent firmware or a
custom firmware to be programmed.
In PIC24FV32KA304 family devices, in addition to the
WDT module, a DSWDT module is present which runs
while the device is in Deep Sleep, if enabled. It is driven
by either the SOSC or LPRC oscillator. The clock source
is selected by the Configuration bit, DSWDTOSC
(FDS<4>).
The DSWDT can be configured to generate a time-out,
at 2.1 ms to 25.7 days, by selecting the respective
postscaler. The postscaler can be selected by the
Configuration bits, DSWDTPS<3:0> (FDS<3:0>).
When the DSWDT is enabled, the clock source is also
enabled.
26.7 In-Circuit Debugger
When MPLAB® ICD 3, MPLAB REAL ICE™ or PICkit™
3 is selected as a debugger, the in-circuit debugging
functionality is enabled. This function allows simple
debugging functions when used with MPLAB IDE.
Debugging functionality is controlled through the PGECx
and PGEDx pins.
DSWDT is one of the sources that can wake-up the
device from Deep Sleep mode.
26.5 Program Verification and
Code Protection
To use the in-circuit debugger function of the device,
the design must implement ICSP connections to
MCLR, VDD, VSS, PGECx, PGEDx and the pin pair. In
addition, when the feature is enabled, some of the
resources are not available for general use. These
resources include the first 80 bytes of data RAM and
two I/O pins.
For all devices in the PIC24FV32KA304 family, code
protection for the boot segment is controlled by the
Configuration bit, BSS0, and the general segment by
the Configuration bit, GSS0. These bits inhibit external
reads and writes to the program memory space This
has no direct effect in normal execution mode.
Write protection is controlled by bit, BWRP, for the boot
segment and bit, GWRP, for the general segment in the
Configuration Word. When these bits are programmed
to ‘0’, internal write and erase operations to program
memory are blocked.
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27.1 MPLAB Integrated Development
Environment Software
27.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software
and hardware development tools:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• Integrated Development Environment
- MPLAB® IDE Software
• A single graphical interface to all debugging tools
- Simulator
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- Programmer (sold separately)
- HI-TECH C® for Various Device Families
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- In-Circuit Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Customizable data windows with direct edit of
contents
• Simulators
• High-level source code debugging
• Mouse over variable inspection
- MPLAB SIM Software Simulator
• Emulators
• Drag and drop variables from source to watch
windows
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
• Extensive on-line help
• Integration of select third party tools, such as
IAR C Compilers
- MPLAB ICD 3
- PICkit™ 3 Debug Express
• Device Programmers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
The MPLAB IDE allows you to:
• Edit your source files (either C or assembly)
• One-touch compile or assemble, and download to
emulator and simulator tools (automatically
updates all project information)
• Low-Cost Demonstration/Development Boards,
Evaluation Kits, and Starter Kits
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
2011-2013 Microchip Technology Inc.
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27.2 MPLAB C Compilers for Various
Device Families
27.5 MPLINK Object Linker/
MPLIB Object Librarian
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal control-
lers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
27.3 HI-TECH C for Various Device
Families
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcontrollers and the dsPIC family of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
27.6 MPLAB Assembler, Linker and
Librarian for Various Device
Families
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, pre-
processor, and one-step driver, and can run on multiple
platforms.
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
27.4 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command line interface
• Rich directive set
• Flexible macro language
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• MPLAB IDE compatibility
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
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2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
27.7 MPLAB SIM Software Simulator
27.9 MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
MPLAB ICD 3 In-Circuit Debugger System is Micro-
chip’s most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Sig-
nal Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC® Flash microcon-
trollers and dsPIC® DSCs with the powerful, yet easy-
to-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is con-
nected to the design engineer’s PC using a high-speed
USB 2.0 interface and is connected to the target with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
MPLAB ICD 2 headers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
development tool.
27.10 PICkit 3 In-Circuit Debugger/
Programmer and
27.8 MPLAB REAL ICE In-Circuit
Emulator System
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and program-
ming of PIC® and dsPIC® Flash microcontrollers at a
most affordable price point using the powerful graphical
user interface of the MPLAB Integrated Development
Environment (IDE). The MPLAB PICkit 3 is connected
to the design engineer’s PC using a full speed USB
interface and can be connected to the target via an
Microchip debug (RJ-11) connector (compatible with
MPLAB ICD 3 and MPLAB REAL ICE). The connector
uses two device I/O pins and the reset line to imple-
ment in-circuit debugging and In-Circuit Serial Pro-
gramming™.
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with in-
circuit debugger systems (RJ11) or with the new high-
speed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
The emulator is field upgradable through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers
significant advantages over competitive emulators
including low-cost, full-speed emulation, run-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
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27.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
27.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
The PICkit™ 2 Development Programmer/Debugger is
a low-cost development tool with an easy to use inter-
face for programming and debugging Microchip’s Flash
families of microcontrollers. The full featured
Windows® programming interface supports baseline
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
(PIC10F,
PIC12F5xx,
PIC16F5xx),
midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
products. With Microchip’s powerful MPLAB Integrated
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
Development Environment (IDE) the PICkit™
2
enables in-circuit debugging on most PIC® microcon-
trollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a break-
point, the file registers can be examined and modified.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
®
for analog filter design, KEELOQ security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta A/D, flow rate sensing,
plus many more.
27.12 MPLAB PM3 Device Programmer
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
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PIC24FV32KA304 FAMILY
The literal instructions that involve data movement may
use some of the following operands:
28.0 INSTRUCTION SET SUMMARY
Note:
This chapter is a brief summary of the
PIC24F instruction set architecture and is
not intended to be a comprehensive
reference source.
• A literal value to be loaded into a W register or file
register (specified by the value of ‘k’)
• The W register or file register where the literal
value is to be loaded (specified by ‘Wb’ or ‘f’)
The PIC24F instruction set adds many enhancements
to the previous PIC® MCU instruction sets, while
maintaining an easy migration from previous PIC MCU
instruction sets. Most instructions are a single program
memory word. Only three instructions require two
program memory locations.
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
• The first source operand, which is a register ‘Wb’
without any address modifier
• The second source operand, which is a literal
value
Each single-word instruction is a 24-bit word divided
into an 8-bit opcode, which specifies the instruction
type and one or more operands, which further specify
the operation of the instruction. The instruction set is
highly orthogonal and is grouped into four basic
categories:
• The destination of the result (only if not the same
as the first source operand), which is typically a
register ‘Wd’ with or without an address modifier
The control instructions may use some of the following
operands:
• A program memory address
• Word or byte-oriented operations
• Bit-oriented operations
• Literal operations
• The mode of the table read and table write
instructions
All instructions are a single word, except for certain
double-word instructions, which were made
double-word instructions so that all of the required
information is available in these 48 bits. In the second
word, the 8 MSbs are ‘0’s. If this second word is
executed as an instruction (by itself), it will execute as
a NOP.
• Control operations
Table 28-1 lists the general symbols used in describing
the instructions. The PIC24F instruction set summary
in Table 28-2 lists all the instructions, along with the
status flags affected by each instruction.
Most word or byte-oriented W register instructions
(including barrel shift instructions) have three
operands:
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
Program Counter (PC) is changed as a result of the
instruction. In these cases, the execution takes two
instruction cycles, with the additional instruction
cycle(s) executed as a NOP. Notable exceptions are the
BRA (unconditional/computed branch), indirect
CALL/GOTO, all table reads and writes, and
RETURN/RETFIE instructions, which are single-word
instructions but take two or three cycles.
• The first source operand, which is typically a
register ‘Wb’ without any address modifier
• The second source operand, which is typically a
register ‘Ws’ with or without an address modifier
• The destination of the result, which is typically a
register ‘Wd’ with or without an address modifier
However, word or byte-oriented file register instructions
have two operands:
Certain instructions that involve skipping over the
subsequent instruction require either two or three
cycles if the skip is performed, depending on whether
the instruction being skipped is a single-word or
two-word instruction. Moreover, double-word moves
require two cycles. The double-word instructions
execute in two instruction cycles.
• The file register specified by the value, ‘f’
• The destination, which could either be the file
register, ‘f’, or the W0 register, which is denoted
as ‘WREG’
Most bit-oriented instructions (including simple
rotate/shift instructions) have two operands:
• The W register (with or without an address
modifier) or file register (specified by the value of
‘Ws’ or ‘f’)
• The bit in the W register or file register (specified
by a literal value or indirectly by the contents of
register ‘Wb’)
2011-2013 Microchip Technology Inc.
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TABLE 28-1: SYMBOLS USED IN OPCODE DESCRIPTIONS
Field
Description
#text
(text)
[text]
{ }
Means literal defined by “text”
Means “content of text”
Means “the location addressed by text”
Optional field or operation
<n:m>
.b
Register bit field
Byte mode selection
.d
Double-Word mode selection
.S
Shadow register select
.w
Word mode selection (default)
bit4
4-bit bit selection field (used in word addressed instructions) {0...15}
MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Absolute address, label or expression (resolved by the linker)
File register address {0000h...1FFFh}
1-bit unsigned literal {0,1}
C, DC, N, OV, Z
Expr
f
lit1
lit4
4-bit unsigned literal {0...15}
lit5
5-bit unsigned literal {0...31}
lit8
8-bit unsigned literal {0...255}
lit10
lit14
lit16
lit23
None
PC
10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode
14-bit unsigned literal {0...16384}
16-bit unsigned literal {0...65535}
23-bit unsigned literal {0...8388608}; LSB must be ‘0’
Field does not require an entry, may be blank
Program Counter
Slit10
Slit16
Slit6
Wb
10-bit signed literal {-512...511}
16-bit signed literal {-32768...32767}
6-bit signed literal {-16...16}
Base W register {W0..W15}
Wd
Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo
Destination W register
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn
Wn
Dividend, Divisor working register pair (direct addressing)
One of 16 working registers {W0..W15}
Wnd
Wns
One of 16 destination working registers {W0..W15}
One of 16 source working registers {W0..W15}
WREG
Ws
W0 (working register used in File register instructions)
Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Source W register { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
Wso
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TABLE 28-2: INSTRUCTION SET OVERVIEW
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
ADD
ADDC
AND
ASR
ADD
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDC
ADDC
AND
AND
AND
AND
AND
ASR
ASR
ASR
ASR
ASR
BCLR
BCLR
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BSET
BSET
BSW.C
BSW.Z
BTG
BTG
BTSC
f
f = f + WREG
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
N, Z
f,WREG
WREG = f + WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
Wd = lit10 + Wd
1
Wd = Wb + Ws
1
Wd = Wb + lit5
1
f = f + WREG + (C)
1
f,WREG
WREG = f + WREG + (C)
Wd = lit10 + Wd + (C)
Wd = Wb + Ws + (C)
Wd = Wb + lit5 + (C)
f = f .AND. WREG
1
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
1
1
1
1
f,WREG
WREG = f .AND. WREG
Wd = lit10 .AND. Wd
Wd = Wb .AND. Ws
1
N, Z
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
1
N, Z
1
N, Z
Wd = Wb .AND. lit5
1
N, Z
f = Arithmetic Right Shift f
WREG = Arithmetic Right Shift f
Wd = Arithmetic Right Shift Ws
Wnd = Arithmetic Right Shift Wb by Wns
Wnd = Arithmetic Right Shift Wb by lit5
Bit Clear f
1
C, N, OV, Z
C, N, OV, Z
C, N, OV, Z
N, Z
f,WREG
1
Ws,Wd
1
Wb,Wns,Wnd
Wb,#lit5,Wnd
f,#bit4
Ws,#bit4
C,Expr
1
1
N, Z
BCLR
BRA
1
None
Bit Clear Ws
1
None
Branch if Carry
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
None
GE,Expr
GEU,Expr
GT,Expr
GTU,Expr
LE,Expr
LEU,Expr
LT,Expr
LTU,Expr
N,Expr
Branch if Greater than or Equal
Branch if Unsigned Greater than or Equal
Branch if Greater than
Branch if Unsigned Greater than
Branch if Less than or Equal
Branch if Unsigned Less than or Equal
Branch if Less than
None
None
None
None
None
None
None
Branch if Unsigned Less than
Branch if Negative
None
None
NC,Expr
NN,Expr
NOV,Expr
NZ,Expr
OV,Expr
Expr
Branch if Not Carry
None
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
None
None
None
Branch if Overflow
None
Branch Unconditionally
Branch if Zero
None
Z,Expr
1 (2)
2
None
Wn
Computed Branch
None
BSET
BSW
f,#bit4
Ws,#bit4
Ws,Wb
Bit Set f
1
None
Bit Set Ws
1
None
Write C bit to Ws<Wb>
Write Z bit to Ws<Wb>
Bit Toggle f
1
None
Ws,Wb
1
None
BTG
f,#bit4
Ws,#bit4
f,#bit4
1
None
Bit Toggle Ws
1
None
BTSC
Bit Test f, Skip if Clear
1
None
(2 or 3)
BTSC
Ws,#bit4
Bit Test Ws, Skip if Clear
1
1
None
(2 or 3)
2011-2013 Microchip Technology Inc.
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TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
f,#bit4
Description
Bit Test f, Skip if Set
Words Cycles
BTSS
BTSS
BTSS
1
1
1
None
(2 or 3)
Ws,#bit4
Bit Test Ws, Skip if Set
1
None
(2 or 3)
BTST
BTST
f,#bit4
Ws,#bit4
Ws,#bit4
Ws,Wb
Bit Test f
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
Z
BTST.C
BTST.Z
BTST.C
BTST.Z
BTSTS
Bit Test Ws to C
C
Bit Test Ws to Z
Z
Bit Test Ws<Wb> to C
Bit Test Ws<Wb> to Z
Bit Test then Set f
Bit Test Ws to C, then Set
Bit Test Ws to Z, then Set
Call Subroutine
C
Ws,Wb
Z
BTSTS
f,#bit4
Z
BTSTS.C Ws,#bit4
BTSTS.Z Ws,#bit4
C
Z
CALL
CLR
CALL
CALL
CLR
lit23
Wn
None
Call Indirect Subroutine
f = 0x0000
None
f
None
CLR
WREG
Ws
WREG = 0x0000
Ws = 0x0000
None
CLR
None
CLRWDT
COM
CLRWDT
Clear Watchdog Timer
WDTO, Sleep
COM
COM
COM
CP
f
f = f
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
N, Z
f,WREG
Ws,Wd
f
WREG = f
N, Z
Wd = Ws
N, Z
CP
Compare f with WREG
Compare Wb with lit5
Compare Wb with Ws (Wb – Ws)
Compare f with 0x0000
Compare Ws with 0x0000
Compare f with WREG, with Borrow
Compare Wb with lit5, with Borrow
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
CP
Wb,#lit5
Wb,Ws
f
CP
CP0
CPB
CP0
CP0
CPB
CPB
CPB
Ws
f
Wb,#lit5
Wb,Ws
Compare Wb with Ws, with Borrow
(Wb – Ws – C)
CPSEQ
CPSGT
CPSLT
CPSNE
CPSEQ
CPSGT
CPSLT
CPSNE
Wb,Wn
Wb,Wn
Wb,Wn
Wb,Wn
Compare Wb with Wn, Skip if =
Compare Wb with Wn, Skip if >
Compare Wb with Wn, Skip if <
Compare Wb with Wn, Skip if
1
1
1
1
1
None
None
None
None
(2 or 3)
1
(2 or 3)
1
(2 or 3)
1
(2 or 3)
DAW
DEC
DAW
Wn
Wn = Decimal Adjust Wn
f = f –1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C
DEC
f
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
None
DEC
f,WREG
Ws,Wd
f
WREG = f –1
1
DEC
Wd = Ws – 1
1
DEC2
DEC2
DEC2
DEC2
DISI
DIV.SW
DIV.SD
DIV.UW
DIV.UD
EXCH
FF1L
FF1R
f = f – 2
1
f,WREG
Ws,Wd
#lit14
Wm,Wn
Wm,Wn
Wm,Wn
Wm,Wn
Wns,Wnd
Ws,Wnd
Ws,Wnd
WREG = f – 2
1
Wd = Ws – 2
1
DISI
DIV
Disable Interrupts for k Instruction Cycles
Signed 16/16-bit Integer Divide
Signed 32/16-bit Integer Divide
Unsigned 16/16-bit Integer Divide
Unsigned 32/16-bit Integer Divide
Swap Wns with Wnd
1
18
18
18
18
1
N, Z, C, OV
N, Z, C, OV
N, Z, C, OV
N, Z, C, OV
None
EXCH
FF1L
FF1R
Find First One from Left (MSb) Side
Find First One from Right (LSb) Side
1
C
1
C
DS39995D-page 258
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
GOTO
GOTO
GOTO
INC
Expr
Go to Address
Go to Indirect
f = f + 1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
None
Wn
None
INC
f
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
N, Z
INC
f,WREG
WREG = f + 1
Wd = Ws + 1
f = f + 2
INC
Ws,Wd
INC2
IOR
INC2
INC2
INC2
IOR
f
f,WREG
WREG = f + 2
Wd = Ws + 2
f = f .IOR. WREG
Ws,Wd
f
IOR
f,WREG
WREG = f .IOR. WREG
N, Z
IOR
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
#lit14
Wd = lit10 .IOR. Wd
N, Z
IOR
Wd = Wb .IOR. Ws
N, Z
IOR
Wd = Wb .IOR. lit5
N, Z
LNK
LSR
LNK
Link Frame Pointer
None
LSR
f
f = Logical Right Shift f
C, N, OV, Z
C, N, OV, Z
C, N, OV, Z
N, Z
LSR
f,WREG
WREG = Logical Right Shift f
Wd = Logical Right Shift Ws
Wnd = Logical Right Shift Wb by Wns
Wnd = Logical Right Shift Wb by lit5
Move f to Wn
LSR
Ws,Wd
LSR
Wb,Wns,Wnd
Wb,#lit5,Wnd
f,Wn
LSR
N, Z
MOV
MOV
None
MOV
[Wns+Slit10],Wnd
f
Move [Wns+Slit10] to Wnd
Move f to f
None
MOV
N, Z
MOV
f,WREG
Move f to WREG
N, Z
MOV
#lit16,Wn
#lit8,Wn
Wn,f
Move 16-bit Literal to Wn
Move 8-bit Literal to Wn
None
MOV.b
MOV
None
Move Wn to f
None
MOV
Wns,[Wns+Slit10]
Wso,Wdo
WREG,f
Move Wns to [Wns+Slit10]
Move Ws to Wd
None
MOV
None
MOV
Move WREG to f
N, Z
MOV.D
MOV.D
MUL.SS
MUL.SU
MUL.US
MUL.UU
MUL.SU
MUL.UU
MUL
Wns,Wd
Move Double from W(ns):W(ns+1) to Wd
Move Double from Ws to W(nd+1):W(nd)
{Wnd+1, Wnd} = Signed(Wb) * Signed(Ws)
{Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws)
{Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws)
{Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws)
{Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5)
{Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5)
W3:W2 = f * WREG
None
Ws,Wnd
None
MUL
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,#lit5,Wnd
Wb,#lit5,Wnd
f
None
None
None
None
None
None
None
NEG
NEG
f
f = f + 1
C, DC, N, OV, Z
C, DC, N, OV, Z
NEG
f,WREG
WREG = f + 1
NEG
Ws,Wd
Wd = Ws + 1
1
1
1
1
1
1
1
1
1
1
1
2
C, DC, N, OV, Z
None
NOP
POP
NOP
No Operation
NOPR
POP
No Operation
None
f
Pop f from Top-of-Stack (TOS)
Pop from Top-of-Stack (TOS) to Wdo
None
POP
Wdo
Wnd
None
POP.D
Pop from Top-of-Stack (TOS) to
W(nd):W(nd+1)
None
POP.S
PUSH
Pop Shadow Registers
1
1
1
1
1
1
1
1
2
1
All
PUSH
f
Push f to Top-of-Stack (TOS)
Push Wso to Top-of-Stack (TOS)
Push W(ns):W(ns+1) to Top-of-Stack (TOS)
Push Shadow Registers
None
None
None
None
PUSH
Wso
Wns
PUSH.D
PUSH.S
2011-2013 Microchip Technology Inc.
DS39995D-page 259
PIC24FV32KA304 FAMILY
TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
PWRSAV
RCALL
PWRSAV
RCALL
RCALL
REPEAT
REPEAT
RESET
RETFIE
RETLW
RETURN
RLC
#lit1
Expr
Wn
Go into Sleep or Idle mode
Relative Call
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
WDTO, Sleep
None
Computed Call
2
None
REPEAT
#lit14
Wn
Repeat Next Instruction lit14 + 1 times
Repeat Next Instruction (Wn) + 1 times
Software Device Reset
Return from Interrupt
1
None
1
None
RESET
RETFIE
RETLW
RETURN
RLC
1
None
3 (2)
3 (2)
3 (2)
1
None
#lit10,Wn
Return with Literal in Wn
Return from Subroutine
f = Rotate Left through Carry f
WREG = Rotate Left through Carry f
Wd = Rotate Left through Carry Ws
f = Rotate Left (No Carry) f
WREG = Rotate Left (No Carry) f
Wd = Rotate Left (No Carry) Ws
f = Rotate Right through Carry f
WREG = Rotate Right through Carry f
Wd = Rotate Right through Carry Ws
f = Rotate Right (No Carry) f
WREG = Rotate Right (No Carry) f
Wd = Rotate Right (No Carry) Ws
Wnd = Sign-Extended Ws
f = FFFFh
None
None
f
C, N, Z
RLC
f,WREG
Ws,Wd
f
1
C, N, Z
RLC
1
C, N, Z
RLNC
RRC
RLNC
RLNC
RLNC
RRC
1
N, Z
f,WREG
Ws,Wd
f
1
N, Z
1
N, Z
1
C, N, Z
RRC
f,WREG
Ws,Wd
f
1
C, N, Z
RRC
1
C, N, Z
RRNC
RRNC
RRNC
RRNC
SE
1
N, Z
f,WREG
Ws,Wd
Ws,Wnd
f
1
N, Z
1
N, Z
SE
1
C, N, Z
SETM
SETM
SETM
SETM
SL
1
None
WREG
WREG = FFFFh
1
None
Ws
Ws = FFFFh
1
None
SL
f
f = Left Shift f
1
C, N, OV, Z
C, N, OV, Z
C, N, OV, Z
N, Z
SL
f,WREG
Ws,Wd
Wb,Wns,Wnd
Wb,#lit5,Wnd
f
WREG = Left Shift f
1
SL
Wd = Left Shift Ws
1
SL
Wnd = Left Shift Wb by Wns
Wnd = Left Shift Wb by lit5
f = f – WREG
1
SL
1
N, Z
SUB
SUB
1
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
SUB
f,WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
WREG = f – WREG
1
SUB
Wn = Wn – lit10
1
SUB
Wd = Wb – Ws
1
SUB
Wd = Wb – lit5
1
SUBB
SUBB
f = f – WREG – (C)
1
SUBB
SUBB
SUBB
f,WREG
WREG = f – WREG – (C)
Wn = Wn – lit10 – (C)
Wd = Wb – Ws – (C)
1
1
1
1
1
1
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
#lit10,Wn
Wb,Ws,Wd
SUBB
SUBR
SUBR
SUBR
SUBR
SUBBR
SUBBR
Wb,#lit5,Wd
f
Wd = Wb – lit5 – (C)
f = WREG – f
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
SUBR
f,WREG
Wb,Ws,Wd
Wb,#lit5,Wd
f
WREG = WREG – f
Wd = Ws – Wb
Wd = lit5 – Wb
f = WREG – f – (C)
WREG = WREG – f – (C)
SUBBR
f,WREG
SUBBR
SUBBR
SWAP.b
SWAP
Wb,Ws,Wd
Wb,#lit5,Wd
Wn
Wd = Ws – Wb – (C)
1
1
1
1
1
1
1
1
1
2
C, DC, N, OV, Z
C, DC, N, OV, Z
None
Wd = lit5 – Wb – (C)
SWAP
Wn = Nibble Swap Wn
Wn = Byte Swap Wn
Wn
None
TBLRDH
TBLRDH
Ws,Wd
Read Prog<23:16> to Wd<7:0>
None
DS39995D-page 260
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
TBLRDL
TBLWTH
TBLWTL
ULNK
TBLRDL
TBLWTH
TBLWTL
ULNK
XOR
Ws,Wd
Ws,Wd
Ws,Wd
Read Prog<15:0> to Wd
1
1
1
1
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
1
None
Write Ws<7:0> to Prog<23:16>
Write Ws to Prog<15:0>
Unlink Frame Pointer
f = f .XOR. WREG
None
None
None
N, Z
XOR
f
XOR
f,WREG
WREG = f .XOR. WREG
Wd = lit10 .XOR. Wd
Wd = Wb .XOR. Ws
N, Z
XOR
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
Ws,Wnd
N, Z
XOR
N, Z
XOR
Wd = Wb .XOR. lit5
N, Z
ZE
ZE
Wnd = Zero-Extend Ws
C, Z, N
2011-2013 Microchip Technology Inc.
DS39995D-page 261
PIC24FV32KA304 FAMILY
NOTES:
DS39995D-page 262
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
29.0 ELECTRICAL CHARACTERISTICS
This section provides an overview of the PIC24FV32KA304 family electrical characteristics. Additional information will
be provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the PIC24FV32KA304 family devices are listed below. Exposure to these maximum rating
conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other
conditions above the parameters indicated in the operation listings of this specification, is not implied.
(†)
Absolute Maximum Ratings
Ambient temperature under bias.............................................................................................................-40°C to +135°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS (PIC24FVXXKA30X) ....................................................................... -0.3V to +6.5V
Voltage on VDD with respect to VSS (PIC24FXXKA30X) .......................................................................... -0.3V to +4.5V
Voltage on any combined analog and digital pin with respect to VSS ............................................ -0.3V to (VDD + 0.3V)
Voltage on any digital only pin with respect to VSS ....................................................................... -0.3V to (VDD + 0.3V)
Voltage on MCLR/VPP pin with respect to VSS ......................................................................................... -0.3V to +9.0V
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin(1)...........................................................................................................................250 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports(1)...............................................................................................................200 mA
Note 1: Maximum allowable current is a function of the device maximum power dissipation (see Table 29-1).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
2011-2013 Microchip Technology Inc.
DS39995D-page 263
PIC24FV32KA304 FAMILY
29.1 DC Characteristics
FIGURE 29-1:
PIC24FV32KA304 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL AND
EXTENDED)
5.5V
5.5V
3.20V
3.20V
2.00V
8 MHz
32 MHz
Frequency
Note:
For frequencies between 8 MHz and 32 MHz, FMAX = 20 MHz * (VDD – 2.0) + 8 MHz.
FIGURE 29-2:
PIC24F32KA304 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL AND
EXTENDED)
3.60V
3.60V
3.00V
3.00V
1.80V
8 MHz
32 MHz
Frequency
Note:
For frequencies between 8 MHz and 32 MHz, FMAX = 20 MHz * (VDD – 1.8) + 8 MHz.
DS39995D-page 264
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
TABLE 29-1: THERMAL OPERATING CONDITIONS
Rating
Symbol
Min
Typ
Max
Unit
Operating Junction Temperature Range
Operating Ambient Temperature Range
TJ
TA
-40
-40
—
—
+140
+125
°C
°C
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD – IOH)
PD
PINT + PI/O
W
W
I/O Pin Power Dissipation:
PI/O = ({VDD – VOH} x IOH) + (VOL x IOL)
Maximum Allowed Power Dissipation
PDMAX
(TJ – TA)/JA
TABLE 29-2: THERMAL PACKAGING CHARACTERISTICS
Characteristic
Symbol
Typ
Max
Unit
Notes
Package Thermal Resistance, 20-Pin SPDIP
Package Thermal Resistance, 28-Pin SPDIP
Package Thermal Resistance, 20-Pin SSOP
Package Thermal Resistance, 28-Pin SSOP
Package Thermal Resistance, 20-Pin SOIC
Package Thermal Resistance, 28-Pin SOIC
Package Thermal Resistance, 28-Pin QFN
Package Thermal Resistance, 44-Pin QFN
Package Thermal Resistance, 48-Pin UQFN
JA
JA
JA
JA
JA
JA
JA
JA
JA
62.4
60
—
—
—
—
—
—
—
—
—
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1
1
1
1
1
1
1
1
1
108
71
75
80.2
32
29
—
Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.
TABLE 29-3: DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX
2.0V to 5.5V PIC24FV32KA3XX
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Operating temperature
Param
No.
Symbol
Characteristic
Supply Voltage
Min
Typ(1) Max Units
Conditions
DC10
DC12
DC16
VDD
1.8
2.0
1.5
1.7
VSS
—
—
—
—
—
3.6
5.5
—
V
V
V
V
V
For F devices
For FV devices
For F devices
For FV devices
VDR
RAM Data Retention
Voltage(2)
—
VPOR
VDD Start Voltage
to Ensure Internal
0.7
Power-on Reset Signal
DC17
SVDD
VDD Rise Rate
to Ensure Internal
Power-on Reset Signal
0.05
—
—
V/ms 0-3.3V in 0.1s
0-2.5V in 60 ms
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: This is the limit to which VDD can be lowered without losing RAM data.
2011-2013 Microchip Technology Inc.
DS39995D-page 265
PIC24FV32KA304 FAMILY
TABLE 29-4: HIGH/LOW–VOLTAGE DETECT CHARACTERISTICS
Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX
2.0V to 5.5V PIC24FV32KA3XX
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
Symbol
No.
Characteristic
Min
Typ Max Units
Conditions
DC18 VHLVD
HLVD Voltage on
VDD Transition
HLVDL<3:0> = 0000(2)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.90
2.13
2.35
2.53
2.62
2.84
3.10
3.25
3.41
3.59
3.79
4.01
4.26
4.55
4.87
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
HLVDL<3:0> = 0001
HLVDL<3:0> = 0010
HLVDL<3:0> = 0011
HLVDL<3:0> = 0100
HLVDL<3:0> = 0101
HLVDL<3:0> = 0110
HLVDL<3:0> = 0111
HLVDL<3:0> = 1000
HLVDL<3:0> = 1001
HLVDL<3:0> = 1010(1)
HLVDL<3:0> = 1011(1)
HLVDL<3:0> = 1100(1)
HLVDL<3:0> = 1101(1)
HLVDL<3:0> = 1110(1)
1.86
2.08
2.22
2.30
2.49
2.73
2.86
3.00
3.16
3.33
3.53
3.74
4.00
4.28
Note 1: These trip points should not be used on PIC24FXXKA30X devices.
2: This trip point should not be used on PIC24FVXXKA30X devices.
TABLE 29-5: BOR TRIP POINTS
Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX
2.0V to 5.5V PIC24FV32KA3XX
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
Sym
No.
Characteristic
Min Typ Max Units
Conditions
DC15
DC19
BOR Hysteresis
BOR Voltage on VDD
Transition
—
—
5
—
—
mV
—
BORV<1:0> = 00
—
Valid for LPBOR and DSBOR
(Note 1)
BORV<1:0> = 01 2.90
3
3.38
V
V
V
V
BORV<1:0> = 10 2.53 2.7 3.07
BORV<1:0> = 11 1.75 1.85 2.05
BORV<1:0> = 11 1.95 2.05 2.16
(Note 2)
(Note 3)
Note 1: LPBOR re-arms the POR circuit but does not cause a BOR.
2: This is valid for PIC24F (3.3V) devices.
3: This is valid for PIC24FV (5V) devices.
DS39995D-page 266
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
TABLE 29-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions:
1.8V to 3.6V PIC24F32KA3XX
2.0V to 5.5V PIC24FV32KA3XX
DC CHARACTERISTICS
Operating temperature:
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Parameter No.
IDD Current
Device
Typical
Max
Units
Conditions
D20
PIC24FV32KA3XX
PIC24F32KA3XX
PIC24FV32KA3XX
PIC24F32KA3XX
269
465
200
410
490
880
407
800
13.0
12.0
2.0
450
830
330
750
—
µA
µA
µA
µA
µA
µA
µA
µA
mA
mA
mA
mA
mA
mA
µA
µA
µA
µA
2.0V
5.0V
1.8V
3.3V
2.0V
5.0V
1.8V
3.3V
5.0V
3.3V
2.0V
5.0V
1.8V
3.3V
2.0V
5.0V
1.8V
3.3V
0.5 MIPS,
FOSC = 1 MHz
(1)
(1)
DC22
—
1 MIPS,
FOSC = 2 MHz
—
—
DC24
DC26
PIC24FV32KA3XX
PIC24F32KA3XX
PIC24FV32KA3XX
20.0
18.0
—
16 MIPS,
FOSC = 32 MHz
(1)
3.5
—
FRC (4 MIPS),
FOSC = 8 MHz
PIC24F32KA3XX
PIC24FV32KA3XX
PIC24F32KA3XX
1.80
3.40
48.0
75.0
8.1
—
—
DC30
250
450
28
LPRC (15.5 KIPS),
FOSC = 31 kHz
13.50
150
Legend: Unshaded rows represent PIC24F32KA3XX devices and shaded rows represent PIC24FV32KA3XX devices.
Note 1: Oscillator is in External Clock mode (FOSCSEL<2:0> = 010, FOSC<1:0> = 00).
2011-2013 Microchip Technology Inc.
DS39995D-page 267
PIC24FV32KA304 FAMILY
TABLE 29-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions:
1.8V to 3.6V PIC24F32KA3XX
2.0V to 5.5V PIC24FV32KA3XX
DC CHARACTERISTICS
Operating temperature:
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Parameter No.
Device
Typical
Max
Units
Conditions
Idle Current (IIDLE)
DC40
PIC24FV32KA3XX
PIC24F32KA3XX
PIC24FV32KA3XX
PIC24F32KA3XX
120
160
50
200
430
100
370
—
µA
µA
µA
µA
µA
µA
µA
µA
mA
mA
mA
mA
mA
mA
µA
µA
µA
µA
2.0V
5.0V
1.8V
3.3V
2.0V
5.0V
1.8V
3.3V
5.0V
3.3V
2.0V
5.0V
1.8V
3.3V
2.0V
5.0V
1.8V
3.3V
0.5 MIPS,
FOSC = 1 MHz
(1)
(1)
90
DC42
165
260
95
—
1 MIPS,
FOSC = 2 MHz
—
180
3.1
2.9
0.65
1.0
0.55
1.0
60
—
DC44
DC46
PIC24FV32KA3XX
PIC24F32KA3XX
PIC24FV32KA3XX
6.5
6.0
—
16 MIPS,
FOSC = 32 MHz
(1)
—
FRC (4 MIPS),
FOSC = 8 MHz
PIC24F32KA3XX
PIC24FV32KA3XX
PIC24F32KA3XX
—
—
DC50
200
350
18
70
LPRC (15.5 KIPS),
FOSC = 31 kHz
2.2
4.0
60
Legend: Unshaded rows represent PIC24F32KA3XX devices and shaded rows represent PIC24FV32KA3XX devices.
Note 1: Oscillator is in External Clock mode (FOSCSEL<2:0> = 010, FOSC<1:0> = 00).
DS39995D-page 268
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
TABLE 29-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions:
1.8V to 3.6V PIC24F32KA3XX
2.0V to 5.5V PIC24FV32KA3XX
DC CHARACTERISTICS
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Parameter
(1)
Device
Typical
Max
Units
Conditions
No.
Power-Down Current (IPD)
DC60
PIC24FV32KA3XX
—
8.0
8.5
9.0
15
-40°C
+25°C
+60°C
+85°C
+125°C
-40°C
6.0
—
µA
µA
µA
µA
2.0V
5.0V
1.8V
3.3V
—
8.0
9.0
10.0
15
+25°C
+60°C
+85°C
+125°C
-40°C
6.0
—
(2)
Sleep Mode
PIC24F32KA3XX
—
0.80
1.5
2.0
7.5
—
+25°C
+60°C
+85°C
+125°C
-40°C
0.025
—
1.0
2.0
3.0
7.5
—
+25°C
+60°C
+85°C
+125°C
-40°C
0.040
—
0.25
0.35
—
DC61
DC70
PIC24FV32KA3XX
PIC24FV32KA3XX
PIC24F32KA3XX
µA
µA
µA
µA
µA
µA
µA
µA
µA
2.0V
5.0V
5.0V
2.0V
5.0V
5.0V
1.8V
3.3V
3.3V
Low-Voltage
Sleep Mode
3.0
7.5
—
+85°C
+125°C
-40°C
(2)
0.03
0.10
—
2.0
6.0
—
+85°C
+125°C
-40°C
Deep Sleep Mode
0.02
0.08
—
1.2
1.2
+85°C
+125°C
Legend: Unshaded rows represent PIC24F32KA3XX devices and shaded rows represent PIC24FV32KA3XX devices.
Note 1: Data in the Typical column is at 3.3V, +25°C (PIC24F32KA3XX) or 5.0V, +25°C (PIC24FV32KA3XX) unless
otherwise stated. Parameters are for design guidance only and are not tested.
2: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as outputs and set low,
PMSLP is set to ‘0’ and WDT, etc., are all switched off.
3: The current is the additional current consumed when the module is enabled. This current should be added to
the base IPD current.
4: This current applies to Sleep only.
5: This current applies to Sleep and Deep Sleep.
6: This current applies to Deep Sleep only.
2011-2013 Microchip Technology Inc.
DS39995D-page 269
PIC24FV32KA304 FAMILY
TABLE 29-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED)
Standard Operating Conditions:
1.8V to 3.6V PIC24F32KA3XX
2.0V to 5.5V PIC24FV32KA3XX
DC CHARACTERISTICS
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Parameter
(1)
Device
Typical
Max
Units
Conditions
No.
(3)
Module Differential Current (IPD)
DC71
DC72
DC75
DC76
PIC24FV32KA3XX
PIC24F32KA3XX
PIC24FV32KA3XX
PIC24F32KA3XX
PIC24FV32KA3XX
PIC24F32KA3XX
PIC24FV32KA3XX
PIC24F32KA3XX
0.50
0.70
—
—
1.5
1.5
—
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
-40°C
+85°C
+125°C
-40°C
2.0V
5.0V
5.0V
1.8V
3.3V
3.3V
2.0V
5.0V
5.0V
1.8V
3.3V
3.3V
2.0V
5.0V
5.0V
1.8V
3.3V
3.3V
2.0V
5.0V
5.0V
1.8V
3.3V
3.3V
Watchdog Timer
Current:
0.50
0.70
—
(4)
IWDT
1.5
1.5
—
+85°C
+125°C
-40°C
0.80
1.50
—
2.0
2.0
—
+85°C
+125°C
-40°C
32 kHz Crystal with RTCC,
DSWDT or Timer1:
ISOSC
0.70
1.0
—
(5)
(SOSCSEL = 0)
1.5
1.5
—
+85°C
+125°C
-40°C
5.4
8.1
—
14.0
14.0
—
+85°C
+125°C
-40°C
(4)
IHLVD
4.9
7.5
—
14.0
14.0
—
+85°C
+125°C
-40°C
5.6
6.5
—
11.2
11.2
—
-40°C
+125°C
-40°C
(4)
IBOR
5.6
6.0
—
11.2
11.2
+85°C
+125°C
Legend: Unshaded rows represent PIC24F32KA3XX devices and shaded rows represent PIC24FV32KA3XX devices.
Note 1: Data in the Typical column is at 3.3V, +25°C (PIC24F32KA3XX) or 5.0V, +25°C (PIC24FV32KA3XX) unless
otherwise stated. Parameters are for design guidance only and are not tested.
2: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as outputs and set low,
PMSLP is set to ‘0’ and WDT, etc., are all switched off.
3: The current is the additional current consumed when the module is enabled. This current should be added to
the base IPD current.
4: This current applies to Sleep only.
5: This current applies to Sleep and Deep Sleep.
6: This current applies to Deep Sleep only.
DS39995D-page 270
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
TABLE 29-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED)
Standard Operating Conditions:
1.8V to 3.6V PIC24F32KA3XX
2.0V to 5.5V PIC24FV32KA3XX
DC CHARACTERISTICS
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Parameter
(1)
Device
Typical
Max
Units
Conditions
No.
(3)
Module Differential Current (IPD)
DC78
PIC24FV32KA3XX
PIC24F32KA3XX
PIC24FV32KA3XX
PIC24F32KA3XX
0.03
0.05
—
—
0.20
0.30
—
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
-40°C
+85°C
+125°C
-40°C
2.0V
5.0V
5.0V
1.8V
3.3V
3.3V
2.0V
5.0V
5.0V
1.8V
3.3V
3.3V
Deep Sleep BOR:
(5)
ILPBOR
0.03
0.05
—
0.20
0.30
—
+85°C
+125°C
-40°C
DC80
0.20
0.70
—
1.5
1.5
—
+85°C
+125°C
-40°C
Deep Sleep WDT:
(6)
IDSWDT (LPRC)
0.20
0.35
—
0.8
1.5
+85°C
+125°C
Legend: Unshaded rows represent PIC24F32KA3XX devices and shaded rows represent PIC24FV32KA3XX devices.
Note 1: Data in the Typical column is at 3.3V, +25°C (PIC24F32KA3XX) or 5.0V, +25°C (PIC24FV32KA3XX) unless
otherwise stated. Parameters are for design guidance only and are not tested.
2: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as outputs and set low,
PMSLP is set to ‘0’ and WDT, etc., are all switched off.
3: The current is the additional current consumed when the module is enabled. This current should be added to
the base IPD current.
4: This current applies to Sleep only.
5: This current applies to Sleep and Deep Sleep.
6: This current applies to Deep Sleep only.
2011-2013 Microchip Technology Inc.
DS39995D-page 271
PIC24FV32KA304 FAMILY
TABLE 29-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX
2.0V to 5.5V PIC24FV32KA3XX
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Operating temperature
Param
No.
Sym
Characteristic
Min
Typ(1)
Max
Units
Conditions
VIL
Input Low Voltage(4)
I/O Pins
DI10
VSS
VSS
VSS
VSS
VSS
VSS
—
—
—
—
—
—
0.2 VDD
0.2 VDD
0.2 VDD
0.2 VDD
0.3 VDD
0.8
V
V
V
V
V
V
DI15
DI16
DI17
DI18
DI19
MCLR
OSCI (XT mode)
OSCI (HS mode)
I/O Pins with I2C™ Buffer
I/O Pins with SMBus Buffer
Input High Voltage(4)
SMBus is disabled
SMBus is enabled
VIH
DI20
I/O Pins:
with Analog Functions
Digital Only
0.8 VDD
0.8 VDD
—
—
VDD
VDD
V
V
DI25
DI26
DI27
DI28
MCLR
0.8 VDD
0.7 VDD
0.7 VDD
—
—
—
VDD
VDD
VDD
V
V
V
OSCI (XT mode)
OSCI (HS mode)
I/O Pins with I2C Buffer:
with Analog Functions
Digital Only
0.7 VDD
0.7 VDD
—
—
VDD
VDD
V
V
DI29
DI30
I/O Pins with SMBus
2.1
50
—
VDD
500
V
2.5V VPIN VDD
ICNPU CNx Pull-up Current
250
A
VDD = 3.3V, VPIN = VSS
IIL
Input Leakage
Current(2,3)
DI50
I/O Ports
—
0.05
0.1
A
VSS VPIN VDD,
Pin at high-impedance
DI55
DI56
MCLR
OSCI
—
—
—
—
0.1
5
A
A
VSS VPIN VDD
VSS VPIN VDD,
XT and HS modes
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: Refer to Table 1-3 for I/O pin buffer types.
DS39995D-page 272
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
TABLE 29-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX
2.0V to 5.5V PIC24FV32KA3XX
DC CHARACTERISTICS
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No.
Sym
Characteristic
Min
Typ(1)
Max
Units
Conditions
VOL
Output Low Voltage
DO10
All I/O Pins
—
—
—
—
—
—
—
—
—
—
—
—
0.4
0.4
0.4
0.4
0.4
0.4
V
V
V
V
V
V
IOL = 8.0 mA
IOL = 4.0 mA
IOL = 3.5 mA
IOL = 2.0 mA
IOL = 1.2 mA
IOL = 0.4 mA
VDD = 4.5V
VDD = 3.6V
VDD = 2.0V
VDD = 4.5V
VDD = 3.6V
VDD = 2.0V
DO16
OSC2/CLKO
VOH
Output High Voltage
DO20
DO26
All I/O Pins
3.8
3
—
—
—
—
—
—
—
—
—
—
—
—
V
V
V
V
V
V
IOH = -3.5 mA
IOH = -3.0 mA
IOH = -1.0 mA
IOH = -2.0 mA
IOH = -1.0 mA
IOH = -0.5 mA
VDD = 4.5V
VDD = 3.6V
VDD = 2.0V
VDD = 4.5V
VDD = 3.6V
VDD = 2.0V
1.6
3.8
3
OSC2/CLKO
1.6
Note 1: Data in “Typ” column is at +25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
TABLE 29-11: DC CHARACTERISTICS: PROGRAM MEMORY
Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX
2.0V to 5.5V PIC24FV32KA3XX
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Operating temperature
Param
No.
Sym
Characteristic
Min
Typ(1)
Max
Units
Conditions
Program Flash Memory
Cell Endurance
D130
D131
EP
VPR
10,000(2)
VMIN
—
—
—
2
—
3.6
—
E/W
V
VDD for Read
VMIN = Minimum operating voltage
D133A TIW
Self-Timed Write Cycle
Time
ms
D134
D135
TRETD Characteristic Retention
40
—
—
—
—
Year Provided no other specifications
are violated
IDDP
Supply Current During
Programming
10
mA
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
2: Self-write and block erase.
2011-2013 Microchip Technology Inc.
DS39995D-page 273
PIC24FV32KA304 FAMILY
TABLE 29-12: DC CHARACTERISTICS: DATA EEPROM MEMORY
Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX
2.0V to 5.5V PIC24FV32KA3XX
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Operating temperature
Param
No.
Sym
Characteristic
Min
Typ(1)
Max
Units
Conditions
Data EEPROM Memory
Cell Endurance
D140
D141
EPD
VPRD
100,000
VMIN
—
—
—
E/W
V
VDD for Read
3.6
VMIN = Minimum operating
voltage
D143A TIWD
D143B TREF
Self-Timed Write Cycle
Time
—
—
4
—
—
ms
Number of Total
Write/Erase Cycles
Before Refresh
10M
E/W
D144
D145
TRETDD Characteristic Retention
40
—
—
7
—
—
Year Provided no other specifications
are violated
IDDPD
Supply Current During
Programming
mA
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
TABLE 29-13: DC CHARACTERISTICS: COMPARATOR SPECIFICATIONS
Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +125°C (unless otherwise stated)
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Comments
D300
D301
D302
VIOFF
VICM
Input Offset Voltage
—
0
20
—
—
40
VDD
—
mV
V
Input Common-Mode Voltage
CMRR
Common-Mode Rejection
Ratio
55
dB
TABLE 29-14: DC CHARACTERISTICS: COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +125°C (unless otherwise stated)
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Comments
VRD310 CVRES
VRD311 CVRAA
VRD312 CVRUR
Resolution
—
—
—
—
—
2k
VDD/32
AVDD – 1.5
—
LSb
LSb
Absolute Accuracy
Unit Resistor Value (R)
DS39995D-page 274
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
TABLE 29-15: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Operating Conditions: -40°C < TA < +125°C (unless otherwise stated)
Param
No.
Symbol
Characteristics
Min
Typ
Max Units
Comments
DVR10 VBG
DVR11 TBG
Band Gap Reference Voltage
0.973 1.024 1.075
V
Band Gap Reference Start-up
Time
—
1
—
ms
DVR20 VRGOUT Regulator Output Voltage
3.1
3.0
4.7
3.3
3.19
10
3.6
3.6
—
V
V
-40°C < TA < +85°C
-40°C < TA < +125°C
DVR21 CEFC
DVR30 VLVR
External Filter Capacitor Value
F Series resistance < 3 Ohm
recommended;
< 5 Ohm is required.
Retention Regulator Output
Voltage
—
2.6
—
V
TABLE 29-16: CTMU CURRENT SOURCE SPECIFICATIONS
Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX
2.0V to 5.5V PIC24FV32KA3XX
DC CHARACTERISTICS
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No.
Sym
Characteristic
Min Typ(1) Max Units
Comments
Conditions
DCT10 IOUT1 CTMU Current
—
—
—
—
—
—
550
5.5
55
—
—
—
—
—
—
nA CTMUICON<9:8> = 01
A CTMUICON<9:8> = 10
A CTMUICON<9:8> = 11
Source, Base Range
DCT11 IOUT2 CTMU Current
Source, 10x Range
2.5V < VDD < VDDMAX
DCT12 IOUT3 CTMU Current
Source, 100x Range
DCT13 IOUT4 CTMU Current
Source, 1000x Range
550
.76
1.6
A CTMUICON<9:8> = 00
(Note 2)
DCT20 VF
Temperature Diode
Forward Voltage
V
DCT21 V
Voltage Change per
Degree Celsius
mV/°C
Note 1: Nominal value at the center point of the current trim range (CTMUICON<7:2> = 000000). On PIC24F32KA
parts, the current output is limited to the typical current value when IOUT4 is chosen.
2: Do not use this current range with a temperature sensing diode.
2011-2013 Microchip Technology Inc.
DS39995D-page 275
PIC24FV32KA304 FAMILY
29.2 AC Characteristics and Timing Parameters
The information contained in this section defines the PIC24FV32KA304 family AC characteristics and timing parameters.
TABLE 29-17: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX
2.0V to 5.5V PIC24FV32KA3XX
AC CHARACTERISTICS
Operating temperature:
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Operating voltage VDD range as described in Section 29.1 “DC Characteristics”.
FIGURE 29-3:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – For All Pins Except OSCO
VDD/2
Load Condition 2 – For OSCO
CL
Pin
RL
VSS
CL
Pin
RL = 464
CL = 50 pF for all pins except OSCO
15 pF for OSCO output
VSS
TABLE 29-18: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
Param
Symbol
Characteristic
Min
Typ(1) Max Units
Conditions
No.
DO50 COSC2
OSCO/CLKO Pin
—
—
15
pF In XT and HS modes when the
external clock is used to drive
OSCI
DO56 CIO
DO58 CB
All I/O Pins and OSCO
SCLx, SDAx
—
—
—
—
50
pF EC mode
pF In I2C™ mode
400
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
DS39995D-page 276
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
FIGURE 29-4:
EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
OSCI
OS20
OS30 OS30
OS31 OS31
OS25
CLKO
OS40
OS41
TABLE 29-19: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX
2.0V to 5.5V PIC24FV32KA3XX
AC CHARACTERISTICS
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No.
Sym
Characteristic
Min
Typ(1)
Max
Units
Conditions
OS10 FOSC External CLKI Frequency
(External clocks allowed
DC
4
—
—
32
8
MHz EC
MHz ECPLL
only in EC mode)
OS15
Oscillator Frequency
0.2
4
4
—
—
—
—
4
25
8
MHz XT
MHz HS
MHz XTPLL
kHz SOSC
31
33
OS20 TOSC TOSC = 1/FOSC
—
—
—
—
See Parameter OS10 for FOSC
value
OS25 TCY
Instruction Cycle Time(2)
62.5
—
—
DC
—
ns
ns
OS30 TosL, External Clock in (OSCI)
TosH High or Low Time
0.45 x TOSC
EC
EC
OS31 TosR, External Clock in (OSCI)
TosF Rise or Fall Time
—
—
20
ns
OS40 TckR CLKO Rise Time(3)
OS41 TckF CLKO Fall Time(3)
—
—
6
6
10
10
ns
ns
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: The instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type, under standard operating conditions,
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at “Min.”
values with an external clock applied to the OSCI/CLKI pin. When an external clock input is used, the “Max.”
cycle time limit is “DC” (no clock) for all devices.
3: Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for
the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).
2011-2013 Microchip Technology Inc.
DS39995D-page 277
PIC24FV32KA304 FAMILY
TABLE 29-20: PLL CLOCK TIMING SPECIFICATIONS
Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX
2.0V to 5.5V PIC24FV32KA3XX
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Operating temperature
Param
No.
Sym
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
OS50 FPLLI PLL Input Frequency
Range
4
—
8
MHz ECPLL, HSPLL modes,
-40°C TA +85°C
OS51 FSYS PLL Output Frequency
Range
16
—
-2
—
1
32
2
MHz -40°C TA +85°C
OS52 TLOCK PLL Start-up Time
(Lock Time)
ms
OS53 DCLK CLKO Stability (Jitter)
1
2
%
Measured over a 100 ms
period
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
TABLE 29-21: AC CHARACTERISTICS: INTERNAL RC ACCURACY
Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX
2.0V to 5.5V PIC24FV32KA3XX
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Characteristic
Min
Typ
Max Units
Conditions
F20
Internal FRC Accuracy @ 8 MHz(1)
FRC
-2
-5
—
—
+2
+5
%
%
+25°C
3.0V VDD 3.6V, F device
3.2V VDD 5.5V, FV device
-40°C TA +85°C 1.8V VDD 3.6V, F device
2.0V VDD 5.5V, FV device
LPRC @ 31 kHz(2)
F21
-15
—
15
%
Note 1: Frequency is calibrated at +25°C and 3.3V. The OSCTUN bits can be used to compensate for temperature
drift.
2: The change of LPRC frequency as VDD changes.
TABLE 29-22: INTERNAL RC OSCILLATOR SPECIFICATIONS
Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX
2.0V to 5.5V PIC24FV32KA3XX
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Sym
Characteristic(1)
Min
Typ
Max
Units
Conditions
TFRC FRC Start-up Time
TLPRC LPRC Start-up Time
—
—
5
—
—
s
s
70
Note 1: These parameters are characterized but not tested in manufacturing.
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2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
FIGURE 29-5:
CLKO AND I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
New Value
Old Value
DO31
DO32
Note:
Refer to Figure 29-3 for load conditions.
TABLE 29-23: CLKO AND I/O TIMING REQUIREMENTS
Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX
2.0V to 5.5V PIC24FV32KA3XX
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Sym
Characteristic
Min
Typ(1)
Max
Units
Conditions
DO31 TIOR Port Output Rise Time
DO32 TIOF Port Output Fall Time
—
—
20
10
10
—
25
25
—
ns
ns
ns
DI35
TINP
INTx Pin High or Low
Time (output)
DI40
TRBP CNx High or Low Time
(input)
2
—
—
TCY
Note 1: Data in “Typ” column is at 3.3V, +25°C (PIC24F32KA3XX); 5.0V, +25°C (PIC24FV32KA3XX), unless
otherwise stated.
2011-2013 Microchip Technology Inc.
DS39995D-page 279
PIC24FV32KA304 FAMILY
TABLE 29-24: COMPARATOR TIMINGS
Param
Symbol
Characteristic
Min
Typ
Max
Units
Comments
No.
300
301
TRESP
Response Time*(1)
—
—
150
—
400
10
ns
TMC2OV Comparator Mode Change to
Output Valid*
s
*
Parameters are characterized but not tested.
Note 1: Response time is measured with one comparator input at (VDD – 1.5)/2, while the other input transitions
from VSS to VDD.
TABLE 29-25: COMPARATOR VOLTAGE REFERENCE SETTLING TIME SPECIFICATIONS
Param
Symbol
Characteristic
Min
Typ
Max
Units
Comments
No.
VR310 TSET
Settling Time(1)
—
—
10
s
Note 1: Settling time is measured while CVRSS = 1and the CVR<3:0> bits transition from ‘0000’ to ‘1111’.
FIGURE 29-6:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING CHARACTERISTICS
VDD
MCLR
SY12
SY10
Internal
POR
PWRT
SY11
SYSRST
System
Clock
Watchdog
Timer Reset
SY20
SY13
SY13
I/O Pins
SY35
DS39995D-page 280
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FIGURE 29-7:
BROWN-OUT RESET CHARACTERISTICS
VDDCORE
(Device not in Brown-out Reset)
DC15
DC19
(Device in Brown-out Reset)
Reset (Due to BOR)
SY25
TVREG + TRST
TABLE 29-26: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET TIMING REQUIREMENTS
Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX
2.0V to 5.5V PIC24FV32KA3XX
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristic
Min. Typ(1)
Max.
Units
Conditions
SY10 TmcL
MCLR Pulse Width (low)
Power-up Timer Period
Power-on Reset Delay
2
50
1
—
64
5
—
90
s
ms
s
ns
SY11
SY12
SY13
TPWRT
TPOR
TIOZ
10
I/O High-Impedance from
MCLR Low or Watchdog
Timer Reset
—
—
100
SY20
TWDT
Watchdog Timer Time-out
Period
0.85
3.4
1
1.0
4.0
—
1.15
4.6
—
ms
ms
s
1.32 prescaler
1:128 prescaler
SY25
SY35
TBOR
Brown-out Reset Pulse
Width
TFSCM
Fail-Safe Clock Monitor
Delay
—
2.0
2.3
s
SY45
SY50
TRST
Internal State Reset Time
—
—
5
—
—
s
s
TVREG
On-Chip Voltage Regulator
Output Delay
10
(Note 2)
SY55
SY65
SY70
TLOCK
TOST
PLL Start-up Time
—
—
—
100
1024
100
—
—
—
s
TOSC
s
Oscillator Start-up Time
TDSWU
Wake-up from Deep Sleep
Time
Based on full discharge of
10 F capacitor on VCAP;
includes TPOR and TRST
SY71
SY72
SY73
TPM
Program Memory Wake-up
Time
—
—
—
1
250
2
—
—
—
s
s
s
Sleep wake-up with
PMSLP = 0
TLVR
THVLD
Retention Regulator
Wake-up Time
HVLD Interrupt Response
Time
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
2: This applies to PIC24FV32KA3XX devices only.
2011-2013 Microchip Technology Inc.
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PIC24FV32KA304 FAMILY
FIGURE 29-8:
TIMER1/2/3/4/5 EXTERNAL CLOCK INPUT TIMING
TxCK Pin
TtL
TtH
TtP
TABLE 29-27: TIMER1/2/3/4/5 EXTERNAL CLOCK INPUT REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Max
Units
Conditions
TtH
TxCK High Pulse
Time
Sync w/Prescaler
Async w/Prescaler
Async Counter
TCY + 20
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
Must also meet
Parameter Ttp
10
20
TtL
TtP
TxCK Low Pulse
Time
Sync w/Prescaler
Async w/Prescaler
Async Counter
TCY + 20
10
Must also meet
Parameter Ttp
20
TxCK External Input Sync w/Prescaler
Period
2 * TCY + 40
N = Prescale Value
(1, 4, 8, 16)
Async w/Prescaler
Greater of:
20 or
2 * TCY + 40
N
Async Counter
40
1
—
2
ns
TCY
ns
Delay for Input Edge Synchronous
to Timer Increment
Asynchronous
—
20
FIGURE 29-9:
INPUT CAPTURE x TIMINGS
ICx Pin
(Input Capture Mode)
IC10
IC11
IC15
TABLE 29-28: INPUT CAPTURE x REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Max
Units
Conditions
IC10
TccL
ICx Input Low Time –
Synchronous Timer
No Prescaler
With Prescaler
No Prescaler
With Prescaler
TCY + 20
20
—
—
—
—
—
ns
ns
ns
ns
ns
Must also meet
Parameter IC15
IC11
IC15
TccH
TccP
ICx Input Low Time –
Synchronous Timer
TCY + 20
20
Must also meet
Parameter IC15
ICx Input Period – Synchronous Timer
2 * TCY + 40
N
N = prescale value
(1, 4, 16)
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PIC24FV32KA304 FAMILY
FIGURE 29-10:
OUTPUT COMPARE x TIMINGS
OCx
(Output Compare or PWM Mode)
OC11
OC10
TABLE 29-29: OUTPUT CAPTURE REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
OC11
TCCR
OC1 Output Rise Time
—
—
—
—
10
—
10
—
ns
ns
ns
ns
OC10
TCCF
OC1 Output Fall Time
FIGURE 29-11:
PWM MODULE TIMING REQUIREMENTS
OC20
OCFx
PWM
OC15
TABLE 29-30: PWM TIMING REQUIREMENTS
Param.
Symbol
Characteristic
Min
Typ†
Max
Units
Conditions
No.
OC15
TFD
Fault Input to PWM I/O
Change
—
—
25
ns
VDD = 3.0V, -40C to +125C
OC20
TFH
Fault Input Pulse Width
50
—
—
ns
VDD = 3.0V, -40C to +125C
†
Data in “Typ” column is at 5V, +25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
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FIGURE 29-12:
I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx
IM34
IM31
IM30
IM33
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 29-3 for load conditions.
TABLE 29-31: I2C™ BUS START/STOP BIT TIMING REQUIREMENTS (MASTER MODE)
Standard Operating Conditions: 2.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial)
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristic
Min(1)
Max
Units
Conditions
IM30
TSU:STA Start Condition 100 kHz mode
TCY/2 (BRG + 1)
TCY/2 (BRG + 1)
—
—
—
—
—
—
—
—
—
—
—
—
s
s
s
s
s
s
s
s
s
ns
ns
ns
Only relevant for
Repeated Start
condition
Setup Time
400 kHz mode
1 MHz mode(2) TCY/2 (BRG + 1)
IM31
IM33
IM34
THD:STA Start Condition 100 kHz mode
Hold Time
TCY/2 (BRG + 1)
After this period, the
first clock pulse is
generated
400 kHz mode
TCY/2 (BRG + 1)
1 MHz mode(2) TCY/2 (BRG + 1)
TSU:STO Stop Condition 100 kHz mode
TCY/2 (BRG + 1)
Setup Time
400 kHz mode
TCY/2 (BRG + 1)
1 MHz mode(2) TCY/2 (BRG + 1)
THD:STO Stop Condition
Hold Time
100 kHz mode
TCY/2 (BRG + 1)
400 kHz mode
TCY/2 (BRG + 1)
1 MHz mode(2) TCY/2 (BRG + 1)
Note 1: BRG is the value of the I2C™ Baud Rate Generator. Refer to Section 17.3 “Setting Baud Rate When
Operating as a Bus Master” for details.
2: Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only).
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FIGURE 29-13:
I2C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM11
IM21
SCLx
IM25
IM10
IM26
IM20
SDAx
In
IM45
IM40
SDAx
Out
Note: Refer to Figure 29-3 for load conditions.
TABLE 29-32: I2C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Standard Operating Conditions: 2.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min(1)
Max
Units
Conditions
IM10
IM11
IM20
IM21
IM25
IM26
IM40
IM45
IM50
TLO:SCL
THI:SCL
TF:SCL
Clock Low Time 100 kHz mode
400 kHz mode
TCY/2 (BRG + 1)
TCY/2 (BRG + 1)
—
—
s
s
s
s
s
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
ns
ns
ns
ns
s
s
s
pF
1 MHz mode(2) TCY/2 (BRG + 1)
—
Clock High Time 100 kHz mode
400 kHz mode
TCY/2 (BRG + 1)
—
TCY/2 (BRG + 1)
—
1 MHz mode(2) TCY/2 (BRG + 1)
—
SDAx and SCLx 100 kHz mode
—
300
300
100
1000
300
300
—
CB is specified to be
from 10 to 400 pF
Fall Time
400 kHz mode
1 MHz mode(2)
20 + 0.1 CB
—
TR:SCL
TSU:DAT
SDAx and SCLx 100 kHz mode
—
CB is specified to be
from 10 to 400 pF
Rise Time
400 kHz mode
1 MHz mode(2)
100 kHz mode
400 kHz mode
1 MHz mode(2)
100 kHz mode
400 kHz mode
1 MHz mode(2)
100 kHz mode
400 kHz mode
1 MHz mode(2)
20 + 0.1 CB
—
250
100
100
0
Data Input
Setup Time
—
—
THD:DAT Data Input
Hold Time
—
0
0.9
—
0
TAA:SCL
TBF:SDA
CB
Output Valid
from Clock
—
3500
1000
—
—
—
Bus Free Time 100 kHz mode
400 kHz mode
4.7
1.3
0.5
—
—
Time the bus must be
free before a new
transmission can start
—
1 MHz mode(2)
—
Bus Capacitive Loading
400
Note 1: BRG is the value of the I2C Baud Rate Generator. Refer to Section 17.3 “Setting Baud Rate When Operating
as a Bus Master” for details.
2: Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only).
2011-2013 Microchip Technology Inc.
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FIGURE 29-14:
I2C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS11
IS21
IS10
IS25
SCLx
IS20
IS26
SDAx
In
IS45
IS40
SDAx
Out
TABLE 29-33: I2C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions: 2.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature
-40°C TA +85°C (Industrial)
-40°C TA +125°C (Extended)
Param
Symbol
No.
Characteristic
100 kHz mode
Min
Max
Units
Conditions
IS10
IS11
TLO:SCL
Clock Low Time
Clock High Time
4.7
—
s
s
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
Device must operate at a
minimum of 10 MHz
(1)
1 MHz mode
0.5
4.0
—
—
s
s
THI:SCL
100 kHz mode
400 kHz mode
Device must operate at a
minimum of 1.5 MHz
0.6
—
s
Device must operate at a
minimum of 10 MHz
(1)
1 MHz mode
0.5
—
300
300
100
1000
300
300
—
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
ns
ns
ns
s
s
s
pF
IS20
IS21
IS25
IS26
IS40
IS45
IS50
TF:SCL
TR:SCL
TSU:DAT
THD:DAT
TAA:SCL
TBF:SDA
CB
SDAx and SCLx
Fall Time
100 kHz mode
400 kHz mode
—
CB is specified to be from
10 to 400 pF
20 + 0.1 CB
(1)
1 MHz mode
—
SDAx and SCLx
Rise Time
100 kHz mode
400 kHz mode
—
CB is specified to be from
10 to 400 pF
20 + 0.1 CB
(1)
1 MHz mode
—
250
100
100
0
Data Input
Setup Time
100 kHz mode
400 kHz mode
—
(1)
1 MHz mode
—
Data Input
Hold Time
100 kHz mode
400 kHz mode
—
0
0.9
0.3
3500
1000
350
—
(1)
1 MHz mode
0
Output Valid From 100 kHz mode
0
Clock
400 kHz mode
0
(1)
1 MHz mode
0
Bus Free Time
100 kHz mode
400 kHz mode
4.7
1.3
0.5
—
Time the bus must be free
before a new transmission
can start
—
(1)
1 MHz mode
—
Bus Capacitive Loading
400
2
Note 1: Maximum pin capacitance = 10 pF for all I C™ pins (for 1 MHz mode only).
DS39995D-page 286
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PIC24FV32KA304 FAMILY
FIGURE 29-15:
I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
IS34
IS31
IS30
IS33
SDAx
Stop
Condition
Start
Condition
TABLE 29-34: I2C™ BUS START/STOP BITS TIMING REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions: 2.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C (Industrial)
AC CHARACTERISTICS
-40°C TA +125°C (Extended)
Param
No.
Symbol
Characteristic
Min
Max Units
Conditions
IS30
TSU:STA Start Condition
Setup Time
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
4.7
0.6
—
—
—
—
—
—
—
—
—
—
—
—
s
s
s
s
s
s
s
s
s
ns
ns
ns
Only relevant for Repeated
Start condition
0.25
4.0
IS31
IS33
IS34
THD:STA Start Condition
Hold Time
After this period, the first
clock pulse is generated
0.6
0.25
4.7
TSU:STO Stop Condition
Setup Time
0.6
0.6
THD:STO Stop Condition
Hold Time
4000
600
250
Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins (for 1 MHz mode only).
2011-2013 Microchip Technology Inc.
DS39995D-page 287
PIC24FV32KA304 FAMILY
FIGURE 29-16:
UARTx BAUD RATE GENERATOR OUTPUT TIMING
UxBRG + 1 * TCY TLW
THW
UxBCLK
UxTX
TBLD
TBHD
FIGURE 29-17:
UARTx START BIT EDGE DETECTION
UxBRG
Any Value
Start bit Detected, UxBRG Started
TCY
Cycle
Clock
TSETUP
TSTDELAY
UxRX
TABLE 29-35: UARTx TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C (Industrial)
-40°C TA +125°C (Extended)
Symbol
Characteristics
UxBCLK High Time
Min
Typ
Max
Units
TLW
20
20
TCY/2
—
ns
ns
ns
ns
s
THW
TBLD
TBHD
TWAK
UxBCLK Low Time
(TCY * UXBRG) + TCY/2
—
50
UxBCLK Falling Edge Delay from UxTX
UxBCLK Rising Edge Delay from UxTX
-50
—
—
1
TCY/2 – 50
—
TCY/2 + 50
—
Minimum Low on UxRX Line to Cause
Wake-up
TCTS
Minimum Low on UxCTS Line to Start
Transmission
Tcy
3
—
—
—
—
—
ns
ns
ns
TSETUP
Start bit Falling Edge to System Clock Rising
Edge Setup Time
TSTDELAY Maximum Delay in the Detection of the
Start bit Falling Edge
—
TCY + TSETUP
DS39995D-page 288
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
FIGURE 29-18:
SPIx MODULE MASTER MODE TIMING CHARACTERISTICS (CKE = 0)
SCKx
(CKP = 0)
SP11
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
SP31
Bit 14 - - - - - -1
LSb
MSb
SDOx
SDIx
SP30
MSb In
SP40
Bit 14 - - - -1
LSb In
SP41
TABLE 29-36: SPIx MASTER MODE TIMING REQUIREMENTS (CKE = 0)
Standard Operating Conditions: 2.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C (Industrial)
-40°C TA +125°C (Extended)
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
SP10
SP11
SP20
SP21
SP30
SP31
SP35
TscL
TscH
TscF
TscR
TdoF
TdoR
SCKx Output Low Time(2)
SCKx Output High Time(2)
SCKx Output Fall Time(3)
SCKx Output Rise Time(3)
SDOx Data Output Fall Time(3)
SDOx Data Output Rise Time(3)
TCY/2
TCY/2
—
—
—
10
10
10
10
—
—
—
25
25
25
25
30
ns
ns
ns
ns
ns
ns
ns
—
—
—
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
SP40
SP41
TdiV2scH, Setup Time of SDIx Data Input
20
20
—
—
—
—
ns
ns
TdiV2scL
TscH2diL, Hold Time of SDIx Data Input
TscL2diL to SCKx Edge
to SCKx Edge
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: The minimum clock period for SCKx is 100 ns; therefore, the clock generated in Master mode must not
violate this specification.
3: This assumes a 50 pF load on all SPIx pins.
2011-2013 Microchip Technology Inc.
DS39995D-page 289
PIC24FV32KA304 FAMILY
FIGURE 29-19:
SPIx MODULE MASTER MODE TIMING CHARACTERISTICS (CKE = 1)
SP36
SCKx
(CKP = 0)
SP11
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
Bit 14 - - - - - -1
LSb
MSb
SDOx
SDIx
SP40
SP30,SP31
Bit 14 - - - -1
MSb In
SP41
LSb In
TABLE 29-37: SPIx MODULE MASTER MODE TIMING REQUIREMENTS (CKE = 1)
Standard Operating Conditions: 2.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
TscL
Characteristic
Min
Typ(1)
Max
Units
Conditions
SP10
SP11
SP20
SP21
SP30
SP31
SP35
SCKx Output Low Time(2)
SCKx Output High Time(2)
SCKx Output Fall Time(3)
SCKx Output Rise Time(3)
SDOx Data Output Fall Time(3)
SDOx Data Output Rise Time(3)
TCY/2
TCY/2
—
—
—
10
10
10
10
—
—
—
25
25
25
25
30
ns
ns
ns
ns
ns
ns
ns
TscH
TscF
TscR
TdoF
TdoR
—
—
—
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
SP36
SP40
SP41
TdoV2sc, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
20
20
—
—
—
—
—
—
ns
ns
ns
TdiV2scH, Setup Time of SDIx Data Input
TdiV2scL to SCKx Edge
TscH2diL, Hold Time of SDIx Data Input
TscL2diL
to SCKx Edge
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: The minimum clock period for SCKx is 100 ns; therefore, the clock generated in Master mode must not
violate this specification.
3: This assumes a 50 pF load on all SPIx pins.
DS39995D-page 290
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
FIGURE 29-20:
SPIx MODULE SLAVE MODE TIMING CHARACTERISTICS (CKE = 0)
SSx
SP52
SP50
SCKx
(CKP = 0)
SP71
SP70
SP72
SP73
SP73
SP72
SCKx
(CKP = 1)
SP35
MSb
LSb
Bit 14 - - - - - -1
SDOx
SDIx
SP51
SP30,SP31
Bit 14 - - - -1
MSb In
SP41
LSb In
SP40
TABLE 29-38: SPIx MODULE SLAVE MODE TIMING REQUIREMENTS (CKE = 0)
Standard Operating Conditions: 2.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
Symbol
No.
(1)
Characteristic
Min
Typ
Max
Units
Conditions
SP70 TscL
SP71 TscH
SP72 TscF
SP73 TscR
SP30 TdoF
SP31 TdoR
SCKx Input Low Time
SCKx Input High Time
30
30
—
—
—
—
—
—
—
10
10
10
10
—
—
—
25
25
25
25
30
ns
ns
ns
ns
ns
ns
ns
(2)
SCKx Input Fall Time
(2)
SCKx Input Rise Time
SDOx Data Output Fall Time
(2)
(2)
SDOx Data Output Rise Time
SP35 TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
SP40 TdiV2scH, Setup Time of SDIx Data Input
TdiV2scL to SCKx Edge
SP41 TscH2diL, Hold Time of SDIx Data Input
TscL2diL to SCKx Edge
20
20
—
—
—
—
—
—
ns
ns
ns
SP50 TssL2scH, SSx to SCKx or SCKx Input
120
TssL2scL
(3)
SP51 TssH2doZ SSx to SDOx Output High-Impedance
10
—
—
50
—
ns
ns
SP52 TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are
not tested.
2: The minimum clock period for SCKx is 100 ns; therefore, the clock generated in Master mode must not violate
this specification.
3: This assumes a 50 pF load on all SPIx pins.
2011-2013 Microchip Technology Inc.
DS39995D-page 291
PIC24FV32KA304 FAMILY
FIGURE 29-21:
SPIx MODULE SLAVE MODE TIMING CHARACTERISTICS (CKE = 1)
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP71
SP70
SP72
SP73
SP72
SCKx
(CKP = 1)
SP35
SP73
SP52
Bit 14 - - - - - -1
MSb
LSb
SDOx
SDIx
SP51
SP30,SP31
LSb In
MSb In
SP41
Bit 14 - - - -1
SP40
TABLE 29-39: SPIx MODULE SLAVE MODE TIMING REQUIREMENTS (CKE = 1)
Standard Operating Conditions: 2.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
(1)
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
SP70 TscL
SP71 TscH
SP72 TscF
SP73 TscR
SP30 TdoF
SP31 TdoR
SCKx Input Low Time
SCKx Input High Time
30
30
—
—
—
—
—
—
—
10
10
10
10
—
—
—
25
25
25
25
30
ns
ns
ns
ns
ns
ns
ns
(2)
SCKx Input Fall Time
SCKx Input Rise Time
(2)
(2)
SDOx Data Output Fall Time
(2)
SDOx Data Output Rise Time
SP35 TscH2doV, SDOx Data Output Valid after SCKx Edge
TscL2doV
SP40 TdiV2scH, Setup Time of SDIx Data Input to
TdiV2scL SCKx Edge
20
20
—
—
—
—
—
—
ns
ns
ns
SP41 TscH2diL, Hold Time of SDIx Data Input to
TscL2diL SCKx Edge
SP50 TssL2scH, SSx to SCKx or SCKx Input
120
TssL2scL
(3)
SP51 TssH2doZ SSx to SDOx Output High-Impedance
10
—
—
50
—
ns
ns
SP52 TscH2ssH SSx after SCKx Edge
1.5 TCY + 40
TscL2ssH
SP60 TssL2doV SDOx Data Output Valid after SSx Edge
—
—
50
ns
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are
not tested.
2: The minimum clock period for SCKx is 100 ns; therefore, the clock generated in Master mode must not violate
this specification.
3: This assumes a 50 pF load on all SPIx pins.
DS39995D-page 292
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
TABLE 29-40: A/D MODULE SPECIFICATIONS
Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX
2.0V to 5.5V PIC24FV32KA3XX
AC CHARACTERISTICS
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristic
Min.
Typ
Max.
Units
Conditions
Device Supply
AD01 AVDD
Module VDD Supply
Greater of:
VDD – 0.3 or 1.8
—
—
—
Lesser of:
VDD + 0.3 or 3.6
V
V
V
PIC24FXXKA30X devices
Greater of:
VDD – 0.3 or 2.0
Lesser of:
VDD + 0.3 or 5.5
PIC24FVXXKA30X
devices
AD02 AVSS
Module VSS Supply
VSS – 0.3
VSS + 0.3
Reference Inputs
AD05 VREFH
AD06 VREFL
AD07 VREF
Reference Voltage High
Reference Voltage Low
AVSS + 1.7
—
—
—
AVDD
V
V
V
AVSS
AVDD – 1.7
AVDD + 0.3
Absolute Reference
Voltage
AVSS – 0.3
AD08 IVREF
AD09 ZVREF
Reference Voltage Input
Current
—
—
1.25
10k
—
—
mA
Reference Input
Impedance
Analog Input
AD10 VINH-VINL Full-Scale Input Span
VREFL
—
—
—
VREFH
AVDD + 0.3
AVDD/2
V
V
V
(Note 2)
AD11 VIN
AD12 VINL
Absolute Input Voltage
AVSS – 0.3
AVSS – 0.3
Absolute VINL Input
Voltage
AD17 RIN
Recommended
—
—
1k
12-bit
Impedance of Analog
Voltage Source
A/D Accuracy
AD20b NR
AD21b INL
Resolution
—
12
±1
—
±9
bits
Integral Nonlinearity
—
—
—
—
—
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5V
AD22b DNL
AD23b GERR
AD24b EOFF
AD25b
Differential Nonlinearity
Gain Error
±1
±1
±1
—
±5
±9
±5
—
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5V
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5V
Offset Error
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5V
Monotonicity(1)
—
Guaranteed
Note 1: The A/D conversion result never decreases with an increase in the input voltage.
2: Measurements are taken with external VREF+ and VREF- used as the A/D voltage reference.
2011-2013 Microchip Technology Inc.
DS39995D-page 293
PIC24FV32KA304 FAMILY
FIGURE 29-22:
A/D CONVERSION TIMING
BSET AD1CON1, SAMP
BCLR AD1CON1, SAMP
(Note 2)
AD55
AD50
Q3/Q4
AD58
AD59
(1)
A/D CLK
. . .
. . .
A/D DATA
11
10
9
2
1
0
OLD DATA
NEW DATA
TCY
ADC1BUFn
AD1IF
SAMP
SAMPLING STOPPED
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEPinstruction to be executed.
2: This is a minimal RC delay (typically 100 ns) which also disconnects the holding capacitor from the analog input.
TABLE 29-41: A/D CONVERSION TIMING REQUIREMENTS(1)
Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX
2.0V to 5.5V PIC24FV32KA3XX
AC CHARACTERISTICS
Operating temperature
-40°C
-40°C
T
A
+85°C for Industrial
+125°C for Extended
TA
Param
No.
Symbol
Characteristic
Min.
Typ
Max.
Units
Conditions
Clock Parameters
AD50
AD51
TAD
TRC
A/D Clock Period
600
—
—
—
—
ns
µs
TCY = 75 ns, AD1CON3 in
default state
A/D Internal RC Oscillator
Period
1.67
Conversion Rate
AD55
TCONV
Conversion Time
—
—
12
14
—
—
TAD
TAD
10-bit results
12-bit results
AD56
AD57
AD58
AD59
FCNV
TSAMP
TACQ
TSWC
Throughput Rate
Sample Time
—
—
—
1
100
—
ksps
TAD
ns
Acquisition Time
750
—
—
—
—
(Note 2)
Switching Time from Convert
to Sample
(Note 3)
AD60
AD61
TDIS
Discharge Time
12
—
—
3
TAD
TAD
Clock Parameters
TPSS
Sample Start Delay from
Setting Sample bit (SAMP)
2
—
Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
2: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD).
3: On the following cycle of the device clock.
DS39995D-page 294
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
30.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
Data for VDD levels greater than 3.3V are applicable to PIC24FV32KA304 family devices only.
30.1 Characteristcs for Industrial Temperature Devices (-40°C to +85°C)
FIGURE 30-1:
TYPICAL AND MAXIMUM IDD vs. FOSC
(EC MODE, 2 MHz TO 32 MHz, -40°C TO +85°C)
20.0
18.0
16.0
14.0
12.0
10.0
8.0
5.5V Max
5.5 V Typ
3.3V Max
3.3V Typ
2.5V Max
2.5V Typ
2.0V Max
2.0V Typ
6.0
4.0
2.0
0.0
2
6
10
14
18
22
26
30
Frequency (MHz)
FIGURE 30-2:
TYPICAL AND MAXIMUM IDD vs. FOSC (EC MODE, 1.95 kHz TO 1 MHz, +25°C)
550
450
350
250
150
5.5V Max
5.5V Typ
3.3V Max
3.3V Typ
2.0V Max
2.0V Typ
50
0
200
400
600
800
1000
Frequency (kHz)
2011-2013 Microchip Technology Inc.
DS39995D-page 295
PIC24FV32KA304 FAMILY
FIGURE 30-3:
TYPICAL AND MAXIMUM IIDLE vs. FREQUENCY (EC MODE, 2 MHz TO 32 MHz)
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
5.5V Max
5.5V Typ
3.3V Max
3.3V Typ
2.5V Max
2.5V Typ
2.0V Max
2.0V Typ
2
6
10
14
18
22
26
30
Frequency (MHz)
FIGURE 30-4:
TYPICAL AND MAXIMUM IIDLE vs. FREQUENCY (EC MODE, 1.95 kHz TO 1 MHz)
180
160
140
120
100
80
5.5V Max
5.5V Typ
3.3V Max
3.3V Typ
2.0V Max
2.0V Typ
60
40
0.0
0.2
0.4
0.6
0.8
1.0
Frequency (MHz)
DS39995D-page 296
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
FIGURE 30-5:
TYPICAL IDD vs. VDD (8 MHZ, EC MODE)
3.5
3.0
2.5
2.0
1.5
1.0
-40C
25C
60C
85C
2
2.5
3
3.5
4
4.5
5
5.5
VDD
FIGURE 30-6:
TYPICAL IDD vs. VDD (FRC MODE)
3.5
3.0
2.5
2.0
-40 C
25 C
60 C
85 C
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VDD
2011-2013 Microchip Technology Inc.
DS39995D-page 297
PIC24FV32KA304 FAMILY
FIGURE 30-7:
TYPICAL AND MAXIMUM IDD vs. TEMPERATURE (FRC MODE)
3.5
3.0
2.5
2.0
5.5V Max
5.5V Typ
3.3V Max
3.3V Typ
2.0V Max
2.0V Typ
1.5
-40
-15
10
35
60
85
Temperature (°C)
FIGURE 30-8:
TYPICAL AND MAXIMUM IIDLE vs. VDD (FRC MODE)
1.10
1.00
0.90
0.80
0.70
-40C Typ
-40C Max
25C Typ
25C Max
60C Typ
60C Max
85C Typ
85C Max
0.60
2
2.5
3
3.5
4
4.5
5
5.5
VDD
DS39995D-page 298
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
FIGURE 30-9:
TYPICAL AND MAXIMUM IIDLE vs. TEMPERATURE (FRC MODE)
1.10
1.00
0.90
0.80
0.70
0.60
5.5V Max
5.5V Typ
3.3V Max
3.3V Typ
2.0V Max
2.0V Typ
-40
-15
10
35
60
85
Temperature (°C)
2011-2013 Microchip Technology Inc.
DS39995D-page 299
PIC24FV32KA304 FAMILY
FIGURE 30-10:
FRC FREQUENCY ACCURACY vs. VDD
0.5
0
-0.5
-1
-40 C
25 C
60 C
85 C
-1.5
-2
-2.5
2
2.5
3
3.5
4
4.5
5
5.5
VDD
FIGURE 30-11:
FRC FREQUENCY ACCURACY vs. TEMPERATURE (2.0V VDD 5.5V)
0.5
0
-0.5
-1
-1.5
-2
-2.5
-3
-3.5
-4
-40
-20
0
20
40
60
80
Temperature (°C)
DS39995D-page 300
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
FIGURE 30-12:
LPRC FREQUENCY ACCURACY vs. VDD
1
0
-1
-2
-3
-4
-40 C
25 C
60 C
85 C
-5
2
2.5
3
3.5
4
4.5
5
5.5
VDD
FIGURE 30-13:
LPRC FREQUENCY ACCURACY vs. TEMPERATURE (2.0V VDD 5.5V)
1
0
-1
-2
-3
-4
-5
-6
-40
-20
0
20
40
60
80
Temperature (°C)
2011-2013 Microchip Technology Inc.
DS39995D-page 301
PIC24FV32KA304 FAMILY
FIGURE 30-14:
TYPICAL AND MAXIMUM IPD vs. VDD
3.5
3.0
2.5
2.0
1.5
1.0
0.5
-40C Typ
-40C Max
25C Typ
25C Max
60C Typ
60C Max
85C Typ
85C Max
0.0
2
2.5
3
3.5
4
VDD
4.5
5
5.5
FIGURE 30-15:
TYPICAL AND MAXIMUM IPD vs. TEMPERATURE
2.0
1.5
1.0
0.5
5.5V Max
5.5V Typ
3.3V Max
3.3V Typ
2.0V Max
2.0V Typ
0.0
-40
-15
10
35
60
85
Temperature (°C)
DS39995D-page 302
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
FIGURE 30-16:
TYPICAL AND MAXIMUM IPD vs. VDD (DEEP SLEEP MODE)
1500
1250
1000
750
-40C Typ
-40C Max
25C Typ
25C Max
60C Typ
60C Max
85C Typ
85C Max
500
250
0
2
2.5
3
3.5
4
4.5
5
5.5
VDD
FIGURE 30-17:
TYPICAL AND MAXIMUM IPD vs. TEMPERATURE (DEEP SLEEP MODE)
1500
1250
1000
750
5.5V Max
5.5V Typ
3.3V Max
3.3V Typ
2.0V Max
2.0V Typ
500
250
0
-40
-15
10
35
60
85
Temperature (°C)
2011-2013 Microchip Technology Inc.
DS39995D-page 303
PIC24FV32KA304 FAMILY
FIGURE 30-18:
TYPICAL IBOR vs. VDD
10.0
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
-40 C
25 C
60 C
85 C
0.0
2
2.5
3
3.5
4
4.5
5
5.5
VDD
FIGURE 30-19:
TYPICAL IWDT vs. VDD
1.2
1.0
0.8
0.6
0.4
0.2
-40C
25C
60C
85C
0.0
2
2.5
3
3.5
4
4.5
5
5.5
VDD
DS39995D-page 304
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
FIGURE 30-20:
TYPICAL IDSBOR vs. VDD
25
20
15
10
5
-40 C
25 C
60 C
85 C
0
2
2.5
3
3.5
4
4.5
5
5.5
VDD
FIGURE 30-21:
TYPICAL IHLVD vs. VDD
10.0
9.0
8.0
7.0
6.0
5.0
4.0
-40C
25C
60C
85C
3.0
2
2.5
3
3.5
4
4.5
5
5.5
VDD
2011-2013 Microchip Technology Inc.
DS39995D-page 305
PIC24FV32KA304 FAMILY
FIGURE 30-22:
TYPICAL IDSWDT vs. VDD
1.4
1.2
1.0
0.8
0.6
0.4
0.2
85 C
60 C
25 C
-40 C
0.0
2
2.5
3
3.5
4
4.5
5
5.5
VDD
FIGURE 30-23:
TYPICAL VBOR vs. TEMPERATURE (BOR TRIP POINT 3)
1.88
1.86
1.84
1.82
1.80
-40
-20
0
20
40
60
80
Temperature (°C)
DS39995D-page 306
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
FIGURE 30-24:
TYPICAL VOH vs. IOH (GENERAL PURPOSE I/O, AS A FUNCTION OF VDD)
6.0
5.0
4.0
3.0
2.0
1.0
5.0V
3.3V
1.8V
0.0
0
-5
-10
-15
-20
-25
IOH (mA)
FIGURE 30-25:
TYPICAL VOH vs. IOH (GENERAL PURPOSE I/O, AS A FUNCTION OF
TEMPERATURE, 2.0V VDD 5.5V)
3.5
3.0
2.5
2.0
1.5
-40 C
25 C
60 C
85 C
1.0
0
-5
-10
-15
IOH (mA)
-20
-25
2011-2013 Microchip Technology Inc.
DS39995D-page 307
PIC24FV32KA304 FAMILY
FIGURE 30-26:
TYPICAL VOL vs. IOL (GENERAL PURPOSE I/O, AS A FUNCTION OF VDD)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.8 V
2.5 V
3.3 V
5.0 V
0
5
10
15
20
25
IOL (mA)
FIGURE 30-27:
TYPICAL VOL vs. IOL (GENERAL PURPOSE I/O, AS A FUNCTION OF
TEMPERATURE, 2.0V VDD 5.5V)
1.2
1.0
0.8
0.6
0.4
0.2
-40 C
25 C
60 C
85 C
0.0
0
5
10
15
IOL (mA)
20
25
DS39995D-page 308
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
FIGURE 30-28:
VIL/VIH vs. VDD (GENERAL PURPOSE I/O, TEMPERATURES AS NOTED)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
Ensured Logic High
VIH Typical
VIL Typical
Indeterminate
VIH Max -40°C
VIL Min 85°C
Ensured Logic Low
0.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VDD
FIGURE 30-29:
VIL/VIH vs. VDD (I2C™, TEMPERATURES AS NOTED)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
Ensured Logic High
VIH Typical
C
VIL Typical
Indeterminate
VIH Max -40°C
VIL Min 85°C
Ensured Logic Low
0.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VDD
2011-2013 Microchip Technology Inc.
DS39995D-page 309
PIC24FV32KA304 FAMILY
FIGURE 30-30:
VIL/VIH vs. VDD (OSCO, TEMPERATURES AS NOTED)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Ensured Logic High
VIH Typical
VIH Max -40C
Indeterminate
VIL Typical
VIH Max -40°C
Ensured Logic Low
VIL Min 85°C
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VDD
FIGURE 30-31:
VIL/VIH vs. VDD (MCLR, TEMPERATURES AS NOTED)
3.0
2.5
2.0
1.5
1.0
0.5
Ensured Logic High
Indeterminate
VIH Typical
V
VIL Typical
VIHMax-40°C
VIL Min 85°C
Ensured Logic Low
0.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VDD
DS39995D-page 310
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
FIGURE 30-32:
1.035
TYPICAL BAND GAP VOLTAGE vs. VDD
1.030
-40C
25C
60C
85C
1.025
1.020
1.015
1.010
2
2.5
3
3.5
4
4.5
5
5.5
VDD
FIGURE 30-33:
TYPICAL BAND GAP VOLTAGE vs. TEMPERATURE (2.0V VDD 5.5V)
1.04
1.03
1.02
1.01
1.00
-40
-15
10
35
60
85
Temperature (°C)
2011-2013 Microchip Technology Inc.
DS39995D-page 311
PIC24FV32KA304 FAMILY
FIGURE 30-34:
TYPICAL VOLTAGE REGULATOR OUTPUT vs. VDD
3.35
3.34
3.33
3.32
3.31
3.30
3.29
3.28
3.27
3.26
-40 C
25 C
60 C
85 C
3.25
2
2.5
3
3.5
4
4.5
5
5.5
VDD
FIGURE 30-35:
TYPICAL VOLTAGE REGULATOR OUTPUT vs. TEMPERATURE
3.35
3.34
3.33
3.32
3.31
3.30
3.29
3.28
3.27
3.26
3.25
2.0V
3.3V
5.5V
-40
-15
10
35
60
85
Temperature (°C)
DS39995D-page 312
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
FIGURE 30-36:
HLVD TRIP POINT VOLTAGE vs. TEMPERATURE (HLVDL<3:0> = 0000,
PIC24F32KA304 FAMILY DEVICES ONLY
1.90
1.85
1.80
1.75
1.70
Average
Maxim um
Minimum
-40
-20
0
20
40
60
80
Temperature (°C)
FIGURE 30-37:
TEMPERATURE SENSOR DIODE VOLTAGE vs. TEMPERATURE
(2.0V VDD 5.5V)
0.90
0.85
0.80
0.75
0.70
0.65
0.60
-40
-20
0
20
40
60
80
Temperature (°C)
2011-2013 Microchip Technology Inc.
DS39995D-page 313
PIC24FV32KA304 FAMILY
FIGURE 30-38:
CTMU OUTPUT CURRENT vs. TEMPERATURE (IRNG<1:0> = 01,
2.0V VDD 5.5V)
0.7
0.65
0.6
0.55
0.5
-40
-20
0
20
40
60
80
Temperature (°C)
FIGURE 30-39:
CTMU OUTPUT CURRENT vs. VDD (IRNG<1:0> = 01)
0.70
0.65
0.60
0.55
-40 C
25 C
60 C
85 C
0.50
2
2.5
3
3.5
4
4.5
5
5.5
VDD
DS39995D-page 314
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
30.2 Characteristics for Extended Temperature Devices (-40°C to +125°C)
Note:
Data for VDD levels greater than 3.3V are applicable to PIC24FV32KA304 family devices only.
FIGURE 30-40:
TYPICAL AND MAXIMUM IIDLE vs. VDD (FRC MODE)
VDD
FIGURE 30-41:
TYPICAL AND MAXIMUM IIDLE vs. TEMPERATURE (FRC MODE)
Temperature (°C)
2011-2013 Microchip Technology Inc.
DS39995D-page 315
PIC24FV32KA304 FAMILY
FIGURE 30-42:
TYPICAL AND MAXIMUM IPD vs. VDD
VDD
FIGURE 30-43:
TYPICAL AND MAXIMUM IPD vs. TEMPERATURE
Temperature (°C)
DS39995D-page 316
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
FIGURE 30-44:
TYPICAL AND MAXIMUM IPD vs. VDD (DEEP SLEEP MODE)
VDD
FIGURE 30-45:
TYPICAL AND MAXIMUM IPD vs. TEMPERATURE (DEEP SLEEP MODE)
Temperature (°C)
2011-2013 Microchip Technology Inc.
DS39995D-page 317
PIC24FV32KA304 FAMILY
FIGURE 30-46:
TYPICAL IWDT vs. VDD
VDD
FIGURE 30-47:
TYPICAL IDSBOR vs. VDD
VDD
DS39995D-page 318
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
FIGURE 30-48:
TYPICAL IHLVD vs. VDD
VDD
2011-2013 Microchip Technology Inc.
DS39995D-page 319
PIC24FV32KA304 FAMILY
FIGURE 30-49:
TYPICAL VOL vs. IOL (GENERAL I/O, 2.0V VDD 5.5V)
IOL (MA)
FIGURE 30-50:
TYPICAL VOH vs. IOH (GENERAL I/O, AS A FUNCTION OF TEMPERATURE,
2.0V VDD 5.5V)
-
-
-
-
-
IOH (mA)
DS39995D-page 320
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
FIGURE 30-51:
VIL/VIH vs. VDD (GENERAL PURPOSE I/O, TEMPERATURES AS NOTED)
VIH Typical
VIL Typical
Ensured Logic High
VIH Max -40°C
VIL Min 125°C
Indeterminate
Ensured Logic Low
VDD
VIL/VIH vs. VDD (I2C™, TEMPERATURES AS NOTED)
VIH Typical
FIGURE 30-52:
VIL Typical
Ensured Logic High
VIH Max -40°C
VIL Min 125°C
Indeterminate
Ensured Logic Low
VDD
2011-2013 Microchip Technology Inc.
DS39995D-page 321
PIC24FV32KA304 FAMILY
FIGURE 30-53:
VIL/VIH vs. VDD (OSCO, TEMPERATURES AS NOTED)
VIH Typical
VIL Typical
Ensured Logic High
VIH Max -40°C
VIL Min 125°C
Indeterminate
Ensured Logic Low
VDD
FIGURE 30-54:
VIL/VIH vs. VDD (MCLR, TEMPERATURES AS NOTED)
VIH Typical
VIL Typical
VIH Max -40°C
VIL Min 125°C
Ensured Logic High
Indeterminate
Ensured Logic Low
VDD
DS39995D-page 322
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
FIGURE 30-55:
TYPICAL BAND GAP VOLTAGE vs. TEMPERATURE (2.0V VDD 5.5V)
Temperature (°C)
FIGURE 30-56:
TYPICAL VOLTAGE REGULATOR OUTPUT vs. TEMPERATURE
Temperature (°C)
2011-2013 Microchip Technology Inc.
DS39995D-page 323
PIC24FV32KA304 FAMILY
NOTES:
DS39995D-page 324
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
31.0 PACKAGING INFORMATION
31.1 Package Marking Information
20-Lead PDIP (300 mil)
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
PIC24FV32KA301
-I/P
e
3
1210017
28-Lead SPDIP (.300")
Example
PIC24FV32KA302
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
e
3
-I/SP
YYWWNNN
1210017
20-Lead SSOP (5.30 mm)
Example
XXXXXXXXXXX
XXXXXXXXXXX
PIC24FV32KA
3
e
301-I/SS
1210017
YYWWNNN
28-Lead SSOP (5.30 mm)
Example
PIC24FV32KA
XXXXXXXXXXXX
XXXXXXXXXXXX
e
3
302-I/SS
1210017
YYWWNNN
Legend: XX...X Product-specific information
Y
YY
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note:
In the event the full Microchip part number cannot be marked on one line, it
will be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2011-2013 Microchip Technology Inc.
DS39995D-page 325
PIC24FV32KA304 FAMILY
20-Lead SOIC (7.50 mm)
Example
PIC24FV32KA301
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
e
3
-I/SO
1210017
YYWWNNN
28-Lead SOIC (7.50 mm)
Example
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
PIC24FV32KA302
-I/SO
e
3
1210017
YYWWNNN
28-Lead QFN (6x6 mm)
Example
PIN 1
PIN 1
24FV32KA
302-I/ML
1210017
XXXXXXXX
XXXXXXXX
YYWWNNN
e
3
DS39995D-page 326
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
44-Lead QFN (8x8x0.9 mm)
Example
PIN 1
PIN 1
XXXXXXXXXXX
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
PIC24FV32KA
e
3
304-I/PT
1210017
44-Lead TQFP (10x10x1 mm)
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
24FV32KA
304-I/PT
1210017
e
3
48-Lead UQFN (6x6x0.5 mm)
Example
PIN 1
PIN 1
XXXXXXXX
XXXXXXXX
YYWWNNN
24FV32KA
e3
304-I/MV
1210017
2011-2013 Microchip Technology Inc.
DS39995D-page 327
PIC24FV32KA304 FAMILY
31.2 Package Details
The following sections give the technical details of the packages.
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DS39995D-page 328
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
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ꢛꢗꢋꢄꢊꢜ
ꢁꢂ ꢃꢄꢅꢀꢁꢀ ꢄ!"ꢆꢇꢀꢄꢅ#ꢈ$ꢀ%ꢈꢆ&"ꢉꢈꢀ'ꢆꢊꢀ ꢆꢉꢊ(ꢀ)"&ꢀ'"!&ꢀ)ꢈꢀꢇꢋꢌꢆ&ꢈ#ꢀ*ꢄ&ꢍꢄꢅꢀ&ꢍꢈꢀꢍꢆ&ꢌꢍꢈ#ꢀꢆꢉꢈꢆꢂ
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1ꢐ,2 1ꢆ!ꢄꢌꢀꢒꢄ'ꢈꢅ!ꢄꢋꢅꢂꢀꢙꢍꢈꢋꢉꢈ&ꢄꢌꢆꢇꢇꢊꢀꢈ$ꢆꢌ&ꢀ ꢆꢇ"ꢈꢀ!ꢍꢋ*ꢅꢀ*ꢄ&ꢍꢋ"&ꢀ&ꢋꢇꢈꢉꢆꢅꢌꢈ!ꢂ
ꢔꢄꢌꢉꢋꢌꢍꢄꢓ ꢙꢈꢌꢍꢅꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢄꢅꢑ ,ꢕꢖꢞꢕꢜꢕ1
2011-2013 Microchip Technology Inc.
DS39995D-page 329
PIC24FV32KA304 FAMILY
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇ!#$ꢌꢑ"ꢇ!ꢕꢅꢉꢉꢇ%ꢏꢋꢉꢌꢑꢄꢇꢒ!!ꢓꢇMꢇ&'ꢔꢁꢇꢕꢕꢇꢖꢗꢆꢘꢇꢙ!!%ꢈꢚꢇ
ꢛꢗꢋꢄꢜ 3ꢋꢉꢀ&ꢍꢈꢀ'ꢋ!&ꢀꢌ"ꢉꢉꢈꢅ&ꢀꢓꢆꢌ4ꢆꢑꢈꢀ#ꢉꢆ*ꢄꢅꢑ!(ꢀꢓꢇꢈꢆ!ꢈꢀ!ꢈꢈꢀ&ꢍꢈꢀꢔꢄꢌꢉꢋꢌꢍꢄꢓꢀꢃꢆꢌ4ꢆꢑꢄꢅꢑꢀꢐꢓꢈꢌꢄ%ꢄꢌꢆ&ꢄꢋꢅꢀꢇꢋꢌꢆ&ꢈ#ꢀꢆ&ꢀ
ꢍ&&ꢓ255***ꢂ'ꢄꢌꢉꢋꢌꢍꢄꢓꢂꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢄꢅꢑ
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: ꢈꢉꢆꢇꢇꢀ9ꢈꢅꢑ&ꢍ
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9ꢈꢆ#ꢀꢙꢍꢄꢌ4ꢅꢈ!!
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ꢁꢂ ꢃꢄꢅꢀꢁꢀ ꢄ!"ꢆꢇꢀꢄꢅ#ꢈ$ꢀ%ꢈꢆ&"ꢉꢈꢀ'ꢆꢊꢀ ꢆꢉꢊ(ꢀ)"&ꢀ'"!&ꢀ)ꢈꢀꢇꢋꢌꢆ&ꢈ#ꢀ*ꢄ&ꢍꢄꢅꢀ&ꢍꢈꢀꢍꢆ&ꢌꢍꢈ#ꢀꢆꢉꢈꢆꢂ
ꢎꢂ ꢒꢄ'ꢈꢅ!ꢄꢋꢅ!ꢀꢒꢀꢆꢅ#ꢀ.ꢁꢀ#ꢋꢀꢅꢋ&ꢀꢄꢅꢌꢇ"#ꢈꢀ'ꢋꢇ#ꢀ%ꢇꢆ!ꢍꢀꢋꢉꢀꢓꢉꢋ&ꢉ"!ꢄꢋꢅ!ꢂꢀꢔꢋꢇ#ꢀ%ꢇꢆ!ꢍꢀꢋꢉꢀꢓꢉꢋ&ꢉ"!ꢄꢋꢅ!ꢀ!ꢍꢆꢇꢇꢀꢅꢋ&ꢀꢈ$ꢌꢈꢈ#ꢀꢕꢂꢎꢕꢀ''ꢀꢓꢈꢉꢀ!ꢄ#ꢈꢂ
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1ꢐ,2 1ꢆ!ꢄꢌꢀꢒꢄ'ꢈꢅ!ꢄꢋꢅꢂꢀꢙꢍꢈꢋꢉꢈ&ꢄꢌꢆꢇꢇꢊꢀꢈ$ꢆꢌ&ꢀ ꢆꢇ"ꢈꢀ!ꢍꢋ*ꢅꢀ*ꢄ&ꢍꢋ"&ꢀ&ꢋꢇꢈꢉꢆꢅꢌꢈ!ꢂ
ꢝ.32 ꢝꢈ%ꢈꢉꢈꢅꢌꢈꢀꢒꢄ'ꢈꢅ!ꢄꢋꢅ(ꢀ"!"ꢆꢇꢇꢊꢀ*ꢄ&ꢍꢋ"&ꢀ&ꢋꢇꢈꢉꢆꢅꢌꢈ(ꢀ%ꢋꢉꢀꢄꢅ%ꢋꢉ'ꢆ&ꢄꢋꢅꢀꢓ"ꢉꢓꢋ!ꢈ!ꢀꢋꢅꢇꢊꢂ
ꢔꢄꢌꢉꢋꢌꢍꢄꢓ ꢙꢈꢌꢍꢅꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢄꢅꢑ ,ꢕꢖꢞꢕꢜꢎ1
DS39995D-page 330
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011-2013 Microchip Technology Inc.
DS39995D-page 331
PIC24FV32KA304 FAMILY
ꢀ ꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇ!#$ꢌꢑ"ꢇ!ꢕꢅꢉꢉꢇ%ꢏꢋꢉꢌꢑꢄꢇꢒ!!ꢓꢇMꢇ&'ꢔꢁꢇꢕꢕꢇꢖꢗꢆꢘꢇꢙ!!%ꢈꢚ
ꢛꢗꢋꢄꢜ 3ꢋꢉꢀ&ꢍꢈꢀ'ꢋ!&ꢀꢌ"ꢉꢉꢈꢅ&ꢀꢓꢆꢌ4ꢆꢑꢈꢀ#ꢉꢆ*ꢄꢅꢑ!(ꢀꢓꢇꢈꢆ!ꢈꢀ!ꢈꢈꢀ&ꢍꢈꢀꢔꢄꢌꢉꢋꢌꢍꢄꢓꢀꢃꢆꢌ4ꢆꢑꢄꢅꢑꢀꢐꢓꢈꢌꢄ%ꢄꢌꢆ&ꢄꢋꢅꢀꢇꢋꢌꢆ&ꢈ#ꢀꢆ&ꢀ
ꢍ&&ꢓ255***ꢂ'ꢄꢌꢉꢋꢌꢍꢄꢓꢂꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢄꢅꢑ
D
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E1
1
2
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6ꢅꢄ&!
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ꢒꢄ'ꢈꢅ!ꢄꢋꢅꢀ9ꢄ'ꢄ&!
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: ꢈꢉꢆꢇꢇꢀ=ꢄ#&ꢍ
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: ꢈꢉꢆꢇꢇꢀ9ꢈꢅꢑ&ꢍ
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9ꢈꢆ#ꢀꢙꢍꢄꢌ4ꢅꢈ!!
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M
M
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ꢁꢂ ꢃꢄꢅꢀꢁꢀ ꢄ!"ꢆꢇꢀꢄꢅ#ꢈ$ꢀ%ꢈꢆ&"ꢉꢈꢀ'ꢆꢊꢀ ꢆꢉꢊ(ꢀ)"&ꢀ'"!&ꢀ)ꢈꢀꢇꢋꢌꢆ&ꢈ#ꢀ*ꢄ&ꢍꢄꢅꢀ&ꢍꢈꢀꢍꢆ&ꢌꢍꢈ#ꢀꢆꢉꢈꢆꢂ
ꢎꢂ ꢒꢄ'ꢈꢅ!ꢄꢋꢅ!ꢀꢒꢀꢆꢅ#ꢀ.ꢁꢀ#ꢋꢀꢅꢋ&ꢀꢄꢅꢌꢇ"#ꢈꢀ'ꢋꢇ#ꢀ%ꢇꢆ!ꢍꢀꢋꢉꢀꢓꢉꢋ&ꢉ"!ꢄꢋꢅ!ꢂꢀꢔꢋꢇ#ꢀ%ꢇꢆ!ꢍꢀꢋꢉꢀꢓꢉꢋ&ꢉ"!ꢄꢋꢅ!ꢀ!ꢍꢆꢇꢇꢀꢅꢋ&ꢀꢈ$ꢌꢈꢈ#ꢀꢕꢂꢎꢕꢀ''ꢀꢓꢈꢉꢀ!ꢄ#ꢈꢂ
-ꢂ ꢒꢄ'ꢈꢅ!ꢄꢋꢅꢄꢅꢑꢀꢆꢅ#ꢀ&ꢋꢇꢈꢉꢆꢅꢌꢄꢅꢑꢀꢓꢈꢉꢀꢗꢐꢔ.ꢀ0ꢁꢖꢂꢘꢔꢂ
1ꢐ,2 1ꢆ!ꢄꢌꢀꢒꢄ'ꢈꢅ!ꢄꢋꢅꢂꢀꢙꢍꢈꢋꢉꢈ&ꢄꢌꢆꢇꢇꢊꢀꢈ$ꢆꢌ&ꢀ ꢆꢇ"ꢈꢀ!ꢍꢋ*ꢅꢀ*ꢄ&ꢍꢋ"&ꢀ&ꢋꢇꢈꢉꢆꢅꢌꢈ!ꢂ
ꢝ.32 ꢝꢈ%ꢈꢉꢈꢅꢌꢈꢀꢒꢄ'ꢈꢅ!ꢄꢋꢅ(ꢀ"!"ꢆꢇꢇꢊꢀ*ꢄ&ꢍꢋ"&ꢀ&ꢋꢇꢈꢉꢆꢅꢌꢈ(ꢀ%ꢋꢉꢀꢄꢅ%ꢋꢉ'ꢆ&ꢄꢋꢅꢀꢓ"ꢉꢓꢋ!ꢈ!ꢀꢋꢅꢇꢊꢂ
ꢔꢄꢌꢉꢋꢌꢍꢄꢓ ꢙꢈꢌꢍꢅꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢄꢅꢑ ,ꢕꢖꢞꢕꢜ-1
DS39995D-page 332
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011-2013 Microchip Technology Inc.
DS39995D-page 333
PIC24FV32KA304 FAMILY
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS39995D-page 334
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011-2013 Microchip Technology Inc.
DS39995D-page 335
PIC24FV32KA304 FAMILY
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS39995D-page 336
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011-2013 Microchip Technology Inc.
DS39995D-page 337
PIC24FV32KA304 FAMILY
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS39995D-page 338
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011-2013 Microchip Technology Inc.
DS39995D-page 339
PIC24FV32KA304 FAMILY
DS39995D-page 340
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
2011-2013 Microchip Technology Inc.
DS39995D-page 341
PIC24FV32KA304 FAMILY
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DS39995D-page 342
2011-2013 Microchip Technology Inc.
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2011-2013 Microchip Technology Inc.
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PIC24FV32KA304 FAMILY
DS39995D-page 344
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
2011-2013 Microchip Technology Inc.
DS39995D-page 345
PIC24FV32KA304 FAMILY
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DS39995D-page 346
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011-2013 Microchip Technology Inc.
DS39995D-page 347
PIC24FV32KA304 FAMILY
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS39995D-page 348
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011-2013 Microchip Technology Inc.
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PIC24FV32KA304 FAMILY
DS39995D-page 350
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
Added the following timing diagrams and timing
requirement tables to Section 29.0 “Electrical
Characteristics”:
APPENDIX A: REVISION HISTORY
Revision A (March 2011)
• Figure 29-6 (Reset, Watchdog Timer, Oscillator
Start-up Timer and Power-up Timer Timing
Characteristics)
Original data sheet for the PIC24FV32KA304 family of
devices.
• Figure 29-7 (Brown-out Reset Characteristics)
Revision B (April 2011)
• Figure 29-9 (Input Capture x Timings) through
Figure 29-21 (SPIx Module Slave Mode Timing
Characteristics (CKE = 1))
Section 25.0 “Charge Time Measurement Unit
(CTMU)” was revised to change the description of the
IRNGx bits in CTMUICON (Register 25-3). Setting ‘01’
is the base current level (0.55 A nominal) and setting
‘00’ is 1000x base current.
• Table 29-28 (Input Capture x Requirements)
through Table 29-39 (SPIx Module Slave Mode
Timing Requirements (CKE = 1))
• Figure 29-22 (A/D Conversion Timing)
Section 29.0 “Electrical Characteristics” was revised
to change the following typical IPD specifications:
Updated Table 29-5 to add specification, DC15.
• DC20h/i/j/k from 204 A to 200 A
• DC60h/i/j/k from 0.15 A to 0.025 A
• DC60l/m/n/o from 0.25 A to 0.040 A
• DC72h/i/j/k from 0.80 A to 0.70 A
Replaced Table 29-6, Table 29-7 and Table 29-8 with
new, shorter versions that remove unimplemented tem-
perature options. (No existing specification values
have been changed in this process.)
Updated Table 29-16 with correct values for
CTMUICON bit settings.
Revision C (April 2012)
Combined previous Table 29-21 and Table 29-22 to
create a new Table 29-21 (AC Characteristics: Internal
RC Accuracy). All existing subsequent tables are
renumbered accordingly.
Updated the Pin Diagrams on Pages 3 through 7, to
change “LVDIN” to “HLVDIN” in all occurrences, and
correct the placement of certain functions.
Updated Table 1-3 to remove references to unimple-
mented package types, corrected several erroneous
pin assignments and removed other alternate but
unimplemented assignments.
Updated Table 29-26 to add specifications, SY35 and
SY55.
Updated Table 29-40:
• Split AD01 into separate entries for “F” and “FV”
device families
For Section 5.0 “Flash Program Memory”, updated
Example 5-2, Example 5-3 and Example 5-4 with new
table offset functions.
• Added specifications, AD08 (IVREF) and AD09
(ZVREF)
Updated Figure 12-1 to correctly show the
implemented Timer1 input options.
• Changed AD17 (2.5 k max. to 1 k max.)
Updated Table 29-41:
For Section 22.0 “12-Bit A/D Converter with
Threshold Detect”:
• Changed AD50 (75 ns min. to 600 ns min.)
• Changed AD51 (250 ns typ. to 1.67 µs typ.)
• Changed AD60 (0.5 TAD min. to 2 TAD min.)
• Updated Register 22-1 to add the MODE12 bit
• Updated the descriptions of the PVCFGx and
CSCNA bits in Register 22-2
• Split AD55 into separate entries for 10-bit and
12-bit conversions
• Updated Register 22-4 to change the VRSREQ
bit to a reserved bit position
Added Section 30.0 “DC and AC Characteristics
Graphs and Tables”, with Figure 30-1 through
Figure 30-39.
• Modified footnote text in Register 22-5
• Corrected CHOLD in Figure 22-2
For Section 25.0 “Charge Time Measurement Unit
(CTMU)”:
Replaced some of the packaging diagrams in
Section 31.0 “Packaging Information” with the
newly revised diagrams.
• Updated the text in Section 25.1 “Measuring
Capacitance” and Section 25.3 “Pulse Genera-
tion and Delay” to better reflect the module’s
implementation
Other minor typographic corrections throughout.
• Updated Figure 25-3 to show additional detail in
pulse generation
2011-2013 Microchip Technology Inc.
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For Section 29.0 “Electrical Characteristics”:
Revision D (March 2013)
• Updated captioning on all specification tables to
include extended temperature data
Throughout the data sheet: corrected the name of
RCON register bit 12 as RETEN, to maintain consis-
tency with other PIC24F devices (was previously
LVREN). In addition, changed the description of the bit
in the RCON register (Register 7-1) to clarify its
function in controlling the Retention Regulator.
• Amended Table 29-8 to include +125°C data for
all existing specifications
• Added new Table 29-27 and Figure 29-8 to char-
acterize external clock input specifications for
general purpose timers (all subsequent tables and
figures are renumbered accordingly)
Throughout the data sheet: corrected the name of
FPOR Configuration register bit 2 as RETCFG, to
maintain consistency with other PIC24F devices (was
previously LVRCFG). In addition, changed the descrip-
tion of the bit in the FPOR Configuration register
(Register 26-6) to clarify its function in enabling the
Retention Regulator.
• Added parameter numbers to several existing but
previous unnumbered parameters in multiple
tables
Updated Section 30.0 “DC and AC Characteristics
Graphs and Tables”:
For
Section 10.4
“Voltage
Regulator-Based
• Added additional graphs for Extended tempera-
ture devices (Section 30.2 “Characteristics for
Extended Temperature Devices (-40°C to
+125°C)”, Figure 30-40 through Figure 30-56)
Power-Saving Features”:
• Removed all references to Fast Wake-up Sleep
mode, not implemented in this device
• Replaced Figure 30-32 with an updated graph
• Changed all references of the High-Voltage
Regulator to On-Chip Voltage Regulator
Replaced some of the packaging diagrams in
Section 31.0 “Packaging Information” with the
newly revised diagrams.
• Removed all references to the Low-Voltage
Regulator, which was replaced in most cases with
Retention Regulator
Updates Product Information System to include
extended temperature devices in the information key.
• Clarified the Retention Regulator’s operation in
Section 10.4.3 “Retention Sleep Mode”
(formerly “Low-Voltage Sleep Mode”)
Other minor typographic corrections throughout.
• Modified Table 10-1 for consistency with the
above changes
Corrects Section 26.2 “On-Chip Voltage Regulator”
to clarify the operation of the on-chip regulator in “F”
and “FV” families, and include DC parameters and
specifications.
DS39995D-page 352
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PIC24FV32KA304 FAMILY
INDEX
Input Capture x ........................................................ 147
MCLR Pin Connections ............................................. 24
On-Chip Regulator Connections .............................. 248
Output Compare x (16-Bit Mode) ............................ 152
Output Compare x (Double-Buffered,
A
A/D
Buffer Data Formats ................................................. 221
Control Registers ..................................................... 210
AD1CHITH/L .................................................... 210
AD1CHS .......................................................... 210
AD1CON1 ........................................................ 210
AD1CON2 ........................................................ 210
AD1CON3 ........................................................ 210
AD1CON5 ........................................................ 210
AD1CSSH/L ..................................................... 210
AD1CTMUENH/L ............................................. 210
Module Specifications .............................................. 293
Result Buffers .......................................................... 210
Sampling Requirements ........................................... 219
Transfer Function ..................................................... 220
16-Bit PWM Mode) .......................................... 154
PIC24F CPU Core ..................................................... 30
PIC24FV32KA304 Family (General) ......................... 15
PSV Operation ........................................................... 55
Recommended Minimum Connections ...................... 23
Reset System ............................................................ 69
RTCC Module .......................................................... 185
Serial Resistor ......................................................... 131
Shared I/O Port Structure ........................................ 135
Simplified UARTx .................................................... 177
SPI1 Module (Enhanced Buffer Mode) .................... 163
SPI1 Module (Standard Buffer Mode) ..................... 162
System Clock ........................................................... 115
Table Register Addressing ........................................ 57
Timer2/3, Timer4/5 (32-Bit) ..................................... 142
Watchdog Timer (WDT) ........................................... 249
AC Characteristics
Capacitive Loading Requirements on
Output Pins ...................................................... 276
Comparator .............................................................. 280
Comparator Voltage Reference Settling Time ......... 280
Internal RC Accuracy ............................................... 278
Internal RC Oscillator Specifications ........................ 278
Load Conditions and Requirements ......................... 276
Reset, Watchdog Timer. Oscillator Start-up Timer,
Power-up Timer, Brown-out
Brown-out Reset
Trip Points ............................................................... 266
C
C Compilers
MPLAB C18 ............................................................. 252
Charge Time Measurement Unit. See CTMU.
Reset Requirements ........................................ 281
Temperature and Voltage Specifications ................. 276
Code Examples
Assembler
MPASM Assembler .................................................. 252
Basic Sequence for Clock Switching ....................... 122
Data EEPROM Bulk Erase ........................................ 67
Data EEPROM Unlock Sequence ............................. 63
Erasing a Program Memory Row, ‘C’ Language ....... 61
Erasing a Program Memory Row,
Assembly Language .......................................... 60
I/O Port Write/Read ................................................. 138
Initiating a Programming Sequence,
B
Baud Rate Generator
Setting as a Bus Master ........................................... 171
Block Diagrams
12-Bit A/D Converter ................................................ 208
12-Bit A/D Converter Analog Input Model ................ 219
16-Bit Asynchronous Timer3 and Timer5 ................ 143
16-Bit Synchronous Timer2 and Timer4 .................. 143
16-Bit Timer1 ........................................................... 139
Accessing Program Memory with
Table Instructions .............................................. 54
CALL Stack Frame ..................................................... 51
Comparator Voltage Reference ............................... 229
Comparator x Module .............................................. 225
CPU Programmer’s Model ......................................... 31
CRC Module ............................................................ 199
CRC Shift Engine ..................................................... 199
CTMU Connections and Internal Configuration
for Capacitance Measurement ......................... 232
CTMU Typical Connections and Internal Configuration
for Pulse Delay Generation .............................. 233
CTMU Typical Connections and Internal Configuration
for Time Measurement ..................................... 232
Data Access from Program Space
‘C’ Language ..................................................... 62
Initiating a Programming Sequence,
Assembly Language .......................................... 62
Loading the Write Buffers, ‘C’ Language ................... 62
Loading the Write Buffers, Assembly Language ....... 61
PWRSAV Instruction Syntax ................................... 125
Reading the Data EEPROM Using the
TBLRD Command ............................................. 68
Setting the RTCWREN Bit ....................................... 186
Single-Word Erase .................................................... 66
Single-Word Write to Data EEPROM ........................ 67
Ultra Low-Power Wake-up Initialization ................... 131
Unlock Sequence .................................................... 126
Code Protection ............................................................... 250
Comparator ...................................................................... 225
Comparator Voltage Reference ....................................... 229
Configuring .............................................................. 229
Configuration Bits ............................................................ 239
Core Features .................................................................... 11
CPU
Address Generation ........................................... 52
Data EEPROM Addressing with TBLPAG and
NVM Registers ................................................... 65
High/Low-Voltage Detect (HLVD) ............................ 205
I2C Module ............................................................... 170
Individual Comparator Configurations ...................... 226
ALU ............................................................................ 33
Control Registers ....................................................... 32
Core Registers ........................................................... 30
Programmer’s Model ................................................. 29
2011-2013 Microchip Technology Inc.
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CRC
Equations
Registers ..................................................................201
Typical Operation .....................................................201
User Interface ..........................................................200
Data .................................................................200
Data Shift Direction ..........................................201
Interrupt Operation ...........................................201
Polynomial .......................................................200
A/D Conversion Clock Period .................................. 219
Baud Rate Reload Calculation ................................. 171
Calculating the PWM Period .................................... 155
Calculation for Maximum PWM Resolution ............. 155
Device and SPIx Clock Speed Relationship ............ 168
PWM Period and Duty Cycle Calculations ............... 155
UARTx Baud Rate with BRGH = 0 .......................... 178
UARTx Baud Rate with BRGH = 1 .......................... 178
Errata ................................................................................... 9
Examples
CTMU
Measuring Capacitance ...........................................231
Measuring Time .......................................................232
Pulse Generation and Delay ....................................233
Customer Change Notification Service ............................358
Customer Notification Service ..........................................358
Customer Support ............................................................358
Baud Rate Error Calculation (BRGH = 0) ................ 178
F
Flash Program Memory
Control Registers ....................................................... 58
Enhanced ICSP Operation ........................................ 58
Programming Algorithm ............................................. 60
Programming Operations ........................................... 58
RTSP Operation ........................................................ 58
Table Instructions ...................................................... 57
D
Data EEPROM Memory .....................................................63
Erasing .......................................................................66
Operations .................................................................65
Programming
Bulk Erase ..........................................................67
Reading Data EEPROM ....................................68
Single-Word Write ..............................................67
Programming Control Registers
G
Guidelines for Getting Started ........................................... 23
H
NVMADR(U) ......................................................65
NVMCON ...........................................................63
NVMKEY ............................................................63
Data Memory
Address Space ...........................................................37
Memory Map ..............................................................37
Near Data Space .......................................................38
Organization ...............................................................38
SFR Space .................................................................38
Software Stack ...........................................................51
Space Width ...............................................................37
DC and AC Characteristics
High/Low-Voltage Detect (HLVD) .................................... 205
I
I/O Ports
Analog Port Pins Configuration ................................ 136
Analog Selection Registers ...................................... 136
Input Change Notification ........................................ 138
Open-Drain Configuration ........................................ 136
Parallel (PIO) ........................................................... 135
I2C
Clock Rates ............................................................. 171
Communicating as Master in Single
Graphs and Tables
Master Environment ........................................ 169
Pin Remapping Options ........................................... 169
Reserved Addresses ............................................... 171
Slave Address Masking ........................................... 171
In-Circuit Debugger .......................................................... 250
In-Circuit Serial Programming (ICSP) .............................. 250
Input Capture
Cascaded (32-Bit) Mode .......................................... 148
Operations ............................................................... 148
Synchronous, Trigger Modes ................................... 147
Input Capture with Dedicated Timers .............................. 147
Instruction Set
Opcode Symbols ..................................................... 256
Overview .................................................................. 257
Summary ................................................................. 255
Internet Address .............................................................. 358
Interrupts
Extended Temperature ....................................315
Industrial Temperature .....................................295
DC Characteristics
BOR Trip Points .......................................................266
Comparator Specifications .......................................274
Comparator Voltage Reference ...............................274
CTMU Current Source .............................................275
Data EEPROM Memory ...........................................274
High/Low-Voltage Detect .........................................266
I/O Pin Input Specifications ......................................272
I/O Pin Output Specifications ...................................273
Idle Current (IIDLE) ...................................................268
Internal Voltage Regulator .......................................275
Operating Current (IDD) ............................................267
Power-Down Current (IPD) .......................................269
Program Memory .....................................................273
Temperature and Voltage Specifications .................265
Development Support ......................................................251
Alternate Interrupt Vector Table (AIVT) ..................... 75
Control and Status Registers ..................................... 78
Implemented Vectors ................................................. 77
Interrupt Vector Table (IVT) ....................................... 75
Reset Sequence ........................................................ 75
Setup Procedures .................................................... 113
Trap Vectors .............................................................. 77
Vector Table .............................................................. 76
E
Electrical Characteristics
Absolute Maximum Ratings .....................................263
Thermal Operating Conditions .................................265
Thermal Packaging ..................................................265
V/F Graphs ...............................................................264
DS39995D-page 354
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
Pulse-Width Modulation (PWM) Mode ............................. 154
Pulse-Width Modulation. See PWM.
PWM
Duty Cycle and Period ............................................. 155
M
Microchip Internet Web Site ............................................. 358
MPLAB ASM30 Assembler, Linker, Librarian .................. 252
MPLAB Integrated Development
Environment Software .............................................. 251
MPLAB PM3 Device Programmer ................................... 254
MPLAB REAL ICE In-Circuit Emulator System ................ 253
MPLINK Object Linker/MPLIB Object Librarian ............... 252
R
Reader Response ............................................................ 359
Register Maps
A/D Converter ............................................................ 47
Analog Select ............................................................ 48
Clock Control ............................................................. 49
CPU Core .................................................................. 39
CRC ........................................................................... 49
CTMU ........................................................................ 48
Deep Sleep ................................................................ 49
I2Cx ........................................................................... 44
ICN ............................................................................ 40
Input Capture ............................................................. 42
Interrupt Controller ..................................................... 41
NVM ........................................................................... 50
Output Compare ........................................................ 43
Pad Configuration ...................................................... 46
PMD ........................................................................... 50
PORTA ...................................................................... 45
PORTB ...................................................................... 45
PORTC ...................................................................... 46
Real-Time Clock and Calendar (RTCC) .................... 48
SPIx ........................................................................... 45
Timer ......................................................................... 42
Triple Comparator ...................................................... 48
UARTx ....................................................................... 44
Ultra Low-Power Wake-up ......................................... 50
Registers
N
Near Data Space ............................................................... 38
O
On-Chip Voltage Regulator .............................................. 248
Oscillator Configuration
Clock Switching ........................................................ 121
Enabling ........................................................... 121
Sequence ......................................................... 121
Configuration Bit Values for Clock Selection ........... 116
CPU Clocking Scheme ............................................ 116
Initial Configuration on POR .................................... 116
Reference Clock Output ........................................... 122
Output Compare
Cascaded (32-Bit) Mode .......................................... 151
Operations ............................................................... 153
Subcycle Resolution ................................................ 156
Synchronous, Trigger Modes ................................... 151
P
Packaging
Details ...................................................................... 328
Marking .................................................................... 325
PIC24F32KA304 Family Device Features (Summary) ....... 14
PIC24FV32KA304 Family Device
AD1CHITH (A/D Scan Compare Hit, High Word) .... 216
AD1CHITH (A/D Scan Compare Hit, Low Word) ..... 216
AD1CHS (A/D Sample Select) ................................ 215
AD1CON1 (A/D Control 1) ....................................... 211
AD1CON2 (A/D Control 2) ....................................... 212
AD1CON3 (A/D Control 3) ....................................... 213
AD1CON5 (A/D Control 5) ....................................... 214
AD1CSSH (A/D Input Scan Select, High Word) ...... 217
AD1CSSL (A/D Input Scan Select, Low Word) ....... 217
AD1CTMUENH (CTMU Enable, High Word) ........... 218
AD1CTMUENL (CTMU Enable, Low Word) ............ 218
ALCFGRPT (Alarm Configuration) .......................... 190
ALMINSEC (Alarm Minutes and Seconds Value) .... 194
ALMTHDY (Alarm Month and Day Value) ............... 193
ALWDHR (Alarm Weekday and Hours Value) ........ 193
ANSA (Analog Selection, PORTA) .......................... 136
ANSB (Analog Selection, PORTB) .......................... 137
ANSC (Analog Selection, PORTC) .......................... 137
CLKDIV (Clock Divider) ........................................... 119
CMSTAT (Comparator x Status) ............................. 228
CMxCON (Comparator x Control) ........................... 227
CORCON (CPU Control) ........................................... 33
CORCON (CPU Core Control) .................................. 80
CRCCON1 (CRC Control 1) .................................... 202
CRCCON2 (CRC Control 2) .................................... 203
CRCXORH (CRC XOR Polynomial, High Byte) ...... 204
CRCXORL (CRC XOR Polynomial, Low Byte) ........ 204
CTMUCON (CTMU Control 1) ................................. 234
CTMUCON2 (CTMU Control 2) ............................... 235
CTMUICON (CTMU Current Control) ...................... 237
CVRCON (Comparator Voltage
Features (Summary) .................................................. 13
Pinout Descriptions ............................................................ 16
Power-Saving ................................................................... 134
Power-Saving Features ................................................... 125
Clock Frequency, Clock Switching ........................... 125
Coincident Interrupts ................................................ 126
Instruction-Based Modes ......................................... 125
Deep Sleep ...................................................... 126
Idle ................................................................... 126
Sleep ................................................................ 125
Selective Peripheral Control .................................... 134
Ultra Low-Power Wake-up ....................................... 131
Voltage, Regulator-Based ........................................ 133
Deep Sleep Mode ............................................ 133
Retention Sleep Mode ..................................... 133
Run Mode ........................................................ 133
Sleep (Standby) Mode ..................................... 133
Product Identification System .......................................... 360
Program and Data Memory
Access Using Table Instructions ................................ 53
Addressing Space ...................................................... 51
Interfacing Spaces ..................................................... 51
Program Space Visibility ............................................ 55
Program Memory
Address Space ........................................................... 35
Data EEPROM ........................................................... 36
Device Configuration Words ...................................... 36
Hard Memory Vectors ................................................ 36
Memory Map .............................................................. 35
Organization ............................................................... 36
Program Verification ........................................................ 250
Reference Control) .......................................... 230
2011-2013 Microchip Technology Inc.
DS39995D-page 355
PIC24FV32KA304 FAMILY
DEVID (Device ID) ...................................................246
DEVREV (Device Revision) .....................................247
DSCON (Deep Sleep Control) .................................129
DSWAKE (Deep Sleep Wake-up Source) ...............130
FBS (Boot Segment Configuration) .........................239
FDS (Deep Sleep Configuration) .............................245
FGS (General Segment Configuration) ....................240
FICD (In-Circuit Debugger Configuration) ................244
FOSC (Oscillator Configuration) ..............................241
FOSCSEL (Oscillator Selection Configuration) ........240
FPOR (Reset Configuration) ....................................243
FWDT (Watchdog Timer Configuration) ..................242
HLVDCON (High/Low-Voltage Detect Control) ........206
SPIxCON2 (SPIx Control 2) ..................................... 167
SPIxSTAT (SPIx Status and Control) ...................... 164
SR (ALU STATUS) .............................................. 32, 79
T1CON (Timer1 Control) ......................................... 140
TxCON (Timer2/4 Control) ....................................... 144
TyCON (Timer3/5 Control) ....................................... 145
ULPWCON (ULPWU Control) ................................. 132
UxMODE (UARTx Mode) ......................................... 180
UxRXREG (UARTx Receive) ................................... 184
UxSTA (UARTx Status and Control) ........................ 182
UxTXREG (UARTx Transmit) .................................. 184
WKDYHR (RTCC Weekday and Hours Value) ........ 192
YEAR (RTCC Year Value) ....................................... 191
I2CxCON (I2Cx Control) ..........................................172
I2CxMSK (I2Cx Slave Mode Address Mask) ...........176
I2CxSTAT (I2Cx Status) ..........................................174
ICxCON1 (Input Capture x Control 1) ......................149
ICxCON2 (Input Capture x Control 2) ......................150
IEC0 (Interrupt Enable Control 0) ..............................90
IEC1 (Interrupt Enable Control 1) ..............................92
IEC2 (Interrupt Enable Control 2) ..............................93
IEC3 (Interrupt Enable Control 3) ..............................94
IEC4 (Interrupt Enable Control 4) ..............................95
IEC5 (Interrupt Enable Control 5) ..............................96
IFS0 (Interrupt Flag Status 0) ....................................83
IFS1 (Interrupt Flag Status 1) ....................................85
IFS2 (Interrupt Flag Status 2) ....................................86
IFS3 (Interrupt Flag Status 3) ....................................87
IFS4 (Interrupt Flag Status 4) ....................................88
IFS5 (Interrupt Flag Status 5) ....................................89
INTCON1 (Interrupt Control 1) ...................................81
INTCON2 (Interrupt Control 2) ...................................82
INTTREG (Interrupt Control and Status) ..................112
IPC0 (Interrupt Priority Control 0) ..............................97
IPC1 (Interrupt Priority Control 1) ..............................98
IPC12 (Interrupt Priority Control 12) ........................107
IPC15 (Interrupt Priority Control 15) ........................108
IPC16 (Interrupt Priority Control 16) ........................109
IPC18 (Interrupt Priority Control 18) ........................110
IPC19 (Interrupt Priority Control 19) ........................110
IPC2 (Interrupt Priority Control 2) ..............................99
IPC20 (Interrupt Priority Control 20) ........................111
IPC3 (Interrupt Priority Control 3) ............................100
IPC4 (Interrupt Priority Control 4) ............................101
IPC5 (Interrupt Priority Control 5) ............................102
IPC6 (Interrupt Priority Control 6) ............................103
IPC7 (Interrupt Priority Control 7) ............................104
IPC8 (Interrupt Priority Control 8) ............................105
IPC9 (Interrupt Priority Control 9) ............................106
MINSEC (RTCC Minutes and Seconds Value) ........192
MTHDY (RTCC Month and Day Value) ...................191
NVMCON (Flash Memory Control) ............................59
NVMCON (Nonvolatile Memory Control) ...................64
OCxCON1 (Output Compare x Control 1) ...............157
OCxCON2 (Output Compare x Control 2) ...............159
OSCCON (Oscillator Control) ..................................117
OSCTUN (FRC Oscillator Tune) ..............................120
PADCFG1 (Pad Configuration Control) ...................176
RCFGCAL (RTCC Calibration
Resets
Brown-out Reset (BOR) ............................................. 73
Clock Source Selection .............................................. 72
Deep Sleep BOR (DSBOR) ....................................... 73
Device Times ............................................................. 72
RCON Flag Operation ............................................... 71
SFR States ................................................................ 73
Revision History ............................................................... 351
RTCC ............................................................................... 185
Alarm Configuration ................................................. 196
Alarm Mask Settings (figure) ................................... 197
Calibration ............................................................... 196
Module Registers ..................................................... 186
Mapping ........................................................... 186
Clock Source Selection ........................... 186
Write Lock ........................................................ 186
Power Control .......................................................... 197
Source Clock ........................................................... 185
S
Serial Peripheral Interface. See SPI.
SFR Space ........................................................................ 38
Software Simulator (MPLAB SIM) ................................... 253
Software Stack ................................................................... 51
T
Timer1 .............................................................................. 139
Timer2/3 ........................................................................... 141
Timer2/3 and Timer4/5 .................................................... 141
Timing Diagrams
A/D Conversion ........................................................ 294
Brown-out Reset Characteristics ............................. 281
CLKO and I/O Timing .............................................. 279
External Clock .......................................................... 277
I2C Bus Data (Master Mode) ................................... 285
I2C Bus Data (Slave Mode) ..................................... 286
I2C Bus Start/Stop Bits (Master Mode) .................... 284
I2C Bus Start/Stop Bits (Slave Mode) ...................... 287
Input Capture x ........................................................ 282
Output Compare x ................................................... 283
PWM Requirements ................................................. 283
Reset, Watchdog Timer. Oscillator Start-up Timer,
Power-up Timer Characteristics ...................... 280
SPIx Master Mode (CKE = 0) .................................. 289
SPIx Master Mode (CKE = 1) .................................. 290
SPIx Slave Mode (CKE = 0) .................................... 291
SPIx Slave Mode (CKE = 1) .................................... 292
Timer1/2/3/4/5 External Clock Input ........................ 282
UARTx Baud Rate Generator Output ...................... 288
UARTx Start Bit Edge Detection .............................. 288
and Configuration) ...........................................187
RCON (Reset Control) ...............................................70
REFOCON (Reference Oscillator Control) ...............123
RTCCSWT (Control/Sample Window Timer) ...........195
RTCPWC (RTCC Configuration 2) ..........................189
SPIxCON1 (SPIx Control 1) .....................................166
DS39995D-page 356
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
Timing Requirements
U
A/D Conversion ........................................................ 294
CLKO and I/O .......................................................... 279
External Clock .......................................................... 277
I2C Bus Data (Master Mode) ............................ 284, 285
I2C Bus Data (Slave Mode) ...................................... 286
I2C Bus Start/Stop Bits (Slave Mode) ...................... 287
Input Capture x ........................................................ 282
Output Capture ........................................................ 283
PLL Clock Specifications ......................................... 278
PWM ........................................................................ 283
SPIx Master Mode (CKE = 0) .................................. 289
SPIx Master Mode (CKE = 1) .................................. 290
SPIx Slave Mode (CKE = 0) .................................... 291
SPIx Slave Mode (CKE = 1) .................................... 292
Timer1/2/3/4/5 External Clock Input ......................... 282
UARTx ..................................................................... 288
UART ............................................................................... 177
Baud Rate Generator (BRG) ................................... 178
Break and Sync Transmit Sequence ....................... 179
IrDA Support ............................................................ 179
Operation of UxCTS and UxRTS Control Pins ........ 179
Receiving in 8-Bit or 9-Bit Data Mode ..................... 179
Transmitting in 8-Bit Data Mode .............................. 179
Transmitting in 9-Bit Data Mode .............................. 179
W
Watchdog Timer
Deep Sleep (DSWDT) ............................................. 250
Watchdog Timer (WDT) ................................................... 248
Windowed Operation ............................................... 249
WWW Address ................................................................ 358
WWW, On-Line Support ...................................................... 9
2011-2013 Microchip Technology Inc.
DS39995D-page 357
PIC24FV32KA304 FAMILY
NOTES:
DS39995D-page 358
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the web site
at: http://microchip.com/support
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
2011-2013 Microchip Technology Inc.
DS39995D-page 359
PIC24FV32KA304 FAMILY
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
TO:
RE:
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Reader Response
Total Pages Sent ________
From:
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Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Literature Number: DS39995D
Application (optional):
Would you like a reply?
Y
N
Device: PIC24FV32KA304 Family
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS39995D-page 360
2011-2013 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PIC 24 FV 32 KA3 04 T - I / PT - XXX
a)
b)
PIC24FV32KA304-I/ML: Wide voltage range,
General Purpose, 32-Kbyte program memory,
44-pin, Industrial temp., QFN package
Microchip Trademark
Architecture
PIC24F16KA302-I/SS: Standard voltage range,
General Purpose, 16-Kbyte program memory,
28-pin, Industrial temp., SSOP package
Flash Memory Family
Program Memory Size (KB)
Product Group
Pin Count
Tape and Reel Flag (if applicable)
Temperature Range
Package
Pattern
Architecture
24 = 16-bit modified Harvard without DSP
Flash Memory Family
F
= Standard voltage range Flash program memory
FV = Wide voltage range Flash program memory
Product Group
Pin Count
KA3 = General purpose microcontrollers
01 = 20-pin
02 = 28-pin
04 = 44-pin
Temperature Range
Package
I
E
=
=
-40C to +85C (Industrial)
-40C to +125C (Industrial)
SP = SPDIP
SO = SOIC
SS = SSOP
ML = QFN
P
= PDIP
PT = TQFP
MV = UQFN
Pattern
Three-digit QTP, SQTP, Code or Special Requirements
(blank otherwise)
ES = Engineering Sample
2011-2013 Microchip Technology Inc.
DS39995D-page 361
PIC24FV32KA304 FAMILY
NOTES:
DS39995D-page 362
2011-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2011-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62077-076-4
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
== ISO/TS 16949 ==
2011-2013 Microchip Technology Inc.
DS39995D-page 363
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China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Los Angeles
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-213-7828
Fax: 886-7-330-9305
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Toronto
Mississauga, Ontario,
Canada
China - Xiamen
Tel: 905-673-0699
Fax: 905-673-6509
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
11/29/12
DS39995D-page 364
2011-2013 Microchip Technology Inc.
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