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PIC32MX440F256H [MICROCHIP]

High-Performance, General Purpose and USB, 32-bit Flash Microcontrollers; 高性能，通用和USB接口， 32位闪存微控制器
PIC32MX440F256H
型号： PIC32MX440F256H
厂家： MICROCHIP    MICROCHIP
描述：

High-Performance, General Purpose and USB, 32-bit Flash Microcontrollers
高性能，通用和USB接口， 32位闪存微控制器

闪存 微控制器
文件： 总214页 (文件大小：4085K)
中文：  中文翻译
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PIC32MX3XX/4XX  
Data Sheet  
High-Performance,  
General Purpose and USB,  
32-bit Flash Microcontrollers  
© 2011 Microchip Technology Inc.  
DS61143H  
Note the following details of the code protection feature on Microchip devices:  
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.  
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the  
intended manner and under normal conditions.  
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our  
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data  
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.  
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.  
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not  
mean that we are guaranteeing the product as “unbreakable.”  
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our  
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts  
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.  
Information contained in this publication regarding device  
applications and the like is provided only for your convenience  
and may be superseded by updates. It is your responsibility to  
ensure that your application meets with your specifications.  
MICROCHIP MAKES NO REPRESENTATIONS OR  
WARRANTIES OF ANY KIND WHETHER EXPRESS OR  
IMPLIED, WRITTEN OR ORAL, STATUTORY OR  
OTHERWISE, RELATED TO THE INFORMATION,  
INCLUDING BUT NOT LIMITED TO ITS CONDITION,  
QUALITY, PERFORMANCE, MERCHANTABILITY OR  
FITNESS FOR PURPOSE. Microchip disclaims all liability  
arising from this information and its use. Use of Microchip  
devices in life support and/or safety applications is entirely at  
the buyer’s risk, and the buyer agrees to defend, indemnify and  
hold harmless Microchip from any and all damages, claims,  
suits, or expenses resulting from such use. No licenses are  
conveyed, implicitly or otherwise, under any Microchip  
intellectual property rights.  
Trademarks  
The Microchip name and logo, the Microchip logo, dsPIC,  
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,  
PIC32 logo, rfPIC and UNI/O are registered trademarks of  
Microchip Technology Incorporated in the U.S.A. and other  
countries.  
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,  
MXDEV, MXLAB, SEEVAL and The Embedded Control  
Solutions Company are registered trademarks of Microchip  
Technology Incorporated in the U.S.A.  
Analog-for-the-Digital Age, Application Maestro, CodeGuard,  
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,  
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial  
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified  
logo, MPLIB, MPLINK, mTouch, Omniscient Code  
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,  
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,  
TSHARC, UniWinDriver, WiperLock and ZENA are  
trademarks of Microchip Technology Incorporated in the  
U.S.A. and other countries.  
SQTP is a service mark of Microchip Technology Incorporated  
in the U.S.A.  
All other trademarks mentioned herein are property of their  
respective companies.  
© 2011, Microchip Technology Incorporated, Printed in the  
U.S.A., All Rights Reserved.  
Printed on recycled paper.  
ISBN: 978-1-61341-149-0  
Microchip received ISO/TS-16949:2002 certification for its worldwide  
headquarters, design and wafer fabrication facilities in Chandler and  
Tempe, Arizona; Gresham, Oregon and design centers in California  
and India. The Company’s quality system processes and procedures  
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping  
devices, Serial EEPROMs, microperipherals, nonvolatile memory and  
analog products. In addition, Microchip’s quality system for the design  
and manufacture of development systems is ISO 9001:2000 certified.  
DS61143H-page 2  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
High-Performance, General Purpose and USB 32-bit  
Flash Microcontrollers  
• Separate PLLs for CPU and USB clocks  
High-Performance 32-bit RISC CPU:  
• Two I2C™ modules  
• MIPS32® M4K® 32-bit core with 5-stage pipeline  
• Two UART modules with:  
• 80 MHz maximum frequency  
- RS-232, RS-485 and LIN support  
- IrDA® with on-chip hardware encoder and  
decoder  
• 1.56 DMIPS/MHz (Dhrystone 2.1) performance at  
0 wait state Flash access  
• Single-cycle multiply and high-performance divide  
unit  
• Up to two SPI modules  
• Parallel Master and Slave Port (PMP/PSP) with  
• MIPS16e® mode for up to 40% smaller code size  
8-bit and 16-bit data and up to 16 address lines  
• Two sets of 32 core register files (32-bit) to reduce  
• Hardware Real-Time Clock and Calendar (RTCC)  
interrupt latency  
• Five 16-bit Timers/Counters (two 16-bit pairs  
• Prefetch Cache module to speed execution from  
combine to create two 32-bit timers)  
Flash  
• Five capture inputs  
• Five compare/PWM outputs  
Microcontroller Features:  
• Five external interrupt pins  
• Operating temperature range of -40ºC to +105ºC  
• High-Speed I/O pins capable of toggling at up to  
• Operating voltage range of 2.3V to 3.6V  
80 MHz  
• 32K to 512K Flash memory (plus an additional  
• High-current sink/source (18 mA/18 mA) on all I/O  
12 KB of boot Flash)  
pins  
• 8K to 32K SRAM memory  
• Pin-compatible with most PIC24/dsPIC® DSC  
• Configurable open-drain output on digital I/O pins  
devices  
Debug Features:  
• Multiple power management modes  
• Two programming and debugging Interfaces:  
• Multiple interrupt vectors with individually  
- 2-wire interface with unintrusive access and  
real-time data exchange with application  
- 4-wire MIPS® standard enhanced JTAG  
interface  
programmable priority  
• Fail-Safe Clock Monitor Mode  
• Configurable Watchdog Timer with on-chip  
Low-Power RC Oscillator for reliable operation  
• Unintrusive hardware-based instruction trace  
• IEEE Standard 1149.2-compatible (JTAG)  
boundary scan  
Peripheral Features:  
• Atomic SET, CLEAR and INVERT operation on  
select peripheral registers  
Analog Features:  
• Up to 4-channel hardware DMA with automatic  
data size detection  
• Up to 16-channel 10-bit Analog-to-Digital  
Converter:  
• USB 2.0-compliant full-speed device and  
On-The-Go (OTG) controller  
- 1000 ksps conversion rate  
- Conversion available during Sleep, Idle  
• Two Analog Comparators  
• USB has a dedicated DMA channel  
• 3 MHz to 25 MHz crystal oscillator  
• Internal 8 MHz and 32 kHz oscillators  
© 2011 Microchip Technology Inc.  
DS61143H-page 3  
PIC32MX3XX/4XX  
TABLE 1:  
PIC32MX GENERAL PURPOSE – FEATURES  
GENERAL PURPOSE  
Device  
PIC32MX320F032H  
PIC32MX320F064H  
PIC32MX320F128H  
PIC32MX340F128H  
PIC32MX340F256H  
PIC32MX340F512H  
64  
64  
PT, MR  
PT, MR  
PT, MR  
PT, MR  
PT, MR  
PT, MR  
PT  
40  
80  
32 + 12(1)  
64 + 12(1)  
8
5/5/5  
0
0
0
4
4
4
Yes No 2/2/2  
Yes No 2/2/2  
Yes No 2/2/2  
Yes No 2/2/2  
Yes No 2/2/2  
Yes No 2/2/2  
16  
16  
16  
16  
16  
16  
2
2
2
2
2
2
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
16 5/5/5  
64  
80 128 + 12(1) 16 5/5/5  
80 128 + 12(1) 32 5/5/5  
80 256 + 12(1) 32 5/5/5  
80 512 + 12(1) 32 5/5/5  
64  
64  
64  
100  
121  
100  
121  
PIC32MX320F128L  
PIC32MX340F128L  
80 128 + 12(1) 16 5/5/5  
80 128 + 12(1) 32 5/5/5  
0
4
Yes No 2/2/2  
Yes No 2/2/2  
16  
16  
2
2
Yes  
Yes  
Yes  
Yes  
BG  
PT  
BG  
100  
121  
100  
121  
PT  
BG  
PT  
BG  
PIC32MX360F256L  
PIC32MX360F512L  
80 256 + 12(1) 32 5/5/5  
4
4
Yes Yes 2/2/2  
Yes Yes 2/2/2  
16  
16  
2
2
Yes  
Yes  
Yes  
Yes  
80 512 + 12(1) 32 5/5/5  
BG = XBGA  
Legend:  
PT = TQFP  
MR = QFN  
Note 1: This device features 12 KB Boot Flash memory.  
2: See Legend for an explanation of the acronyms. See Section 30.0 “Packaging Information” for details.  
DS61143H-page 4  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
TABLE 2:  
PIC32MX USB – FEATURES  
USB  
Device  
PIC32MX420F032H  
PIC32MX440F128H  
PIC32MX440F256H  
PIC32MX440F512H  
64 PT, MR 40  
32 + 12(1)  
8
5/5/5  
5/5/5  
5/5/5  
5/5/5  
0
4
4
4
2
2
2
2
Yes No 2/1/2  
Yes No 2/1/2  
Yes No 2/1/2  
Yes No 2/1/2  
16  
16  
16  
16  
2
2
2
2
Yes Yes  
Yes Yes  
Yes Yes  
Yes Yes  
64  
64  
80  
80  
80  
128 + 12(1) 32  
256 + 12(1) 32  
512 + 12(1) 32  
PT, MR  
PT, MR  
PT, MR  
PT  
64  
100  
121  
100  
121  
100  
121  
PIC32MX440F128L  
PIC32MX460F256L  
PIC32MX460F512L  
80  
80  
80  
128 + 12(1) 32  
256 + 12(1) 32  
5/5/5  
5/5/5  
5/5/5  
4
4
4
2
2
2
Yes No 2/2/2  
Yes Yes 2/2/2  
Yes Yes 2/2/2  
16  
16  
16  
2
2
2
Yes Yes  
Yes Yes  
Yes Yes  
BG  
PT  
BG  
PT  
512 + 12(1) 32  
BG = XBGA  
BG  
Legend:  
PT = TQFP  
MR = QFN  
Note 1: This device features 12 KB Boot Flash memory.  
2: See Legend for an explanation of the acronyms. See Section 30.0 “Packaging Information” for details.  
© 2011 Microchip Technology Inc.  
DS61143H-page 5  
PIC32MX3XX/4XX  
Pin Diagrams  
= Pins are up to 5V tolerant  
64-Pin QFN (General Purpose)  
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49  
1
2
3
4
5
6
7
8
9
PMD5/RE5  
PMD6/RE6  
48 SOSCO/T1CK/CN0/RC14  
SOSCI/CN1/RC13  
47  
PMD7/RE7  
46 OC1/RD0  
IC4/PMCS1/PMA14/INT4/RD11  
SCK2/PMA5/CN8/RG6  
SDI2/PMA4/CN9/RG7  
SDO2/PMA3/CN10/RG8  
45  
44  
43  
IC3/PMCS2/PMA15/INT3/RD10  
U1CTS/IC2/INT2/RD9  
PIC32MX320F032H  
PIC32MX320F064H  
PIC32MX320F128H  
PIC32MX340F128H  
PIC32MX340F256H  
PIC32MX340F512H  
42 RTCC/IC1/INT1/RD8  
MCLR  
SS2/PMA2/CN11/RG9  
VSS  
41  
40  
Vss  
OSC2/CLKO/RC15  
VDD 10  
39 OSC1/CLKI/RC12  
38 VDD  
11  
AN5/C1IN+/CN7/RB5  
AN4/C1IN-/CN6/RB4 12  
AN3/C2IN+/CN5/RB3 13  
14  
PGEC1/AN1/VREF-/CVREF-/CN3/RB1 15  
16  
SCL1/RG2  
SDA1/RG3  
37  
36  
35  
34  
33  
AN2/C2IN-/SS1/CN4/RB2  
U1RTS/SCK1/INT0/RF6  
U1RX/SDI1/RF2  
PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0  
U1TX/SDO1/RF3  
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32  
Note: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to  
VSS externally.  
DS61143H-page 6  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
Pin Diagrams (Continued)  
= Pins are up to 5V tolerant  
64-Pin TQFP (General Purpose)  
SOSCO/T1CK/CN0/RC14  
48  
PMD5/RE5  
PMD6/RE6  
1
SOSCI/CN1/RC13  
OC1/RD0  
2
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
PMD7/RE7  
3
SCK2/PMA5/CN8/RG6  
IC4/PMCS1/PMA14/INT4/RD11  
IC3/PMCS2/PMA15/INT3/RD10  
4
SDI2/PMA4/CN9/RG7  
SDO2/PMA3/CN10/RG8  
MCLR  
5
6
PIC32MX320F032H  
PIC32MX320F064H  
PIC32MX320F128H  
PIC32MX340F128H  
PIC32MX340F256H  
PIC32MX340F512H  
U1CTS/IC2/INT2/RD9  
RTCC/IC1/INT1/RD8  
7
Vss  
SS2/PMA2/CN11/RG9  
VSS  
8
OSC2/CLKO/RC15  
OSC1/CLKI/RC12  
VDD  
9
VDD  
10  
11  
12  
13  
14  
15  
16  
AN5/C1IN+/CN7/RB5  
AN4/C1IN-/CN6/RB4  
SCL1/RG2  
SDA1/RG3  
AN3/C2IN+/CN5/RB3  
AN2/C2IN-/SS1/CN4/RB2  
PGEC1/AN1/VREF-/CVREF-/CN3/RB1  
PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0  
U1RTS/SCK1/INT0/RF6  
U1RX/SDI1/RF2  
U1TX/SDO1/RF3  
© 2011 Microchip Technology Inc.  
DS61143H-page 7  
PIC32MX3XX/4XX  
Pin Diagrams (Continued)  
= Pins are up to 5V tolerant  
100-Pin TQFP (General Purpose)  
VSS  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
1
2
3
4
5
6
7
8
RG15  
VDD  
PMD5/RE5  
PMD6/RE6  
PMD7/RE7  
T2CK/RC1  
T3CK/RC2  
T4CK/RC3  
T5CK/RC4  
SOSCO/T1CK/CN0/RC14  
SOSCI/CN1/RC13  
OC1/RD0  
IC4/PMCS1/PMA14/RD11  
IC3/PMCS2/PMA15/RD10  
IC2/RD9  
RTCC/IC1/RD8  
INT4/RA15  
INT3/RA14  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
SCK2/PMA5/CN8/RG6  
SDI2/PMA4/CN9/RG7  
SDO2/PMA3/CN10/RG8  
MCLR  
PMA2/SS2/CN11/RG9  
VSS  
VSS  
PIC32MX320F128L  
PIC32MX340F128L  
PIC32MX360F256L  
PIC32MX360F512L  
OSC2/CLKO/RC15  
OSC1/CLKI/RC12  
VDD  
TDO/RA5  
VDD  
TDI/RA4  
SDA2/RA3  
SCL2/RA2  
SCL1/RG2  
SDA1/RG3  
SCK1/INT0/RF6  
SDI1/RF7  
TMS/RA0  
INT1/RE8  
INT2/RE9  
AN5/C1IN+/CN7/RB5  
AN4/C1IN-/CN6/RB4  
AN3/C2IN+/CN5/RB3  
AN2/C2IN-/SS1/CN4/RB2  
PGEC1/AN1/CN3/RB1  
PGED1/AN0/CN2/RB0  
SDO1/RF8  
U1RX/RF2  
U1TX/RF3  
DS61143H-page 8  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
Pin Diagrams (Continued)  
(1)  
121-Pin XBGA  
= Pins are up to 5V tolerant  
PIC32MX320F128L  
PIC32MX340F128L  
PIC32MX360F256L  
PIC32MX360F512L  
1
2
3
4
5
6
7
8
9
10  
11  
A
B
RE4  
NC  
RE3  
RG13  
RE2  
RE0  
RE1  
RG0  
RA7  
RF1  
RF0  
ENVREG  
VSS  
RD12  
RD3  
RD2  
VSS  
RD1  
RG15  
VCORE/  
VCAP  
RD5  
RC14  
C
D
E
F
RE6  
RC1  
RC4  
MCLR  
RE8  
RB5  
RB3  
RB1  
RB6  
VDD  
RE7  
RC3  
RG8  
RE9  
RB4  
RB2  
RB0  
RA9  
RG12  
RE5  
RG6  
RG9  
RA0  
VSS  
RG14  
VSS  
RA6  
VSS  
VDD  
VSS  
VDD  
NC  
NC  
NC  
RD7  
RD6  
VSS  
RD4  
RD13  
RA15  
VDD  
VDD  
RD0  
RD8  
RC12  
RA5  
RF6  
RC13  
NC  
RD11  
RD10  
RA14  
RC15  
RA4  
RC2  
RG7  
NC  
RG1  
NC  
RD9  
VSS  
NC  
G
H
J
VSS  
VDD  
RA1  
RF12  
VSS  
NC  
RA3  
RG2  
RF8  
RF3  
RF4  
VDD  
NC  
RF7  
NC  
RA2  
RB7  
RA10  
AVSS  
AVDD  
RB8  
RB9  
RB11  
NC  
RB12  
RB14  
RB13  
NC  
RG3  
RF2  
K
L
VDD  
RD15  
RD14  
RB10  
RB15  
RF5  
RF13  
Note 1: Refer to Table 3 for full pin names.  
© 2011 Microchip Technology Inc.  
DS61143H-page 9  
PIC32MX3XX/4XX  
TABLE 3:  
PIN NAMES: PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F128L, AND  
PIC32MX360F512L DEVICES  
Pin  
Number  
Pin  
Number  
Full Pin Name  
Full Pin Name  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
A10  
A11  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
B9  
B10  
B11  
C1  
C2  
C3  
C4  
C5  
C6  
C7  
C8  
C9  
C10  
C11  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
D9  
D10  
D11  
E1  
E2  
E3  
E4  
E5  
E6  
E7  
PMD4/RE4  
E8  
E9  
E10  
E11  
F1  
INT4/RA15  
RTCC/IC1/RD8  
IC2/RD9  
PMD3/RE3  
TRD0/RG13  
PMD0/RE0  
INT3/RA14  
MCLR  
PMD8/RG0  
PMD10/RF1  
ENVREG  
F2  
SDO2/PMA3/CN10/RG8  
SS2/PMA2/CN11/RG9  
SDI2/PMA4/CN9/RG7  
VSS  
F3  
VSS  
F4  
IC5/PMD12/RD12  
OC3/RD2  
F5  
F6  
No Connect (NC)  
No Connect (NC)  
VDD  
OC2/RD1  
F7  
No Connect (NC)  
RG15  
F8  
F9  
OSC1/CLKI/RC12  
VSS  
PMD2/RE2  
F10  
F11  
G1  
G2  
G3  
G4  
G5  
G6  
G7  
G8  
G9  
G10  
G11  
H1  
H2  
H3  
H4  
H5  
H6  
H7  
H8  
H9  
H10  
H11  
J1  
PMD1/RE1  
OSC2/CLKO/RC15  
INT1/RE8  
TRD3/RA7  
PMD11/RF0  
VCAP/VCORE  
PMRD/CN14/RD5  
OC4/RD3  
INT2/RE9  
TMS/RA0  
No Connect (NC)  
VDD  
VSS  
VSS  
SOSCO/T1CK/CN0/RC14  
PMD6/RE6  
VSS  
No Connect (NC)  
TDO/RA5  
VDD  
TRD1/RG12  
TRD2/RG14  
TRCLK/RA6  
No Connect (NC)  
PMD15/CN16/RD7  
OC5/PMWR/CN13/RD4  
VDD  
SDA2/RA3  
TDI/RA4  
AN5/C1IN+/CN7/RB5  
AN4/C1IN-/CN6/RB4  
VSS  
VDD  
No Connect (NC)  
VDD  
SOSCI/CN1/RC13  
IC4/PMCS1/PMA14/RD11  
T2CK/RC1  
No Connect (NC)  
SDI1/RF7  
PMD7/RE7  
SCK1/INT0/RF6  
SCL1/RG2  
PMD5/RE5  
VSS  
SCL2/RA2  
VSS  
AN3/C2IN+/CN5/RB3  
AN2/C2IN-/SS1/CN4/RB2  
PGED2/AN7/RB7  
AVDD  
No Connect (NC)  
PMD14/CN15/RD6  
PMD13/CN19/RD13  
OC1/RD0  
J2  
J3  
J4  
J5  
AN11/PMA12/RB11  
TCK/RA1  
No Connect (NC)  
IC3/PMCS2/PMA15/RD10  
T5CK/RC4  
J6  
J7  
AN12/PMA11/RB12  
No Connect (NC)  
No Connect (NC)  
SDO1/RF8  
J8  
T4CK/RC3  
J9  
SCK2/PMA5/CN8/RG6  
T3CK/RC2  
J10  
J11  
K1  
K2  
K3  
SDA1/RG3  
VDD  
PGEC1/AN1/CN3/RB1  
PGED1/AN0/CN2/RB0  
VREF+/CVREF+/PMA6/RA10  
PMD9/RG1  
VSS  
DS61143H-page 10  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
TABLE 3:  
PIN NAMES: PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F128L, AND  
PIC32MX360F512L DEVICES (CONTINUED)  
Pin  
Number  
Pin  
Number  
Full Pin Name  
Full Pin Name  
K4  
K5  
K6  
K7  
K8  
K9  
K10  
K11  
L1  
AN8/C1OUT/RB8  
No Connect (NC)  
U2CTS/RF12  
L3  
L4  
AVSS  
AN9/C2OUT/RB9  
L5  
AN10/CVREFOUT/PMA13/RB10  
U2RTS/RF13  
AN14/PMALH/PMA1/RB14  
VDD  
L6  
L7  
AN13/PMA10/RB13  
U1RTS/CN21/RD15  
U1TX/RF3  
L8  
AN15/OCFB/PMALL/PMA0/CN12/RB15  
CN20/U1CTS/RD14  
L9  
U1RX/RF2  
L10  
L11  
U2RX/PMA9/CN17/RF4  
U2TX/PMA8/CN18/RF5  
PGEC2/AN6/OCFA/RB6  
VREF-/CVREF-/PMA7/RA9  
L2  
© 2011 Microchip Technology Inc.  
DS61143H-page 11  
PIC32MX3XX/4XX  
Pin Diagrams (Continued)  
64-Pin QFN (USB)  
= Pins are up to 5V tolerant  
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49  
PMD5/RE5  
PMD6/RE6  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
48 SOSCO/T1CK/CN0/RC14  
SOSCI/CN1/RC13  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
PMD7/RE7  
OC1/INT0/RD0  
SCK2/PMA5/CN8/RG6  
SDI2/PMA4/CN9/RG7  
SDO2/PMA3/CN10/RG8  
IC4/PMCS1/PMA14/INT4/RD11  
SCL1/IC3/PMCS2/PMA15/INT3/RD10  
U1CTS/SDA1/IC2/INT2/RD9  
RTCC/IC1/INT1/RD8  
Vss  
MCLR  
PIC32MX420F032H  
PIC32MX440F128H  
PIC32MX440F256H  
PIC32MX440F512H  
SS2/PMA2/CN11/RG9  
VSS  
OSC2/CLKO/RC15  
OSC1/CLKI/RC12  
VDD  
AN5/C1IN+/VBUSON/CN7/RB5  
AN4/C1IN-/CN6/RB4  
VDD  
D+/RG2  
D-/RG3  
AN3/C2IN+/CN5/RB3  
AN2/C2IN-/CN4/RB2  
VUSB  
VBUS  
PGEC1/AN1/VREF-/CVREF-/CN3/RB1  
PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0  
USBID/RF3  
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32  
Note: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to  
VSS externally.  
DS61143H-page 12  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
Pin Diagrams (Continued)  
64-Pin TQFP (USB)  
= Pins are up to 5V tolerant  
PMD5/RE5  
PMD6/RE6  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
SOSCO/T1CK/CN0/RC14  
SOSCI/CN1/RC13  
2
PMD7/RE7  
3
OC1/INT0/RD0  
SCK2/PMA5/CN8/RG6  
SDI2/PMA4/CN9/RG7  
SDO2/PMA3/CN10/RG8  
MCLR  
4
IC4/PMCS1/PMA14/INT4/RD11  
SCL1/IC3/PMCS2/PMA15/INT3/RD10  
U1CTS/SDA1/IC2/INT2/RD9  
RTCC/IC1/INT1/RD8  
Vss  
5
6
PIC32MX420F032H  
PIC32MX440F128H  
PIC32MX440F256H  
PIC32MX440F512H  
7
SS2/PMA2/CN11/RG9  
8
VSS  
9
OSC2/CLKO/RC15  
VDD  
10  
11  
12  
13  
14  
15  
16  
OSC1/CLKI/RC12  
AN5/C1IN+/VBUSON/CN7/RB5  
AN4/C1IN-/CN6/RB4  
VDD  
D+/RG2  
D-/RG3  
AN3/C2IN+/CN5/RB3  
AN2/C2IN-/CN4/RB2  
VUSB  
PGEC1/AN1/VREF-/CVREF-/CN3/RB1  
PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0  
VBUS  
USBID/RF3  
© 2011 Microchip Technology Inc.  
DS61143H-page 13  
PIC32MX3XX/4XX  
Pin Diagrams (Continued)  
100-Pin TQFP (USB)  
= Pins are up to 5V tolerant  
RG15  
1
VSS  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
VDD  
SOSCO/T1CK/CN0/RC14  
SOSCI/CN1/RC13  
SDO1/OC1/INT0/RD0  
IC4/PMCS1/PMA14/RD11  
SCK1/IC3/PMCS2/PMA15/RD10  
SS1/IC2/RD9  
RTCC/IC1/RD8  
SDA1/INT4/RA15  
SCL1/INT3/RA14  
VSS  
OSC2/CLKO/RC15  
OSC1/CLKI/RC12  
VDD  
TDO/RA5  
TDI/RA4  
2
PMD5/RE5  
3
PMD6/RE6  
4
PMD7/RE7  
5
T2CK/RC1  
6
T3CK/RC2  
7
T4CK/RC3  
8
T5CK/SDI1/RC4  
9
SCK2/PMA5/CN8/RG6  
10  
SDI2/PMA4/CN9/RG7  
11  
PIC32MX440F128L  
PIC32MX460F256L  
PIC32MX460F512L  
SDO2/PMA3/CN10/RG8  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
MCLR  
SS2/PMA2/CN11/RG9  
VSS  
VDD  
TMS/RA0  
INT1/RE8  
INT2/RE9  
SDA2/RA3  
SCL2/RA2  
D+/RG2  
D-/RG3  
AN5/C1IN+/VBUSON/CN7/RB5  
AN4/C1IN-/CN6/RB4  
AN3/C2IN+/CN5/RB3  
AN2/C2IN-/CN4/RB2  
PGEC1/AN1/CN3/RB1  
PGED1/AN0/CN2/RB0  
VUSB  
VBUS  
U1TX/RF8  
U1RX/RF2  
USBID/RF3  
DS61143H-page 14  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
Pin Diagrams (Continued)  
(1)  
121-Pin XBGA  
= Pins are up to 5V tolerant  
PIC32MX440F128L  
PIC32MX460F256L  
PIC32MX460F512L  
1
2
3
4
5
6
7
8
9
10  
11  
A
B
RE4  
NC  
RE3  
RG13  
RE2  
RE0  
RE1  
RG0  
RA7  
RF1  
RF0  
ENVREG  
VSS  
RD12  
RD3  
RD2  
VSS  
RD1  
RG15  
VCORE/  
VCAP  
RD5  
RC14  
C
D
E
F
RE6  
RC1  
RC4  
MCLR  
RE8  
RB5  
RB3  
RB1  
RB6  
VDD  
RE7  
RC3  
RG8  
RE9  
RB4  
RB2  
RB0  
RA9  
RG12  
RE5  
RG6  
RG9  
RA0  
VSS  
RG14  
VSS  
RA6  
VSS  
VDD  
VSS  
VDD  
NC  
NC  
NC  
RD7  
RD6  
VSS  
RD4  
RD13  
RA15  
VDD  
VDD  
RD0  
RD8  
RC12  
RA5  
RC13  
NC  
RD11  
RD10  
RA14  
RC15  
RA4  
RC2  
RG7  
NC  
RG1  
NC  
RD9  
VSS  
NC  
G
H
J
VSS  
VDD  
RA1  
RF12  
VSS  
NC  
RA3  
RG2  
RF8  
RF3  
RF4  
VDD  
NC  
VBUS  
NC  
VUSB  
NC  
RA2  
RB7  
RA10  
AVSS  
AVDD  
RB8  
RB9  
RB11  
NC  
RB12  
RB14  
RB13  
RG3  
RF2  
K
L
VDD  
RD15  
RD14  
RB10  
RB15  
RF5  
RF13  
Note 1: Refer to Table 4 for full pin names.  
© 2011 Microchip Technology Inc.  
DS61143H-page 15  
PIC32MX3XX/4XX  
TABLE 4:  
PIN NAMES: PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L  
DEVICES  
Pin  
Number  
Pin  
Number  
Full Pin Name  
Full Pin Name  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
A10  
A11  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
B9  
B10  
B11  
C1  
C2  
C3  
C4  
C5  
C6  
C7  
C8  
C9  
C10  
C11  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
D9  
D10  
D11  
E1  
E2  
E3  
E4  
E5  
E6  
E7  
PMD4/RE4  
E8  
E9  
E10  
E11  
F1  
SDA1/INT4/RA15  
RTCC/IC1/RD8  
SS1/IC2/RD9  
SCL1/INT3/RA14  
MCLR  
PMD3/RE3  
TRD0/RG13  
PMD0/RE0  
PMD8/RG0  
PMD10/RF1  
ENVREG  
F2  
SDO2/PMA3/CN10/RG8  
SS2/PMA2/CN11/RG9  
SDI2/PMA4/CN9/RG7  
VSS  
F3  
VSS  
F4  
IC5/PMD12/RD12  
OC3/RD2  
F5  
F6  
No Connect (NC)  
No Connect (NC)  
Vdd  
OC2/RD1  
F7  
No Connect (NC)  
RG15  
F8  
F9  
OSC1/CLKI/RC12  
VSS  
PMD2/RE2  
PMD1/RE1  
TRD3/RA7  
PMD11/RF0  
VCAP/VCORE  
PMRD/CN14/RD5  
OC4/RD3  
F10  
F11  
G1  
G2  
G3  
G4  
G5  
G6  
G7  
G8  
G9  
G10  
G11  
H1  
H2  
H3  
H4  
H5  
H6  
H7  
H8  
H9  
H10  
H11  
J1  
OSC2/CLKO/RC15  
INT1/RE8  
INT2/RE9  
TMS/RA0  
No Connect (NC)  
VDD  
VSS  
VSS  
SOSCO/T1CK/CN0/RC14  
PMD6/RE6  
VSS  
No Connect (NC)  
TDO/RA5  
VDD  
TRD1/RG12  
SDA2/RA3  
TRD2/RG14  
TDI/RA4  
TRCLK/RA6  
AN5/C1IN+/VBUSON/CN7/RB5  
AN4/C1IN-/CN6/RB4  
VSS  
No Connect (NC)  
PMD15/CN16/RD7  
OC5/PMWR/CN13/RD4  
VDD  
VDD  
No Connect (NC)  
VDD  
SOSCI/CN1/RC13  
IC4/PMCS1/PMA14/RD11  
T2CK/RC1  
No Connect (NC)  
VBUS  
PMD7/RE7  
VUSB  
PMD5/RE5  
D+/RG2  
VSS  
SCL2/RA2  
VSS  
AN3/C2IN+/CN5/RB3  
AN2/C2IN-/CN4/RB2  
PGED2/AN7/RB7  
AVDD  
No Connect (NC)  
PMD14/CN15/RD6  
CN19/PMD13/RD13  
SDO1/OC1/INT0/RD0  
No Connect (NC)  
SCK1/IC3/PMCS2/PMA15/RD10  
T5CK/SDI1/RC4  
T4CK/RC3  
J2  
J3  
J4  
J5  
AN11/PMA12/RB11  
TCK/RA1  
J6  
J7  
AN12/PMA11/RB12  
No Connect (NC)  
No Connect (NC)  
U1TX/RF8  
J8  
J9  
SCK2/PMA5/CN8/RG6  
T3CK/RC2  
J10  
J11  
K1  
K2  
K3  
D-/RG3  
VDD  
PGEC1/AN1/CN3/RB1  
PGED1/AN0/CN2/RB0  
VREF+/CVREF+/PMA6/RA10  
PMD9/RG1  
VSS  
DS61143H-page 16  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
TABLE 4:  
PIN NAMES: PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L  
DEVICES (CONTINUED)  
Pin  
Number  
Pin  
Number  
Full Pin Name  
Full Pin Name  
K4  
K5  
K6  
K7  
K8  
K9  
K10  
K11  
L1  
AN8/C1OUT/RB8  
No Connect (NC)  
U2CTS/RF12  
L3  
L4  
AVSS  
AN9/C2OUT/RB9  
L5  
AN10/CVREFOUT/PMA13/RB10  
U2RTS/RF13  
AN14/PMALH/PMA1/RB14  
VDD  
L6  
L7  
AN13/PMA10/RB13  
U1RTS/CN21/RD15  
USBID/RF3  
L8  
AN15/OCFB/PMALL/PMA0/CN12/RB15  
U1CTS/CN20/RD14  
L9  
U1RX/RF2  
L10  
L11  
U2RX/PMA9/CN17/RF4  
U2TX/PMA8/CN18/RF5  
PGEC2/AN6/OCFA/RB6  
VREF-/CVREF-/PMA7/RA9  
L2  
© 2011 Microchip Technology Inc.  
DS61143H-page 17  
PIC32MX3XX/4XX  
Table of Contents  
1.0 Device Overview ........................................................................................................................................................................ 21  
2.0 Guidelines for Getting Started with 32-bit Microcontrollers ........................................................................................................ 31  
3.0 CPU............................................................................................................................................................................................ 37  
4.0 Memory Organization................................................................................................................................................................. 43  
5.0 Flash Program Memory.............................................................................................................................................................. 85  
6.0 Resets ........................................................................................................................................................................................ 87  
7.0 Interrupt Controller ..................................................................................................................................................................... 89  
8.0 Oscillator Configuration.............................................................................................................................................................. 93  
9.0 Prefetch Cache........................................................................................................................................................................... 95  
10.0 Direct Memory Access (DMA) Controller .................................................................................................................................. 97  
11.0 USB On-The-Go (OTG).............................................................................................................................................................. 99  
12.0 I/O Ports ................................................................................................................................................................................... 101  
13.0 Timer1 ...................................................................................................................................................................................... 103  
14.0 Timer2/3 and Timer4/5............................................................................................................................................................ 105  
15.0 Input Capture............................................................................................................................................................................ 107  
16.0 Output Compare....................................................................................................................................................................... 109  
17.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 111  
18.0 Inter-Integrated Circuit™ (I2C™).............................................................................................................................................. 113  
19.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 115  
20.0 Parallel Master Port (PMP) ...................................................................................................................................................... 119  
21.0 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 121  
22.0 10-bit Analog-to-Digital Converter (ADC)................................................................................................................................. 123  
23.0 Comparator .............................................................................................................................................................................. 125  
24.0 Comparator Voltage Reference (CVREF).................................................................................................................................. 127  
25.0 Power-Saving Features ........................................................................................................................................................... 129  
26.0 Special Features ...................................................................................................................................................................... 131  
27.0 Instruction Set .......................................................................................................................................................................... 141  
28.0 Development Support............................................................................................................................................................... 147  
29.0 Electrical Characteristics.......................................................................................................................................................... 151  
30.0 Packaging Information.............................................................................................................................................................. 191  
Index ................................................................................................................................................................................................. 209  
DS61143H-page 18  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
TO OUR VALUED CUSTOMERS  
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip  
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and  
enhanced as new volumes and updates are introduced.  
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via  
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We  
welcome your feedback.  
Most Current Data Sheet  
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:  
http://www.microchip.com  
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.  
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).  
Errata  
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current  
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision  
of silicon and revision of document to which it applies.  
To determine if an errata sheet exists for a particular device, please check with one of the following:  
•
•
Microchip’s Worldwide Web site; http://www.microchip.com  
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are  
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Register on our web site at www.microchip.com to receive the most current information on all of our products.  
© 2011 Microchip Technology Inc.  
DS61143H-page 19  
PIC32MX3XX/4XX  
NOTES:  
DS61143H-page 20  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
This document contains device-specific information for  
the PIC32MX3XX/4XX devices.  
1.0  
DEVICE OVERVIEW  
Note 1: This data sheet summarizes the features  
of the PIC32MX3XX/4XX family of  
devices. It is not intended to be a  
comprehensive reference source. To  
complement the information in this data  
sheet, refer to the “PIC32 Family  
Reference Manual”, which is available  
Figure 1-1 illustrates a general block diagram of the core  
and peripheral modules in the PIC32MX3XX/4XX family  
of devices.  
Table 1-1 lists the functions of the various pins shown  
in the pinout diagrams.  
from  
the  
Microchip  
web  
site  
(www.microchip.com/PIC32).  
2: Some registers and associated bits  
described in this section may not be  
available on all devices. Refer to  
Section 4.0 “Memory Organization” in  
this data sheet for device-specific register  
and bit information.  
(1,2)  
FIGURE 1-1:  
BLOCK DIAGRAM  
VCORE/VCAP  
OSC2/CLKO  
OSC1/CLKI  
OSC/SOSC  
Oscillators  
Power-up  
Timer  
VDD,VSS  
MCLR  
FRC/LPRC  
Oscillators  
ENVREG  
Oscillator  
Start-up Timer  
Voltage  
Regulator  
PLL  
Power-on  
Reset  
Precision  
Band Gap  
Reference  
DIVIDERS  
PLL-USB  
Watchdog  
Timer  
USBCLK  
SYSCLK  
PBCLK  
Brown-out  
Reset  
Timing  
Generation  
CN1-22  
Peripheral Bus Clocked by SYSCLK  
Timer1-5  
PORTA  
PORTB  
PORTC  
PORTD  
PORTE  
PORTF  
PORTG  
Priority  
Interrupt  
Controller  
PWM  
OC1-5  
JTAG  
BSCAN  
DMAC  
USB  
ICD  
32  
EJTAG  
®
INT  
IC1-5  
SPI1,2  
I2C1,2  
®
MIPS32 M4K CPU Core  
IS  
DS  
32  
Bus Matrix  
32  
32  
32  
32  
32  
32  
PMP  
10-bit ADC  
UART1,2  
RTCC  
32  
32  
32  
Prefetch  
Module  
Peripheral Bridge  
Data RAM  
128  
128-bit wide  
Program Flash Memory  
Flash  
Controller  
Comparators  
Note 1: Some features are not available on all device variants.  
2: BOR functionality is provided when the on-board voltage regulator is enabled.  
© 2011 Microchip Technology Inc.  
DS61143H-page 21  
PIC32MX3XX/4XX  
TABLE 1-1:  
PINOUT I/O DESCRIPTIONS  
Pin Number(1)  
Pin  
Buffer  
Type  
Pin Name  
Description  
64-pin  
100-pin 121-pin  
Type  
QFN/TQFP TQFP  
XBGA  
AN0  
16  
15  
14  
13  
12  
11  
17  
18  
21  
22  
23  
24  
27  
28  
29  
30  
39  
25  
24  
23  
22  
21  
20  
26  
27  
32  
33  
34  
35  
41  
42  
43  
44  
63  
K2  
K1  
J2  
J1  
H2  
H1  
L1  
J3  
K4  
L4  
L5  
J5  
J7  
L7  
K7  
L8  
F9  
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Analog Analog input channels.  
AN1  
Analog  
Analog  
Analog  
Analog  
Analog  
Analog  
Analog  
Analog  
Analog  
Analog  
Analog  
Analog  
Analog  
Analog  
Analog  
AN2  
AN3  
AN4  
AN5  
AN6  
AN7  
AN8  
AN9  
AN10  
AN11  
AN12  
AN13  
AN14  
AN15  
CLKI  
ST/CMOS External clock source input. Always associated with  
OSC1 pin function.  
CLKO  
40  
64  
F11  
O
—
Oscillator crystal output. Connects to crystal or  
resonator in Crystal Oscillator mode. Optionally  
functions as CLKO in RC and EC modes. Always  
associated with OSC2 pin function.  
OSC1  
OSC2  
39  
40  
63  
64  
F9  
I
ST/CMOS Oscillator crystal input. ST buffer when configured in  
RC mode; CMOS otherwise.  
F11  
I/O  
—
Oscillator crystal output. Connects to crystal or  
resonator in Crystal Oscillator mode. Optionally  
functions as CLKO in RC and EC modes.  
SOSCI  
47  
48  
73  
74  
C10  
B11  
I
ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS  
otherwise.  
SOSCO  
O
—
32.768 kHz low-power oscillator crystal output.  
Legend: CMOS = CMOS compatible input or output  
ST = Schmitt Trigger input with CMOS levels  
TTL = TTL input buffer  
Analog = Analog input  
O = Output  
P = Power  
I = Input  
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.  
DS61143H-page 22  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
TABLE 1-1:  
Pin Name  
PINOUT I/O DESCRIPTIONS (CONTINUED)  
Pin Number(1)  
Pin  
Buffer  
Type  
Description  
64-pin  
100-pin 121-pin  
Type  
QFN/TQFP TQFP  
XBGA  
CN0  
CN1  
CN2  
CN3  
CN4  
CN5  
CN6  
CN7  
CN8  
CN9  
CN10  
CN11  
CN12  
CN13  
CN14  
CN15  
CN16  
CN17  
CN18  
CN19  
CN20  
CN21  
IC1  
48  
47  
16  
15  
14  
13  
12  
11  
4
74  
73  
25  
24  
23  
22  
21  
20  
10  
11  
B11  
C10  
K2  
I
I
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
—
Change notification inputs.  
Can be software programmed for internal weak  
pull-ups on all inputs.  
I
K1  
I
J2  
I
J1  
I
H2  
H1  
E3  
I
I
I
5
F4  
I
6
12  
14  
44  
81  
82  
83  
84  
49  
50  
80  
47  
48  
68  
69  
70  
71  
79  
26  
72  
76  
77  
78  
81  
44  
55,72  
18  
19  
F2  
I
8
F3  
I
30  
52  
53  
54  
55  
31  
32  
—
—
—
42  
43  
44  
45  
52  
17  
46  
49  
50  
51  
52  
30  
35,46  
42  
43  
L8  
I
C8  
B8  
I
I
D7  
C7  
L10  
L11  
D8  
L9  
I
I
I
I
I
I
K9  
I
E9  
I
Capture inputs 1-5.  
IC2  
E10  
D11  
C11  
A9  
I
IC3  
I
IC4  
I
IC5  
I
OCFA  
OC1  
OC2  
OC3  
OC4  
OC5  
OCFB  
INT0  
INT1  
INT2  
L1  
I
Output Compare Fault A Input.  
Output Compare output 1.  
Output Compare output 2  
Output Compare output 3.  
Output Compare output 4.  
Output Compare output 5.  
Output Compare Fault B Input.  
External interrupt 0.  
D9  
A11  
A10  
B9  
O
O
O
O
O
I
—
—
—
C8  
L8  
—
ST  
ST  
ST  
ST  
H9,D9  
61  
I
I
External interrupt 1.  
62  
I
External interrupt 2.  
Legend: CMOS = CMOS compatible input or output  
ST = Schmitt Trigger input with CMOS levels  
TTL = TTL input buffer  
Analog = Analog input  
O = Output  
P = Power  
I = Input  
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.  
© 2011 Microchip Technology Inc.  
DS61143H-page 23  
PIC32MX3XX/4XX  
TABLE 1-1:  
PINOUT I/O DESCRIPTIONS (CONTINUED)  
Pin Number(1)  
Pin  
Type  
Buffer  
Type  
Pin Name  
Description  
64-pin 100-pin 121-pin  
QFN/TQFP TQFP  
XBGA  
INT3  
INT4  
RA0  
44  
45  
—
—
—
—
—
—
—
—
—
—
—
—
16  
15  
14  
13  
12  
11  
17  
18  
21  
22  
23  
24  
27  
28  
29  
30  
—
—
—
—
39  
47  
48  
40  
66  
67  
17  
38  
58  
59  
60  
61  
91  
92  
28  
29  
66  
67  
25  
24  
23  
22  
21  
20  
26  
27  
32  
33  
34  
35  
41  
42  
43  
44  
6
E11  
E8  
G3  
J6  
I
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
External interrupt 3.  
External interrupt 4.  
I
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
PORTA is a bidirectional I/O port.  
RA1  
RA2  
H11  
G10  
G11  
G9  
C5  
B5  
L2  
RA3  
RA4  
RA5  
RA6  
RA7  
RA9  
RA10  
RA14  
RA15  
RB0  
K3  
E11  
E8  
K2  
K1  
J2  
PORTB is a bidirectional I/O port.  
RB1  
RB2  
RB3  
J1  
RB4  
H2  
H1  
L1  
RB5  
RB6  
RB7  
J3  
RB8  
K4  
L4  
RB9  
RB10  
RB11  
RB12  
RB13  
RB14  
RB15  
RC1  
RC2  
RC3  
RC4  
RC12  
RC13  
RC14  
RC15  
L5  
J5  
J7  
L7  
K7  
L8  
D1  
E4  
E2  
E1  
F9  
PORTC is a bidirectional I/O port.  
7
8
9
63  
73  
74  
64  
C10  
B11  
F11  
Legend: CMOS = CMOS compatible input or output  
ST = Schmitt Trigger input with CMOS levels  
TTL = TTL input buffer  
Analog = Analog input  
O = Output  
P = Power  
I = Input  
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.  
DS61143H-page 24  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
TABLE 1-1:  
Pin Name  
PINOUT I/O DESCRIPTIONS (CONTINUED)  
Pin Number(1)  
Pin  
Buffer  
Type  
Description  
64-pin  
100-pin 121-pin  
Type  
QFN/TQFP TQFP  
XBGA  
RD0  
RD1  
RD2  
RD3  
RD4  
RD5  
RD6  
RD7  
RD8  
RD9  
RD10  
RD11  
RD12  
RD13  
RD14  
RD15  
RE0  
RE1  
RE2  
RE3  
RE4  
RE5  
RE6  
RE7  
RE8  
RE9  
RF0  
RF1  
RF2  
RF3  
RF4  
RF5  
RF6  
RF7  
RF8  
RF12  
RF13  
46  
49  
50  
51  
52  
53  
54  
55  
42  
43  
44  
45  
—
—
—
—
60  
61  
62  
63  
64  
1
72  
76  
77  
78  
81  
82  
83  
84  
68  
69  
70  
71  
79  
80  
47  
48  
93  
94  
98  
99  
100  
3
D9  
A11  
A10  
B9  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
PORTD is a bidirectional I/O port.  
C8  
B8  
D7  
C7  
E9  
E10  
D11  
C11  
A9  
D8  
L9  
K9  
A4  
PORTE is a bidirectional I/O port.  
B4  
B3  
A2  
A1  
D3  
C1  
D2  
G1  
G2  
B6  
2
4
3
5
—
—
58  
59  
34  
33  
31  
32  
35  
—
—
—
—
18  
19  
87  
88  
52  
51  
49  
50  
55  
54  
53  
40  
39  
PORTF is a bidirectional I/O port.  
A6  
K11  
K10  
L10  
L11  
H9  
H8  
J10  
K6  
L6  
Legend: CMOS = CMOS compatible input or output  
ST = Schmitt Trigger input with CMOS levels  
TTL = TTL input buffer  
Analog = Analog input  
O = Output  
P = Power  
I = Input  
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.  
© 2011 Microchip Technology Inc.  
DS61143H-page 25  
PIC32MX3XX/4XX  
TABLE 1-1:  
PINOUT I/O DESCRIPTIONS (CONTINUED)  
Pin Number(1)  
Pin  
Type  
Buffer  
Type  
Pin Name  
Description  
64-pin 100-pin 121-pin  
QFN/TQFP TQFP  
XBGA  
RG0  
—
—
90  
89  
10  
11  
12  
14  
96  
97  
95  
1
A5  
E6  
E3  
F4  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
—
PORTG is a bidirectional I/O port.  
RG1  
RG6  
4
RG7  
5
RG8  
6
F2  
RG9  
8
F3  
RG12  
RG13  
RG14  
RG15  
RG2  
—
C3  
A3  
C4  
B2  
H10  
J11  
B11  
D1  
E4  
E2  
E1  
L9  
—
—
—
37  
36  
48  
—
57  
56  
74  
6
PORTG input pins.  
RG3  
I
T1CK  
T2CK  
T3CK  
T4CK  
T5CK  
U1CTS  
U1RTS  
U1RX  
U1TX  
U2CTS  
U2RTS  
U2RX  
U2TX  
SCK1  
SDI1  
I
Timer1 external clock input.  
Timer2 external clock input.  
Timer3 external clock input.  
Timer4 external clock input.  
Timer5 external clock input.  
UART1 clear to send.  
I
—
7
I
—
8
I
—
9
I
43  
35, 49  
34, 50  
33, 51  
21  
29  
31  
32  
35  
34  
33  
14  
4
47  
48  
52  
I
K9  
K11  
O
I
UART1 ready to send.  
ST  
—
UART1 receive.  
51, 53 J10, K10  
O
I
UART1 transmit.  
40  
39  
49  
50  
K6  
L6  
ST  
—
UART2 clear to send.  
O
I
UART2 ready to send.  
L10  
L11  
ST  
—
UART2 receive.  
O
I/O  
I
UART2 transmit.  
55, 70 D11, H9  
9, 54 E1, H8  
53, 72 D9, J10  
ST  
ST  
—
Synchronous serial clock input/output for SPI1.  
SPI1 data in.  
SDO1  
SS1  
O
I/O  
I/O  
I
SPI1 data out.  
23, 69  
10  
E10, J2  
E3  
ST  
ST  
ST  
—
SPI1 slave synchronization or frame pulse I/O.  
Synchronous serial clock input/output for SPI2.  
SPI2 data in.  
SCK2  
SDI2  
5
11  
F4  
SDO2  
SS2  
6
12  
F2  
O
I/O  
SPI2 data out.  
8
14  
F3  
ST  
ST  
ST  
ST  
ST  
SPI2 slave synchronization or frame pulse I/O.  
Synchronous serial clock input/output for I2C1.  
Synchronous serial data input/output for I2C1.  
Synchronous serial clock input/output for I2C2.  
Synchronous serial data input/output for I2C2.  
SCL1  
SDA1  
SCL2  
SDA2  
37, 44  
36, 43  
32  
31  
57, 66 E11, H10 I/O  
56, 67  
58  
E8, J11  
H11  
I/O  
I/O  
I/O  
59  
G10  
Legend: CMOS = CMOS compatible input or output  
ST = Schmitt Trigger input with CMOS levels  
TTL = TTL input buffer  
Analog = Analog input  
O = Output  
P = Power  
I = Input  
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.  
DS61143H-page 26  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
TABLE 1-1:  
Pin Name  
PINOUT I/O DESCRIPTIONS (CONTINUED)  
Pin Number(1)  
Pin  
Buffer  
Type  
Description  
64-pin  
100-pin 121-pin  
Type  
QFN/TQFP TQFP  
XBGA  
TMS  
23  
27  
28  
24  
42  
15  
16  
23  
12  
11  
21  
14  
13  
22  
30  
17  
38  
60  
61  
68  
28  
29  
34  
21  
20  
32  
23  
22  
33  
44  
G3  
J6  
I
I
ST  
ST  
ST  
—
JTAG Test mode select pin.  
JTAG test clock input pin.  
JTAG test data input pin.  
JTAG test data output pin.  
Real-Time Clock Alarm Output.  
TCK  
TDI  
G11  
G9  
E9  
L2  
I
TDO  
O
O
I
RTCC  
CVREF-  
CVREF+  
CVREFOUT  
C1IN-  
C1IN+  
C1OUT  
C2IN-  
C2IN+  
C2OUT  
PMA0  
—
Analog Comparator Voltage Reference (low).  
Analog Comparator Voltage Reference (high).  
Analog Comparator Voltage Reference Output.  
Analog Comparator 1 Negative Input.  
K3  
L5  
I
O
I
H2  
H1  
K4  
J2  
I
Analog Comparator 1 Positive Input.  
O
I
—
Comparator 1 Output.  
Analog Comparator 2 Negative Input.  
Analog Comparator 2 Positive Input.  
J1  
I
L4  
O
I/O  
—
Comparator 2 Output.  
L8  
TTL/ST Parallel Master Port Address Bit 0 Input (Buffered  
Slave modes) and Output (Master modes).  
PMA1  
29  
43  
K7  
I/O  
TTL/ST Parallel Master Port Address Bit 1 Input (Buffered  
Slave modes) and Output (Master modes).  
PMA2  
8
14  
12  
11  
10  
29  
28  
50  
49  
42  
41  
35  
34  
71  
70  
71  
70  
F3  
F2  
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Parallel Master Port Address (De-multiplexed Master  
Modes).  
PMA3  
6
PMA4  
5
F4  
PMA5  
4
E3  
PMA6  
16  
22  
32  
31  
28  
27  
24  
23  
45  
44  
45  
44  
K3  
PMA7  
L2  
PMA8  
L11  
L10  
L7  
PMA9  
PMA10  
PMA11  
PMA12  
PMA13  
PMA14  
PMA15  
PMCS1  
PMCS2  
J7  
J5  
L5  
C11  
D11  
C11  
D11  
Parallel Master Port Chip Select 1 Strobe.  
Parallel Master Port Chip Select 2 Strobe.  
Legend: CMOS = CMOS compatible input or output  
ST = Schmitt Trigger input with CMOS levels  
TTL = TTL input buffer  
Analog = Analog input  
O = Output  
P = Power  
I = Input  
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.  
© 2011 Microchip Technology Inc.  
DS61143H-page 27  
PIC32MX3XX/4XX  
TABLE 1-1:  
PINOUT I/O DESCRIPTIONS (CONTINUED)  
Pin Number(1)  
Pin  
Type  
Buffer  
Type  
Pin Name  
Description  
64-pin 100-pin 121-pin  
QFN/TQFP TQFP  
XBGA  
PMD0  
PMD1  
PMD2  
PMD3  
PMD4  
PMD5  
PMD6  
PMD7  
PMD8  
PMD9  
PMD10  
PMD11  
PMD12  
PMD13  
PMD14  
PMD15  
PMRD  
PMWR  
PMALL  
60  
61  
62  
63  
64  
1
93  
94  
98  
99  
100  
3
A4  
B4  
B3  
A2  
A1  
D3  
C1  
D2  
A5  
E6  
A6  
B6  
A9  
D8  
D7  
C7  
B8  
C8  
L8  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
O
TTL/ST Parallel Master Port Data (De-multiplexed Master  
mode) or Address/Data (Multiplexed Master modes).  
TTL/ST  
TTL/ST  
TTL/ST  
TTL/ST  
TTL/ST  
TTL/ST  
TTL/ST  
TTL/ST  
TTL/ST  
TTL/ST  
TTL/ST  
TTL/ST  
TTL/ST  
TTL/ST  
TTL/ST  
2
4
3
5
—
—
—
—
—
—
—
—
53  
52  
30  
90  
89  
88  
87  
79  
80  
83  
84  
82  
81  
44  
—
—
—
Parallel Master Port Read Strobe.  
Parallel Master Port Write Strobe.  
O
O
Parallel Master Port Address Latch Enable low-byte  
(Multiplexed Master modes).  
PMALH  
29  
43  
K7  
O
—
Parallel Master Port Address Latch Enable high-byte  
(Multiplexed Master modes).  
VBUS  
VUSB  
34  
35  
54  
55  
H8  
H9  
I
Analog USB Bus Power Monitor.  
P
—
USB Internal Transceiver Supply. If the USB module  
is not used, this pin must be connected to VDD.  
VBUSON  
D+  
11  
37  
36  
33  
57  
—
—
—
—
—
16  
20  
57  
56  
51  
86  
91  
97  
96  
95  
92  
25  
H1  
H10  
J11  
K10  
A7  
O
I/O  
I/O  
I
—
USB Host and OTG Bus Power Control Output.  
Analog USB D+.  
Analog USB D-.  
D-  
USBID  
ENVREG  
TRCLK  
TRD0  
TRD1  
TRD2  
TRD3  
PGED1  
ST  
ST  
—
USB OTG ID Detect.  
I
Enable for On-Chip Voltage Regulator.  
Trace Clock.  
C5  
A3  
O
O
—
Trace Data Bits 0-3.  
C3  
C4  
B5  
O
—
O
—
O
—
K2  
I/O  
ST  
Data I/O pin for programming/debugging  
communication channel 1.  
PGEC1  
15  
24  
K1  
I
ST  
Clock input pin for programming/debugging  
communication channel 1.  
Legend: CMOS = CMOS compatible input or output  
ST = Schmitt Trigger input with CMOS levels  
TTL = TTL input buffer  
Analog = Analog input  
O = Output  
P = Power  
I = Input  
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.  
DS61143H-page 28  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
TABLE 1-1:  
Pin Name  
PINOUT I/O DESCRIPTIONS (CONTINUED)  
Pin Number(1)  
Pin  
Buffer  
Type  
Description  
64-pin  
100-pin 121-pin  
Type  
QFN/TQFP TQFP  
XBGA  
PGED2  
PGEC2  
MCLR  
AVDD  
18  
17  
7
27  
26  
13  
30  
31  
J3  
I/O  
I
ST  
ST  
ST  
P
Data I/O pin for programming/debugging  
communication channel 2.  
L1  
F1  
J4  
L3  
Clock input pin for programming/debugging  
communication channel 2.  
I/P  
P
Master Clear (Reset) input. This pin is an active-low  
Reset to the device.  
19  
Positive supply for analog modules. This pin must be  
connected at all times.  
AVSS  
VDD  
20  
P
P
P
Ground reference for analog modules.  
10, 26, 38 2, 16, 37, C2, C9,  
—
Positive supply for peripheral logic and I/O pins.  
46, 62  
E5, F8,  
G5, H4,  
H6, K8  
VCORE/  
VCAP  
56  
85  
B7  
P
P
—
—
Capacitor for Internal Voltage Regulator.  
Ground reference for logic and I/O pins.  
Vss  
9, 25, 41  
15, 36, A8, B10,  
45, 65, D4, D5,  
75  
E7, F10,  
F5, G6,  
G7, H3  
VREF+  
VREF-  
16  
15  
29  
28  
K3  
L2  
I
I
Analog Analog voltage reference (high) input.  
Analog Analog voltage reference (low) input.  
Legend: CMOS = CMOS compatible input or output  
ST = Schmitt Trigger input with CMOS levels  
TTL = TTL input buffer  
Analog = Analog input  
O = Output  
P = Power  
I = Input  
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.  
© 2011 Microchip Technology Inc.  
DS61143H-page 29  
PIC32MX3XX/4XX  
NOTES:  
DS61143H-page 30  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
2.2  
Decoupling Capacitors  
2.0  
GUIDELINES FOR GETTING  
STARTED WITH 32-BIT  
MICROCONTROLLERS  
The use of decoupling capacitors on every pair of  
power supply pins, such as VDD, VSS, AVDD and  
AVSS is required. See Figure 2-1.  
Note 1: This data sheet summarizes the features  
of the PIC32MX3XX/4XX family of  
devices. It is not intended to be a  
comprehensive reference source. To  
complement the information in this data  
sheet, refer to the “PIC32 Family  
Reference Manual”, which is available  
Consider the following criteria when using decoupling  
capacitors:  
• Value and type of capacitor: Recommendation  
of 0.1 µF (100 nF), 10-20V. This capacitor should  
be a low-ESR and have resonance frequency in  
the range of 20 MHz and higher. It is  
recommended that ceramic capacitors be used.  
from  
the  
Microchip  
web  
site  
(www.microchip.com/PIC32).  
• Placement on the printed circuit board: The  
decoupling capacitors should be placed as close  
to the pins as possible. It is recommended to  
place the capacitors on the same side of the  
board as the device. If space is constricted, the  
capacitor can be placed on another layer on the  
PCB using a via; however, ensure that the trace  
length from the pin to the capacitor is within  
one-quarter inch (6 mm) in length.  
2: Some registers and associated bits  
described in this section may not be avail-  
able on all devices. Refer to Section 4.0  
“Memory Organization” in this data  
sheet for device-specific register and bit  
information.  
2.1  
Basic Connection Requirements  
• Handling high frequency noise: If the board is  
experiencing high frequency noise, upward of  
tens of MHz, add a second ceramic-type capacitor  
in parallel to the above described decoupling  
capacitor. The value of the second capacitor can  
be in the range of 0.01 µF to 0.001 µF. Place this  
second capacitor next to the primary decoupling  
capacitor. In high-speed circuit designs, consider  
implementing a decade pair of capacitances as  
close to the power and ground pins as possible.  
For example, 0.1 µF in parallel with 0.001 µF.  
Getting started with the PIC32MX3XX/4XX family of  
32-bit Microcontrollers (MCUs) requires attention to a  
minimal set of device pin connections before  
proceeding with development. The following is a list of  
pin names, which must always be connected:  
• All VDD and VSS pins  
(see Section 2.2 “Decoupling Capacitors”)  
• All AVDD and AVSS pins (regardless if ADC module  
is not used)  
(see Section 2.2 “Decoupling Capacitors”)  
• Maximizing performance: On the board layout  
from the power supply circuit, run the power and  
return traces to the decoupling capacitors first,  
and then to the device pins. This ensures that the  
decoupling capacitors are first in the power chain.  
Equally important is to keep the trace length  
between the capacitor and the power pins to a  
minimum thereby reducing PCB track inductance.  
• VCAP/VCORE  
(see Section 2.3 “Capacitor on Internal Voltage  
Regulator (VCAP/VCORE)”)  
• MCLR pin  
(see Section 2.4 “Master Clear (MCLR) Pin”)  
• PGECx/PGEDx pins used for In-Circuit Serial  
Programming™ (ICSP™) and debugging purposes  
(see Section 2.5 “ICSP Pins”)  
• OSC1 and OSC2 pins when external oscillator  
source is used  
(see Section 2.8 “External Oscillator Pins”)  
Additionally, the following pins may be required:  
• VREF+/VREF- pins used when external voltage  
reference for ADC module is implemented  
Note:  
The AVDD and AVSS pins must be  
connected independent of ADC use and  
ADC voltage reference source.  
© 2011 Microchip Technology Inc.  
DS61143H-page 31  
PIC32MX3XX/4XX  
FIGURE 2-1:  
RECOMMENDED  
MINIMUM CONNECTION  
2.4  
Master Clear (MCLR) Pin  
The MCLR pin provides for two specific device  
functions:  
0.1 µF  
Ceramic  
• Device Reset  
VDD  
CEFC  
CBP  
• Device Programming and Debugging  
Pulling The MCLR pin low generates a device reset.  
Figure 2-2 illustrates a typical MCLR circuit. During  
device programming and debugging, the resistance  
and capacitance that can be added to the pin must  
be considered. Device programmers and debuggers  
drive the MCLR pin. Consequently, specific voltage  
levels (VIH and VIL) and fast signal transitions must  
not be adversely affected. Therefore, specific values  
of R and C will need to be adjusted based on the  
application and PCB requirements.  
R
R1  
MCLR  
C
PIC32MX  
VDD  
VSS  
VDD  
VSS  
0.1 µF  
Ceramic  
CBP  
0.1 µF  
Ceramic  
CBP  
For example, as illustrated in Figure 2-2, it is  
recommended that the capacitor C, be isolated from  
the MCLR pin during programming and debugging  
operations.  
0.1 µF  
Ceramic  
CBP  
0.1 µF  
Ceramic  
CBP  
10Ω  
Place the components shown in Figure 2-2 within  
one-quarter inch (6 mm) from the MCLR pin.  
2.2.1  
BULK CAPACITORS  
The use of a bulk capacitor is recommended to improve  
power supply stability. Typical values range from 4.7 µF  
to 47 µF. This capacitor should be located as close to  
the device as possible.  
FIGURE 2-2:  
EXAMPLE OF MCLR PIN  
CONNECTIONS  
VDD  
2.3  
Capacitor on Internal Voltage  
Regulator (VCAP/VCORE)  
R
R1  
MCLR  
2.3.1  
INTERNAL REGULATOR MODE  
PIC32MX  
JP  
C
A low-ESR (< 1 Ohm) capacitor is required on the  
VCAP/VCORE pin, which is used to stabilize the internal  
voltage regulator output. The VCAP/VCORE pin must not  
be connected to VDD, and must have a CEFC capacitor,  
with at least a 6V rating, connected to ground. The type  
can be ceramic or tantalum. Refer to Section 29.0  
“Electrical Characteristics” for additional information  
on CEFC specifications. This mode is enabled by  
connecting the ENVREG pin to VDD.  
Note 1: R ≤10 kΩ is recommended. A suggested start-  
ing value is 10 kΩ. Ensure that the MCLR pin  
VIH and VIL specifications are met.  
2: R1 ≤ 470Ω will limit any current flowing into  
MCLR from the external capacitor C, in the  
event of MCLR pin breakdown, due to  
Electrostatic Discharge (ESD) or Electrical  
Overstress (EOS). Ensure that the MCLR pin  
VIH and VIL specifications are met.  
2.3.2  
EXTERNAL REGULATOR MODE  
In this mode the core voltage is supplied externally  
through the VCORE/VCAP pin. A low-ESR capacitor of  
10 µF is recommended on the VCAP/VCORE pin. This  
mode is enabled by grounding the ENVREG pin.  
3: The capacitor can be sized to prevent uninten-  
tional resets from brief glitches or to extend the  
device reset period during POR.  
The placement of this capacitor should be close to the  
VCAP/VCORE. It is recommended that the trace length  
not exceed one-quarter inch (6 mm). Refer to  
Section 26.3 “On-Chip Voltage Regulator” for  
details.  
DS61143H-page 32  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
Pull-up resistors, series diodes and capacitors on the  
TMS, TDO, TDI and TCK pins are not recommended  
as they will interfere with the programmer/debugger  
communications to the device. If such discrete compo-  
nents are an application requirement, they should be  
removed from the circuit during programming and  
debugging. Alternately, refer to the AC/DC characteris-  
tics and timing requirements information in the respec-  
tive device Flash programming specification for  
information on capacitive loading limits and pin input  
voltage high (VIH) and input low (VIL) requirements.  
2.5  
ICSP Pins  
The PGECx and PGEDx pins are used for In-Circuit  
Serial Programming™ (ICSP™) and debugging pur-  
poses. It is recommended to keep the trace length  
between the ICSP connector and the ICSP pins on the  
device as short as possible. If the ICSP connector is  
expected to experience an ESD event, a series resistor  
is recommended, with the value in the range of a few  
tens of Ohms, not to exceed 100 Ohms.  
Pull-up resistors, series diodes and capacitors on the  
PGECx and PGEDx pins are not recommended as they  
will interfere with the programmer/debugger communi-  
cations to the device. If such discrete components are  
an application requirement, they should be removed  
from the circuit during programming and debugging.  
Alternately, refer to the AC/DC characteristics and tim-  
ing requirements information in the respective device  
Flash programming specification for information on  
capacitive loading limits and pin input voltage high (VIH)  
and input low (VIL) requirements.  
2.7  
Trace  
The trace pins can be connected to a hardware-trace-  
enabled programmer to provide a compress real time  
instruction trace. When used for trace the TRD3,  
TRD2, TRD1, TRD0 and TRCLK pins should be dedi-  
cated for this use. The trace hardware requires a 22  
Ohm series resistor between the trace pins and the  
trace connector.  
Ensure that the “Communication Channel Select” (i.e.,  
PGECx/PGEDx pins) programmed into the device  
matches the physical connections for the ICSP to  
MPLAB® ICD 2, MPLAB ICD 3 or MPLAB REAL ICE™.  
2.8  
External Oscillator Pins  
Many MCUs have options for at least two oscillators: a  
high-frequency primary oscillator and a low-frequency  
secondary oscillator (refer to Section 8.0 “Oscillator  
Configuration” for details).  
For more information on ICD 2, ICD 3 and REAL ICE  
connection requirements, refer to the following  
documents that are available on the Microchip web  
site.  
• “MPLAB® ICD 2 In-Circuit Debugger User’s  
Guide” DS51331  
• “Using MPLAB® ICD 2” (poster) DS51265  
• “MPLAB® ICD 2 Design Advisory” DS51566  
• “Using MPLAB® ICD 3” (poster) DS51765  
• “MPLAB® ICD 3 Design Advisory” DS51764  
• “MPLAB® REAL ICE™ In-Circuit Debugger  
User’s Guide” DS51616  
The oscillator circuit should be placed on the same  
side of the board as the device. Also, place the  
oscillator circuit close to the respective oscillator pins,  
not exceeding one-half inch (12 mm) distance  
between them. The load capacitors should be placed  
next to the oscillator itself, on the same side of the  
board. Use a grounded copper pour around the  
oscillator circuit to isolate them from surrounding  
circuits. The grounded copper pour should be routed  
directly to the MCU ground. Do not run any signal  
traces or power traces inside the ground pour. Also, if  
using a two-sided board, avoid any traces on the  
other side of the board where the crystal is placed. A  
suggested layout is illustrated in Figure 2-3.  
• “Using MPLAB® REAL ICE™” (poster) DS51749  
2.6  
JTAG  
The TMS, TDO, TDI and TCK pins are used for testing  
and debugging according to the Joint Test Action  
Group (JTAG) standard. It is recommended to keep the  
trace length between the JTAG connector and the  
JTAG pins on the device as short as possible. If the  
JTAG connector is expected to experience an ESD  
event, a series resistor is recommended, with the value  
in the range of a few tens of Ohms, not to exceed 100  
Ohms.  
FIGURE 2-3:  
SUGGESTED PLACEMENT  
OF THE OSCILLATOR  
CIRCUIT  
Oscillator  
Secondary  
Guard Trace  
Guard Ring  
Main Oscillator  
© 2011 Microchip Technology Inc.  
DS61143H-page 33  
PIC32MX3XX/4XX  
2.9  
Configuration of Analog and  
Digital Pins During ICSP  
Operations  
2.10 Unused I/Os  
Unused I/O pins should not be allowed to float as  
inputs. They can be configured as outputs and driven  
to a logic-low state.  
If MPLAB ICD 2, ICD 3 or REAL ICE is selected as a  
debugger, it automatically initializes all of the Analog-  
to-Digital input pins (ANx) as “digital” pins by setting all  
bits in the ADPCFG register.  
Alternately, inputs can be reserved by connecting the  
pin to VSS through a 1k to 10k resistor and configuring  
the pin as an input.  
The bits in this register that correspond to the Analog-  
to-Digital pins that are initialized by MPLAB ICD 2, ICD  
3 or REAL ICE, must not be cleared by the user  
application firmware; otherwise, communication errors  
will result between the debugger and the device.  
If your application needs to use certain Analog-to-  
Digital pins as analog input pins during the debug  
session, the user application must clear the  
corresponding bits in the ADPCFG register during  
initialization of the ADC module.  
When MPLAB ICD 2, ICD 3 or REAL ICE is used as a  
programmer, the user application firmware must  
correctly configure the ADPCFG register. Automatic  
initialization of this register is only done during  
debugger operation. Failure to correctly configure the  
register(s) will result in all Analog-to-Digital pins being  
recognized as analog input pins, resulting in the port  
value being read as a logic ‘0’, which may affect user  
application functionality.  
DS61143H-page 34  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
2.11 Referenced Sources  
This device data sheet is based on the following  
individual chapters of the “PIC32 Family Reference  
Manual”. These documents should be considered as  
the general reference for the operation of a particular  
module or device feature.  
Note 1: To access the documents listed below,  
browse to the documentation section of  
the PIC32MX460F512L product page on  
the  
Microchip  
web  
site  
(www.microchip.com) or select a family  
reference manual section from the  
following list.  
In addition to parameters, features, and  
other documentation, the resulting page  
provides links to the related family  
reference manual sections.  
• Section 1. “Introduction” (DS61127)  
• Section 2. “CPU” (DS61113)  
• Section 3. “Memory Organization” (DS61115)  
• Section 4. “Prefetch Cache” (DS61119)  
• Section 5. “Flash Program Memory” (DS61121)  
• Section 6. “Oscillator Configuration” (DS61112)  
• Section 7. “Resets” (DS61118)  
• Section 8. “Interrupt Controller” (DS61108)  
• Section 9. “Watchdog Timer and Power-up Timer” (DS61114)  
• Section 10. “Power-Saving Features” (DS61130)  
• Section 12. “I/O Ports” (DS61120)  
• Section 13. “Parallel Master Port (PMP)” (DS61128)  
• Section 14. “Timers” (DS61105)  
• Section 15. “Input Capture” (DS61122)  
• Section 16. “Output Compare” (DS61111)  
• Section 17. “10-bit Analog-to-Digital Converter (ADC)” (DS61104)  
• Section 19. “Comparator” (DS61110)  
• Section 20. “Comparator Voltage Reference (CVREF)” (DS61109)  
• Section 21. “Universal Asynchronous Receiver Transmitter (UART)” (DS61107)  
• Section 23. “Serial Peripheral Interface (SPI)” (DS61106)  
• Section 24. “Inter-Integrated Circuit™ (I2C™)” (DS61116)  
• Section 27. “USB On-The-Go (OTG)” (DS61126)  
• Section 29. “Real-Time Clock and Calendar (RTCC)” (DS61125)  
• Section 31. “Direct Memory Access (DMA) Controller” (DS61117)  
• Section 32. “Configuration” (DS61124)  
• Section 33. “Programming and Diagnostics” (DS61129)  
© 2011 Microchip Technology Inc.  
DS61143H-page 35  
PIC32MX3XX/4XX  
NOTES:  
DS61143H-page 36  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
- Atomic interrupt enable/disable  
3.0  
CPU  
- GPR shadow registers to minimize latency  
for interrupt handlers  
Note 1: This data sheet summarizes the features  
of the PIC32MX3XX/4XX family of  
devices. It is not intended to be a compre-  
hensive reference source. To comple-  
ment the information in this data sheet,  
refer to Section 2. “CPU” (DS61113) of  
the “PIC32 Family Reference Manual”,  
which is available from the Microchip web  
- Bit field manipulation instructions  
• MIPS16e® Code Compression  
- 16-bit encoding of 32-bit instructions to  
improve code density  
- Special PC-relative instructions for efficient  
loading of addresses and constants  
site  
(www.microchip.com/PIC32).  
- SAVE & RESTORE macro instructions for  
setting up and tearing down stack frames  
within subroutines  
Resources for the MIPS32® M4K®  
Processor Core are available at:  
www.mips.com/products/cores/  
- Improved support for handling 8 and 16-bit  
data types  
32-64-bit-cores/mips32-m4k/.  
2: Some registers and associated bits  
described in this section may not be avail-  
able on all devices. Refer to Section 4.0  
“Memory Organization” in this data  
sheet for device-specific register and bit  
information.  
• Simple Fixed Mapping Translation (FMT)  
mechanism  
• Simple Dual Bus Interface  
- Independent 32-bit address and data busses  
- Transactions can be aborted to improve  
interrupt latency  
The MIPS32® M4K® Processor Core is the heart of the  
PIC32MX3XX/4XX family processor. The CPU fetches  
instructions, decodes each instruction, fetches source  
operands, executes each instruction and writes the  
results of instruction execution to the proper destina-  
tions.  
• Autonomous Multiply/Divide Unit  
- Maximum issue rate of one 32x16 multiply  
per clock  
- Maximum issue rate of one 32x32 multiply  
every other clock  
- Early-in iterative divide. Minimum 11 and  
maximum 34 clock latency (dividend (rs) sign  
extension-dependent)  
3.1  
Features  
• Power Control  
• 5-stage pipeline  
- Minimum frequency: 0 MHz  
• 32-bit Address and Data Paths  
• MIPS32 Enhanced Architecture (Release 2)  
- Low-Power mode (triggered by WAIT  
instruction)  
- Multiply-Accumulate and Multiply-Subtract  
Instructions  
- Extensive use of local gated clocks  
• EJTAG Debug and Instruction Trace  
- Support for single stepping  
- Targeted Multiply Instruction  
- Zero/One Detect Instructions  
- WAITInstruction  
- Virtual instruction and data address/value  
-
breakpoints  
- Conditional Move Instructions (MOVN, MOVZ)  
- Vectored interrupts  
- PC tracing with trace compression  
- Programmable exception vector base  
®
®
FIGURE 3-1:  
CPU  
MIPS M4K BLOCK DIAGRAM  
Trace I/F  
EJTAG  
MDU  
Trace  
TAP  
Off-Chip  
Debug I/F  
Execution  
Core  
(RF/ALU/Shift)  
FMT  
Bus Interface  
Dual Bus I/F  
System  
Coprocessor  
Power  
Mgmt.  
© 2011 Microchip Technology Inc.  
DS61143H-page 37  
PIC32MX3XX/4XX  
3.2.2  
MULTIPLY/DIVIDE UNIT (MDU)  
3.2  
Architecture Overview  
The MIPS32® M4K® Processor Core includes a multi-  
ply/divide unit (MDU) that contains a separate pipeline  
for multiply and divide operations. This pipeline oper-  
ates in parallel with the integer unit (IU) pipeline and  
does not stall when the IU pipeline stalls. This allows  
MDU operations to be partially masked by system stalls  
and/or other integer unit instructions.  
The MIPS32® M4K® Processor Core contains several  
logic blocks working together in parallel, providing an  
efficient high performance computing engine. The  
following blocks are included with the core:  
• Execution Unit  
• Multiply/Divide Unit (MDU)  
• System Control Coprocessor (CP0)  
• Fixed Mapping Translation (FMT)  
• Dual Internal Bus interfaces  
• Power Management  
The high-performance MDU consists of a 32x16 booth  
recoded multiplier, result/accumulation registers (HI  
and LO), a divide state machine, and the necessary  
multiplexers and control logic. The first number shown  
(‘32’ of 32x16) represents the rs operand. The second  
number (‘16’ of 32x16) represents the rt operand. The  
PIC32MX core only checks the value of the latter (rt)  
operand to determine how many times the operation  
must pass through the multiplier. The 16x16 and 32x16  
operations pass through the multiplier once. A 32x32  
operation passes through the multiplier twice.  
• MIPS16e Support  
• Enhanced JTAG (EJTAG) Controller  
3.2.1  
EXECUTION UNIT  
The MIPS32® M4K® Processor Core execution unit  
implements a load/store architecture with single-cycle  
ALU operations (logical, shift, add, subtract) and an  
autonomous multiply/divide unit. The core contains  
thirty-two 32-bit general purpose registers used for  
integer operations and address calculation. One addi-  
tional register file shadow set (containing thirty-two reg-  
isters) is added to minimize context switching overhead  
during interrupt/exception processing. The register file  
consists of two read ports and one write port and is fully  
bypassed to minimize operation latency in the pipeline.  
The MDU supports execution of one 16x16 or 32x16  
multiply operation every clock cycle; 32x32 multiply  
operations can be issued every other clock cycle.  
Appropriate interlocks are implemented to stall the  
issuance of back-to-back 32x32 multiply operations.  
The multiply operand size is automatically determined  
by logic built into the MDU.  
Divide operations are implemented with a simple 1 bit  
per clock iterative algorithm. An early-in detection  
checks the sign extension of the dividend (rs) operand.  
If rs is 8 bits wide, 23 iterations are skipped. For a 16-  
bit-wide rs, 15 iterations are skipped, and for a 24-bit-  
wide rs, 7 iterations are skipped. Any attempt to issue  
a subsequent MDU instruction while a divide is still  
active causes an IU pipeline stall until the divide  
operation is completed.  
The execution unit includes:  
• 32-bit adder used for calculating the data address  
• Address unit for calculating the next instruction  
address  
• Logic for branch determination and branch target  
address calculation  
• Load aligner  
Table 3-1 lists the repeat rate (peak issue rate of cycles  
until the operation can be reissued) and latency (num-  
ber of cycles until a result is available) for the PIC32MX  
core multiply and divide instructions. The approximate  
latency and repeat rates are listed in terms of pipeline  
clocks.  
• Bypass multiplexers used to avoid stalls when  
executing instructions streams where data  
producing instructions are followed closely by  
consumers of their results  
• Leading Zero/One detect unit for implementing the  
CLZand CLOinstructions  
• Arithmetic Logic Unit (ALU) for performing bitwise  
logical operations  
• Shifter and Store Aligner  
DS61143H-page 38  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
®
®
TABLE 3-1:  
MIPS M4K PROCESSOR CORE HIGH-PERFORMANCE INTEGER  
MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES  
Opcode  
Operand Size (mul rt) (div rs)  
Latency  
Repeat Rate  
MULT/MULTU, MADD/MADDU,  
MSUB/MSUBU  
16 bits  
32 bits  
16 bits  
32 bits  
8 bits  
1
2
1
2
MUL  
2
1
3
2
DIV/DIVU  
12  
19  
26  
33  
11  
18  
25  
32  
16 bits  
24 bits  
32 bits  
The MIPS architecture defines that the result of a mul-  
tiply or divide operation be placed in the HI and LO reg-  
isters. Using the Move-From-HI (MFHI) and Move-  
From-LO (MFLO) instructions, these values can be  
transferred to the general purpose register file.  
the product to the current contents of the HI and LO  
registers. Similarly, the MSUBinstruction multiplies two  
operands and then subtracts the product from the HI  
and LO registers. The MADD and MSUB operations  
are commonly used in DSP algorithms.  
In addition to the HI/LO targeted operations, the  
MIPS32 architecture also defines a multiply instruction,  
MUL, which places the least significant results in the  
primary register file instead of the HI/LO register pair.  
By avoiding the explicit MFLO instruction, required  
when using the LO register, and by supporting multiple  
3.2.3  
SYSTEM CONTROL  
COPROCESSOR (CP0)  
In the MIPS architecture, CP0 is responsible for the vir-  
tual-to-physical address translation, the exception con-  
trol system, the processor’s diagnostics capability, the  
operating modes (kernel, user and debug), and  
whether interrupts are enabled or disabled. Configura-  
tion information, such as presence of options like  
MIPS16e, is also available by accessing the CP0  
registers, listed in Table 3-2.  
destination  
registers,  
the  
throughput  
of  
multiply-intensive operations is increased.  
Two other instructions, multiply-add (MADD) and multi-  
ply-subtract (MSUB), are used to perform the multiply-  
accumulate and multiply-subtract operations. The  
MADDinstruction multiplies two numbers and then adds  
TABLE 3-2:  
COPROCESSOR 0 REGISTERS  
Register Register  
Number Name  
Function  
0-6  
7
Reserved  
HWREna  
BadVAddr(1)  
Count(1)  
Reserved  
Compare(1)  
Status(1)  
IntCtl(1)  
SRSCtl(1)  
SRSMap(1)  
Cause(1)  
EPC(1)  
Reserved  
Enables access via the RDHWRinstruction to selected hardware registers  
Reports the address for the most recent address-related exception  
Processor cycle count  
8
9
10  
11  
12  
12  
12  
12  
13  
14  
15  
15  
16  
16  
16  
16  
Reserved  
Timer interrupt control  
Processor status and control  
Interrupt system status and control  
Shadow register set status and control  
Provides mapping from vectored interrupt to a shadow set  
Cause of last general exception  
Program counter at last exception  
Processor identification and revision  
Exception vector base register  
PRId  
EBASE  
Config  
Configuration register  
Config1  
Configuration register 1  
Config2  
Configuration register 2  
Config3  
Configuration register 3  
© 2011 Microchip Technology Inc.  
DS61143H-page 39  
PIC32MX3XX/4XX  
TABLE 3-2:  
COPROCESSOR 0 REGISTERS (CONTINUED)  
Register Register  
Number Name  
Function  
17-22  
23  
Reserved  
Debug(2)  
DEPC(2)  
Reserved  
Debug control and exception status  
Program counter at last debug exception  
Reserved  
24  
25-29  
30  
Reserved  
ErrorEPC(1)  
DESAVE(2)  
Program counter at last error  
Debug handler scratchpad register  
31  
Note 1: Registers used in exception processing.  
2: Registers used during debug.  
Coprocessor 0 also contains the logic for identifying  
and managing exceptions. Exceptions can be caused  
by a variety of sources, including alignment errors in  
data, external events or program errors. Table 3-3  
shows the exception types in order of priority.  
TABLE 3-3:  
Exception  
Reset  
PIC32MX3XX/4XX FAMILY CORE EXCEPTION TYPES  
Description  
Assertion MCLR or a Power-on Reset (POR)  
DSS  
EJTAG Debug Single Step  
DINT  
EJTAG Debug Interrupt. Caused by the assertion of the external EJ_DINT input, or by setting the  
EjtagBrk bit in the ECR register  
NMI  
Interrupt  
DIB  
Assertion of NMI signal  
Assertion of unmasked hardware or software interrupt signal  
EJTAG debug hardware instruction break matched  
AdEL  
Fetch address alignment error  
Fetch reference to protected address  
IBE  
DBp  
Sys  
Bp  
Instruction fetch bus error  
EJTAG Breakpoint (execution of SDBBPinstruction)  
Execution of SYSCALLinstruction  
Execution of BREAKinstruction  
RI  
Execution of a Reserved Instruction  
CpU  
CEU  
Ov  
Execution of a coprocessor instruction for a coprocessor that is not enabled  
Execution of a CorExtendinstruction when CorExtendis not enabled  
Execution of an arithmetic instruction that overflowed  
Execution of a trap (when trap condition is true)  
Tr  
DDBL/DDBS EJTAG Data Address Break (address only) or EJTAG Data Value Break on Store (address + value)  
AdEL  
Load address alignment error  
Load reference to protected address  
AdES  
Store address alignment error  
Store to protected address  
DBE  
Load or store bus error  
DDBL  
EJTAG data hardware breakpoint matched in load data compare  
DS61143H-page 40  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
3.3  
Power Management  
3.4  
EJTAG Debug Support  
The MIPS32® M4K® Processor Core offers a number  
of power management features, including low-power  
design, active power management and power-down  
modes of operation. The core is a static design that  
supports slowing or halting the clocks, which reduces  
system power consumption during idle periods.  
The MIPS32® M4K® Processor Core provides for an  
Enhanced JTAG (EJTAG) interface for use in the  
software debug of application and kernel code. In  
addition to standard user mode and kernel modes of  
operation, the core provides a Debug mode that is  
entered after a debug exception (derived from a  
hardware breakpoint, single-step exception, etc.) is  
taken and continues until a debug exception return  
(DERET) instruction is executed. During this time, the  
processor executes the debug exception handler  
routine.  
3.3.1  
INSTRUCTION-CONTROLLED  
POWER MANAGEMENT  
The mechanism for invoking power-down mode is  
through execution of the WAIT instruction. For more  
information on power management, see Section 25.0  
“Power-Saving Features”.  
The EJTAG interface operates through the Test Access  
Port (TAP), a serial communication port used for  
transferring test data in and out of the core. In addition  
to the standard JTAG instructions, special instructions  
defined in the EJTAG specification define what  
registers are selected and how they are used.  
3.3.2  
LOCAL CLOCK GATING  
The majority of the power consumed by the  
PIC32MX3XX/4XX family core is in the clock tree and  
clocking registers. The PIC32MX family uses extensive  
use of local gated-clocks to reduce this dynamic power  
consumption.  
© 2011 Microchip Technology Inc.  
DS61143H-page 41  
PIC32MX3XX/4XX  
NOTES:  
DS61143H-page 42  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
4.1  
Key Features  
4.0  
MEMORY ORGANIZATION  
• 32-bit native data width  
Note 1: This data sheet summarizes the features  
of the PIC32MX3XX/4XX family of  
devices. It is not intended to be a  
comprehensive reference source. To  
complement the information in this data  
sheet, refer to Section 3. “Memory  
Organization” (DS61115) of the “PIC32  
Family Reference Manual”, which is  
available from the Microchip web site  
(www.microchip.com/PIC32).  
• Separate User and Kernel mode address space  
• Flexible program Flash memory partitioning  
• Flexible data RAM partitioning for data and  
program space  
• Separate boot Flash memory for protected code  
• Robust bus exception handling to intercept  
runaway code  
• Simple memory mapping with Fixed Mapping  
Translation (FMT) unit  
PIC32MX3XX/4XX microcontrollers provide 4 GB of  
unified virtual memory address space. All memory  
regions including program, data memory, SFRs and  
Configuration registers reside in this address space at  
their respective unique addresses. The program and  
data memories can be optionally partitioned into user  
and kernel memories. In addition, the data memory can  
be made executable, allowing PIC32MX3XX/4XX to  
execute from data memory.  
• Cacheable and non-cacheable address regions  
4.2  
PIC32MX3XX/4XX Memory Layout  
PIC32MX3XX/4XX microcontrollers implement two  
address spaces: Virtual and Physical. All hardware  
resources such as program memory, data memory and  
peripherals are located at their respective physical  
addresses. Virtual addresses are exclusively used by  
the CPU to fetch and execute instructions as well as  
access peripherals. Physical addresses are used by  
peripherals such as DMA and Flash controller that  
access memory independently of CPU.  
© 2011 Microchip Technology Inc.  
DS61143H-page 43  
PIC32MX3XX/4XX  
FIGURE 4-1:  
MEMORY MAP ON RESET FOR PIC32MX320F032H AND PIC32MX420F032H  
DEVICES  
(1)  
Virtual  
Physical  
Memory Map  
Memory Map  
0xFFFFFFFF  
0xBFC03000  
0xBFC02FFF  
0xFFFFFFFF  
Reserved  
Device  
Configuration  
Registers  
0xBFC02FF0  
0xBFC02FEF  
Boot Flash  
Reserved  
SFRs  
0xBFC00000  
0xBF900000  
0xBF8FFFFF  
Reserved  
0xBF800000  
Reserved  
Program Flash(2)  
Reserved  
RAM(2)  
0xBD008000  
0xBD007FFF  
0xBD000000  
0xA0002000  
0xA0001FFF  
0xA0000000  
0x1FC03000  
0x1FC02FFF  
Device  
Configuration  
Registers  
Reserved  
0x9FC03000  
0x9FC02FFF  
Device  
Configuration  
Registers  
0x1FC02FF0  
0x1FC02FEF  
0x9FC02FEF  
0x9FC02FEF  
Boot Flash  
Reserved  
SFRs  
0x1FC00000  
Boot Flash  
Reserved  
0x9FC00000  
0x1F900000  
0x1F8FFFFF  
0x9D008000  
0x9D007FFF  
0x1F800000  
Program Flash(2)  
Reserved  
Reserved  
0x9D000000  
0x1D008000  
0x1D007FFF  
0x80002000  
0x80001FFF  
Program Flash(2)  
0x1D000000  
RAM(2)  
Reserved  
RAM(2)  
0x80000000  
0x00000000  
0x00002000  
0x00001FFF  
0x00000000  
Reserved  
Note 1: Memory areas are not shown to scale.  
2: The size of this memory region is programmable (see Section 3. “Memory Organization”  
(DS61115)) and can be changed by initialization code provided by end-user development  
tools (refer to the specific development tool documentation for information).  
DS61143H-page 44  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
(1)  
FIGURE 4-2:  
MEMORY MAP ON RESET FOR PIC32MX320F064H DEVICE  
Virtual  
Physical  
Memory Map  
Memory Map  
0xFFFFFFFF  
0xBFC03000  
0xBFC02FFF  
0xFFFFFFFF  
Reserved  
Device  
Configuration  
Registers  
0xBFC02FF0  
0xBFC02FEF  
Boot Flash  
Reserved  
SFRs  
0xBFC00000  
0xBF900000  
0xBF8FFFFF  
Reserved  
0xBF800000  
Reserved  
Program Flash(2)  
Reserved  
RAM(2)  
0xBD010000  
0xBD00FFFF  
0xBD000000  
0xA0004000  
0xA0003FFF  
0xA0000000  
0x1FC03000  
0x1FC02FFF  
Device  
Configuration  
Registers  
Reserved  
0x9FC03000  
0x9FC02FFF  
Device  
Configuration  
Registers  
0x1FC02FF0  
0x1FC02FEF  
0x9FC02FEF  
0x9FC02FEF  
Boot Flash  
Reserved  
SFRs  
0x1FC00000  
Boot Flash  
Reserved  
0x9FC00000  
0x1F900000  
0x1F8FFFFF  
0x9D010000  
0x9D00FFFF  
0x1F800000  
Program Flash(2)  
Reserved  
Reserved  
0x9D000000  
0x1D010000  
0x1D00FFFF  
0x80004000  
0x80003FFF  
Program Flash(2)  
0x1D000000  
RAM(2)  
Reserved  
RAM(2)  
0x80000000  
0x00000000  
0x00004000  
0x00003FFF  
0x00000000  
Reserved  
Note 1: Memory areas are not shown to scale.  
2: The size of this memory region is programmable (see Section 3. “Memory Organization”  
(DS61115)) and can be changed by initialization code provided by end-user development  
tools (refer to the specific development tool documentation for information).  
© 2011 Microchip Technology Inc.  
DS61143H-page 45  
PIC32MX3XX/4XX  
FIGURE 4-3:  
MEMORY MAP ON RESET FOR PIC32MX320F128H AND PIC32MX320F128L  
DEVICES  
(1)  
Virtual  
Physical  
Memory Map  
Memory Map  
0xFFFFFFFF  
0xBFC03000  
0xBFC02FFF  
0xFFFFFFFF  
Reserved  
Device  
Configuration  
Registers  
0xBFC02FF0  
0xBFC02FEF  
Boot Flash  
Reserved  
SFRs  
0xBFC00000  
0xBF900000  
0xBF8FFFFF  
Reserved  
0xBF800000  
Reserved  
Program Flash(2)  
Reserved  
RAM(2)  
0xBD020000  
0xBD01FFFF  
0xBD000000  
0xA0004000  
0xA0003FFF  
0xA0000000  
0x1FC03000  
0x1FC02FFF  
Device  
Configuration  
Registers  
Reserved  
0x9FC03000  
0x9FC02FFF  
Device  
Configuration  
Registers  
0x1FC02FF0  
0x1FC02FEF  
0x9FC02FEF  
0x9FC02FEF  
Boot Flash  
Reserved  
SFRs  
0x1FC00000  
Boot Flash  
Reserved  
0x9FC00000  
0x1F900000  
0x1F8FFFFF  
0x9D020000  
0x9D01FFFF  
0x1F800000  
Program Flash(2)  
Reserved  
Reserved  
0x9D000000  
0x1D020000  
0x1D01FFFF  
0x80004000  
0x80003FFF  
Program Flash(2)  
0x1D000000  
RAM(2)  
Reserved  
RAM(2)  
0x80000000  
0x00000000  
0x00004000  
0x00003FFF  
0x00000000  
Reserved  
Note 1: Memory areas are not shown to scale.  
2: The size of this memory region is programmable (see Section 3. “Memory Organization”  
(DS61115)) and can be changed by initialization code provided by end-user development  
tools (refer to the specific development tool documentation for information).  
DS61143H-page 46  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
FIGURE 4-4:  
MEMORY MAP ON RESET FOR PIC32MX340F128H, PIC32MX340F128L,  
PIC32MX440F128H AND PIC32MX440F128L DEVICES  
(1)  
Virtual  
Physical  
Memory Map  
Memory Map  
0xFFFFFFFF  
0xBFC03000  
0xBFC02FFF  
0xFFFFFFFF  
Reserved  
Device  
Configuration  
Registers  
0xBFC02FF0  
0xBFC02FEF  
Boot Flash  
Reserved  
SFRs  
0xBFC00000  
0xBF900000  
0xBF8FFFFF  
Reserved  
0xBF800000  
Reserved  
Program Flash(2)  
Reserved  
RAM(2)  
0xBD020000  
0xBD01FFFF  
0xBD000000  
0xA0008000  
0xA0007FFF  
0xA0000000  
0x1FC03000  
0x1FC02FFF  
Device  
Configuration  
Registers  
Reserved  
0x9FC03000  
0x9FC02FFF  
Device  
Configuration  
Registers  
0x1FC02FF0  
0x1FC02FEF  
0x9FC02FEF  
0x9FC02FEF  
Boot Flash  
Reserved  
SFRs  
0x1FC00000  
Boot Flash  
Reserved  
0x9FC00000  
0x1F900000  
0x1F8FFFFF  
0x9D020000  
0x9D01FFFF  
0x1F800000  
Program Flash(2)  
Reserved  
Reserved  
0x9D000000  
0x1D020000  
0x1D01FFFF  
0x80008000  
0x80007FFF  
Program Flash(2)  
0x1D000000  
RAM(2)  
Reserved  
RAM(2)  
0x80000000  
0x00000000  
0x00008000  
0x00007FFF  
0x00000000  
Reserved  
Note 1: Memory areas are not shown to scale.  
2: The size of this memory region is programmable (see Section 3. “Memory Organization”  
(DS61115)) and can be changed by initialization code provided by end-user development  
tools (refer to the specific development tool documentation for information).  
© 2011 Microchip Technology Inc.  
DS61143H-page 47  
PIC32MX3XX/4XX  
FIGURE 4-5:  
MEMORY MAP ON RESET FOR PIC32MX340F256H, PIC32MX360F256L,  
PIC32MX440F256H AND PIC32MX460F256L DEVICES  
(1)  
Virtual  
Physical  
Memory Map  
Memory Map  
0xFFFFFFFF  
0xBFC03000  
0xBFC02FFF  
0xFFFFFFFF  
Reserved  
Device  
Configuration  
Registers  
0xBFC02FF0  
0xBFC02FEF  
Boot Flash  
Reserved  
SFRs  
0xBFC00000  
0xBF900000  
0xBF8FFFFF  
Reserved  
0xBF800000  
Reserved  
Program Flash(2)  
Reserved  
RAM(2)  
0xBD040000  
0xBD03FFFF  
0xBD000000  
0xA0008000  
0xA0007FFF  
0xA0000000  
0x1FC03000  
0x1FC02FFF  
Device  
Configuration  
Registers  
Reserved  
0x9FC03000  
0x9FC02FFF  
Device  
Configuration  
Registers  
0x1FC02FF0  
0x1FC02FEF  
0x9FC02FEF  
0x9FC02FEF  
Boot Flash  
Reserved  
SFRs  
0x1FC00000  
Boot Flash  
Reserved  
0x9FC00000  
0x1F900000  
0x1F8FFFFF  
0x9D040000  
0x9D03FFFF  
0x1F800000  
Program Flash(2)  
Reserved  
Reserved  
0x9D000000  
0x1D040000  
0x1D03FFFF  
0x80008000  
0x80007FFF  
Program Flash(2)  
0x1D000000  
RAM(2)  
Reserved  
RAM(2)  
0x80000000  
0x00000000  
0x00008000  
0x00007FFF  
0x00000000  
Reserved  
Note 1: Memory areas are not shown to scale.  
2: The size of this memory region is programmable (see Section 3. “Memory Organization”  
(DS61115)) and can be changed by initialization code provided by end-user development  
tools (refer to the specific development tool documentation for information).  
DS61143H-page 48  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
FIGURE 4-6:  
MEMORY MAP ON RESET FOR PIC32MX340F512H, PIC32MX360F512L,  
PIC32MX440F512H AND PIC32MX460F512L DEVICES  
(1)  
Virtual  
Physical  
Memory Map  
Memory Map  
0xFFFFFFFF  
0xBFC03000  
0xBFC02FFF  
0xFFFFFFFF  
Reserved  
Device  
Configuration  
Registers  
0xBFC02FF0  
0xBFC02FEF  
Boot Flash  
Reserved  
SFRs  
0xBFC00000  
0xBF900000  
0xBF8FFFFF  
Reserved  
0xBF800000  
Reserved  
Program Flash(2)  
Reserved  
RAM(2)  
0xBD080000  
0xBD07FFFF  
0xBD000000  
0xA0008000  
0xA0007FFF  
0xA0000000  
0x1FC03000  
0x1FC02FFF  
Device  
Configuration  
Registers  
Reserved  
0x9FC03000  
0x9FC02FFF  
Device  
Configuration  
Registers  
0x1FC02FF0  
0x1FC02FEF  
0x9FC02FEF  
0x9FC02FEF  
Boot Flash  
Reserved  
SFRs  
0x1FC00000  
Boot Flash  
Reserved  
0x9FC00000  
0x1F900000  
0x1F8FFFFF  
0x9D080000  
0x9D07FFFF  
0x1F800000  
Program Flash(2)  
Reserved  
Reserved  
0x9D000000  
0x1D080000  
0x1D07FFFF  
0x80008000  
0x80007FFF  
Program Flash(2)  
0x1D000000  
RAM(2)  
Reserved  
RAM(2)  
0x80000000  
0x00000000  
0x00008000  
0x00007FFF  
0x00000000  
Reserved  
Note 1: Memory areas are not shown to scale.  
2: The size of this memory region is programmable (see Section 3. “Memory Organization”  
(DS61115)) and can be changed by initialization code provided by end-user development  
tools (refer to the specific development tool documentation for information).  
© 2011 Microchip Technology Inc.  
DS61143H-page 49  
TABLE 4-1:  
BUS MATRIX REGISTERS MAP  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BMXCHEDMA  
—
—
—
—
—
—
—
—
—
—
BMXWSDRM  
—
—
—
—
BMXERRIXI BMXERRICD BMXERRDMA BMXERRDS BMXERRIS 001F  
BMX  
2000  
CON(1)  
—
—
—
—
—
—
BMXARB<2:0>  
—
0042  
0000  
0000  
0000  
0000  
0000  
0000  
xxxx  
xxxx  
0000  
0000  
xxxx  
xxxx  
0000  
3000  
31:16  
15:0  
—
—
—
—
—
—
BMX  
2010  
DKPBA(1)  
BMXDKPBA<15:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BMX  
2020  
DUDBA(1)  
BMXDUDBA<15:0>  
31:16  
15:0  
—
—
BMX  
2030  
DUPBA(1)  
BMXDUPBA<15:0>  
31:16  
15:0  
BMX  
2040  
BMXDRMSZ<31:0>  
DRMSZ  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
BMXPUPBA<19:16>  
BMX  
2050  
PUPBA(1)  
BMXPUPBA<15:0>  
31:16  
15:0  
BMX  
2060  
BMXPFMSZ<31:0>  
PFMSZ  
31:16  
15:0  
BMX  
2070  
BMXBOOTSZ<31:0>  
BOOTSZ  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
This register has corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.  
(1)  
TABLE 4-2:  
INTERRUPT REGISTERS MAP FOR PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
MVEC  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT4EP  
—
—
INT3EP  
—
—
INT2EP  
—
—
INT1EP  
—
SS0  
0000  
1000 INTCON  
1010 INTSTAT(2)  
TPC<2:0>  
—
INT0EP 0000  
31:16  
15:0  
—
0000  
0000  
0000  
0000  
0000  
0000  
—
SRIPL<2:0>  
VEC<5:0>  
31:16  
15:0  
1020  
1030  
1040  
1060  
1070  
1090  
10A0  
10B0  
10C0  
10D0  
10E0  
10F0  
1100  
1110  
1120  
1140  
IPTMR  
IFS0  
IFS1  
IEC0  
IEC1  
IPC0  
IPC1  
IPC2  
IPC3  
IPC4  
IPC5  
IPC6  
IPC7  
IPC8  
IPC9  
IPC11  
IPTMR<31:0>  
SPI1RXIF SPI1TXIF SPI1EIF  
31:16 I2C1MIF  
I2C1SIF  
I2C1BIF  
U1TXIF  
T3IF  
U1RXIF  
INT2IF  
U1EIF  
OC2IF  
—
OC5IF  
OC1IF  
—
IC5IF  
IC1IF  
—
T5IF  
T1IF  
INT4IF  
INT0IF  
OC4IF  
CS1IF  
IC4IF  
CS0IF  
DMA1IF  
AD1IF  
IC4IE  
T4IF  
CTIF  
15:0  
INT3IF  
—
OC3IF  
IC3IF  
IC2IF  
USBIF  
U2RXIF  
T2IF  
INT1IF  
—
31:16  
—
FSCMIF  
I2C1SIE  
OC3IE  
—
—
—
—
FCEIF  
U2EIF  
—
DMA3IF  
DMA2IF  
PMPIF  
OC4IE  
CS1IE  
DMA0IF 0000  
15:0 RTCCIF  
31:16 I2C1MIE  
I2C2MIF  
I2C2SIF  
U1TXIE  
T3IE  
I2C2BIF  
U2TXIF  
U1EIE  
OC2IE  
—
SPI2RXIF SPI2TXIF SPI2EIF  
CMP2IF  
T5IE  
T1IE  
—
CMP1IF  
CNIF  
T4IE  
CTIE  
0000  
0000  
0000  
I2C1BIE  
IC3IE  
—
U1RXIE  
SPI1RXIE SPI1TXIE SPI1EIE  
OC5IE  
OC1IE  
—
IC5IE  
IC1IE  
—
INT4IE  
15:0  
INT3IE  
—
INT2IE  
IC2IE  
USBIE  
U2RXIE  
T2IE  
INT1IE  
—
INT0IE  
CS0IE  
DMA1IE  
AD1IE  
31:16  
—
—
FCEIE  
U2EIE  
DMA3IE  
DMA2IE  
PMPIE  
DMA0IE 0000  
CNIE  
15:0 RTCCIE  
FSCMIE  
—
I2C2MIE  
—
I2C2SIE  
I2C2BIE  
U2TXIE  
SPI2RXIE SPI2TXIE SPI2EIE  
CMP2IE  
CMP1IE  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT0IP<2:0>  
CS0IP<2:0>  
INT1IP<2:0>  
IC1IP<2:0>  
INT2IP<2:0>  
IC2IP<2:0>  
INT3IP<2:0>  
IC3IP<2:0>  
INT4IP<2:0>  
IC4IP<2:0>  
SPI1IP<2:0>  
IC5IP<2:0>  
AD1IP<2:0>  
I2C1IP<2:0>  
SPI2IP<2:0>  
CMP1IP<2:0>  
RTCCIP<2:0>  
I2C2IP<2:0>  
DMA3IP<2:0>  
DMA1IP<2:0>  
—
INT0IS<1:0>  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CS1IP<2:0>  
CTIP<2:0>  
OC1IP<2:0>  
T1IP<2:0>  
OC2IP<2:0>  
T2IP<2:0>  
OC3IP<2:0>  
T3IP<2:0>  
OC4IP<2:0>  
T4IP<2:0>  
OC5IP<2:0>  
T5IP<2:0>  
CNIP<2:0>  
U1IP<2:0>  
CMP2IP<2:0>  
PMPIP<2:0>  
FSCMIP<2:0>  
U2IP<2:0>  
DMA2IP<2:0>  
DMA0IP<2:0>  
—
CS1IS<1:0>  
—
—
CS0IS<1:0>  
INT1IS<1:0>  
IC1IS<1:0>  
CTIS<1:0>  
OC1IS<1:0>  
T1IS<1:0>  
31:16  
15:0  
—
—
—
—
31:16  
15:0  
—
—
INT2IS<1:0>  
IC2IS<1:0>  
OC2IS<1:0>  
T2IS<1:0>  
—
—
31:16  
15:0  
—
—
INT3IS<1:0>  
IC3IS<1:0>  
OC3IS<1:0>  
T3IS<1:0>  
—
—
31:16  
15:0  
—
—
INT4IS<1:0>  
IC4IS<1:0>  
OC4IS<1:0>  
T4IS<1:0>  
—
—
31:16  
15:0  
—
—
SPI1IS<1:0>  
IC5IS<1:0>  
OC5IS<1:0>  
T5IS<1:0>  
—
—
31:16  
15:0  
—
—
AD1IS<1:0>  
I2C1IS<1:0>  
SPI2IS<1:0>  
CMP1IS<1:0>  
RTCCIS<1:0>  
I2C2IS<1:0>  
DMA3IS<1:0>  
DMA1IS<1:0>  
CNIS<1:0>  
U1IS<1:0>  
—
—
31:16  
15:0  
—
—
CMP2IS<1:0>  
PMPIS<1:0>  
FSCMIS<1:0>  
U2IS<1:0>  
—
—
31:16  
15:0  
—
—
—
—
31:16  
15:0  
—
—
DMA2IS<1:0>  
DMA0IS<1:0>  
—
—
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
USBIP<2:0>  
USBIS<1:0>  
FCEIP<2:0>  
FCEIS<1:0>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
Except where noted, all registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV  
Registers” for more information.  
2:  
This register does not have associated CLR, SET, and INV registers.  
TABLE 4-3:  
INTERRUPT REGISTERS MAP FOR PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX340F128L,  
PIC32MX360F256L AND PIC32MX360F512L DEVICES ONLY  
(1)  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
MVEC  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT4EP  
—
—
INT3EP  
—
—
INT2EP  
—
—
INT1EP  
—
SS0  
0000  
1000 INTCON  
1010 INTSTAT(2)  
TPC<2:0>  
—
INT0EP 0000  
31:16  
15:0  
—
0000  
0000  
0000  
0000  
0000  
0000  
—
SRIPL<2:0>  
VEC<5:0>  
31:16  
15:0  
1020  
1030  
1040  
1060  
1070  
1090  
10A0  
10B0  
10C0  
10D0  
10E0  
10F0  
1100  
1110  
1120  
1140  
IPTMR  
IFS0  
IFS1  
IEC0  
IEC1  
IPC0  
IPC1  
IPC2  
IPC3  
IPC4  
IPC5  
IPC6  
IPC7  
IPC8  
IPC9  
IPC11  
IPTMR<31:0>  
31:16 I2C1MIF  
I2C1SIF  
I2C1BIF  
U1TXIF  
T3IF  
—
U1RXIF  
INT2IF  
U1EIF  
OC2IF  
—
SPI1RXIF SPI1TXIF SPI1EIF  
OC5IF  
OC1IF  
—
IC5IF  
IC1IF  
—
T5IF  
T1IF  
INT4IF  
INT0IF  
OC4IF  
CS1IF  
IC4IF  
CS0IF  
DMA1IF  
AD1IF  
IC4IE  
T4IF  
CTIF  
15:0  
INT3IF  
—
OC3IF  
IC3IF  
IC2IF  
—
T2IF  
INT1IF  
—
31:16  
—
FSCMIF  
I2C1SIE  
OC3IE  
—
—
—
FCEIF  
U2EIF  
—
DMA3IF  
DMA2IF  
PMPIF  
OC4IE  
CS1IE  
DMA0IF 0000  
15:0 RTCCIF  
31:16 I2C1MIE  
I2C2MIF  
I2C2SIF  
U1TXIE  
T3IE  
—
I2C2BIF  
U2TXIF  
U1EIE  
OC2IE  
—
U2RXIF  
SPI2RXIF SPI2TXIF SPI2EIF  
CMP2IF  
T5IE  
T1IE  
—
CMP1IF  
CNIF  
T4IE  
CTIE  
0000  
0000  
0000  
I2C1BIE  
IC3IE  
—
U1RXIE  
SPI1RXIE SPI1TXIE SPI1EIE  
OC5IE  
OC1IE  
—
IC5IE  
IC1IE  
—
INT4IE  
15:0  
INT3IE  
—
INT2IE  
IC2IE  
—
T2IE  
FCEIE  
—
INT1IE  
—
INT0IE  
CS0IE  
DMA1IE  
AD1IE  
31:16  
—
DMA3IE  
DMA2IE  
PMPIE  
DMA0IE 0000  
CNIE  
15:0 RTCCIE  
FSCMIE  
—
I2C2MIE  
—
—
—
—
—
SPI2RXIE SPI2TXIE SPI2EIE  
CMP2IE  
CMP1IE  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT0IP<2:0>  
CS0IP<2:0>  
INT1IP<2:0>  
IC1IP<2:0>  
INT2IP<2:0>  
IC2IP<2:0>  
INT3IP<2:0>  
IC3IP<2:0>  
INT4IP<2:0>  
IC4IP<2:0>  
SPI1IP<2:0>  
IC5IP<2:0>  
AD1IP<2:0>  
I2C1IP<2:0>  
SPI2IP<2:0>  
CMP1IP<2:0>  
RTCCIP<2:0>  
I2C2IP<2:0>  
DMA3IP<2:0>  
DMA1IP<2:0>  
—
INT0IS<1:0>  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CS1IP<2:0>  
CTIP<2:0>  
OC1IP<2:0>  
T1IP<2:0>  
OC2IP<2:0>  
T2IP<2:0>  
OC3IP<2:0>  
T3IP<2:0>  
OC4IP<2:0>  
T4IP<2:0>  
OC5IP<2:0>  
T5IP<2:0>  
CNIP<2:0>  
U1IP<2:0>  
CMP2IP<2:0>  
PMPIP<2:0>  
FSCMIP<2:0>  
U2IP<2:0>  
DMA2IP<2:0>  
DMA0IP<2:0>  
—
CS1IS<1:0>  
—
—
CS0IS<1:0>  
INT1IS<1:0>  
IC1IS<1:0>  
CTIS<1:0>  
OC1IS<1:0>  
T1IS<1:0>  
31:16  
15:0  
—
—
—
—
31:16  
15:0  
—
—
INT2IS<1:0>  
IC2IS<1:0>  
OC2IS<1:0>  
T2IS<1:0>  
—
—
31:16  
15:0  
—
—
INT3IS<1:0>  
IC3IS<1:0>  
OC3IS<1:0>  
T3IS<1:0>  
—
—
31:16  
15:0  
—
—
INT4IS<1:0>  
IC4IS<1:0>  
OC4IS<1:0>  
T4IS<1:0>  
—
—
31:16  
15:0  
—
—
SPI1IS<1:0>  
IC5IS<1:0>  
OC5IS<1:0>  
T5IS<1:0>  
—
—
31:16  
15:0  
—
—
AD1IS<1:0>  
I2C1IS<1:0>  
SPI2IS<1:0>  
CMP1IS<1:0>  
RTCCIS<1:0>  
I2C2IS<1:0>  
DMA3IS<1:0>  
DMA1IS<1:0>  
CNIS<1:0>  
U1IS<1:0>  
—
—
31:16  
15:0  
—
—
CMP2IS<1:0>  
PMPIS<1:0>  
FSCMIS<1:0>  
U2IS<1:0>  
—
—
31:16  
15:0  
—
—
—
—
31:16  
15:0  
—
—
DMA2IS<1:0>  
DMA0IS<1:0>  
—
—
31:16  
—
—
—
—
—
—
—
—
—
—
—
—
15:0  
—
—
—
—
—
FCEIP<2:0>  
FCEIS<1:0>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV  
Registers” for more information.  
2:  
This register does not have associated CLR, SET, and INV registers.  
TABLE 4-4:  
INTERRUPT REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H AND PIC32MX320F128L  
DEVICES ONLY  
(1)  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
MVEC  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT4EP  
—
—
INT3EP  
—
—
INT2EP  
—
—
INT1EP  
—
SS0  
0000  
1000 INTCON  
1010 INTSTAT(2)  
TPC<2:0>  
—
INT0EP 0000  
31:16  
15:0  
—
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
—
SRIPL<2:0>  
VEC<5:0>  
31:16  
15:0  
1020  
1030  
1040  
1060  
1070  
1090  
10A0  
10B0  
10C0  
10D0  
10E0  
10F0  
1100  
1110  
1140  
IPTMR  
IFS0  
IFS1  
IEC0  
IEC1  
IPC0  
IPC1  
IPC2  
IPC3  
IPC4  
IPC5  
IPC6  
IPC7  
IPC8  
IPC11  
IPTMR<31:0>  
SPI1RXIF SPI1TXIF SPI1EIF  
31:16 I2C1MIF  
I2C1SIF  
I2C1BIF  
U1TXIF  
T3IF  
—
U1RXIF  
INT2IF  
U1EIF  
OC2IF  
—
OC5IF  
OC1IF  
—
IC5IF  
IC1IF  
—
T5IF  
T1IF  
INT4IF  
INT0IF  
OC4IF  
CS1IF  
—
IC4IF  
CS0IF  
—
T4IF  
CTIF  
—
15:0  
INT3IF  
—
OC3IF  
IC3IF  
IC2IF  
—
T2IF  
INT1IF  
—
31:16  
—
—
—
FCEIF  
U2EIF  
—
—
15:0 RTCCIF  
31:16 I2C1MIE  
FSCMIF  
I2C2MIF  
I2C2SIF  
U1TXIE  
T3IE  
—
I2C2BIF  
U2TXIF  
U1EIE  
OC2IE  
—
U2RXIF  
SPI2RXIF SPI2TXIF SPI2EIF  
CMP2IF  
T5IE  
T1IE  
—
CMP1IF  
PMPIF  
OC4IE  
CS1IE  
—
AD1IF  
IC4IE  
CS0IE  
—
CNIF  
T4IE  
CTIE  
—
I2C1SIE  
OC3IE  
—
I2C1BIE  
IC3IE  
—
U1RXIE  
SPI1RXIE SPI1TXIE SPI1EIE  
OC5IE  
OC1IE  
—
IC5IE  
IC1IE  
—
INT4IE  
15:0  
INT3IE  
—
INT2IE  
IC2IE  
—
T2IE  
FCEIE  
—
INT1IE  
—
INT0IE  
31:16  
—
—
15:0 RTCCIE  
FSCMIE  
—
I2C2MIE  
—
—
—
—
—
SPI2RXIE SPI2TXIE SPI2EIE  
CMP2IE  
CMP1IE  
PMPIE  
AD1IE  
CNIE  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT0IP<2:0>  
CS0IP<2:0>  
INT1IP<2:0>  
IC1IP<2:0>  
INT2IP<2:0>  
IC2IP<2:0>  
INT3IP<2:0>  
IC3IP<2:0>  
INT4IP<2:0>  
IC4IP<2:0>  
SPI1IP<2:0>  
IC5IP<2:0>  
AD1IP<2:0>  
I2C1IP<2:0>  
SPI2IP<2:0>  
CMP1IP<2:0>  
RTCCIP<2:0>  
I2C2IP<2:0>  
—
INT0IS<1:0>  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CS1IP<2:0>  
CTIP<2:0>  
OC1IP<2:0>  
T1IP<2:0>  
OC2IP<2:0>  
T2IP<2:0>  
OC3IP<2:0>  
T3IP<2:0>  
OC4IP<2:0>  
T4IP<2:0>  
OC5IP<2:0>  
T5IP<2:0>  
CNIP<2:0>  
U1IP<2:0>  
CMP2IP<2:0>  
PMPIP<2:0>  
FSCMIP<2:0>  
U2IP<2:0>  
—
CS1IS<1:0>  
—
—
CS0IS<1:0>  
INT1IS<1:0>  
IC1IS<1:0>  
INT2IS<1:0>  
IC2IS<1:0>  
INT3IS<1:0>  
IC3IS<1:0>  
INT4IS<1:0>  
IC4IS<1:0>  
SPI1IS<1:0>  
IC5IS<1:0>  
AD1IS<1:0>  
I2C1IS<1:0>  
SPI2IS<1:0>  
CMP1IS<1:0>  
RTCCIS<1:0>  
I2C2IS<1:0>  
CTIS<1:0>  
OC1IS<1:0>  
T1IS<1:0>  
31:16  
15:0  
—
—
—
—
31:16  
15:0  
—
—
OC2IS<1:0>  
T2IS<1:0>  
—
—
31:16  
15:0  
—
—
OC3IS<1:0>  
T3IS<1:0>  
—
—
31:16  
15:0  
—
—
OC4IS<1:0>  
T4IS<1:0>  
—
—
31:16  
15:0  
—
—
OC5IS<1:0>  
T5IS<1:0>  
—
—
31:16  
15:0  
—
—
CNIS<1:0>  
U1IS<1:0>  
—
—
31:16  
15:0  
—
—
CMP2IS<1:0>  
PMPIS<1:0>  
FSCMIS<1:0>  
U2IS<1:0>  
—
—
31:16  
15:0  
—
—
—
—
31:16  
—
—
—
—
—
—
—
—
—
—
—
—
15:0  
—
—
—
—
—
FCEIP<2:0>  
FCEIS<1:0>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV  
Registers” for more information.  
2:  
This register does not have associated CLR, SET, and INV registers.  
(1)  
TABLE 4-5:  
INTERRUPT REGISTERS MAP FOR PIC32MX440F128H, PIC32MX440F256H AND PIC32MX440F512H DEVICES ONLY  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
MVEC  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT4EP  
—
—
INT3EP  
—
—
INT2EP  
—
—
INT1EP  
—
SS0  
0000  
1000 INTCON  
1010 INTSTAT(2)  
TPC<2:0>  
—
INT0EP 0000  
31:16  
15:0  
—
0000  
0000  
0000  
0000  
0000  
0000  
—
SRIPL<2:0>  
VEC<5:0>  
31:16  
15:0  
1020  
1030  
1040  
1060  
1070  
1090  
10A0  
10B0  
10C0  
10D0  
10E0  
10F0  
1100  
1110  
1120  
1140  
IPTMR  
IFS0  
IFS1  
IEC0  
IEC1  
IPC0  
IPC1  
IPC2  
IPC3  
IPC4  
IPC5  
IPC6  
IPC7  
IPC8  
IPC9  
IPC11  
IPTMR<31:0>  
31:16 I2C1MIF  
I2C1SIF  
I2C1BIF  
U1TXIF  
T3IF  
U1RXIF  
INT2IF  
U1EIF  
OC2IF  
—
—
—
—
INT1IF  
—
OC5IF  
OC1IF  
—
IC5IF  
IC1IF  
—
T5IF  
T1IF  
INT4IF  
INT0IF  
OC4IF  
CS1IF  
IC4IF  
CS0IF  
DMA1IF  
AD1IF  
IC4IE  
T4IF  
CTIF  
15:0  
INT3IF  
—
OC3IF  
IC3IF  
IC2IF  
USBIF  
U2RXIF  
—
T2IF  
31:16  
—
FSCMIF  
I2C1SIE  
OC3IE  
—
—
—
—
FCEIF  
U2EIF  
—
—
DMA3IF  
DMA2IF  
PMPIF  
OC4IE  
CS1IE  
DMA0IF 0000  
15:0 RTCCIF  
31:16 I2C1MIE  
I2C2MIF  
I2C2SIF  
U1TXIE  
T3IE  
I2C2BIF  
U2TXIF  
U1EIE  
OC2IE  
—
SPI2RXIF SPI2TXIF SPI2EIF  
CMP2IF  
T5IE  
T1IE  
—
CMP1IF  
CNIF  
T4IE  
CTIE  
0000  
0000  
0000  
I2C1BIE  
IC3IE  
—
U1RXIE  
—
INT1IE  
—
OC5IE  
OC1IE  
—
IC5IE  
IC1IE  
—
INT4IE  
15:0  
INT3IE  
—
INT2IE  
IC2IE  
USBIE  
U2RXIE  
T2IE  
INT0IE  
CS0IE  
DMA1IE  
AD1IE  
31:16  
—
—
FCEIE  
U2EIE  
DMA3IE  
DMA2IE  
PMPIE  
DMA0IE 0000  
CNIE  
15:0 RTCCIE  
FSCMIE  
—
I2C2MIE  
—
I2C2SIE  
I2C2BIE  
U2TXIE  
SPI2RXIE SPI2TXIE SPI2EIE  
CMP2IE  
CMP1IE  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT0IP<2:0>  
CS0IP<2:0>  
INT1IP<2:0>  
IC1IP<2:0>  
INT2IP<2:0>  
IC2IP<2:0>  
INT3IP<2:0>  
IC3IP<2:0>  
INT4IP<2:0>  
IC4IP<2:0>  
—
INT0IS<1:0>  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CS1IP<2:0>  
CTIP<2:0>  
OC1IP<2:0>  
T1IP<2:0>  
OC2IP<2:0>  
T2IP<2:0>  
OC3IP<2:0>  
T3IP<2:0>  
OC4IP<2:0>  
T4IP<2:0>  
OC5IP<2:0>  
T5IP<2:0>  
CNIP<2:0>  
U1IP<2:0>  
CMP2IP<2:0>  
PMPIP<2:0>  
FSCMIP<2:0>  
U2IP<2:0>  
DMA2IP<2:0>  
DMA0IP<2:0>  
—
CS1IS<1:0>  
—
—
CS0IS<1:0>  
INT1IS<1:0>  
IC1IS<1:0>  
INT2IS<1:0>  
IC2IS<1:0>  
INT3IS<1:0>  
IC3IS<1:0>  
INT4IS<1:0>  
IC4IS<1:0>  
CTIS<1:0>  
OC1IS<1:0>  
T1IS<1:0>  
31:16  
15:0  
—
—
—
—
31:16  
15:0  
—
—
OC2IS<1:0>  
T2IS<1:0>  
—
—
31:16  
15:0  
—
—
OC3IS<1:0>  
T3IS<1:0>  
—
—
31:16  
15:0  
—
—
OC4IS<1:0>  
T4IS<1:0>  
—
—
31:16  
15:0  
—
—
—
—
—
—
OC5IS<1:0>  
T5IS<1:0>  
—
—
IC5IP<2:0>  
AD1IP<2:0>  
I2C1IP<2:0>  
SPI2IP<2:0>  
CMP1IP<2:0>  
RTCCIP<2:0>  
I2C2IP<2:0>  
DMA3IP<2:0>  
DMA1IP<2:0>  
—
IC5IS<1:0>  
AD1IS<1:0>  
I2C1IS<1:0>  
SPI2IS<1:0>  
CMP1IS<1:0>  
RTCCIS<1:0>  
I2C2IS<1:0>  
DMA3IS<1:0>  
DMA1IS<1:0>  
31:16  
15:0  
—
—
CNIS<1:0>  
U1IS<1:0>  
—
—
31:16  
15:0  
—
—
CMP2IS<1:0>  
PMPIS<1:0>  
FSCMIS<1:0>  
U2IS<1:0>  
—
—
31:16  
15:0  
—
—
—
—
31:16  
15:0  
—
—
DMA2IS<1:0>  
DMA0IS<1:0>  
—
—
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
USBIP<2:0>  
USBIS<1:0>  
FCEIP<2:0>  
FCEIS<1:0>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
Except where noted, all registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV  
Registers” for more information.  
2:  
This register does not have associated CLR, SET, and INV registers.  
(1)  
TABLE 4-6:  
INTERRUPT REGISTERS MAP FOR THE PIC32MX420F032H DEVICE ONLY  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
MVEC  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT4EP  
—
—
INT3EP  
—
—
INT2EP  
—
—
INT1EP  
—
SS0  
0000  
1000 INTCON  
1010 INTSTAT(2)  
TPC<2:0>  
—
INT0EP 0000  
31:16  
15:0  
—
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
—
SRIPL<2:0>  
VEC<5:0>  
31:16  
15:0  
1020  
1030  
1040  
1060  
1070  
1090  
10A0  
10B0  
10C0  
10D0  
10E0  
10F0  
1100  
1110  
1140  
IPTMR  
IFS0  
IFS1  
IEC0  
IEC1  
IPC0  
IPC1  
IPC2  
IPC3  
IPC4  
IPC5  
IPC6  
IPC7  
IPC8  
IPC11  
IPTMR<31:0>  
31:16 I2C1MIF  
I2C1SIF  
I2C1BIF  
U1TXIF  
T3IF  
U1RXIF  
INT2IF  
U1EIF  
OC2IF  
—
—
—
—
INT1IF  
—
OC5IF  
OC1IF  
—
IC5IF  
IC1IF  
—
T5IF  
T1IF  
INT4IF  
INT0IF  
OC4IF  
CS1IF  
—
IC4IF  
CS0IF  
—
T4IF  
CTIF  
—
15:0  
INT3IF  
—
OC3IF  
IC3IF  
IC2IF  
USBIF  
U2RXIF  
—
T2IF  
31:16  
—
—
—
—
FCEIF  
U2EIF  
—
—
—
15:0 RTCCIF  
31:16 I2C1MIE  
FSCMIF  
I2C2MIF  
I2C2SIF  
U1TXIE  
T3IE  
I2C2BIF  
U2TXIF  
U1EIE  
OC2IE  
—
SPI2RXIF SPI2TXIF SPI2EIF  
CMP2IF  
T5IE  
T1IE  
—
CMP1IF  
PMPIF  
OC4IE  
CS1IE  
—
AD1IF  
IC4IE  
CS0IE  
—
CNIF  
T4IE  
CTIE  
—
I2C1SIE  
OC3IE  
—
I2C1BIE  
IC3IE  
—
U1RXIE  
—
INT1IE  
—
OC5IE  
OC1IE  
—
IC5IE  
IC1IE  
—
INT4IE  
15:0  
INT3IE  
—
INT2IE  
IC2IE  
USBIE  
U2RXIE  
T2IE  
INT0IE  
31:16  
—
—
FCEIE  
U2EIE  
—
15:0 RTCCIE  
FSCMIE  
—
I2C2MIE  
—
I2C2SIE  
I2C2BIE  
U2TXIE  
SPI2RXIE SPI2TXIE SPI2EIE  
CMP2IE  
CMP1IE  
PMPIE  
AD1IE  
CNIE  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT0IP<2:0>  
CS0IP<2:0>  
INT1IP<2:0>  
IC1IP<2:0>  
INT2IP<2:0>  
IC2IP<2:0>  
INT3IP<2:0>  
IC3IP<2:0>  
INT4IP<2:0>  
IC4IP<2:0>  
—
INT0IS<1:0>  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CS1IP<2:0>  
CTIP<2:0>  
OC1IP<2:0>  
T1IP<2:0>  
OC2IP<2:0>  
T2IP<2:0>  
OC3IP<2:0>  
T3IP<2:0>  
OC4IP<2:0>  
T4IP<2:0>  
OC5IP<2:0>  
T5IP<2:0>  
CNIP<2:0>  
U1IP<2:0>  
CMP2IP<2:0>  
PMPIP<2:0>  
FSCMIP<2:0>  
U2IP<2:0>  
—
CS1IS<1:0>  
—
—
CS0IS<1:0>  
INT1IS<1:0>  
IC1IS<1:0>  
INT2IS<1:0>  
IC2IS<1:0>  
INT3IS<1:0>  
IC3IS<1:0>  
INT4IS<1:0>  
IC4IS<1:0>  
CTIS<1:0>  
OC1IS<1:0>  
T1IS<1:0>  
31:16  
15:0  
—
—
—
—
31:16  
15:0  
—
—
OC2IS<1:0>  
T2IS<1:0>  
—
—
31:16  
15:0  
—
—
OC3IS<1:0>  
T3IS<1:0>  
—
—
31:16  
15:0  
—
—
OC4IS<1:0>  
T4IS<1:0>  
—
—
31:16  
15:0  
—
—
—
—
—
—
OC5IS<1:0>  
T5IS<1:0>  
—
—
IC5IP<2:0>  
AD1IP<2:0>  
I2C1IP<2:0>  
SPI2IP<2:0>  
CMP1IP<2:0>  
RTCCIP<2:0>  
I2C2IP<2:0>  
—
IC5IS<1:0>  
AD1IS<1:0>  
I2C1IS<1:0>  
SPI2IS<1:0>  
CMP1IS<1:0>  
RTCCIS<1:0>  
I2C2IS<1:0>  
31:16  
15:0  
—
—
CNIS<1:0>  
U1IS<1:0>  
—
—
31:16  
15:0  
—
—
CMP2IS<1:0>  
PMPIS<1:0>  
FSCMIS<1:0>  
U2IS<1:0>  
—
—
31:16  
15:0  
—
—
—
—
31:16  
—
—
—
—
—
—
—
—
—
—
15:0  
—
—
USBIP<2:0>  
USBIS<1:0>  
FCEIP<2:0>  
FCEIS<1:0>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV  
Registers” for more information.  
2:  
This register does not have associated CLR, SET, and INV registers.  
(1)  
TABLE 4-7:  
TIMER1-5 REGISTERS MAP  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
ON  
—
—
—
—
—
SIDL  
—
—
TWDIS  
—
—
TWIP  
—
—
—
—
—
—
—
—
—
—
—
TGATE  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TSYNC  
—
—
TCS  
—
—
—
—
0000  
0000  
0000  
0000  
0000  
FFFF  
0000  
0000  
0000  
0000  
0000  
FFFF  
0000  
0000  
0000  
0000  
0000  
FFFF  
0000  
0000  
0000  
0000  
0000  
FFFF  
0000  
0000  
0000  
0000  
0000  
FFFF  
0600 T1CON  
TCKPS<1:0>  
31:16  
15:0  
—
0610  
0620  
TMR1  
PR1  
TMR1<15:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PR1<15:0>  
31:16  
15:0  
—
ON  
—
—
—
—
—
SIDL  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TGATE  
—
—
TCKPS<2:0>  
—
—
T32  
—
—
—
—
—
TCS(2)  
—
—
—
—
0800 T2CON  
—
—
31:16  
15:0  
0810  
0820  
TMR2  
PR2  
TMR2<15:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PR2<15:0>  
31:16  
15:0  
—
ON  
—
—
—
—
—
SIDL  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TGATE  
—
—
TCKPS<2:0>  
—
—
—
—
—
—
—
—
TCS(2)  
—
—
—
—
0A00 T3CON  
31:16  
15:0  
0A10  
0A20  
TMR3  
PR3  
TMR3<15:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PR3<15:0>  
31:16  
15:0  
—
ON  
—
—
—
—
—
SIDL  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TGATE  
—
—
TCKPS<2:0>  
—
—
T32  
—
—
—
—
—
TCS(2)  
—
—
—
—
0C00 T4CON  
31:16  
15:0  
0C10  
0C20  
TMR4  
PR4  
TMR4<15:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PR4<15:0>  
31:16  
15:0  
—
ON  
—
—
—
—
—
SIDL  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TGATE  
—
—
TCKPS<2:0>  
—
—
—
—
—
—
—
—
TCS(2)  
—
—
—
—
0E00 T5CON  
31:16  
15:0  
0E10  
0E20  
TMR5  
PR5  
TMR5<15:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PR5<15:0>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more  
information.  
2:  
This bit is not available on 64-pin devices.  
TABLE 4-8:  
INPUT CAPTURE1-5 REGISTERS MAP  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000  
0000  
xxxx  
xxxx  
0000  
0000  
xxxx  
xxxx  
0000  
0000  
xxxx  
xxxx  
0000  
0000  
xxxx  
xxxx  
0000  
0000  
xxxx  
xxxx  
2000 IC1CON(1)  
ON  
SIDL  
FEDGE  
C32  
ICTMR  
ICI<1:0>  
ICOV  
ICBNE  
ICM<2:0>  
31:16  
15:0  
2010  
IC1BUF  
IC1BUF<31:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2200 IC2CON(1)  
ON  
SIDL  
FEDGE  
C32  
ICTMR  
ICI<1:0>  
ICOV  
ICBNE  
ICM<2:0>  
31:16  
15:0  
2210  
IC2BUF  
IC2BUF<31:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2400 IC3CON(1)  
ON  
SIDL  
FEDGE  
C32  
ICTMR  
ICI<1:0>  
ICI<1:0>  
ICI<1:0>  
ICOV  
ICBNE  
ICM<2:0>  
31:16  
15:0  
2410  
IC3BUF  
IC3BUF<31:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2600 IC4CON(1)  
ON  
SIDL  
FEDGE  
C32  
ICTMR  
ICOV  
ICBNE  
ICM<2:0>  
31:16  
15:0  
2610  
IC4BUF  
IC4BUF<31:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2800 IC5CON(1)  
ON  
SIDL  
FEDGE  
C32  
ICTMR  
ICOV  
ICBNE  
ICM<2:0>  
31:16  
15:0  
2810  
IC5BUF  
IC5BUF<31:0>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.  
(1)  
TABLE 4-9:  
OUTPUT COMPARE1-5 REGISTERS MAP  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000  
0000  
xxxx  
xxxx  
xxxx  
xxxx  
0000  
0000  
xxxx  
xxxx  
xxxx  
xxxx  
0000  
0000  
xxxx  
xxxx  
xxxx  
xxxx  
0000  
0000  
xxxx  
xxxx  
xxxx  
xxxx  
0000  
0000  
xxxx  
xxxx  
xxxx  
xxxx  
3000 OC1CON  
ON  
SIDL  
OC32  
OCFLT  
OCTSEL  
OCM<2:0>  
31:16  
15:0  
3010  
OC1R  
OC1R<31:0>  
31:16  
15:0  
3020 OC1RS  
3200 OC2CON  
OC1RS<31:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ON  
SIDL  
OC32  
OCFLT  
OCTSEL  
OCM<2:0>  
31:16  
15:0  
3210  
OC2R  
OC2R<31:0>  
31:16  
15:0  
3220 OC2RS  
3400 OC3CON  
OC2RS<31:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ON  
SIDL  
OC32  
OCFLT  
OCTSEL  
OCM<2:0>  
31:16  
15:0  
3410  
OC3R  
OC3R<31:0>  
31:16  
15:0  
3420 OC3RS  
3600 OC4CON  
OC3RS<31:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ON  
SIDL  
OC32  
OCFLT  
OCTSEL  
OCM<2:0>  
31:16  
15:0  
3610  
OC4R  
OC4R<31:0>  
31:16  
15:0  
3620 OC4RS  
3800 OC5CON  
OC4RS<31:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ON  
SIDL  
OC32  
OCFLT  
OCTSEL  
OCM<2:0>  
31:16  
15:0  
3810  
OC5R  
OC5R<31:0>  
31:16  
15:0  
3820 OC5RS  
OC5RS<31:0>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more  
information.  
(1)  
TABLE 4-10: I2C1-2 REGISTERS MAP  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
ON  
—
—
—
—
—
SIDL  
—
—
SCLREL  
—
—
STRICT  
—
—
A10M  
—
—
—
SMEN  
—
—
GCEN  
—
—
STREN  
—
—
ACKDT  
—
—
ACKEN  
—
—
RCEN  
—
—
PEN  
—
—
RSEN  
—
—
SEN  
—
0000  
1000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
1000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
5000 I2C1CON  
5010 I2C1STAT  
DISSLW  
—
31:16  
15:0 ACKSTAT TRSTAT  
—
—
—
BCL  
GCSTAT  
ADD10  
IWCOL  
I2COV  
D/A  
P
S
R/W  
RBF  
TBF  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16  
15:0  
5020 I2C1ADD  
5030 I2C1MSK  
—
—
—
—
—
—
—
—
—
—
ON  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SIDL  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADD<9:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MSK<9:0>  
31:16  
15:0  
—
—
—
5040  
I2C1BRG  
—
I2C1BRG<11:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
5050 I2C1TRN  
5260 I2C1RCV  
5200 I2C2CON  
5210 I2C2STAT  
5220 I2C2ADD  
5230 I2C2MSK  
—
—
—
I2CT1DATA<7:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
I2CR1DATA<7:0>  
31:16  
15:0  
—
—
—
—
—
—
GCEN  
—
—
STREN  
—
—
ACKDT  
—
—
ACKEN  
—
—
RCEN  
—
—
PEN  
—
—
RSEN  
—
—
SEN  
—
SCLREL  
—
STRICT  
—
A10M  
—
DISSLW  
—
SMEN  
—
31:16  
15:0 ACKSTAT TRSTAT  
—
—
BCL  
—
GCSTAT  
—
ADD10  
—
IWCOL  
—
I2COV  
—
D/A  
P
S
R/W  
—
RBF  
—
TBF  
—
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADD<9:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MSK<9:0>  
31:16  
15:0  
—
—
—
—
—
—
5240  
I2C2BRG  
—
I2C2BRG<11:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5250 I2C2TRN  
5260 I2C2RCV  
—
I2CT2DATA<7:0>  
31:16  
15:0  
—
—
—
—
—
—
I2CR2DATA<7:0>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV  
Registers” for more information.  
TABLE 4-11: UART1-2 REGISTERS MAP  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
ON  
—
—
—
—
—
SIDL  
—
—
IREN  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000  
6000 U1MODE(1)  
6010 U1STA(1)  
6020 U1TXREG  
6030 U1RXREG  
6040 U1BRG(1)  
6200 U2MODE(1)  
6210 U2STA(1)  
6220 U2TXREG  
6230 U2RXREG  
6240 U2BRG(1)  
RTSMD  
UEN<1:0>  
WAKE  
LPBACK  
ABAUD  
RXINV  
BRGH  
PDSEL<1:0>  
STSEL 0000  
0000  
31:16  
15:0  
—
—
—
UTXBF  
—
ADM_EN  
TRMT  
—
ADDR<7:0>  
UTXISEL<1:0>  
UTXINV  
—
URXEN  
—
UTXBRK  
UTXEN  
—
URXISEL<1:0>  
ADDEN  
—
RIDLE  
—
PERR  
—
FERR  
—
OERR  
—
URXDA 0110  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000  
0000  
0000  
0000  
0000  
0000  
0000  
—
—
—
—
TX8  
—
Transmit Register  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RX8  
—
Receive Register  
31:16  
15:0  
—
—
—
—
—
—
BRG<15:0>  
31:16  
15:0  
—
ON  
—
—
—
—
—
SIDL  
—
—
IREN  
—
—
—
—
—
—
—
—
—
—
—
RTSMD  
UEN<1:0>  
WAKE  
LPBACK  
ABAUD  
RXINV  
BRGH  
PDSEL<1:0>  
STSEL 0000  
0000  
31:16  
15:0  
—
—
—
UTXBF  
—
ADM_EN  
TRMT  
—
ADDR<7:0>  
UTXISEL<1:0>  
UTXINV  
—
URXEN  
—
UTXBRK  
UTXEN  
—
URXISEL<1:0>  
ADDEN  
—
RIDLE  
—
PERR  
—
FERR  
—
OERR  
—
URXDA 0110  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000  
0000  
0000  
0000  
0000  
0000  
—
—
—
—
TX8  
—
Transmit Register  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RX8  
—
Receive Register  
31:16  
15:0  
—
—
—
—
—
—
BRG<15:0>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.  
(1,2)  
TABLE 4-12: SPI1-2 REGISTERS MAP  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16 FRMEN FRMSYNC FRMPOL  
—
—
—
—
SMP  
—
—
CKE  
—
—
SSEN  
—
—
CKP  
—
MSTEN  
—
—
—
—
—
—
—
—
—
—
—
SPIFE  
—
—
—
—
0000  
0000  
0000  
5800 SPI1CON  
5810 SPI1STAT  
5820 SPI1BUF  
5830 SPI1BRG  
5A00 SPI2CON  
5A10 SPI2STAT  
5A20 SPI2BUF  
5A30 SPI2BRG  
15:0  
31:16  
15:0  
ON  
—
—
—
—
SIDL  
—
DISSDO MODE32 MODE16  
—
—
—
—
—
—
—
—
—
—
SPIBUSY  
—
—
—
SPIROV  
—
SPITBE  
—
SPIRBF 0008  
0000  
31:16  
15:0  
DATA<31:0>  
0000  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000  
0000  
0008  
0000  
0000  
BRG<8:0>  
31:16 FRMEN FRMSYNC FRMPOL  
—
—
CKE  
—
—
SSEN  
—
—
CKP  
—
MSTEN  
—
—
—
—
—
—
—
—
—
—
—
SPIFE  
—
—
—
—
15:0  
31:16  
15:0  
ON  
—
—
—
—
SIDL  
—
DISSDO MODE32 MODE16  
SMP  
—
—
—
—
—
—
—
—
—
—
—
SPIBUSY  
—
—
—
SPIROV  
—
SPITBE  
—
SPIRBF 0008  
0000  
31:16  
15:0  
DATA<31:0>  
0000  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000  
0000  
BRG<8:0>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV  
Registers” for more information.  
2:  
SPI2 Module is not present on PIC32MX420FXXXX/440FXXXX devices.  
TABLE 4-13: ADC REGISTERS MAP  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
ON  
—
—
—
SIDL  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLRASAM  
—
—
—
—
—
ASAM  
—
—
SAMP  
—
—
0000  
9000 AD1CON1(1)  
9010 AD1CON2(1)  
9020 AD1CON3(1)  
9040 AD1CHS(1)  
9060 AD1PCFG(1)  
9050 AD1CSSL(1)  
9070 ADC1BUF0  
9080 ADC1BUF1  
9090 ADC1BUF2  
90A0 ADC1BUF3  
90B0 ADC1BUF4  
90C0 ADC1BUF5  
90D0 ADC1BUF6  
90E0 ADC1BUF7  
90F0 ADC1BUF8  
9100 ADC1BUF9  
FORM<2:0>  
SSRC<2:0>  
DONE 0000  
31:16  
15:0  
—
—
—
—
CSCNA  
—
—
—
—
—
—
—
—
BUFS  
—
—
—
—
—
ALTS  
—
0000  
0000  
0000  
0000  
0000  
0000  
0000  
VCFG2  
—
VCFG1  
—
VCFG0  
—
OFFCAL  
—
SMPI<3:0>  
BUFM  
—
31:16  
15:0  
—
—
—
ADRC  
—
—
SAMC<4:0>  
ADCS<7:0>  
31:16 CH0NB  
—
—
—
—
CH0SB<3:0>  
CH0NA  
—
—
—
—
—
—
—
CH0SA<3:0>  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16  
—
—
—
—
—
—
—
15:0 PCFG15  
31:16  
PCFG14  
—
PCFG13  
—
PCFG12  
—
PCFG11  
—
PCFG10  
—
PCFG9  
—
PCFG8  
—
PCFG7  
—
PCFG6  
—
PCFG5  
—
PCFG4  
—
PCFG3  
—
PCFG2  
—
PCFG1  
—
PCFG0 0000  
0000  
—
—
15:0 CSSL15  
31:16  
15:0  
CSSL14  
CSSL13  
CSSL12  
CSSL11  
CSSL10  
CSSL9  
CSSL8  
CSSL7  
CSSL6  
CSSL5  
CSSL4  
CSSL3  
CSSL2  
CSSL1  
CSSL0 0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
ADC Result Word 0 (ADC1BUF0<31:0>)  
ADC Result Word 1 (ADC1BUF1<31:0>)  
ADC Result Word 2 (ADC1BUF2<31:0>)  
ADC Result Word 3 (ADC1BUF3<31:0>)  
ADC Result Word 4 (ADC1BUF4<31:0>)  
ADC Result Word 5 (ADC1BUF5<31:0>)  
ADC Result Word 6 (ADC1BUF6<31:0>)  
ADC Result Word 7 (ADC1BUF7<31:0>)  
ADC Result Word 8 (ADC1BUF8<31:0>)  
ADC Result Word 9 (ADC1BUF9<31:0>)  
31:16  
15:0  
31:16  
15:0  
31:16  
15:0  
31:16  
15:0  
31:16  
15:0  
31:16  
15:0  
31:16  
15:0  
31:16  
15:0  
31:16  
15:0  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.  
TABLE 4-13: ADC REGISTERS MAP (CONTINUED)  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
9110 ADC1BUFA  
9120 ADC1BUFB  
9130 ADC1BUFC  
9140 ADC1BUFD  
9150 ADC1BUFE  
9160 ADC1BUFF  
ADC Result Word A (ADC1BUFA<31:0>)  
ADC Result Word B (ADC1BUFB<31:0>)  
ADC Result Word C (ADC1BUFC<31:0>)  
ADC Result Word D (ADC1BUFD<31:0>)  
ADC Result Word E (ADC1BUFE<31:0>)  
ADC Result Word F (ADC1BUFF<31:0>)  
31:16  
15:0  
31:16  
15:0  
31:16  
15:0  
31:16  
15:0  
31:16  
15:0  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.  
TABLE 4-14: DMA GLOBAL REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES ONLY  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
ON  
—
—
—
—
—
—
SIDL  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000  
0000  
0000  
0000  
0000  
0000  
3000 DMACON(1)  
3010 DMASTAT  
3020 DMAADDR  
SUSPEND  
31:16  
15:0  
—
—
—
—
—
RDWR  
DMACH<1:0>  
31:16  
15:0  
DMAADDR<31:0>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.  
(1)  
TABLE 4-15: DMA CRC REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES ONLY  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CRCEN  
—
—
CRCAPP  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000  
0000  
0000  
0000  
0000  
0000  
3030 DCRCCON  
3040 DCRCDATA  
3050 DCRCXOR  
PLEN<3:0>  
CRCCH<1:0>  
31:16  
15:0  
—
—
DCRCDATA<15:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
DCRCXOR<15:0>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more  
information.  
TABLE 4-16: DMA CHANNELS 0-3 REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX  
(1)  
DEVICES ONLY  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHCHNS  
—
—
—
—
—
—
—
—
—
—
0000  
0000  
00FF  
FF00  
3060 DCH0CON  
3070 DCH0ECON  
3080 DCH0INT  
3090 DCH0SSA  
30A0 DCH0DSA  
30B0 DCH0SSIZ  
30C0 DCH0DSIZ  
30D0 DCH0SPTR  
30E0 DCH0DPTR  
30F0 DCH0CSIZ  
3100 DCH0CPTR  
3110 DCH0DAT  
3120 DCH1CON  
3130 DCH1ECON  
3140 DCH1INT  
3150 DCH1SSA  
CHEN  
CHAED  
CHCHN  
CHAEN  
CHEDET  
CHPRI<1:0>  
31:16  
15:0  
CHAIRQ<7:0>  
CHSIRQ<7:0>  
CFORCE CABORT  
PATEN  
CHDDIE  
CHDDIF  
SIRQEN  
AIRQEN  
CHBCIE  
CHBCIF  
—
—
—
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHSDIE  
CHSDIF  
CHSHIE  
CHSHIF  
CHDHIE  
CHDHIF  
CHCCIE  
CHCCIF  
CHTAIE  
CHTAIF  
CHERIE 0000  
CHERIF 0000  
0000  
31:16  
15:0  
CHSSA<31:0>  
0000  
31:16  
15:0  
0000  
CHDSA<31:0>  
0000  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
00FF  
FF00  
—
CHSSIZ<7:0>  
31:16  
15:0  
—
—
—
CHDSIZ<7:0>  
31:16  
15:0  
—
—
—
—
CHSTR<7:0>  
31:16  
15:0  
—
—
—
—
CHDPTR<7:0>  
31:16  
15:0  
—
—
—
—
CHCSIZ<7:0>  
31:16  
15:0  
—
—
—
—
CHCPTR<7:0>  
31:16  
15:0  
—
—
—
—
—
CHPDAT<7:0>  
31:16  
15:0  
—
—
—
—
—
—
—
CHCHNS  
—
CHEN  
CHAED  
CHCHN  
CHAEN  
CHEDET  
CHPRI<1:0>  
31:16  
15:0  
CHAIRQ<7:0>  
CHSIRQ<7:0>  
CFORCE CABORT  
PATEN  
CHDDIE  
CHDDIF  
SIRQEN  
AIRQEN  
CHBCIE  
CHBCIF  
—
—
—
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHSDIE  
CHSDIF  
CHSHIE  
CHSHIF  
CHDHIE  
CHDHIF  
CHCCIE  
CHCCIF  
CHTAIE  
CHTAIF  
CHERIE 0000  
CHERIF 0000  
0000  
31:16  
15:0  
CHSSA<31:0>  
0000  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers except DCHxSPTR, DCHxDPTR and DCHxCPTR have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR,  
SET and INV Registers” for more information.  
TABLE 4-16: DMA CHANNELS 0-3 REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX  
(1)  
DEVICES ONLY (CONTINUED)  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
00FF  
FF00  
3160 DCH1DSA  
3170 DCH1SSIZ  
3180 DCH1DSIZ  
3190 DCH1SPTR  
31A0 DCH1DPTR  
31B0 DCH1CSIZ  
31C0 DCH1CPTR  
31D0 DCH1DAT  
31E0 DCH2CON  
31F0 DCH2ECON  
3200 DCH2INT  
3210 DCH2SSA  
3220 DCH2DSA  
3230 DCH2SSIZ  
3240 DCH2DSIZ  
3250 DCH2SPTR  
CHDSA<31:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHSSIZ<7:0>  
31:16  
15:0  
—
—
—
CHDSIZ<7:0>  
31:16  
15:0  
—
—
—
—
CHSPTR<7:0>  
31:16  
15:0  
—
—
—
—
CHDPTR<7:0>  
31:16  
15:0  
—
—
—
—
CHCSIZ<7:0>  
31:16  
15:0  
—
—
—
—
CHCPTR<7:0>  
31:16  
15:0  
—
—
—
—
—
CHPDAT<7:0>  
31:16  
15:0  
—
—
—
—
—
—
—
CHCHNS  
—
CHEN  
CHAED  
CHCHN  
CHAEN  
CHEDET  
CHPRI<1:0>  
31:16  
15:0  
CHAIRQ<7:0>  
CHSIRQ<7:0>  
CFORCE CABORT  
PATEN  
CHDDIE  
CHDDIF  
SIRQEN  
AIRQEN  
CHBCIE  
CHBCIF  
—
—
—
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHSDIE  
CHSDIF  
CHSHIE  
CHSHIF  
CHDHIE  
CHDHIF  
CHCCIE  
CHCCIF  
CHTAIE  
CHTAIF  
CHERIE 0000  
CHERIF 0000  
0000  
31:16  
15:0  
CHSSA<31:0>  
0000  
31:16  
15:0  
0000  
CHDSA<31:0>  
0000  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000  
0000  
0000  
0000  
0000  
0000  
CHSSIZ<7:0>  
31:16  
15:0  
—
CHDSIZ<7:0>  
31:16  
15:0  
—
—
CHSPTR<7:0>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers except DCHxSPTR, DCHxDPTR and DCHxCPTR have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR,  
SET and INV Registers” for more information.  
TABLE 4-16: DMA CHANNELS 0-3 REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX  
(1)  
DEVICES ONLY (CONTINUED)  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
00FF  
FF00  
3260 DCH2DPTR  
3270 DCH2CSIZ  
3280 DCH2CPTR  
3290 DCH2DAT  
32A0 DCH3CON  
32B0 DCH3ECON  
32C0 DCH3INT  
32D0 DCH3SSA  
32E0 DCH3DSA  
32F0 DCH3SSIZ  
3300 DCH3DSIZ  
3310 DCH3SPTR  
3320 DCH3DPTR  
3330 DCH3CSIZ  
3340 DCH3CPTR  
3350 DCH3DAT  
—
CHDPTR<7:0>  
31:16  
15:0  
—
—
—
—
CHCSIZ<7:0>  
31:16  
15:0  
—
—
—
—
CHCPTR<7:0>  
31:16  
15:0  
—
—
—
—
—
CHPDAT<7:0>  
31:16  
15:0  
—
—
—
—
—
—
—
CHCHNS  
—
CHEN  
CHAED  
CHCHN  
CHAEN  
CHEDET  
CHPRI<1:0>  
31:16  
15:0  
CHAIRQ<7:0>  
CHSIRQ<7:0>  
CFORCE CABORT  
PATEN  
CHDDIE  
CHDDIF  
SIRQEN  
AIRQEN  
CHBCIE  
CHBCIF  
—
—
—
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHSDIE  
CHSDIF  
CHSHIE  
CHSHIF  
CHDHIE  
CHDHIF  
CHCCIE  
CHCCIF  
CHTAIE  
CHTAIF  
CHERIE 0000  
CHERIF 0000  
0000  
31:16  
15:0  
CHSSA<31:0>  
0000  
31:16  
15:0  
0000  
CHDSA<31:0>  
0000  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
CHSSIZ<7:0>  
31:16  
15:0  
—
CHDSIZ<7:0>  
31:16  
15:0  
—
—
CHSTR<7:0>  
31:16  
15:0  
—
—
CHDPTR<7:0>  
31:16  
15:0  
—
—
CHCSIZ<7:0>  
31:16  
15:0  
—
—
CHCPTR<7:0>  
31:16  
15:0  
—
—
CHPDAT<7:0>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers except DCHxSPTR, DCHxDPTR and DCHxCPTR have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR,  
SET and INV Registers” for more information.  
(1)  
TABLE 4-17: COMPARATOR REGISTERS MAP  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
ON  
—
—
COE  
—
—
CPOL  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
COUT  
—
—
—
—
—
—
—
—
—
—
—
CREF  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000  
00C3  
0000  
00C3  
0000  
A000 CM1CON  
A010 CM2CON  
A060 CMSTAT  
EVPOL<1:0>  
CCH<1:0>  
31:16  
15:0  
—
—
ON  
—
COE  
—
CPOL  
—
COUT  
—
EVPOL<1:0>  
CREF  
—
CCH<1:0>  
31:16  
15:0  
—
—
—
—
—
—
—
SIDL  
—
—
—
C2OUT  
C1OUT 0000  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more  
information.  
(1)  
TABLE 4-18: COMPARATOR VOLTAGE REFERENCE REGISTERS MAP  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000  
0000  
9800 CVRCON  
ON  
CVROE  
CVRR  
CVRSS  
CVR<3:0>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more  
information.  
TABLE 4-19: FLASH CONTROLLER REGISTERS MAP  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
F400 NVMCON(1)  
F410 NVMKEY  
WR  
WREN  
WRERR  
LVDERR LVDSTAT  
NVMOP<3:0>  
31:16  
15:0  
NVMKEY<31:0>  
NVMADDR<31:0>  
NVMDATA<31:0>  
31:16  
15:0  
(1)  
F420 NVMADDR  
31:16  
15:0  
F430 NVMDATA  
31:16  
15:0  
NVMSRC  
F440  
NVMSRCADDR<31:0>  
ADDR  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.  
(1,2)  
TABLE 4-20: SYSTEM CONTROL REGISTERS MAP  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
—
—
—
—
ON  
—
—
—
—
—
PLLODIV<2:0>  
FRCDIV<2:0>  
—
SOSCRDY  
—
SLOCK  
—
PBDIV<1:0>  
PLLMULT<2:0>  
0000  
F000 OSCCON  
F010 OSCTUN  
0000 WDTCON  
COSC<2:0>  
—
—
—
—
—
—
—
—
—
NOSC<2:0>  
CLKLOCK ULOCK  
SLPEN  
—
CF  
—
UFRCEN SOSCEN OSWEN 0000  
31:16  
15:0  
0000  
0000  
0000  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TUN<5:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
SWDTPS<4:0>  
WDTCLR 0000  
31:16  
15:0  
—
—
—
—
SWR  
—
—
—
—
—
—
WDTO  
—
—
SLEEP  
—
—
IDLE  
—
—
—
POR  
—
0000  
0000  
0000  
F600  
RCON  
CMR  
—
VREGS  
—
EXTR  
—
BOR  
—
31:16  
15:0  
F610 RSWRST  
F230 SYSKEY(3)  
—
—
—
—
—
—
—
—
SWRST 0000  
0000  
31:16  
15:0  
SYSKEY<31:0>  
0000  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV  
Registers” for more information.  
2:  
3:  
Reset values are dependent on the DEVCFGx Configuration bits and the type of reset.  
This register does not have associated CLR, SET, and INV registers.  
TABLE 4-21: PORTA REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L,  
(1)  
PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISA10  
—
—
TRISA9  
—
—
—
—
—
—
—
—
—
—
TRISA7  
—
—
TRISA6  
—
—
TRISA5  
—
—
TRISA4  
—
—
TRISA3  
—
—
TRISA2  
—
—
TRISA1  
—
—
0000  
6000  
TRISA  
15:0 TRISA15 TRISA14  
TRISA0 C6FF  
31:16  
15:0  
—
RA15  
—
—
RA14  
—
—
RA0  
—
0000  
xxxx  
0000  
xxxx  
0000  
6010 PORTA  
RA10  
—
RA9  
—
RA7  
—
RA6  
—
RA5  
—
RA4  
—
RA3  
—
RA2  
—
RA1  
—
31:16  
15:0  
6020  
6030  
LATA  
LATA15  
—
LATA14  
—
LATA10  
—
LATA9  
—
LATA7  
—
LATA6  
—
LATA5  
—
LATA4  
—
LATA3  
—
LATA2  
—
LATA1  
—
LATA0  
—
31:16  
ODCA  
15:0 ODCA15 ODCA14  
ODCA10  
ODCA9  
ODCA7  
ODCA6  
ODCA5  
ODCA4  
ODCA3  
ODCA2  
ODCA1  
ODCA0 0000  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more  
information.  
(1)  
TABLE 4-22: PORTB REGISTERS MAP  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
—
—
—
—
—
—
—
TRISB9  
—
—
TRISB8  
—
—
TRISB7  
—
—
TRISB6  
—
—
TRISB5  
—
—
TRISB4  
—
—
TRISB3  
—
—
TRISB2  
—
—
TRISB1  
—
—
0000  
6040  
TRISB  
15:0 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10  
TRISB0 FFFF  
31:16  
15:0  
—
RB15  
—
—
RB14  
—
—
RB13  
—
—
RB12  
—
—
RB11  
—
—
RB10  
—
—
RB0  
—
0000  
xxxx  
0000  
xxxx  
0000  
6050 PORTB  
RB9  
RB8  
RB7  
RB6  
RB5  
RB4  
RB3  
RB2  
RB1  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
6060  
6070  
LATB  
LATB15  
—
LATB14  
—
LATB13  
—
LATB12  
—
LATB11  
—
LATB10  
—
LATB9  
—
LATB8  
—
LATB7  
—
LATB6  
—
LATB5  
—
LATB4  
—
LATB3  
—
LATB2  
—
LATB1  
—
LATB0  
—
31:16  
ODCB  
15:0 ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 ODCB10  
ODCB9  
ODCB8  
ODCB7  
ODCB6  
ODCB5  
ODCB4  
ODCB3  
ODCB2  
ODCB1  
ODCB0 0000  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more  
information.  
TABLE 4-23: PORTC REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L,  
(1)  
PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISC4  
—
—
TRISC3  
—
—
TRISC2  
—
—
TRISC1  
—
—
—
—
—
—
—
—
—
0000  
F01E  
0000  
xxxx  
0000  
xxxx  
0000  
0000  
6080  
TRISC  
15:0 TRISC15 TRISC14 TRISC13 TRISC12  
31:16  
15:0  
—
RC15  
—
—
RC14  
—
—
RC13  
—
—
RC12  
—
6090 PORTC  
RC4  
—
RC3  
—
RC2  
—
RC1  
—
31:16  
60A0  
60B0  
LATC  
15:0 LATC15  
31:16  
LATC14  
—
LATC13  
—
LATC12  
—
LATC4  
—
LATC3  
—
LATC2  
—
LATC1  
—
—
ODCC  
15:0 ODCC15 ODCC14 ODCC13 ODCC12  
ODCC4  
ODCC3  
ODCC2  
ODCC1  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more  
information.  
TABLE 4-24: PORTC REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H,  
PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H AND PIC32MX440F512H  
(1)  
DEVICES ONLY  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000  
F000  
0000  
xxxx  
0000  
xxxx  
0000  
0000  
6080  
TRISC  
15:0 TRISC15 TRISC14 TRISC13 TRISC12  
31:16  
15:0  
—
RC15  
—
—
RC14  
—
—
RC13  
—
—
RC12  
—
6090 PORTC  
31:16  
60A0  
60B0  
LATC  
15:0 LATC15  
31:16  
LATC14  
—
LATC13  
—
LATC12  
—
—
ODCC  
15:0 ODCC15 ODCC14 ODCC13 ODCC12  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more  
information.  
TABLE 4-25: PORTD REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L,  
(1)  
PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
—
—
—
—
—
—
—
TRISD9  
—
—
TRISD8  
—
—
TRISD7  
—
—
TRISD6  
—
—
TRISD5  
—
—
TRISD4  
—
—
TRISD3  
—
—
TRISD2  
—
—
TRISD1  
—
—
0000  
60C0 TRISD  
60D0 PORTD  
15:0 TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10  
TRISD0 FFFF  
31:16  
15:0  
—
RD15  
—
—
RD14  
—
—
RD13  
—
—
RD12  
—
—
RD11  
—
—
RD10  
—
—
RD0  
—
0000  
xxxx  
0000  
xxxx  
0000  
RD9  
—
RD8  
—
RD7  
—
RD6  
—
RD5  
—
RD4  
—
RD3  
—
RD2  
—
RD1  
—
31:16  
60E0  
60F0  
LATD  
15:0 LATD15  
31:16  
LATD14  
—
LATD13  
—
LATD12  
—
LATD11  
—
LATD10  
—
LATD9  
—
LATD8  
—
LATD7  
—
LATD6  
—
LATD5  
—
LATD4  
—
LATD3  
—
LATD2  
—
LATD1  
—
LATD0  
—
—
ODCD  
15:0 ODCD15 ODCD14 ODCD13 ODCD12 ODCD11 ODCD10  
ODCD9  
ODCD8  
ODCD7  
ODCD6  
ODCD5  
ODCD4  
ODCD3  
ODCD2  
ODCD1  
ODCD0 0000  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more  
information.  
TABLE 4-26: PORTD REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H,  
PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H AND PIC32MX440F512H  
(1)  
DEVICES ONLY  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISD9  
—
—
TRISD8  
—
—
TRISD7  
—
—
TRISD6  
—
—
TRISD5  
—
—
TRISD4  
—
—
TRISD3  
—
—
TRISD2  
—
—
TRISD1  
—
—
0000  
60C0 TRISD  
60D0 PORTD  
TRISD11 TRISD10  
TRISD0 0FFF  
31:16  
15:0  
—
RD11  
—
—
RD10  
—
—
RD0  
—
0000  
xxxx  
0000  
xxxx  
0000  
RD9  
—
RD8  
—
RD7  
—
RD6  
—
RD5  
—
RD4  
—
RD3  
—
RD2  
—
RD1  
—
31:16  
15:0  
60E0  
60F0  
LATD  
LATD11  
—
LATD10  
—
LATD9  
—
LATD8  
—
LATD7  
—
LATD6  
—
LATD5  
—
LATD4  
—
LATD3  
—
LATD2  
—
LATD1  
—
LATD0  
—
31:16  
15:0  
ODCD  
ODCD11 ODCD10  
ODCD9  
ODCD8  
ODCD7  
ODCD6  
ODCD5  
ODCD4  
ODCD3  
ODCD2  
ODCD1  
ODCD0 0000  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more  
information.  
TABLE 4-27: PORTE REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L,  
(1)  
PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISE9  
—
—
TRISE8  
—
—
TRISE7  
—
—
TRISE6  
—
—
TRISE5  
—
—
TRISE4  
—
—
TRISE3  
—
—
TRISE2  
—
—
TRISE1  
—
—
0000  
6100  
TRISE  
TRISE0 03FF  
31:16  
15:0  
—
RE0  
—
0000  
xxxx  
0000  
xxxx  
0000  
6110 PORTE  
RE9  
RE8  
RE7  
—
RE6  
RE5  
RE4  
RE3  
RE2  
RE1  
31:16  
15:0  
—
—
—
—
—
—
—
—
6120  
6130  
LATE  
LATE9  
—
LATE8  
—
LATE7  
—
LATE6  
—
LATE5  
—
LATE4  
—
LATE3  
—
LATE2  
—
LATE1  
—
LATE0  
—
31:16  
15:0  
ODCE  
ODCE9  
ODCE8  
ODCE7  
ODCE6  
ODCE5  
ODCE4  
ODCE3  
ODCE2  
ODCE1  
ODCE0 0000  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more  
information.  
TABLE 4-28: PORTE REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H,  
PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H AND PIC32MX440F512H  
(1)  
DEVICES ONLY  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISE7  
—
—
TRISE6  
—
—
TRISE5  
—
—
TRISE4  
—
—
TRISE3  
—
—
TRISE2  
—
—
TRISE1  
—
—
0000  
6100  
TRISE  
TRISE0 00FF  
31:16  
15:0  
—
RE0  
—
0000  
xxxx  
0000  
xxxx  
0000  
6110 PORTE  
RE7  
—
RE6  
RE5  
RE4  
RE3  
RE2  
RE1  
31:16  
15:0  
—
—
—
—
—
—
6120  
6130  
LATE  
LATE7  
—
LATE6  
—
LATE5  
—
LATE4  
—
LATE3  
—
LATE2  
—
LATE1  
—
LATE0  
—
31:16  
15:0  
ODCE  
ODCE7  
ODCE6  
ODCE5  
ODCE4  
ODCE3  
ODCE2  
ODCE1  
ODCE0 0000  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more  
information.  
TABLE 4-29: PORTF REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L AND PIC32MX360F512L DEVICES  
(1)  
ONLY  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISF8  
—
—
TRISF7  
—
—
TRISF6  
—
—
TRISF5  
—
—
TRISF4  
—
—
TRISF3  
—
—
TRISF2  
—
—
TRISF1  
—
—
0000  
6140  
TRISF  
TRISF13 TRISF12  
TRISF0 31FF  
31:16  
15:0  
—
RF13  
—
—
RF12  
—
—
RF0  
—
0000  
xxxx  
0000  
xxxx  
0000  
6150 PORTF  
RF8  
RF7  
RF6  
RF5  
RF4  
RF3  
RF2  
RF1  
31:16  
15:0  
—
—
—
—
—
—
—
—
6160  
6170  
LATF  
LATF13  
—
LATF12  
—
LATF8  
—
LATF7  
—
LATF6  
—
LATF5  
—
LATF4  
—
LATF3  
—
LATF2  
—
LATF1  
—
LATF0  
—
31:16  
15:0  
ODCF  
ODCF13 ODCF12  
ODCF8  
ODCF7  
ODCF6  
ODCF5  
ODCF4  
ODCF3  
ODCF2  
ODCF1  
ODCF0 0000  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more  
information.  
(1)  
TABLE 4-30: PORTF REGISTERS MAP FOR PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISF8  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISF5  
—
—
TRISF4  
—
—
TRISF3  
—
—
TRISF2  
—
—
TRISF1  
—
—
0000  
6140  
TRISF  
TRISF13 TRISF12  
TRISF0 313F  
31:16  
15:0  
—
RF13  
—
—
RF12  
—
—
RF0  
—
0000  
xxxx  
0000  
xxxx  
0000  
6150 PORTF  
RF8  
RF5  
RF4  
RF3  
RF2  
RF1  
31:16  
15:0  
—
—
—
—
—
—
6160  
6170  
LATF  
LATF13  
—
LATF12  
—
LATF8  
—
LATF5  
—
LATF4  
—
LATF3  
—
LATF2  
—
LATF1  
—
LATF0  
—
31:16  
15:0  
ODCF  
ODCF13 ODCF12  
ODCF8  
ODCF5  
ODCF4  
ODCF3  
ODCF2  
ODCF1  
ODCF0 0000  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more  
information.  
TABLE 4-31: PORTF REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H,  
(1)  
PIC32MX340F256H AND PIC32MX340F512H DEVICES ONLY  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISF6  
—
—
TRISF5  
—
—
TRISF4  
—
—
TRISF3  
—
—
TRISF2  
—
—
TRISF1  
—
—
0000  
6140  
TRISF  
TRISF0 07FF  
31:16  
15:0  
—
RF0  
—
0000  
xxxx  
0000  
xxxx  
0000  
6150 PORTF  
RF6  
RF5  
RF4  
RF3  
RF2  
RF1  
31:16  
15:0  
—
—
—
—
—
—
6160  
6170  
LATF  
LATF6  
—
LATF5  
—
LATF4  
—
LATF3  
—
LATF2  
—
LATF1  
—
LATF0  
—
31:16  
15:0  
ODCF  
ODCF6  
ODCF5  
ODCF4  
ODCF3  
ODCF2  
ODCF1  
ODCF0 0000  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more  
information.  
(1)  
TABLE 4-32: PORTF REGISTERS MAP FOR PIC32MX420F032H, PIC32MX440F128H AND PIC2MX440F256H DEVICES ONLY  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISF5  
—
—
TRISF4  
—
—
TRISF3  
—
—
TRISF2  
—
—
TRISF1  
—
—
0000  
6140  
TRISF  
TRISF0 03FF  
31:16  
15:0  
—
RF0  
—
0000  
xxxx  
0000  
xxxx  
0000  
6150 PORTF  
RF5  
RF4  
RF3  
RF2  
RF1  
31:16  
15:0  
—
—
—
—
—
6160  
6170  
LATF  
LATF5  
—
LATF4  
—
LATF3  
—
LATF2  
—
LATF1  
—
LATF0  
—
31:16  
15:0  
ODCF  
ODCF5  
ODCF4  
ODCF3  
ODCF2  
ODCF1  
ODCF0 0000  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more  
information.  
TABLE 4-33: PORTG REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L,  
(1)  
PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISG9  
—
—
TRISG8  
—
—
TRISG7  
—
—
TRISG6  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISG3  
—
—
TRISG2  
—
—
TRISG1  
—
—
0000  
6180  
TRISG  
15:0 TRISG15 TRISG14 TRISG13 TRISG12  
TRISG0 F3CF  
31:16  
15:0  
—
RG15  
—
—
RG14  
—
—
RG13  
—
—
RG12  
—
—
RG0  
—
0000  
xxxx  
0000  
6190 PORTG  
RG9  
—
RG8  
—
RG7  
—
RG6  
—
RG3  
—
RG2  
—
RG1  
—
31:16  
61A0  
61B0  
LATG  
15:0 LATG15  
31:16  
LATG14  
—
LATG13  
—
LATG12  
—
LATG9  
—
LATG8  
—
LATG7  
—
LATG6  
—
LATG3  
—
LATG2  
—
LATG1  
—
LATG0 xxxx  
0000  
ODCG0 0000  
—
—
ODCG  
15:0 ODCG15 ODCG14 ODCG13 ODCG12  
ODCG9  
ODCG8  
ODCG7  
ODCG6  
ODCG3  
ODCG2  
ODCG1  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more  
information.  
TABLE 4-34: PORTG REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H,  
PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H AND PIC32MX440F512H  
(1)  
DEVICES ONLY  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISG9  
—
—
TRISG8  
—
—
TRISG7  
—
—
TRISG6  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISG3  
—
—
TRISG2  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000  
03cc  
0000  
xxxx  
0000  
xxxx  
0000  
0000  
6180  
TRISG  
31:16  
15:0  
6190 PORTG  
RG9  
—
RG8  
—
RG7  
—
RG6  
—
RG3  
—
RG2  
—
31:16  
15:0  
61A0  
61B0  
LATG  
LATG9  
—
LATG8  
—
LATG7  
—
LATG6  
—
LATG3  
—
LATG2  
—
31:16  
15:0  
ODCG  
ODCG9  
ODCG8  
ODCG7  
ODCG6  
ODCG3  
ODCG2  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more  
information.  
TABLE 4-35: CHANGE NOTICE AND PULL-UP REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L,  
(1)  
PIC32MX360F512L, PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
ON  
—
—
—
—
—
SIDL  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000  
0000  
61C0 CNCON  
31:16  
—
—
—
—
—
—
CNEN21 CNEN20 CNEN19 CNEN18 CNEN17 CNEN16 0000  
CNEN5 CNEN4 CNEN3 CNEN2 CNEN1 CNEN0 0000  
CNPUE21 CNPUE20 CNPUE19 CNPUE18 CNPUE17 CNPUE16 0000  
61D0  
CNEN  
15:0 CNEN15 CNEN14 CNEN13 CNEN12  
31:16  
CNEN11  
—
CNEN10  
—
CNEN9  
—
CNEN8  
—
CNEN7  
—
CNEN6  
—
—
—
—
—
61E0 CNPUE  
15:0 CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10 CNPUE9 CNPUE8 CNPUE7 CNPUE6 CNPUE5 CNPUE4 CNPUE3 CNPUE2 CNPUE1 CNPUE1 0000  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more  
information.  
TABLE 4-36: CHANGE NOTICE AND PULL-UP REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H,  
PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H  
(1)  
AND PIC32MX440F512H DEVICES ONLY  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
ON  
—
—
—
—
—
SIDL  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000  
0000  
61C0 CNCON  
31:16  
—
—
—
—
—
—
—
—
—
CNEN18 CNEN17 CNEN16 0000  
CNEN2 CNEN1 CNEN0 0000  
CNPUE18 CNPUE17 CNPUE16 0000  
61D0  
CNEN  
15:0 CNEN15 CNEN14 CNEN13 CNEN12  
31:16  
CNEN11  
—
CNEN10  
—
CNEN9  
—
CNEN8  
—
CNEN7  
—
CNEN6  
—
CNEN5  
—
CNEN4  
—
CNEN3  
—
—
—
—
—
61E0 CNPUE  
15:0 CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10 CNPUE9 CNPUE8 CNPUE7 CNPUE6 CNPUE5 CNPUE4 CNPUE3 CNPUE2 CNPUE1 CNPUE1 0000  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more  
information.  
(1)  
TABLE 4-37: PARALLEL MASTER PORT REGISTERS MAP  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
ON  
—
—
—
—
—
SIDL  
—
—
—
—
—
—
—
—
—
—
ALP  
—
—
CS2P  
—
—
CS1P  
—
—
—
—
—
WRSP  
—
—
RDSP  
—
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
008F  
7000 PMCON  
7010 PMMODE  
7020 PMADDR  
7030 PMDOUT  
ADRMUX<1:0>  
PMPTTL PTWREN PTRDEN  
CSF<1:0>  
31:16  
15:0  
—
—
—
MODE16  
—
—
—
—
BUSY  
—
IRQM<1:0>  
—
INCM<1:0>  
MODE<1:0>  
WAITB<1:0>  
WAITM<3:0>  
— —  
WAITE<1:0>  
— —  
31:16  
—
—
—
—
—
—
—
—
—
15:0 CS2EN/A15 CS1EN/A14  
ADDR<13:0>  
31:16  
15:0  
DATAOUT<31:0>  
DATAIN<31:0>  
31:16  
15:0  
7040  
PMDIN  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
7050 PMAEN  
7060 PMSTAT  
PTEN<15:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IBF  
IBOV  
IB3F  
IB2F  
IB1F  
IB0F  
OBE  
OBUF  
OB3E  
OB2E  
OB1E  
OB0E  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more  
information.  
TABLE 4-38: PROGRAMMING AND DIAGNOSTICS REGISTERS MAP  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000  
0008  
F200 DDPCON  
Legend:  
JTAGEN  
TROEN  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
TABLE 4-39: PREFETCH REGISTERS MAP  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHECOH 0000  
4000 CHECON(1)  
4010 CHEACC(1)  
4020 CHETAG(1)  
4030 CHEMSK(1)  
DCSZ<1:0>  
PREFEN<1:0>  
PFMWS<2:0>  
0007  
31:16 CHEWEN  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000  
00xx  
CHEIDX<3:0>  
15:0  
31:16  
15:0  
—
LTAGBOOT  
LTAG<23:16>  
LVALID  
xxx0  
xxx2  
LTAG<15:4>  
LLOCK  
LTYPE  
—
—
—
—
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000  
xxxx  
xxxx  
xxxx  
xxxx  
xxxx  
xxxx  
xxxx  
xxxx  
xxxx  
0000  
0000  
xxxx  
xxxx  
xxxx  
xxxx  
xxxx  
xxxx  
LMASK<15:5>  
—
—
31:16  
15:0  
4040  
4050  
4060  
4070  
CHEW0  
CHEW1  
CHEW2  
CHEW3  
CHEW0<31:0>  
CHEW1<31:0>  
CHEW2<31:0>  
CHEW3<31:0>  
31:16  
15:0  
31:16  
15:0  
31:16  
15:0  
—
—
—
—
—
—
—
CHELRU<24:16>  
31:16  
15:0  
4080 CHELRU  
CHELRU<15:0>  
CHEHIT<31:0>  
31:16  
15:0  
4090  
40A0  
CHEHIT  
CHEMIS  
31:16  
15:0  
CHEMIS<31:0>  
31:16  
15:0  
40C0 CHEPFABT  
CHEPFABT<31:0>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.  
(1)  
TABLE 4-40: RTCC REGISTERS MAP  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
ON  
—
—
—
—
SIDL  
—
—
—
—
—
—
—
—
CAL<11:0>  
0000  
RTCWREN RTCSYNC HALFSEC RTCOE 0000  
0200 RTCCON  
0210 RTCALRM  
0220 RTCTIME  
0230 RTCDATE  
0240 ALRMTIME  
0250 ALRMDATE  
—
—
—
—
—
—
RTSECSEL RTCCLKON  
—
—
—
—
31:16  
—
—
—
—
—
—
—
0000  
0000  
xxxx  
xx00  
xxxx  
xx0x  
xxxx  
xx00  
00xx  
xx0x  
15:0 ALRMEN  
31:16  
CHIME  
PIV  
ALRMSYNC  
AMASK<3:0>  
ARPT<7:0>  
HR10<3:0>  
HR01<3:0>  
SEC01<3:0>  
YEAR01<3:0>  
DAY01<3:0>  
MIN01<3:0>  
SEC01<3:0>  
MIN10<3:0>  
MIN01<3:0>  
15:0  
SEC10<3:0>  
YEAR10<3:0>  
DAY10<3:0>  
MIN10<3:0>  
SEC10<3:0>  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16  
MONTH10<3:0>  
MONTH01<3:0>  
WDAY01<3:0>  
MIN01<3:0>  
15:0  
—
—
31:16  
MIN10<3:0>  
15:0  
—
—
—
—
—
—
31:16  
15:0  
—
—
—
—
—
—
—
—
MONTH10<3:0>  
MONTH01<3:0>  
WDAY01<3:0>  
DAY10<3:0>  
DAY01<3:0>  
—
—
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more  
information.  
TABLE 4-41: DEVCFG: DEVICE CONFIGURATION WORD SUMMARY  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
xxxx  
2FF0 DEVCFG3  
2FF4 DEVCFG2  
2FF8 DEVCFG1  
2FFC DEVCFG0  
15:0 USERID15 USERID14 USERID13 USERID12 USERID11 USERID10 USERID9 USERID8 USERID7 USERID6 USERID5 USERID4 USERID3 USERID2 USERID1 USERID0 xxxx  
31:16  
15:0 UPLLEN(1)  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UPLLIDIV<2:0>(1)  
—
—
—
—
—
—
—
—
—
FPLLODIV<2:0>  
FPLLIDIV<2:0>  
xxxx  
xxxx  
FPLLMUL<2:0>  
31:16  
15:0  
—
—
—
FWDTEN  
IESO  
—
—
—
—
—
—
WDTPS<4:0>  
xxxx  
FCKSM<1:0>  
FPBDIV<1:0>  
OSCIOFNC  
POSCMOD<1:0>  
FSOSCEN  
—
—
—
—
FNOSC<2:0>  
PWP17  
xxxx  
31:16  
15:0  
—
—
—
CP  
—
—
—
—
BWP  
—
—
—
PWP19  
ICESEL  
PWP18  
—
PWP16 xxxx  
PWP15  
PWP14  
PWP13  
PWP12  
—
DEBUG<1:0>  
xxxx  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
These bits are only available on PIC32MX4XX devices.  
TABLE 4-42: DEVICE AND REVISION ID SUMMARY  
Bits  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
23/7  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
VER<3:0>  
DEVID<27:16>  
xxxx  
xxxx  
F220  
DEVID  
DEVID<15:0>  
Legend:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
(1)  
TABLE 4-43: USB REGISTERS MAP  
Bits  
23/7  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IDIF  
—
—
—
—
ACTVIF  
—
—
—
—
—
—
—
—
—
—
—
U1OTG  
IR(2)  
5040  
5050  
5060  
5070  
T1MSECIF LSTATEIF  
SESVDIF SESENDIF  
VBUSVDIF 0000  
31:16  
15:0  
—
—
—
—
—
0000  
VBUSVDIE 0000  
0000  
VBUSVD 0000  
0000  
U1OTG  
IE  
IDIE  
—
T1MSECIE LSTATEIE  
ACTVIE  
—
SESVDIE SESENDIE  
31:16  
15:0  
—
—
—
—
LSTATE  
—
—
SESVD  
—
—
SESEND  
—
—
U1OTG  
STAT(3)  
ID  
—
31:16  
15:0  
—
—
—
U1OTG  
CON  
DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON  
OTGEN VBUSCHG VBUSDIS 0000  
31:16  
15:0  
—
UACTPND(4)  
—
—
—
—
—
—
—
—
USLPGRD  
—
—
—
—
—
—
—
—
—
0000  
5080 U1PWRC  
USUSPEND USBPWR 0000  
31:16  
—
—
0000  
5200  
5210  
5220  
5230  
U1IR(2)  
U1IE  
URSTIF 0000  
DETACHIF 0000  
15:0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
STALLIF ATTACHIF RESUMEIF  
IDLEIF  
—
TRNIF  
—
SOFIF  
—
UERRIF  
—
—
—
—
—
0000  
URSTIE 0000  
DETACHIE 0000  
STALLIE ATTACHIE RESUMEIE  
IDLEIE  
—
TRNIE  
—
SOFIE  
—
UERRIE  
31:16  
15:0  
—
BTSEF  
—
—
BMXEF  
—
—
DMAEF  
—
—
CRC5EF  
EOFEF  
—
—
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
U1EIR  
U1EIE  
BTOEF  
—
DFN8EF CRC16EF  
PIDEF  
—
31:16  
15:0  
—
—
CRC5EE  
EOFEE  
—
BTSEE  
—
BMXEE  
DMAEE  
BTOEE  
—
DFN8EE CRC16EE  
PIDEE  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DIR  
—
—
PPBI  
—
—
—
—
5240 U1STAT(3)  
5250 U1CON  
ENDPT<3:0>(4)  
—
31:16  
—
—
SE0(4)  
—
—
PKTDIS  
TOKBUSY  
—
—
USBRST  
—
—
USBEN 0000  
SOFEN 0000  
15:0  
—
—
—
—
—
—
—
—
JSTATE(4)  
HOSTEN RESUME  
PPBRST  
—
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LSPDEN  
—
—
—
—
—
0000  
0000  
0000  
0000  
5260 U1ADDR  
5270 U1BDTP1  
DEVADDR<6:0>  
—
31:16  
15:0  
—
—
—
—
—
—
BDTPTRL<7:1>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV  
Registers” for more information.  
2:  
3:  
4:  
This register does not have associated CLR, SET, and INV registers.  
All bits in this register are read-only; therefore, CLR, SET, and INV registers are not supported.  
The reset value for this bit is undefined.  
(1)  
TABLE 4-43: USB REGISTERS MAP (CONTINUED)  
Bits  
23/7  
—
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
5280 U1FRML(3)  
5290 U1FRMH(3)  
52A0 U1TOK  
52B0 U1SOF  
52C0 U1BDTP2  
52D0 U1BDTP3  
52E0 U1CNFG1  
FRML<7:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FRMH<10:8>  
—
31:16  
15:0  
PID<3:0>  
EP<3:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNT<7:0>  
31:16  
15:0  
—
BDTPTRH<7:0>  
31:16  
15:0  
—
—
BDTPTRU<7:0>  
31:16  
15:0  
—
UTEYE  
—
—
USBSIDL  
—
—
—
—
—
—
—
—
—
—
—
UOEMON USBFRZ  
—
—
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5300  
5310  
5320  
5330  
5340  
5350  
5360  
5370  
U1EP0  
U1EP1  
U1EP2  
U1EP3  
U1EP4  
U1EP5  
U1EP6  
U1EP7  
LSPD  
—
RETRYDIS  
EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000  
0000  
EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000  
0000  
EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000  
0000  
EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000  
0000  
EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000  
0000  
EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000  
0000  
EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000  
0000  
EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16  
15:0  
—
—
—
—
—
—
—
31:16  
15:0  
—
—
—
—
—
—
—
31:16  
15:0  
—
—
—
—
—
—
—
31:16  
15:0  
—
—
—
—
—
—
—
31:16  
15:0  
—
—
—
—
—
—
—
31:16  
15:0  
—
—
—
—
—
—
—
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV  
Registers” for more information.  
2:  
3:  
4:  
This register does not have associated CLR, SET, and INV registers.  
All bits in this register are read-only; therefore, CLR, SET, and INV registers are not supported.  
The reset value for this bit is undefined.  
(1)  
TABLE 4-43: USB REGISTERS MAP (CONTINUED)  
Bits  
23/7  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
25/9  
24/8  
22/6  
21/5  
20/4  
19/3  
18/2  
17/1  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000  
5380  
5390  
U1EP8  
U1EP9  
EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000  
0000  
EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000  
0000  
EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000  
0000  
EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000  
0000  
EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000  
0000  
EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000  
0000  
EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000  
0000  
EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000  
31:16  
15:0  
—
—
—
—
—
31:16  
15:0  
—
—
—
—
—
53A0 U1EP10  
53B0 U1EP11  
53C0 U1EP12  
53D0 U1EP13  
53E0 U1EP14  
53F0 U1EP15  
31:16  
15:0  
—
—
—
—
—
31:16  
15:0  
—
—
—
—
—
31:16  
15:0  
—
—
—
—
—
31:16  
15:0  
—
—
—
—
—
31:16  
15:0  
—
—
—
—
—
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV  
Registers” for more information.  
2:  
3:  
4:  
This register does not have associated CLR, SET, and INV registers.  
All bits in this register are read-only; therefore, CLR, SET, and INV registers are not supported.  
The reset value for this bit is undefined.  
PIC32MX3XX/4XX  
RTSP is performed by software executing from either  
Flash or RAM memory. EJTAG is performed using the  
EJTAG port of the device and a EJTAG capable  
programmer. ICSP is performed using a serial data  
connection to the device and allows much faster pro-  
gramming times than RTSP. RTSP techniques are  
described in this chapter. The ICSP and EJTAG  
methods are described in the “PIC32MX Flash  
Programming Specification” (DS61145), which can be  
downloaded from the Microchip web site.  
5.0  
FLASH PROGRAM MEMORY  
Note 1: This data sheet summarizes the features  
of the PIC32MX3XX/4XX family of  
devices. It is not intended to be a compre-  
hensive reference source. To comple-  
ment the information in this data sheet,  
refer to Section 5. “Flash Program  
Memory” (DS61121) of the “PIC32  
Family Reference Manual”, which is  
available from the Microchip web site  
(www.microchip.com/PIC32).  
Note:  
Flash LVD Delay (LVDstartup) must be  
taken into account between setting up and  
executing any Flash command operation.  
See Example 5-1 for a code example to  
set up and execute a Flash command  
operation.  
2: Some registers and associated bits  
described in this section may not be  
available on all devices. Refer to  
Section 4.0 “Memory Organization” in  
this data sheet for device-specific register  
and bit information.  
PIC32MX3XX/4XX devices contain an internal  
program Flash memory for executing user code. There  
are three methods by which the user can program this  
memory:  
• Run-Time Self Programming (RTSP)  
• In-Circuit Serial Programming™ (ICSP™)  
• EJTAG Programming  
EXAMPLE 5-1:  
NVMCON = 0x4004;  
Wait(delay);  
// Enable and configure for erase operation  
// Delay for 6 µs for LVDstartup  
NVMKEY = 0xAA996655;  
NVMKEY = 0x556699AA;  
NVMCONSET = 0x8000;  
// Initiate operation  
while(NVMCONbits.WR==1); // Wait for current operation to complete  
© 2011 Microchip Technology Inc.  
DS61143H-page 85  
PIC32MX3XX/4XX  
NOTES:  
DS61143H-page 86  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
The Reset module combines all Reset sources and  
controls the device Master Reset signal, SYSRST. The  
following is a list of device Reset sources:  
6.0  
RESETS  
Note 1: This data sheet summarizes the features  
of the PIC32MX3XX/4XX family of  
devices. It is not intended to be a  
comprehensive reference source. To  
complement the information in this data  
sheet, refer to Section 7. “Resets”  
(DS61118) of the “PIC32 Family  
Reference Manual”, which is available  
• POR: Power-on Reset  
• MCLR: Master Clear Reset Pin  
• SWR: Software Reset  
• WDTR: Watchdog Timer Reset  
• BOR: Brown-out Reset  
• CMR: Configuration Mismatch Reset  
from  
the  
Microchip  
web  
site  
A simplified block diagram of the Reset module is  
illustrated in Figure 6-1.  
(www.microchip.com/PIC32).  
2: Some registers and associated bits  
described in this section may not be  
available on all devices. Refer to  
Section 4.0 “Memory Organization” in  
this data sheet for device-specific register  
and bit information.  
FIGURE 6-1:  
SYSTEM RESET BLOCK DIAGRAM  
MCLR  
MCLR  
WDTR  
Glitch Filter  
Sleep or Idle  
WDT  
Time-out  
Voltage  
Regulator  
Enabled  
POR  
Power-up  
Timer  
SYSRST  
VDD  
VDD Rise  
Detect  
BOR  
Brown-out  
Reset  
Configuration  
Mismatch  
Reset  
CMR  
SWR  
Software Reset  
© 2011 Microchip Technology Inc.  
DS61143H-page 87  
PIC32MX3XX/4XX  
NOTES:  
DS61143H-page 88  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
PIC32MX3XX/4XX devices generate interrupt requests  
in response to interrupt events from peripheral mod-  
ules. The Interrupt Control module exists externally to  
the CPU logic and prioritizes the interrupt events before  
presenting them to the CPU.  
7.0  
INTERRUPT CONTROLLER  
Note 1: This data sheet summarizes the features  
of the PIC32MX3XX/4XX family of  
devices. It is not intended to be a  
comprehensive reference source. To  
complement the information in this data  
sheet, refer to Section 8. “Interrupt  
Controller” (DS61108) of the “PIC32  
Family Reference Manual”, which is  
available from the Microchip web site  
(www.microchip.com/PIC32).  
The PIC32MX3XX/4XX interrupts module includes the  
following features:  
• Up to 96 interrupt sources  
• Up to 64 interrupt vectors  
• Single and Multi-Vector mode operations  
• Five external interrupts with edge polarity control  
• Interrupt proximity timer  
2: Some registers and associated bits  
described in this section may not be  
available on all devices. Refer to  
Section 4.0 “Memory Organization” in  
this data sheet for device-specific register  
and bit information.  
• Module Freeze in Debug mode  
• Seven user-selectable priority levels for each  
vector  
• Four user-selectable subpriority levels within each  
priority  
• Dedicated shadow set for highest priority level  
• Software can generate any interrupt  
• User-configurable interrupt vector table location  
• User-configurable interrupt vector spacing  
FIGURE 7-1:  
INTERRUPT CONTROLLER MODULE  
Vector Number  
Interrupt Controller  
CPU Core  
Priority Level  
Shadow Set Number  
Note: Several of the registers cited in this section are not in the interrupt controller module. These registers (and  
bits) are associated with the CPU. Details about them are available in Section 3.0 “CPU”.  
To avoid confusion, a typographic distinction is made for registers in the CPU. The register names in this  
section, and all other sections of this manual, are signified by uppercase letters only. The CPU register  
names are signified by upper and lowercase letters. For example, INTSTAT is an Interrupts register;  
whereas, IntCtl is a CPU register.  
© 2011 Microchip Technology Inc.  
DS61143H-page 89  
PIC32MX3XX/4XX  
TABLE 7-1:  
INTERRUPT IRQ AND VECTOR LOCATION  
Vector  
Number  
Interrupt Source(1)  
IRQ  
Interrupt Bit Location  
Highest Natural Order Priority  
Flag  
Enable  
Priority  
Subpriority  
CT – Core Timer Interrupt  
0
0
IFS0<0>  
IFS0<1>  
IFS0<2>  
IFS0<3>  
IFS0<4>  
IFS0<5>  
IFS0<6>  
IFS0<7>  
IFS0<8>  
IFS0<9>  
IFS0<10>  
IFS0<11>  
IFS0<12>  
IFS0<13>  
IFS0<14>  
IFS0<15>  
IFS0<16>  
IFS0<17>  
IFS0<18>  
IFS0<19>  
IFS0<20>  
IFS0<21>  
IFS0<22>  
IFS0<23>  
IFS0<24>  
IFS0<25>  
IFS0<26>  
IFS0<27>  
IFS0<28>  
IFS0<29>  
IFS0<30>  
IFS0<31>  
IFS1<0>  
IFS1<1>  
IFS1<2>  
IFS1<3>  
IFS1<4>  
IEC0<0>  
IEC0<1>  
IEC0<2>  
IEC0<3>  
IEC0<4>  
IEC0<5>  
IEC0<6>  
IEC0<7>  
IEC0<8>  
IEC0<9>  
IEC0<10>  
IEC0<11>  
IEC0<12>  
IEC0<13>  
IEC0<14>  
IEC0<15>  
IEC0<16>  
IEC0<17>  
IEC0<18>  
IEC0<19>  
IEC0<20>  
IEC0<21>  
IEC0<22>  
IEC0<23>  
IEC0<24>  
IEC0<25>  
IEC0<26>  
IEC0<27>  
IEC0<28>  
IEC0<29>  
IEC0<30>  
IEC0<31>  
IEC1<0>  
IEC1<1>  
IEC1<2>  
IEC1<3>  
IEC1<4>  
IPC0<4:2>  
IPC0<12:10>  
IPC0<20:18>  
IPC0<28:26>  
IPC1<4:2>  
IPC0<1:0>  
IPC0<9:8>  
CS0 – Core Software Interrupt 0  
CS1 – Core Software Interrupt 1  
INT0 – External Interrupt 0  
T1 – Timer1  
1
1
2
2
IPC0<17:16>  
IPC0<25:24>  
IPC1<1:0>  
3
3
4
4
IC1 – Input Capture 1  
5
5
IPC1<12:10>  
IPC1<20:18>  
IPC1<28:26>  
IPC2<4:2>  
IPC1<9:8>  
OC1 – Output Compare 1  
INT1 – External Interrupt 1  
T2 – Timer2  
6
6
IPC1<17:16>  
IPC1<25:24>  
IPC2<1:0>  
7
7
8
8
IC2 – Input Capture 2  
9
9
IPC2<12:10>  
IPC2<20:18>  
IPC2<28:26>  
IPC3<4:2>  
IPC2<9:8>  
OC2 – Output Compare 2  
INT2 – External Interrupt 2  
T3 – Timer3  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
23  
23  
24  
24  
24  
25  
25  
25  
26  
27  
28  
29  
30  
IPC2<17:16>  
IPC2<25:24>  
IPC3<1:0>  
IC3 – Input Capture 3  
IPC3<12:10>  
IPC3<20:18>  
IPC3<28:26>  
IPC4<4:2>  
IPC3<9:8>  
OC3 – Output Compare 3  
INT3 – External Interrupt 3  
T4 – Timer4  
IPC3<17:16>  
IPC3<25:24>  
IPC4<1:0>  
IC4 – Input Capture 4  
IPC4<12:10>  
IPC4<20:18>  
IPC4<28:26>  
IPC5<4:2>  
IPC4<9:8>  
OC4 – Output Compare 4  
INT4 – External Interrupt 4  
T5 – Timer5  
IPC4<17:16>  
IPC4<25:24>  
IPC5<1:0>  
IC5 – Input Capture 5  
IPC5<12:10>  
IPC5<20:18>  
IPC5<28:26>  
IPC5<28:26>  
IPC5<28:26>  
IPC6<4:2>  
IPC5<9:8>  
OC5 – Output Compare 5  
SPI1E – SPI1 Fault  
IPC5<17:16>  
IPC5<25:24>  
IPC5<25:24>  
IPC5<25:24>  
IPC6<1:0>  
SPI1TX – SPI1 Transfer Done  
SPI1RX – SPI1 Receive Done  
U1E – UART1 Error  
U1RX – UART1 Receiver  
U1TX – UART1 Transmitter  
I2C1B – I2C1 Bus Collision Event  
I2C1S – I2C1 Slave Event  
I2C1M – I2C1 Master Event  
CN – Input Change Interrupt  
AD1 – ADC1 Convert Done  
PMP – Parallel Master Port  
CMP1 – Comparator Interrupt  
CMP2 – Comparator Interrupt  
IPC6<4:2>  
IPC6<1:0>  
IPC6<4:2>  
IPC6<1:0>  
IPC6<12:10>  
IPC6<12:10>  
IPC6<12:10>  
IPC6<20:18>  
IPC6<28:26>  
IPC7<4:2>  
IPC6<9:8>  
IPC6<9:8>  
IPC6<9:8>  
IPC6<17:16>  
IPC6<25:24>  
IPC7<1:0>  
IPC7<12:10>  
IPC7<20:18>  
IPC7<9:8>  
IPC7<17:16>  
Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MX General Purpose –  
Features” and TABLE 2: “PIC32MX USB – Features” for available peripherals.  
DS61143H-page 90  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
TABLE 7-1:  
INTERRUPT IRQ AND VECTOR LOCATION (CONTINUED)  
Vector  
Number  
Interrupt Source(1)  
IRQ  
Interrupt Bit Location  
Highest Natural Order Priority  
Flag  
Enable  
Priority  
Subpriority  
SPI2E – SPI2 Fault  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
31  
31  
31  
32  
32  
32  
33  
33  
33  
34  
35  
IFS1<5>  
IFS1<6>  
IFS1<7>  
IFS1<8>  
IFS1<9>  
IFS1<10>  
IFS1<11>  
IFS1<12>  
IFS1<13>  
IFS1<14>  
IFS1<15>  
IEC1<5>  
IEC1<6>  
IEC1<7>  
IEC1<8>  
IEC1<9>  
IEC1<10>  
IEC1<11>  
IEC1<12>  
IEC1<13>  
IEC1<14>  
IEC1<15>  
IPC7<28:26>  
IPC7<28:26>  
IPC7<28:26>  
IPC8<4:2>  
IPC7<25:24>  
IPC7<25:24>  
IPC7<25:24>  
IPC8<1:0>  
SPI2TX – SPI2 Transfer Done  
SPI2RX – SPI2 Receive Done  
U2E – UART2 Error  
U2RX – UART2 Receiver  
IPC8<4:2>  
IPC8<1:0>  
U2TX – UART2 Transmitter  
I2C2B – I2C2 Bus Collision Event  
I2C2S – I2C2 Slave Event  
I2C2M – I2C2 Master Event  
FSCM – Fail-Safe Clock Monitor  
IPC8<4:2>  
IPC8<1:0>  
IPC8<12:10>  
IPC8<12:10>  
IPC8<12:10>  
IPC8<20:18>  
IPC8<28:26>  
IPC8<9:8>  
IPC8<9:8>  
IPC8<9:8>  
IPC8<17:16>  
IPC8<25:24>  
RTCC – Real-Time Clock and  
Calendar  
DMA0 – DMA Channel 0  
DMA1 – DMA Channel 1  
DMA2 – DMA Channel 2  
DMA3 – DMA Channel 3  
FCE – Flash Control Event  
USB  
48  
49  
50  
51  
56  
57  
36  
37  
38  
39  
44  
45  
IFS1<16>  
IFS1<17>  
IFS1<18>  
IFS1<19>  
IFS1<24>  
IFS1<25>  
IEC1<16>  
IEC1<17>  
IEC1<18>  
IEC1<19>  
IEC1<24>  
IEC1<25>  
IPC9<4:2>  
IPC9<12:10>  
IPC9<20:18>  
IPC9<28:26>  
IPC11<4:2>  
IPC9<1:0>  
IPC9<9:8>  
IPC9<17:16>  
IPC9<25:24>  
IPC11<1:0>  
IPC11<9:8>  
IPC11<12:10>  
Lowest Natural Order Priority  
Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MX General Purpose –  
Features” and TABLE 2: “PIC32MX USB – Features” for available peripherals.  
© 2011 Microchip Technology Inc.  
DS61143H-page 91  
PIC32MX3XX/4XX  
NOTES:  
DS61143H-page 92  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
The PIC32MX oscillator system has the following  
modules and features:  
8.0  
OSCILLATOR  
CONFIGURATION  
• A total of four external and internal oscillator  
options as clock sources  
Note 1: This data sheet summarizes the features  
of the PIC32MX3XX/4XX family of  
devices. It is not intended to be a  
comprehensive reference source. To  
complement the information in this data  
sheet, refer to the “PIC32 Family  
• On-chip PLL (phase-locked loop) with user-  
selectable input divider, multiplier and output  
divider to boost operating frequency on select  
internal and external oscillator sources  
• On-chip user-selectable divisor postscaler on  
select oscillator sources  
Reference  
Manual”  
Section  
6.  
“Oscillator Configuration” (DS61112),  
which is available from the Microchip web  
site (www.microchip.com/PIC32).  
• Software-controllable switching between various  
clock sources  
• A Fail-Safe Clock Monitor (FSCM) that detects  
clock failure and permits safe application recovery  
or shut down  
2: Some registers and associated bits  
described in this section may not be  
available on all devices. Refer to  
Section 4.0 “Memory Organization” in  
this data sheet for device-specific register  
and bit information.  
• Dedicated on-chip PLL for USB peripheral  
FIGURE 8-1:  
PIC32MX3XX/4XX FAMILY CLOCK DIAGRAM  
USB PLL  
USB Clock (48 MHz)  
UFIN  
div 2  
div x  
PLL x24  
UFRCEN  
UFIN = 4 MHz  
UPLLIDIV<2:0>  
UPLLEN  
Primary Oscillator (POSC)  
(3)  
OSC1  
C1  
C2  
XT, HS, EC  
To Internal  
Logic  
4 MHz ≤ FIN ≤ 5 MHz  
FIN  
(2)  
XTPLL, HSPLL,  
ECPLL, FRCPLL  
RF  
Peripherals  
PBCLK  
Postscaler  
div x  
XTAL  
div x  
div y  
PLL  
Enable  
(1)  
S
PLL Input Divider  
FPLLIDIV<2:0>  
PLL Output Divider  
PLLODIV<2:0>  
R
(3)  
(4)  
PBDIV<1:0>  
OSC2  
PLL Multiplier  
PLLMULT<2:0>  
FRC  
Oscillator  
COSC<2:0>  
FRC  
8 MHz typical  
FRC/16  
FRCDIV  
div 16  
TUN<5:0>  
CPU and Select Peripherals  
SYSCLK  
Postscaler  
FRCDIV<2:0>  
31.25 kHz typical  
LPRC  
SOSC  
LPRC  
Oscillator  
Secondary Oscillator (SOSC)  
SOSCO  
SOSCI  
32.768 kHz  
SOSCEN and FSOSCEN  
Clock Control Logic  
FSCM INT  
Fail-Safe  
Clock  
Monitor  
FSCM Event  
Notes: 1. A series resistor, RS, may be required for AT strip-cut crystals.  
2. The internal feedback resistor, RF, is typically in the range of 2 to 10 MΩ.  
3. Refer to the “PIC32 Family Reference Manual” Section 6. “Oscillator  
Configuration” (DS61112) for help determining the best oscillator  
components.  
NOSC<2:0>  
COSC<2:0>  
FSCMEN<1:0>  
OSWEN  
WDT, PWRT  
4. PBCLK out is available on the OSC2 pin in certain clock modes.  
Timer1, RTCC  
© 2011 Microchip Technology Inc.  
DS61143H-page 93  
PIC32MX3XX/4XX  
NOTES:  
DS61143H-page 94  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
Prefetch cache increases performance for applications  
executing out of the cacheable program Flash memory  
regions by implementing instruction caching, constant  
data caching and instruction prefetching.  
9.0  
PREFETCH CACHE  
Note 1: This data sheet summarizes the features  
of the PIC32MX3XX/4XX family of  
devices. It is not intended to be a  
comprehensive reference source. To  
complement the information in this data  
sheet, refer to Section 4. “Prefetch  
Cache” (DS61119) of the “PIC32 Family  
Reference Manual”, which is available  
9.1  
Features  
• 16 Fully Associative Lockable Cache Lines  
• 16-byte Cache Lines  
• Up to four Cache Lines Allocated to Data  
from  
the  
Microchip  
web  
site  
• Two Cache Lines with Address Mask to hold  
repeated instructions  
(www.microchip.com/PIC32).  
2: Some registers and associated bits  
described in this section may not be  
available on all devices. Refer to  
Section 4.0 “Memory Organization” in  
this data sheet for device-specific register  
and bit information.  
• Pseudo LRU replacement policy  
• All Cache Lines are software writable  
• 16-byte parallel memory fetch  
• Predictive Instruction Prefetch  
FIGURE 9-1:  
PREFETCH MODULE BLOCK DIAGRAM  
CTRL  
FSM  
Cache Line  
Tag Logic  
CTRL  
Bus Control  
Cache Control  
Prefetch Control  
Hit LRU  
Cache  
Line  
Address  
Encode  
RDATA  
Miss LRU  
Hit Logic  
Prefetch  
Prefetch  
RDATA  
CTRL  
PFM  
© 2011 Microchip Technology Inc.  
DS61143H-page 95  
PIC32MX3XX/4XX  
NOTES:  
DS61143H-page 96  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
• Automatic Word-Size Detection:  
10.0 DIRECT MEMORY ACCESS  
(DMA) CONTROLLER  
- Transfer Granularity, down to byte level  
- Bytes need not be word-aligned at source  
and destination  
Note 1: This data sheet summarizes the features  
of the PIC32MX3XX/4XX family of  
devices. It is not intended to be a  
comprehensive reference source. To  
complement the information in this data  
sheet, refer to Section 31. “Direct  
Memory Access (DMA) Controller”  
(DS61117) of the “PIC32 Family  
Reference Manual”, which is available  
• Fixed Priority Channel Arbitration  
• Flexible DMA Channel Operating Modes:  
- Manual (software) or automatic (interrupt)  
DMA requests  
- One-Shot or Auto-Repeat Block Transfer  
modes  
- Channel-to-channel chaining  
• Flexible DMA Requests:  
from  
the  
Microchip  
web  
site  
- A DMA request can be selected from any of  
the peripheral interrupt sources  
(www.microchip.com/PIC32).  
2: Some registers and associated bits  
described in this section may not be  
available on all devices. Refer to  
Section 4.0 “Memory Organization” in  
this data sheet for device-specific register  
and bit information.  
- Each channel can select any (appropriate)  
observable interrupt as its DMA request  
source  
- A DMA transfer abort can be selected from  
any of the peripheral interrupt sources  
- Pattern (data) match transfer termination  
• Multiple DMA Channel Status Interrupts:  
- DMA channel block transfer complete  
- Source empty or half empty  
The PIC32MX Direct Memory Access (DMA) controller  
is a bus master module useful for data transfers  
between different devices without CPU intervention.  
The source and destination of a DMA transfer can be  
any of the memory mapped modules existent in the  
PIC32MX (such as Peripheral Bus (PBUS) devices:  
SPI, UART, PMP, and so on) or memory itself.  
- Destination full or half-full  
- DMA transfer aborted due to an external  
event  
- Invalid DMA address generated  
• DMA Debug Support Features:  
Following are some of the key features of the DMA  
controller module:  
- Most recent address accessed by a DMA  
channel  
• Four Identical Channels, each featuring:  
- Auto-Increment Source and Destination  
Address Registers  
- Most recent DMA channel to transfer data  
• CRC Generation Module:  
- Source and Destination Pointers  
- CRC module can be assigned to any of the  
available channels  
- Memory to Memory and Memory to  
Peripheral Transfers  
- CRC module is highly configurable  
FIGURE 10-1:  
DMA BLOCK DIAGRAM  
INT Controller  
System IRQ  
Address  
Decoder  
Channel 0  
Control  
Peripheral Bus  
I
0
Channel 1  
Control  
Bus  
Interface  
I
I
Y
1
Device Bus + Bus Arbitration  
2
Channel n  
Control  
I
Global Control  
(DMACON)  
n
Channel Priority  
Arbitration  
© 2011 Microchip Technology Inc.  
DS61143H-page 97  
PIC32MX3XX/4XX  
NOTES:  
DS61143H-page 98  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
The PIC32MX USB module includes the following  
features:  
11.0 USB ON-THE-GO (OTG)  
Note 1: This data sheet summarizes the features  
of the PIC32MX3XX/4XX family of  
devices. It is not intended to be a compre-  
• USB Full-Speed Support for Host and Device  
• Low-Speed Host Support  
• USB OTG Support  
hensive  
reference  
source.  
To  
• Integrated Signaling Resistors  
complement the information in this data  
sheet, refer to Section 27. “USB On-  
The-Go (OTG)” (DS61126) of the “PIC32  
Family Reference Manual”, which is  
available from the Microchip web site  
(www.microchip.com/PIC32).  
• Integrated Analog Comparators for VBUS  
Monitoring  
• Integrated USB Transceiver  
• Transaction Handshaking Performed by  
Hardware  
2: Some registers and associated bits  
described in this section may not be  
available on all devices. Refer to  
Section 4.0 “Memory Organization” in  
this data sheet for device-specific register  
and bit information.  
• Endpoint Buffering Anywhere in System RAM  
• Integrated DMA to Access System RAM and  
Flash  
Note:  
The implementation and use of the USB  
specifications, as well as other third-party  
specifications or technologies, may  
require licensing; including, but not limited  
to, USB Implementers Forum, Inc. (also  
referred to as USB-IF). The user is fully  
The Universal Serial Bus (USB) module contains ana-  
log and digital components to provide a USB 2.0 full-  
speed and low-speed embedded host, full-speed  
device, or OTG implementation with a minimum of  
external components. This module in Host mode is  
intended for use as an embedded host and therefore  
does not implement a UHCI or OHCI controller.  
responsible  
for  
investigating  
and  
satisfying any applicable licensing  
obligations.  
The USB module consists of the clock generator, the  
USB voltage comparators, the transceiver, the Serial  
Interface Engine (SIE), a dedicated USB DMA control-  
ler, pull-up and pull-down resistors, and the register  
interface. A block diagram of the PIC32MX USB OTG  
module is presented in Figure 11-1.  
The clock generator provides the 48 MHz clock  
required for USB full-speed and low-speed communi-  
cation. The voltage comparators monitor the voltage on  
the VBUS pin to determine the state of the bus. The  
transceiver provides the analog translation between  
the USB bus and the digital logic. The SIE is a state  
machine that transfers data to and from the endpoint  
buffers, and generates the hardware protocol for data  
transfers. The USB DMA controller transfers data  
between the data buffers in RAM and the SIE. The inte-  
grated pull-up and pull-down resistors eliminate the  
need for external signaling components. The register  
interface allows the CPU to configure and  
communicate with the module.  
© 2011 Microchip Technology Inc.  
DS61143H-page 99  
PIC32MX3XX/4XX  
FIGURE 11-1:  
PIC32MX3XX/4XX FAMILY USB INTERFACE DIAGRAM  
USBEN  
FRC  
USB Suspend  
Oscillator  
8 MHz Typical  
CPU Clock Not POSC  
Sleep  
TUN<5:0>(4)  
Primary Oscillator  
(POSC)  
(5)  
UFIN  
PLL  
Div x  
Div 2  
UFRCEN(3)  
OSC1  
UPLLEN(6)  
UPLLIDIV(6)  
USB Suspend  
To Clock Generator for Core and Peripherals  
Sleep or Idle  
OSC2  
(PB out)(1)  
USB Module  
USB  
SRP Charge  
SRP Discharge  
Voltage  
VBUS  
Comparators  
48 MHz USB Clock(7)  
Full Speed Pull-up  
D+(2)  
Registers  
and  
Control  
Interface  
Host Pull-down  
SIE  
Transceiver  
Low Speed Pull-up  
D-(2)  
DMA  
System  
RAM  
Host Pull-down  
ID Pull-up  
ID(8)  
(8)  
VBUSON  
Transceiver Power 3.3V  
VUSB  
Note 1:  
PB clock is only available on this pin for select EC modes.  
Pins can be used as digital inputs when USB is not enabled.  
This bit field is contained in the OSCCON register.  
This bit field is contained in the OSCTRM register.  
USB PLL UFIN requirements: 4 MHz.  
This bit field is contained in the DEVCFG2 register.  
A 48 MHz clock is required for proper USB operation.  
Pins can be used as GPIO when the USB module is disabled.  
2:  
3:  
4:  
5:  
6:  
7:  
8:  
DS61143H-page 100  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
General purpose I/O pins are the simplest of peripher-  
als. They allow the PIC® MCU to monitor and control  
other devices. To add flexibility and functionality, some  
pins are multiplexed with alternate function(s). These  
functions depend on which peripheral features are on  
the device. In general, when a peripheral is functioning,  
that pin may not be used as a general purpose I/O pin.  
12.0 I/O PORTS  
Note 1: This data sheet summarizes the features  
of the PIC32MX3XX/4XX family of  
devices. It is not intended to be a  
comprehensive reference source. To  
complement the information in this data  
sheet, refer to Section 12. “I/O Ports”  
(DS61120) of the “PIC32 Family  
Reference Manual”, which is available  
Following are some of the key features of this module:  
• Individual Output Pin Open-drain Enable/Disable  
• Individual Input Pin Weak Pull-up Enable/Disable  
from  
the  
Microchip  
web  
site  
• Monitor Selective Inputs and Generate Interrupt  
when Change in Pin State is Detected  
(www.microchip.com/PIC32).  
2: Some registers and associated bits  
described in this section may not be  
available on all devices. Refer to  
Section 4.0 “Memory Organization” in  
this data sheet for device-specific register  
and bit information.  
• Operation during CPU Sleep and Idle modes  
• Fast Bit Manipulation using CLR, SET and INV  
Registers  
Figure 12-1 illustrates a block diagram of a typical  
multiplexed I/O port.  
FIGURE 12-1:  
BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE  
Peripheral Module  
Peripheral Module Enable  
Peripheral Output Enable  
Peripheral Output Data  
PIO Module  
RD ODC  
Data Bus  
SYSCLK  
D
Q
ODC  
CK  
EN  
Q
WR ODC  
RD TRIS  
1
0
I/O Cell  
0
1
D
D
Q
Q
1
0
TRIS  
LAT  
CK  
EN  
WR TRIS  
Output Multiplexers  
Q
Q
I/O Pin  
CK  
EN  
WR LAT  
WR PORT  
RD LAT  
1
0
RD PORT  
Q
Q
D
Q
Q
D
Sleep  
CK  
CK  
SYSCLK  
Synchronization  
Peripheral Input  
R
Peripheral Input Buffer  
Legend:  
Note:  
R = Peripheral input buffer types may vary. Refer to Table 1-1 for peripheral details.  
This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure  
for any specific port/peripheral combination may be different than it is shown here.  
© 2011 Microchip Technology Inc.  
DS61143H-page 101  
PIC32MX3XX/4XX  
The maximum input voltage allowed on the input pins  
is the same as the maximum VIH specification. Refer to  
Section 29.0 “Electrical Characteristics” for VIH  
specification details.  
12.1 Parallel I/O (PIO) Ports  
All port pins have three registers (TRIS, LAT and  
PORT) that are directly associated with their operation.  
TRIS is a data direction or tri-state control register that  
determines whether a digital pin is an input or an out-  
put. Setting a TRISx register bit = 1configures the cor-  
responding I/O pin as an input; setting a TRISx register  
bit = 0configures the corresponding I/O pin as an out-  
put. All port I/O pins are defined as inputs after a device  
Reset. Certain I/O pins are shared with analog  
peripherals and default to analog inputs after a device  
Reset.  
Note:  
Analog levels on any pin that is defined as  
a digital input (including the ANx pins)  
may cause the input buffer to consume  
current that exceeds the device specifica-  
tions.  
12.1.3  
ANALOG INPUTS  
Certain pins can be configured as analog inputs used  
by the ADC and Comparator modules. Setting the cor-  
responding bits in the AD1PCFG register = 0enables  
the pin as an analog input pin and must have the corre-  
sponding TRIS bit set = 1 (input). If the TRIS bit is  
cleared = 0 (output), the digital output level (VOH or  
VOL) will be converted. Any time a port I/O pin is config-  
ured as analog, its digital input is disabled and the cor-  
responding PORTx register bit will read ‘0’. The  
AD1PCFG Register has a default value of 0x0000;  
therefore, all pins that share ANx functions are analog  
(not digital) by default.  
PORT is a register used to read the current state of the  
signal applied to the port I/O pins. Writing to a PORTx  
register performs a write to the port’s latch, LATx  
register, latching the data to the port’s I/O pins.  
LAT is a register used to write data to the port I/O pins.  
The LATx latch register holds the data written to either  
the LATx or PORTx registers. Reading the LATx latch  
register reads the last value written to the  
corresponding port or latch register.  
Not all port I/O pins are implemented on some devices,  
therefore, the corresponding PORTx, LATx and TRISx  
register bits will read as zeros.  
12.1.4  
DIGITAL OUTPUTS  
Pins are configured as digital outputs by setting the cor-  
responding TRIS register bits = 0. When configured as  
digital outputs, these pins are CMOS drivers or can be  
configured as open drain outputs by setting the corre-  
sponding bits in the ODCx Open-Drain Configuration  
register.  
12.1.1  
CLR, SET AND INV REGISTERS  
Every I/O module register has a corresponding CLR  
(clear), SET (set) and INV (invert) register designed to  
provide fast atomic bit manipulations. As the name of  
the register implies, a value written to a SET, CLR or  
INV register effectively performs the implied operation,  
but only on the corresponding base register and only  
bits specified as ‘1’ are modified. Bits specified as ‘0’  
are not modified.  
The open-drain feature allows the generation of  
outputs higher than VDD (e.g., 5V) on any desired 5V  
tolerant pins by using external pull-up resistors. The  
maximum open-drain voltage allowed is the same as  
the maximum VIH specification.  
Reading SET, CLR and INV registers returns undefined  
values. To see the affects of a write operation to a SET,  
CLR or INV register, the base register must be read.  
See the “Pin Diagrams” section for the available pins  
and their functionality.  
12.1.5  
ANALOG OUTPUTS  
Note:  
Using a PORTxINV register to toggle a bit  
is recommended because the operation is  
performed in hardware atomically, using  
fewer instructions as compared to the tra-  
ditional read-modify-write method shown  
below:  
Certain pins can be configured as analog outputs, such  
as the CVREF output voltage used by the comparator  
module. Configuring the Comparator Reference mod-  
ule to provide this output will present the analog output  
voltage on the pin, independent of the TRIS register  
setting for the corresponding pin.  
PORTC ^= 0x0001;  
12.1.2  
DIGITAL INPUTS  
12.1.6  
INPUT CHANGE NOTIFICATION  
Pins are configured as digital inputs by setting the cor-  
responding TRIS register bits = 1. When configured as  
inputs, they are either TTL buffers or Schmitt Triggers.  
Several digital pins share functionality with analog  
inputs and default to the analog inputs at POR. Setting  
the corresponding bit in the AD1PCFG register = 1  
enables the pin as a digital pin.  
The input change notification function of the I/O ports  
(CNx) allows devices to generate interrupt requests in  
response to change of state on selected pin.  
Each CNx pin also has a weak pull-up, which acts as a  
current source connected to the pin. The pull-ups are  
enabled by setting corresponding bit in CNPUE register.  
DS61143H-page 102  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
This family of PIC32MX devices features one  
synchronous/asynchronous 16-bit timer that can oper-  
ate as a free-running interval timer for various timing  
applications and counting external events. This timer  
can also be used with the Secondary Oscillator (SOSC)  
for real-time clock applications. The following modes  
are supported:  
13.0 TIMER1  
Note 1: This data sheet summarizes the features  
of the PIC32MX3XX/4XX family of  
devices. It is not intended to be a compre-  
hensive reference source. To comple-  
ment the information in this data sheet,  
refer to Section 14. “Timers” (DS61105)  
of the “PIC32 Family Reference Manual”,  
which is available from the Microchip web  
site (www.microchip.com/PIC32).  
• Synchronous Internal Timer  
• Synchronous Internal Gated Timer  
• Synchronous External Timer  
• Asynchronous External Timer  
2: Some registers and associated bits  
described in this section may not be  
available on all devices. Refer to  
Section 4.0 “Memory Organization” in  
this data sheet for device-specific register  
and bit information.  
13.1 Additional Supported Features  
• Selectable clock prescaler  
• Timer operation during CPU Idle and Sleep mode  
• Fast bit manipulation using CLR, SET and INV  
registers  
• Asynchronous mode can be used with the SOSC  
to function as a Real-Time Clock (RTC)  
(1)  
FIGURE 13-1:  
TIMER1 BLOCK DIAGRAM  
PR1  
Equal  
16-bit Comparator  
TMR1  
TSYNC (T1CON<2>)  
1
0
Sync  
Reset  
0
1
T1IF  
Event Flag  
Q
Q
D
TGATE (T1CON<7>)  
TCS (T1CON<1>)  
ON (T1CON<15>)  
TGATE (T1CON<7>)  
SOSCO/T1CK  
SOSCI  
x1  
Prescaler  
Gate  
Sync  
SOSCEN  
10  
00  
1, 8, 64, 256  
PBCLK  
2
TCKPS<1:0>  
(T1CON<5:4>)  
Note 1: The default state of the SOSCEN (OSCCON<1>) during a device Reset is controlled by the FSOSCEN bit in  
Configuration Word DEVCFG1.  
© 2011 Microchip Technology Inc.  
DS61143H-page 103  
PIC32MX3XX/4XX  
NOTES:  
DS61143H-page 104  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
Two 32-bit synchronous timers are available by  
combining Timer2 with Timer3 and Timer4 with Timer5.  
The 32-bit timers can operate in three modes:  
14.0 TIMER2/3 AND TIMER4/5  
Note 1: This data sheet summarizes the features  
of the PIC32MX3XX/4XX family of  
devices. It is not intended to be a compre-  
hensive reference source. To comple-  
ment the information in this data sheet,  
refer to Section 14. “Timers” (DS61105)  
of the “PIC32 Family Reference Manual”,  
which is available from the Microchip web  
site (www.microchip.com/PIC32).  
• Synchronous Internal 32-bit Timer  
• Synchronous Internal 32-bit Gated Timer  
• Synchronous External 32-bit Timer  
Note:  
Throughout this chapter, references to  
registers TxCON, TMRx and PRx use ‘x’  
to represent Timer2 through 5 in 16-bit  
modes. In 32-bit modes, ‘x’ represents  
Timer2 or 4; ‘y’ represents Timer3 or 5.  
2: Some registers and associated bits  
described in this section may not be  
available on all devices. Refer to  
Section 4.0 “Memory Organization” in  
this data sheet for device-specific register  
and bit information.  
14.1 Additional Supported Features  
• Selectable clock prescaler  
• Timers operational during CPU Idle  
• Time base for input capture and output compare  
modules (Timer2 and Timer3 only)  
This family of PIC32MX devices features four  
synchronous 16-bit timers (default) that can operate as  
a free-running interval timer for various timing applica-  
tions and counting external events. The following  
modes are supported:  
• ADC event trigger (Timer3 only)  
• Fast bit manipulation using CLR, SET and INV  
registers  
• Synchronous Internal 16-bit Timer  
• Synchronous Internal 16-bit Gated Timer  
• Synchronous External 16-bit Timer  
FIGURE 14-1:  
TIMER2, 3, 4, 5 BLOCK DIAGRAM (16-BIT)  
Sync  
TMRx  
ADC Event  
Trigger(1)  
Comparator x 16  
PRx  
Equal  
Reset  
0
1
TxIF  
Event Flag  
TGATE (TxCON<7>)  
TCS (TxCON<1>)  
ON (TxCON<15>)  
Q
Q
D
TGATE (TxCON<7>)  
TxCK(2)  
x1  
Prescaler  
1, 2, 4, 8, 16,  
32, 64, 256  
Gate  
Sync  
10  
PBCLK  
00  
3
TCKPS (TxCON<6:4>)  
Note 1: ADC event trigger is available on Timer3 only.  
2: TxCK pins not available on 64-pin devices.  
© 2011 Microchip Technology Inc.  
DS61143H-page 105  
PIC32MX3XX/4XX  
FIGURE 14-2:  
TIMER2/3, 4/5 BLOCK DIAGRAM (32-BIT)  
Reset  
TMRy  
TMRx  
Sync  
LSHalfWord  
MSHalfWord  
ADC Event  
Trigger(3)  
32-bit Comparator  
Equal  
PRy  
PRx  
TyIF Event  
Flag  
0
1
Q
Q
D
TGATE (TxCON<7>)  
TCS (TxCON<1>)  
ON (TxCON<15>)  
TGATE (TxCON<7>)  
TxCK(2)  
x1  
Prescaler  
1, 2, 4, 8, 16,  
32, 64, 256  
Gate  
Sync  
10  
00  
PBCLK  
3
TCKPS (TxCON<6:4>)  
Note 1: In this diagram, the use of ‘x’ in registers TxCON, TMRx, PRx and TxCK refers to either  
Timer2 or Timer4; the use of ‘y’ in registers TyCON, TMRy, PRy and TyIF refers to either Timer3 or Timer5.  
2: TxCK pins are not available on 64-pin devices.  
3: ADC event trigger is available only on Timer2/3 pair.  
DS61143H-page 106  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
2. Capture timer value on every edge (rising and  
falling)  
15.0 INPUT CAPTURE  
Note 1: This data sheet summarizes the features  
of the PIC32MX3XX/4XX family of  
devices. It is not intended to be a  
comprehensive reference source. To  
complement the information in this data  
sheet, refer to Section 15. “Input  
Capture” (DS61122) of the “PIC32  
Family Reference Manual”, which is  
available from the Microchip web site  
(www.microchip.com/PIC32).  
3. Capture timer value on every edge (rising and  
falling), specified edge first.  
4. Prescaler Capture Event modes  
- Capture timer value on every 4th rising edge  
of input at ICx pin  
- Capture timer value on every 16th rising  
edge of input at ICx pin  
Each input capture channel can select between one of  
two 16-bit timers (Timer2 or Timer3) for the time base,  
or two 16-bit timers (Timer2 and Timer3) together to  
form a 32-bit timer. The selected timer can use either  
an internal or external clock.  
2: Some registers and associated bits  
described in this section may not be  
available on all devices. Refer to  
Section 4.0 “Memory Organization” in  
this data sheet for device-specific register  
and bit information.  
Other operational features include:  
• Device wake-up from capture pin during CPU  
Sleep and Idle modes  
• Interrupt on input capture event  
The Input Capture module is useful in applications  
requiring frequency (period) and pulse measurement.  
The PIC32MX3XX/4XX devices support up to five input  
capture channels.  
• 4-word FIFO buffer for capture values  
- Interrupt optionally generated after 1, 2, 3 or  
4 buffer locations are filled  
The Input Capture module captures the 16-bit or 32-bit  
value of the selected Time Base registers when an  
event occurs at the ICx pin. The events that cause a  
capture event are listed below in three categories:  
• Input capture can also be used to provide  
additional sources of external interrupts  
1. Simple Capture Event modes  
-
Capture timer value on every falling edge of  
input at ICx pin  
-
Capture timer value on every rising edge of  
input at ICx pin  
FIGURE 15-1:  
INPUT CAPTURE BLOCK DIAGRAM  
ICx Input  
Timer3 Timer2  
ICTMR  
0
1
C32  
FIFO Control  
ICxBUF<31:16>  
ICxBUF<15:0>  
Prescaler  
1, 4, 16  
Edge Detect  
ICM<2:0>  
FEDGE  
ICM<2:0>  
ICBNE  
ICOV  
Interrupt  
Event  
Generation  
ICxCON  
ICI<1:0>  
Data Space Interface  
Peripheral Data Bus  
Interrupt  
© 2011 Microchip Technology Inc.  
DS61143H-page 107  
PIC32MX3XX/4XX  
NOTES:  
DS61143H-page 108  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
The Output Compare module (OCMP) is used to gen-  
erate a single pulse or a train of pulses in response to  
selected time base events. For all modes of operation,  
the OCMP module compares the values stored in the  
OCxR and/or the OCxRS registers to the value in the  
selected timer. When a match occurs, the OCMP mod-  
ule generates an event based on the selected mode of  
operation.  
16.0 OUTPUT COMPARE  
Note 1: This data sheet summarizes the features  
of the PIC32MX3XX/4XX family of  
devices. It is not intended to be a  
comprehensive reference source. To  
complement the information in this data  
sheet, refer to Section 16. “Output  
Compare” (DS61111) of the “PIC32  
Family Reference Manual”, which is  
available from the Microchip web site  
(www.microchip.com/PIC32).  
The following are some of the key features:  
• Multiple output compare modules in a device  
• Programmable interrupt generation on compare  
event  
2: Some registers and associated bits  
described in this section may not be  
available on all devices. Refer to  
Section 4.0 “Memory Organization” in  
this data sheet for device-specific register  
and bit information.  
• Single and Dual Compare modes  
• Single and continuous output pulse generation  
• Pulse-Width Modulation (PWM) mode  
• Hardware-based PWM Fault detection and  
automatic output disable  
• Programmable selection of 16-bit or 32-bit time  
bases.  
• Can operate from either of two available 16-bit  
time bases or a single 32-bit time base  
FIGURE 16-1:  
OUTPUT COMPARE MODULE BLOCK DIAGRAM  
Set Flag bit  
(1)  
OCxIF  
(1)  
OCxRS  
Output  
Logic  
(1)  
S
R
Q
(1)  
OCxR  
OCx  
3
Output Enable  
Logic  
Output  
Enable  
OCM<2:0>  
Mode Select  
Comparator  
OCFA or OCFB  
(see Note 2)  
0
1
0
OCTSEL  
1
16  
16  
Period match signals  
from time bases  
(see Note 3)  
TMR register inputs  
from time bases  
(see Note 3)  
Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare  
channels 1 through 5.  
2: The OCFA pin controls the OC1-OC4 channels. The OCFB pin controls the OC5 channel.  
3: Each output compare channel can use one of two selectable 16-bit time bases or a single 32-bit timer base.  
© 2011 Microchip Technology Inc.  
DS61143H-page 109  
PIC32MX3XX/4XX  
NOTES:  
DS61143H-page 110  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
The SPI module is a synchronous serial interface use-  
ful for communicating with external peripherals and  
other microcontroller devices. These peripheral  
devices may be Serial EEPROMs, shift registers, dis-  
play drivers, Analog-to-Digital Converters, etc. The  
PIC32MX SPI module is compatible with Motorola® SPI  
and SIOP interfaces.  
17.0 SERIAL PERIPHERAL  
INTERFACE (SPI)  
Note 1: This data sheet summarizes the features  
of the PIC32MX3XX/4XX family of  
devices. It is not intended to be a compre-  
hensive reference source. To comple-  
ment the information in this data sheet,  
refer to Section 23. “Serial Peripheral  
Interface (SPI)” (DS61106) of the  
“PIC32 Family Reference Manual”, which  
is available from the Microchip web site  
(www.microchip.com/PIC32).  
Following are some of the key features of this module:  
• Master and Slave Modes Support  
• Four Different Clock Formats  
• Framed SPI Protocol Support  
• User Configurable 8-bit, 16-bit and 32-bit Data  
Width  
2: Some registers and associated bits  
described in this section may not be  
available on all devices. Refer to  
Section 4.0 “Memory Organization” in  
this data sheet for device-specific register  
and bit information.  
• Separate SPI Data Registers for Receive and  
Transmit  
• Programmable Interrupt Event on every 8-bit,  
16-bit and 32-bit Data Transfer  
• Operation during CPU Sleep and Idle Mode  
• Fast Bit Manipulation using CLR, SET and INV  
Registers  
FIGURE 17-1:  
SPI MODULE BLOCK DIAGRAM  
Internal  
Data Bus  
SPIxBUF  
Read  
Write  
Registers share address SPIxBUF  
SPIxRXB  
SPIxTXB  
Transmit  
Receive  
SPIxSR  
SDIx  
bit 0  
SDOx  
Shift  
Control  
Slave Select  
and Frame  
Sync Control  
Clock  
Control  
Edge  
Select  
SSx/FSYNC  
SCKx  
Baud Rate  
PBCLK  
Generator  
Enable Master Clock  
Note: Access SPIxTXB and SPIxRXB registers via SPIxBUF register.  
© 2011 Microchip Technology Inc.  
DS61143H-page 111  
PIC32MX3XX/4XX  
NOTES:  
DS61143H-page 112  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
The PIC32MX3XX/4XX devices have up to two I2C  
interface modules, denoted as I2C1 and I2C2. Each  
I2C module has a 2-pin interface: the SCLx pin is clock  
and the SDAx pin is data.  
Each I2C module, ‘I2Cx’ (x = 1 or 2), offers the following  
key features:  
• I2C Interface Supporting both Master and Slave  
Operation.  
• I2C Slave Mode Supports 7 and 10-bit Address.  
• I2C Master Mode Supports 7 and 10-bit Address.  
18.0 INTER-INTEGRATED  
2
CIRCUIT™ (I C™)  
Note 1: This data sheet summarizes the features  
of the PIC32MX3XX/4XX family of  
devices. It is not intended to be a compre-  
hensive reference source. To comple-  
ment the information in this data sheet,  
refer to Section 24. “Inter-Integrated  
Circuit (I2C™)” (DS61116) of the “PIC32  
Family Reference Manual”, which is  
available from the Microchip web site  
(www.microchip.com/PIC32).  
• I2C Port allows Bidirectional Transfers between  
Master and Slaves.  
• Serial Clock Synchronization for I2C Port can be  
used as a Handshake Mechanism to Suspend  
and Resume Serial Transfer (SCLREL control).  
• I2C Supports Multi-master Operation; Detects Bus  
Collision and Arbitrates Accordingly.  
2: Some registers and associated bits  
described in this section may not be  
available on all devices. Refer to  
Section 4.0 “Memory Organization” in  
this data sheet for device-specific register  
and bit information.  
• Provides Support for Address Bit Masking.  
The I2C module provides complete hardware support  
for both Slave and Multi-Master modes of the I2C serial  
communication standard. Figure 18-1 illustrates the I2C  
module block diagram.  
© 2011 Microchip Technology Inc.  
DS61143H-page 113  
PIC32MX3XX/4XX  
2
FIGURE 18-1:  
I C™ BLOCK DIAGRAM (X = 1 OR 2)  
Internal  
Data Bus  
I2CxRCV  
Read  
Shift  
Clock  
SCLx  
SDAx  
I2CxRSR  
LSB  
Address Match  
Write  
Read  
Match Detect  
I2CxMSK  
Write  
Read  
I2CxADD  
Start and Stop  
Bit Detect  
Write  
Start and Stop  
Bit Generation  
I2CxSTAT  
I2CxCON  
Read  
Write  
Collision  
Detect  
Acknowledge  
Generation  
Read  
Clock  
Stretching  
Write  
Read  
I2CxTRN  
LSB  
Shift Clock  
Reload  
Control  
Write  
Read  
BRG Down Counter  
PBCLK  
I2CxBRG  
DS61143H-page 114  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
The primary features of the UART module are:  
19.0 UNIVERSAL ASYNCHRONOUS  
RECEIVER TRANSMITTER  
(UART)  
• Full-duplex, 8-bit or 9-bit data transmission  
• Even, odd or no parity options (for 8-bit data)  
• One or two Stop bits  
Note 1: This data sheet summarizes the features  
of the PIC32MX3XX/4XX family of  
devices. It is not intended to be a  
comprehensive reference source. To  
complement the information in this data  
sheet, refer to Section 21. “Universal  
Asynchronous Receiver Transmitter  
(UART)” (DS61107) of the “PIC32 Family  
Reference Manual”, which is available  
• Hardware auto-baud feature  
• Hardware flow control option  
• Fully integrated Baud Rate Generator (BRG) with  
16-bit prescaler  
• Baud rates ranging from 76 bps to 20 Mbps at 80  
MHz  
• 4-level-deep First-In-First-Out (FIFO) Transmit  
Data Buffer  
from  
the  
Microchip  
web  
site  
• 4-level-deep FIFO Receive Data Buffer  
(www.microchip.com/PIC32).  
• Parity, framing and buffer overrun error detection  
2: Some registers and associated bits  
described in this section may not be  
available on all devices. Refer to  
Section 4.0 “Memory Organization” in  
this data sheet for device-specific register  
and bit information.  
• Support for interrupt only on address detect (9th  
bit = 1)  
• Separate transmit and receive interrupts  
• Loopback mode for diagnostic support  
• LIN protocol support  
• IrDA encoder and decoder with 16x baud clock  
output for external IrDA encoder/decoder support  
The UART module is one of the serial I/O modules  
available in PIC32MX3XX/4XX family devices. The  
UART is a full-duplex, asynchronous communication  
channel that communicates with peripheral devices  
and personal computers through protocols such as RS-  
232, RS-485, LIN 1.2 and IrDA®. The module also sup-  
ports the hardware flow control option, with UxCTS and  
UxRTS pins, and also includes an IrDA encoder and  
decoder.  
Figure 19-1 illustrates a simplified block diagram of the  
UART.  
FIGURE 19-1:  
UART SIMPLIFIED BLOCK DIAGRAM  
Baud Rate Generator  
IrDA®  
BCLKx  
UxRTS  
UxCTS  
Hardware Flow Control  
UARTx Receiver  
UxRX  
UxTX  
UARTx Transmitter  
© 2011 Microchip Technology Inc.  
DS61143H-page 115  
PIC32MX3XX/4XX  
FIGURE 19-2:  
TRANSMISSION (8-BIT OR 9-BIT DATA)  
Write to UxTXREG  
Character 1  
BCLK/16  
(Shift Clock)  
UxTX  
Start bit  
bit 0  
bit 1  
Character 1  
bit 7/8  
Stop bit  
UxTXIF Cleared by User  
UxTXIF  
Character 1 to  
Transmit Shift Register  
TRMT bit  
FIGURE 19-3:  
TWO CONSECUTIVE TRANSMISSIONS  
Write to UxTXREG  
Character 1 Character 2  
BCLK/16  
(Shift Clock)  
UxTX  
Start bit  
Start bit  
Character 2  
bit 0  
bit 1  
Character 1  
bit 7/8  
bit 0  
Stop bit  
UxTXIF  
(UTXISEL0 = 0)  
UxTXIF Cleared by User in Software  
UxTXIF  
(UTXISEL0 = 1)  
Character 1 to  
Transmit Shift Register  
Character 2 to  
Transmit Shift Register  
TRMT bit  
DS61143H-page 116  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
FIGURE 19-4:  
UART RECEPTION  
Start  
bit  
Start  
bit 7 Stop bit bit 0  
bit  
UxRX  
bit 0 bit1  
Stop  
bit  
bit 7  
UxRXIF  
(RXISEL = 0x)  
Character 1  
to UxRXREG  
Character 2  
to UxRXREG  
RIDLE bit  
Note:  
This timing diagram shows 2 characters received on the UxRX input.  
FIGURE 19-5:  
UART RECEPTION WITH RECEIVE OVERRUN  
Character 1  
bit 0 bit 1  
Characters 2, 3, 4, 5  
Character 6  
Start  
Start  
bit  
Start  
bit 7/8 Stop bit bit 0  
bit  
UxRX  
bit  
Stop  
Stop  
bit  
bit 7/8  
bit 7/8  
bit  
Character 1, 2, 3, 4  
Stored in Receive  
FIFO  
Character 5  
Held in UxRSR  
OERR Cleared by User  
OERR bit  
RIDLE bit  
Note:  
This diagram shows 6 characters received without the user reading the input buffer. The 5th character  
received is held in the Receive Shift register. An overrun error occurs at the start of the 6th character.  
© 2011 Microchip Technology Inc.  
DS61143H-page 117  
PIC32MX3XX/4XX  
NOTES:  
DS61143H-page 118  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
Key features of the PMP module include:  
20.0 PARALLEL MASTER PORT  
(PMP)  
• 8-bit,16-bit interface  
• Up to 16 programmable address lines  
• Up to two Chip Select lines  
Note 1: This data sheet summarizes the features  
of the PIC32MX3XX/4XX family of  
devices. It is not intended to be a compre-  
hensive reference source. To comple-  
ment the information in this data sheet,  
refer to Section 13. “Parallel Master  
Port (PMP)” (DS61128) of the “PIC32  
Family Reference Manual”, which is  
available from the Microchip web site  
(www.microchip.com/PIC32).  
• Programmable strobe options  
- Individual read and write strobes, or  
- Read/write strobe with enable strobe  
• Address auto-increment/auto-decrement  
• Programmable address/data multiplexing  
• Programmable polarity on control signals  
• Parallel Slave Port support  
- Legacy addressable  
2: Some registers and associated bits  
described in this section may not be  
available on all devices. Refer to  
Section 4.0 “Memory Organization” in  
this data sheet for device-specific register  
and bit information.  
- Address support  
- 4-byte deep auto-incrementing buffer  
• Programmable Wait states  
• Operate during CPU Sleep and Idle modes  
• Fast bit manipulation using CLR, SET and INV  
registers  
The PMP is a parallel 8-bit/16-bit input/output module  
specifically designed to communicate with a wide  
variety of parallel devices, such as communications  
peripherals, LCDs, external memory devices and  
microcontrollers. Because the interface to parallel  
peripherals varies significantly, the PMP module is  
highly configurable.  
• Freeze option for in-circuit debugging  
Note:  
On 64-pin devices, data pins PMD<15:8>  
are not available.  
FIGURE 20-1:  
PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES  
Address Bus  
Data Bus  
Control Lines  
PMA<0>  
PMALL  
PIC32MX3XX/4XX  
Parallel  
Master Port  
PMA<1>  
PMALH  
FLASH  
EEPROM  
SRAM  
Up to 16-bit Address  
PMA<13:2>  
PMA<14>  
PMCS1  
PMA<15>  
PMCS2  
PMRD  
PMRD/PMWR  
FIFO  
buffer  
PMWR  
PMENB  
Microcontroller  
LCD  
PMD<7:0>  
PMD<15:8>  
(1)  
16/8-bit Data (with or without multiplexed addressing)  
Note 1: On 64-pin devices, data pins PMD<15:8> are not available in 16-bit Master modes.  
© 2011 Microchip Technology Inc.  
DS61143H-page 119  
PIC32MX3XX/4XX  
NOTES:  
DS61143H-page 120  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
The following are some of the key features of this  
module:  
21.0 REAL-TIME CLOCK AND  
CALENDAR (RTCC)  
• Time: Hours, Minutes and Seconds  
• 24-Hour Format (Military Time)  
• Visibility of One-Half-Second Period  
Note 1: This data sheet summarizes the features  
of the PIC32MX3XX/4XX family of  
devices. It is not intended to be a compre-  
hensive reference source. To comple-  
ment the information in this data sheet,  
refer to Section 29. “Real-Time Clock  
and Calendar (RTCC)” (DS61125) of the  
“PIC32 Family Reference Manual”, which  
is available from the Microchip web site  
(www.microchip.com/PIC32).  
• Provides Calendar: Weekday, Date, Month and  
Year  
• Alarm Intervals are configurable for Half of a  
Second, One Second, 10 Seconds, One Minute,  
10 Minutes, One Hour, One Day, One Week, One  
Month and One Year  
• Alarm Repeat with Decrementing Counter  
• Alarm with Indefinite Repeat: Chime  
• Year Range: 2000 to 2099  
2: Some registers and associated bits  
described in this section may not be  
available on all devices. Refer to  
Section 4.0 “Memory Organization” in  
this data sheet for device-specific register  
and bit information.  
• Leap Year Correction  
• BCD Format for Smaller Firmware Overhead  
• Optimized for Long-Term Battery Operation  
• Fractional Second Synchronization  
The PIC32MX RTCC module is intended for applica-  
tions in which accurate time must be maintained for  
extended periods of time with minimal or no CPU inter-  
vention. Low-power optimization provides extended  
battery lifetime while keeping track of time.  
• User Calibration of the Clock Crystal Frequency  
with Auto-Adjust  
• Calibration Range: 0.66 Seconds Error per  
Month  
• Calibrates up to 260 ppm of Crystal Error  
• Requirements: External 32.768 kHz Clock Crystal  
• Alarm Pulse or Seconds Clock Output on RTCC  
pin  
FIGURE 21-1:  
RTCC BLOCK DIAGRAM  
32.768 kHz Input  
from Secondary  
Oscillator (SOSC)  
RTCC Prescalers  
0.5s  
YEAR, MTH, DAY  
RTCVAL  
WKDAY  
RTCC Timer  
Alarm  
HR, MIN, SEC  
Event  
Comparator  
MTH, DAY  
WKDAY  
Compare Registers  
with Masks  
ALRMVAL  
HR, MIN, SEC  
Repeat Counter  
RTCC Interrupt  
RTCC Interrupt Logic  
Alarm Pulse  
Seconds Pulse  
RTCC Pin  
RTCOE  
© 2011 Microchip Technology Inc.  
DS61143H-page 121  
PIC32MX3XX/4XX  
NOTES:  
DS61143H-page 122  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
• Automatic Channel Scan mode  
22.0  
10-BIT ANALOG-TO-DIGITAL  
CONVERTER (ADC)  
• Selectable conversion trigger source  
• 16-word conversion result buffer  
• Selectable Buffer Fill modes  
Note 1: This data sheet summarizes the features  
of the PIC32MX3XX/4XX family of  
devices. It is not intended to be a compre-  
hensive reference source. Refer to Sec-  
tion 17. “10-bit Analog-to-Digital  
Converter (ADC)” (DS61104) of the  
“PIC32 Family Reference Manual”, which  
is available from the Microchip web site  
(www.microchip.com/PIC32).  
• Eight conversion result format options  
• Operation during CPU Sleep and Idle modes  
A block diagram of the 10-bit ADC is illustrated in  
Figure 22-1. The 10-bit ADC has 16 analog input pins,  
designated AN0-AN15. In addition, there are two ana-  
log input pins for external voltage reference connec-  
tions. These voltage reference inputs may be shared  
with other analog input pins and may be common to  
other analog module references.  
2: Some registers and associated bits  
described in this section may not be  
available on all devices. Refer to  
Section 4.0 “Memory Organization” in  
this data sheet for device-specific register  
and bit information.  
The analog inputs are connected through two multi-  
plexers (MUXs) to one SHA. The analog input MUXs  
can be switched between two sets of analog inputs  
between conversions. Unipolar differential conversions  
are possible on all channels, other than the pin used as  
the reference, using a reference input pin (see  
Figure 22-1).  
The PIC32MX3XX/4XX 10-bit Analog-to-Digital  
Converter (ADC) includes the following features:  
• Successive Approximation Register (SAR)  
conversion  
The Analog Input Scan mode sequentially converts  
user-specified channels. A control register specifies  
which analog input channels will be included in the  
scanning sequence.  
• Up to 1000 kilo samples per second (ksps)  
conversion speed  
• Up to 16 analog input pins  
The 10-bit ADC is connected to a 16-word result buffer.  
Each 10-bit result is converted to one of eight, 32-bit  
output formats when it is read from the result buffer.  
• External voltage reference input pins  
• One unipolar, differential Sample-and-Hold  
Amplifier (SHA)  
FIGURE 22-1:  
ADC1 MODULE BLOCK DIAGRAM  
(1)  
(1)  
AVDD  
AVSS  
VREF+  
VREF-  
VCFG<2:0>  
AN0  
ADC1BUF0  
ADC1BUF1  
ADC1BUF2  
AN15  
S/H  
VREFH  
VREFL  
CHANNEL  
SCAN  
+
CH0SB<4:0>  
-
SAR ADC  
CH0SA<4:0>  
CSCNA  
AN1  
ADC1BUFE  
ADC1BUFF  
VREFL  
CH0NA CH0NB  
Alternate  
Input Selection  
Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs.  
© 2011 Microchip Technology Inc.  
DS61143H-page 123  
PIC32MX3XX/4XX  
FIGURE 22-2:  
ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM  
ADRC  
ADC Internal  
RC Clock(1)  
1
0
TAD  
ADCS<7:0>  
8
ADC Conversion  
Clock Multiplier  
TPB  
2,4,..., 512  
Note 1: See the ADC electrical characteristics for the exact RC clock value.  
DS61143H-page 124  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
The PIC32MX3XX/4XX Analog Comparator module  
contains one or more comparator(s) that can be  
configured in a variety of ways.  
23.0 COMPARATOR  
Note 1: This data sheet summarizes the features  
of the PIC32MX3XX/4XX family of  
devices. It is not intended to be a compre-  
hensive reference source. Refer to  
Section 19. “Comparator” (DS61110) of  
the “PIC32 Family Reference Manual”,  
which is available from the Microchip web  
site (www.microchip.com/PIC32).  
Following are some of the key features of this module:  
• Selectable inputs available include:  
- Analog inputs multiplexed with I/O pins  
- On-chip internal absolute voltage reference  
(IVREF)  
- Comparator voltage reference (CVREF)  
• Outputs can be inverted  
2: Some registers and associated bits  
described in this section may not be  
available on all devices. Refer to  
Section 4.0 “Memory Organization” in  
this data sheet for device-specific register  
and bit information.  
• Selectable interrupt generation  
A block diagram of the comparator module is illustrated  
in Figure 23-1.  
FIGURE 23-1:  
COMPARATOR BLOCK DIAGRAM  
Comparator 1  
COUT (CM1CON)  
C1OUT (CMSTAT)  
CREF  
ON  
CPOL  
(1)  
C1IN+  
(2)  
CVREF  
C1OUT  
CCH<1:0>  
C1  
C1IN-  
C1IN+  
C2IN+  
COE  
(2)  
IVREF  
Comparator 2  
ON  
COUT (CM2CON)  
C2OUT (CMSTAT)  
CREF  
CPOL  
C2IN+  
(2)  
CVREF  
C2OUT  
CCH<1:0>  
C2  
C2IN-  
COE  
C2IN+  
C1IN+  
(2)  
IVREF  
Note 1: On USB variants, when USB is enabled, this pin is controlled by the USB module and therefore  
is not available as a comparator input.  
2: Internally connected.  
© 2011 Microchip Technology Inc.  
DS61143H-page 125  
PIC32MX3XX/4XX  
NOTES:  
DS61143H-page 126  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
The CVREF is a 16-tap, resistor ladder network that pro-  
vides a selectable reference voltage. Although its pri-  
mary purpose is to provide a reference for the analog  
comparators, it also may be used independently of  
them.  
24.0 COMPARATOR VOLTAGE  
REFERENCE (CVREF)  
Note 1: This data sheet summarizes the features  
of the PIC32MX3XX/4XX family of  
devices. It is not intended to be a compre-  
hensive reference source. Refer to Sec-  
A block diagram of the module is illustrated in  
Figure 24-1. The resistor ladder is segmented to  
provide two ranges of voltage reference values and has  
a power-down function to conserve power when the  
reference is not being used. The module’s supply refer-  
ence can be provided from either device VDD/VSS or an  
external voltage reference. The CVREF output is avail-  
able for the comparators and typically available for pin  
output.  
tion  
20.  
“Comparator  
Voltage  
Reference (CVREF)” (DS61109) of the  
“PIC32 Family Reference Manual”, which  
is available from the Microchip web site  
(www.microchip.com/PIC32).  
2: Some registers and associated bits  
described in this section may not be  
available on all devices. Refer to  
Section 4.0 “Memory Organization” in  
this data sheet for device-specific register  
and bit information.  
The comparator voltage reference has the following  
features:  
• High and low range selection  
• Sixteen output levels available for each range  
• Internally connected to comparators to conserve  
device pins  
• Output can be connected to a pin  
FIGURE 24-1:  
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM  
CVRSS = 1  
CVRSS = 0  
VREF+  
AVDD  
8R  
CVR3:CVR0  
R
CVREN  
CVREF  
R
R
R
16 Steps  
CVREF  
OUT  
CVRCON<CVROE>  
R
R
R
CVRR  
VREF-  
AVSS  
8R  
CVRSS = 1  
CVRSS = 0  
© 2011 Microchip Technology Inc.  
DS61143H-page 127  
PIC32MX3XX/4XX  
NOTES:  
DS61143H-page 128  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
• LPRC Idle Mode: the system clock is derived from  
the LPRC.  
25.0 POWER-SAVING FEATURES  
Note 1: This data sheet summarizes the features  
of the PIC32MX3XX/4XX family of  
devices. It is not intended to be a compre-  
hensive reference source. To comple-  
ment the information in this data sheet,  
refer to Section 10. “Power-Saving  
Features” (DS61130) of the “PIC32  
Family Reference Manual”, which is  
available from the Microchip web site  
(www.microchip.com/PIC32).  
Peripherals continue to operate, but can option-  
ally be individually disabled. This is the lowest  
power mode for the device with a clock running.  
• Sleep Mode: the CPU, the system clock source,  
and any peripherals that operate from the system  
clock source, are halted.  
Some peripherals can operate in Sleep using spe-  
cific clock sources. This is the lowest power mode  
for the device.  
2: Some registers and associated bits  
described in this section may not be  
available on all devices. Refer to  
Section 4.0 “Memory Organization” in  
this data sheet for device-specific register  
and bit information.  
25.3 Power-Saving Operation  
The purpose of all power-saving is to reduce power  
consumption by reducing the device clock frequency.  
To achieve this, low-frequency clock sources can be  
selected. In addition, the peripherals and CPU can be  
halted or disabled to further reduce power  
consumption.  
This section describes power-saving for the  
PIC32MX3XX/4XX. The PIC32MX devices offer a total  
of nine methods and modes that are organized into two  
categories that allow the user to balance power con-  
sumption with device performance. In all of the meth-  
ods and modes described in this section, power-saving  
is controlled by software.  
25.3.1  
SLEEP MODE  
Sleep mode has the lowest power consumption of the  
device Power-Saving operating modes. The CPU and  
most peripherals are halted. Select peripherals can  
continue to operate in Sleep mode and can be used to  
wake the device from Sleep. See the individual periph-  
eral module sections for descriptions of behavior in  
Sleep mode.  
25.1 Power-Saving with CPU Running  
When the CPU is running, power consumption can be  
controlled by reducing the CPU clock frequency, lower-  
ing the PBCLK, and by individually disabling modules.  
These methods are grouped into the following modes:  
Sleep mode includes the following characteristics:  
• The CPU is halted.  
• The system clock source is typically shut down.  
See Section 25.3.2 “Idle Mode” for specific  
information.  
• FRC Run mode: the CPU is clocked from the FRC  
clock source with or without postscalers.  
• LPRC Run mode: the CPU is clocked from the  
LPRC clock source.  
• There can be a wake-up delay based on the  
oscillator selection.  
• SOSC Run mode: the CPU is clocked from the  
SOSC clock source.  
• The Fail-Safe Clock Monitor (FSCM) does not  
operate during Sleep mode.  
• Peripheral Bus Scaling mode: peripherals are  
clocked at programmable fraction of the CPU  
clock (SYSCLK).  
• The BOR circuit, if enabled, remains operative  
during Sleep mode.  
• The WDT, if enabled, is not automatically cleared  
prior to entering Sleep mode.  
25.2 CPU Halted Methods  
• Some peripherals can continue to operate in  
Sleep mode. These peripherals include I/O pins  
that detect a change in the input signal, WDT,  
ADC, UART and peripherals that use an external  
clock input or the internal LPRC oscillator, e.g.,  
RTCC and Timer 1.  
The device supports two power-saving modes, Sleep  
and Idle, both of which halt the clock to the CPU. These  
modes operate with all clock sources, as listed below:  
• POSC Idle Mode: the system clock is derived from  
the POSC. The system clock source continues to  
operate.  
• I/O pins continue to sink or source current in the  
same manner as they do when the device is not in  
Sleep.  
Peripherals continue to operate, but can  
optionally be individually disabled.  
• The USB module can override the disabling of the  
POSC or FRC. Refer to Section 11.0 “USB On-  
The-Go (OTG)” for specific details.  
• FRC Idle Mode: the system clock is derived from  
the FRC with or without postscalers. Peripherals  
continue to operate, but can optionally be  
individually disabled.  
• Some modules can be individually disabled by  
software prior to entering Sleep in order to further  
reduce consumption.  
• SOSC Idle Mode: the system clock is derived from  
the SOSC. Peripherals continue to operate, but  
can optionally be individually disabled.  
© 2011 Microchip Technology Inc.  
DS61143H-page 129  
PIC32MX3XX/4XX  
The processor will exit, or ‘wake-up’, from Sleep on one  
of the following events:  
The processor will wake or exit from Idle mode on the  
following events:  
• On any interrupt from an enabled source that is  
operating in Sleep. The interrupt priority must be  
greater than the current CPU priority.  
• On any interrupt event for which the interrupt  
source is enabled. The priority of the interrupt  
event must be greater than the current priority of  
CPU. If the priority of the interrupt event is lower  
than or equal to current priority of CPU, the CPU  
will remain halted and the device will remain in  
Idle mode.  
• On any form of device Reset.  
• On a WDT time-out. See Section 26.2 “Watchdog  
Timer (WDT)”.  
If the interrupt priority is lower than or equal to current  
priority, the CPU will remain halted, but the PBCLK will  
start running and the device will enter into Idle mode.  
• On any source of device Reset.  
• On a WDT time-out interrupt. See Section 26.2  
“Watchdog Timer (WDT)”.  
Note: There is no FRZ mode for this module.  
25.3.3  
PERIPHERAL BUS SCALING  
METHOD  
25.3.2  
IDLE MODE  
In the Idle mode, the CPU is halted but the System  
clock (SYSCLK) source is still enabled. This allows  
peripherals to continue operation when the CPU is  
halted. Peripherals can be individually configured to  
halt when entering Idle by setting their respective SIDL  
bit. Latency when exiting Idle mode is very low due to  
the CPU oscillator source remaining active.  
Most of the peripherals on the device are clocked using  
the PBCLK. The peripheral bus can be scaled relative  
to the SYSCLK to minimize the dynamic power con-  
sumed by the peripherals. The PBCLK divisor is con-  
trolled by PBDIV<1:0> (OSCCON<20:19>), allowing  
SYSCLK-to-PBCLK ratios of 1:1, 1:2, 1:4 and 1:8. All  
peripherals using PBCLK are affected when the divisor  
is changed. Peripherals such as USB, Interrupt Con-  
troller, DMA, Bus Matrix and Prefetch Cache are  
clocked directly from SYSCLK, as a result, they are not  
affected by PBCLK divisor changes  
Note:  
Changing the PBCLK divider ratio  
requires recalculation of peripheral timing.  
For example, assume the UART is config-  
ured for 9600 baud with a PB clock ratio of  
1:1 and a POSC of 8 MHz. When the PB  
clock divisor of 1:2 is used, the input fre-  
quency to the baud clock is cut in half;  
therefore, the baud rate is reduced to 1/2  
its former value. Due to numeric truncation  
in calculations (such as the baud rate divi-  
sor), the actual baud rate may be a tiny  
percentage different than expected. For  
this reason, any timing calculation  
required for a peripheral should be per-  
formed with the new PB clock frequency  
instead of scaling the previous value  
based on a change in PB divisor ratio.  
Changing the PBCLK divisor affects:  
• The CPU to peripheral access latency. The CPU  
has to wait for next PBCLK edge for a read to  
complete. In 1:8 mode this results in a latency of  
one to seven SYSCLKs.  
• The power consumption of the peripherals. Power  
consumption is directly proportional to the fre-  
quency at which the peripherals are clocked. The  
greater the divisor, the lower the power consumed  
by the peripherals.  
To minimize dynamic power the PB divisor should be  
chosen to run the peripherals at the lowest frequency  
that provides acceptable system performance. When  
selecting a PBCLK divider, peripheral clock require-  
ments such as baud rate accuracy should be taken into  
account. For example, the UART peripheral may not be  
able to achieve all baud rate values at some PBCLK  
divider depending on the SYSCLK value.  
Oscillator start-up and PLL lock delays are  
applied when switching to a clock source  
that was disabled and that uses a crystal  
and/or the PLL. For example, assume the  
clock source is switched from POSC to  
LPRC just prior to entering Sleep in order to  
save power. No oscillator start-up delay  
would be applied when exiting Idle. How-  
ever, when switching back to POSC, the  
appropriate  
PLL  
and/or  
oscillator  
startup/lock delays would be applied.  
The device enters Idle mode when the SLPEN  
(OSCCON<4>) bit is clear and a WAIT instruction is  
executed.  
DS61143H-page 130  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
PIC32MX3XX/4XX devices include several features  
intended to maximize application flexibility and reliabil-  
ity and minimize cost through elimination of external  
components. These are:  
26.0 SPECIAL FEATURES  
Note:  
This data sheet summarizes the features of  
the PIC32MX3XX/4XX family family of  
devices. It is not intended to be a compre-  
hensive reference source. To complement  
the information in this data sheet, refer to  
Section 9. “Watchdog Timer and  
Power-up Timer” (DS61114), Section  
32. “Configuration” (DS61124) and  
Section 33. “Programming and Diag-  
nostics” (DS61129) of the “PIC32 Family  
Reference Manual”, which is available from  
• Flexible Device Configuration  
• Watchdog Timer  
• JTAG Interface  
• In-Circuit Serial Programming™ (ICSP™)  
26.1 Configuration Bits  
The Configuration bits can be programmed to select  
various device configurations.  
the  
Microchip  
web  
site  
(www.microchip.com/PIC32).  
REGISTER 26-1: DEVCFG0: DEVICE CONFIGURATION WORD 0  
Bit  
Bit  
Bit  
Bit  
Bit  
Bit  
Bit  
Bit  
Bit  
Range  
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1  
24/16/8/0  
r-0  
—
r-1  
r-1  
—
r-1  
r-1  
—
r-1  
R/P  
CP  
r-1  
r-1  
—
r-1  
—
r-1  
—
R/P  
BWP  
R/P  
31:24  
23:16  
15:8  
7:0  
R/P  
R/P  
R/P  
—
R/P  
—
R/P  
—
R/P  
—
PWP<7:4>  
R/P  
r-1  
—
r-1  
—
r-1  
—
r-1  
—
r-1  
—
PWP<3:0>  
r-1  
r-1  
r-1  
r-1  
R/P  
R/P  
R/P  
—
—
—
—
ICESEL  
DEBUG<1:0>  
Legend:  
R = Readable bit  
W = Writable bit  
P = Programmable bit  
r = Reserved bit  
U = Unimplemented bit  
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)  
bit 31  
bit 30-29 Reserved: Write ‘1’  
bit 28 CP: Code-Protect bit  
Reserved: Write ‘0’  
Prevents boot and program Flash memory from being read or modified by an external  
programming device.  
1= Protection disabled  
0= Protection enabled  
bit 27-25 Reserved: Write ‘1’  
bit 24 BWP: Boot Flash Write-Protect bit  
Prevents boot Flash memory from being modified during code execution.  
1= Boot Flash is writable  
0= Boot Flash is not writable  
bit 23-20 Reserved: Write ‘1’  
© 2011 Microchip Technology Inc.  
DS61143H-page 131  
PIC32MX3XX/4XX  
REGISTER 26-1: DEVCFG0: DEVICE CONFIGURATION WORD 0 (CONTINUED)  
bit 19-12 PWP<7:0>: Program Flash Write-Protect bits  
Prevents selected program Flash memory pages from being modified during code execution. The PWP bits  
represent the one’s compliment of the number of write protected program Flash memory pages.  
11111111= Disabled  
11111110= 0xBD00_0FFF  
11111101= 0xBD00_1FFF  
11111100= 0xBD00_2FFF  
11111011= 0xBD00_3FFF  
11111010= 0xBD00_4FFF  
11111001= 0xBD00_5FFF  
11111000= 0xBD00_6FFF  
11110111= 0xBD00_7FFF  
11110110= 0xBD00_8FFF  
11110101= 0xBD00_9FFF  
11110100= 0xBD00_AFFF  
11110011= 0xBD00_BFFF  
11110010= 0xBD00_CFFF  
11110001= 0xBD00_DFFF  
11110000= 0xBD00_EFFF  
11101111= 0xBD00_FFFF  
.
.
.
01111111= 0xBD07_FFFF  
bit 11-4 Reserved: Write ‘1’  
bit 3  
ICESEL: In-Circuit Emulator/Debugger Communication Channel Select bit  
1= PGEC2/PGED2 pair is used  
0= PGEC1/PGED1 pair is used  
bit 2  
Reserved: Write ‘1’  
bit 1-0  
DEBUG<1:0>: Background Debugger Enable bits (forced to ‘11’ if code-protect is enabled)  
11= Debugger disabled  
10= Debugger enabled  
01= Reserved (same as ‘11’ setting)  
00= Reserved (same as ‘11’ setting)  
DS61143H-page 132  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
REGISTER 26-2: DEVCFG1: DEVICE CONFIGURATION WORD 1  
Bit  
Bit  
Bit  
Bit  
Bit  
Bit  
Bit  
Bit  
Bit  
Range  
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1  
24/16/8/0  
r-1  
—
r-1  
—
r-1  
r-1  
—
r-1  
r-1  
—
r-1  
—
r-1  
r-1  
—
r-1  
31:24  
23:16  
15:8  
7:0  
—
R/P  
—
R/P  
R/P  
R/P  
R/P  
R/P  
FWDTEN  
R/P  
—
R/P  
—
R/P  
WDTPS<4:0>  
R/P  
R/P  
r-1  
—
r-1  
—
R/P  
R/P  
FCKSM<1:0>  
FPBDIV<1:0>  
OSCIOFNC  
R/P  
POSCMOD<1:0>  
R/P  
r-1  
R/P  
r-1  
R/P  
R/P  
IESO  
—
FSOSCEN  
—
FNOSC<2:0>  
Legend:  
R = Readable bit  
W = Writable bit  
P = Programmable bit  
r = Reserved bit  
U = Unimplemented bit  
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)  
bit 31-24 Reserved: Write ‘1’  
bit 23 FWDTEN: Watchdog Timer Enable bit  
1= The WDT is enabled and cannot be disabled by software  
0= The WDT is not enabled; it can be enabled in software  
bit 22-21 Reserved: Write ‘1’  
bit 20-16 WDTPS<4:0>: Watchdog Timer Postscale Select bits  
10100= 1:1048576  
10011= 1:524288  
10010= 1:262144  
10001= 1:131072  
10000= 1:65536  
01111= 1:32768  
01110= 1:16384  
01101= 1:8192  
01100= 1:4096  
01011= 1:2048  
01010= 1:1024  
01001= 1:512  
01000= 1:256  
00111= 1:128  
00110= 1:64  
00101= 1:32  
00100= 1:16  
00011= 1:8  
00010= 1:4  
00001= 1:2  
00000= 1:1  
All other combinations not shown result in operation = ‘10100’  
bit 15-14 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits  
1x= Clock switching is disabled, Fail-Safe Clock Monitor is disabled  
01= Clock switching is enabled, Fail-Safe Clock Monitor is disabled  
00= Clock switching is enabled, Fail-Safe Clock Monitor is enabled  
Note 1: Do not disable POSC (POSCMOD = 00) when using this oscillator source.  
© 2011 Microchip Technology Inc.  
DS61143H-page 133  
PIC32MX3XX/4XX  
REGISTER 26-2: DEVCFG1: DEVICE CONFIGURATION WORD 1 (CONTINUED)  
bit 13-12 FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits  
11= PBCLK is SYSCLK divided by 8  
10= PBCLK is SYSCLK divided by 4  
01= PBCLK is SYSCLK divided by 2  
00= PBCLK is SYSCLK divided by 1  
bit 11  
bit 10  
Reserved: Write ‘1’  
OSCIOFNC: CLKO Enable Configuration bit  
1= CLKO output signal active on the OSCO pin; primary oscillator must be disabled or configured for the  
External Clock mode (EC) for the CLKO to be active (POSCMOD<1:0> = 11OR 00)  
0= CLKO output disabled  
bit 9-8  
bit 7  
POSCMOD<1:0>: Primary Oscillator Configuration bits  
11= Primary oscillator disabled  
10= HS oscillator mode selected  
01= XT oscillator mode selected  
00= External clock mode selected  
IESO: Internal External Switchover bit  
1= Internal External Switchover mode enabled (Two-Speed Start-up enabled)  
0= Internal External Switchover mode disabled (Two-Speed Start-up disabled)  
bit 6  
bit 5  
Reserved: Write ‘1’  
FSOSCEN: Secondary Oscillator Enable bit  
1= Enable Secondary Oscillator  
0= Disable Secondary Oscillator  
bit 4-3  
bit 2-0  
Reserved: Write ‘1’  
FNOSC<2:0>: Oscillator Selection bits  
111= Fast RC Oscillator with divide-by-N (FRCDIV)  
110= FRCDIV16 Fast RC Oscillator with fixed divide-by-16 postscaler  
101= Low-Power RC Oscillator (LPRC)  
100= Secondary Oscillator (SOSC)  
011= Primary Oscillator with PLL module (XT+PLL, HS+PLL, EC+PLL)  
010= Primary Oscillator (XT, HS, EC)(1)  
001= Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL)  
000= Fast RC Oscillator (FRC)  
Note 1: Do not disable POSC (POSCMOD = 00) when using this oscillator source.  
DS61143H-page 134  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
REGISTER 26-3: DEVCFG2: DEVICE CONFIGURATION WORD 2  
Bit  
Bit  
Bit  
Bit  
Bit  
Bit  
Bit  
Bit  
Bit  
Range  
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1  
24/16/8/0  
r-1  
—
r-1  
—
r-1  
r-1  
r-1  
—
r-1  
r-1  
—
r-1  
—
r-1  
—
r-1  
—
r-1  
—
r-1  
r-1  
31:24  
23:16  
15:8  
7:0  
—
r-1  
—
R/P  
—
R/P  
r-1  
R/P  
—
R/P  
—
r-1  
—
r-1  
—
r-1  
FPLLODIV<2:0>  
R/P  
R/P  
R/P  
R/P  
R/P  
UPLLEN  
r-1  
—
R/P  
—
R/P  
—
R/P  
UPLLIDIV<2:0>  
R/P  
—
FPLLMUL<2:0>  
FPLLIDIV<2:0>  
Legend:  
R = Readable bit  
W = Writable bit  
P = Programmable bit  
r = Reserved bit  
U = Unimplemented bit  
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)  
bit 31-19 Reserved: Write ‘1’  
bit 18-16 FPLLODIV<2:0>: Default Postscaler for PLL bits  
111= PLL output divided by 256  
110= PLL output divided by 64  
101= PLL output divided by 32  
100= PLL output divided by 16  
011= PLL output divided by 8  
010= PLL output divided by 4  
001= PLL output divided by 2  
000= PLL output divided by 1  
bit 15  
UPLLEN: USB PLL Enable bit  
1= Disable and bypass USB PLL  
0= Enable USB PLL  
bit 14-11 Reserved: Write ‘1’  
bit 10-8 UPLLIDIV<2:0>: PLL Input Divider bits  
111= 12x divider  
110= 10x divider  
101= 6x divider  
100= 5x divider  
011= 4x divider  
010= 3x divider  
010= 3x divider  
001= 2x divider  
000= 1x divider  
bit 7  
Reserved: Write ‘1’  
bit 6-4  
FPLLMUL<2:0>: PLL Multiplier bits  
111= 24x multiplier  
110= 21x multiplier  
101= 20x multiplier  
100= 19x multiplier  
011= 18x multiplier  
010= 17x multiplier  
001= 16x multiplier  
000= 15x multiplier  
bit 3  
Reserved: Write ‘1’  
bit 2-0  
FPLLIDIV<2:0>: PLL Input Divider bits  
111= 12x divider  
110= 10x divider  
101= 6x divider  
100= 5x divider  
011= 4x divider  
010= 3x divider  
001= 2x divider  
000= 1x divider  
© 2011 Microchip Technology Inc.  
DS61143H-page 135  
PIC32MX3XX/4XX  
REGISTER 26-4: DEVCFG3: DEVICE CONFIGURATION WORD 3  
Bit  
Bit  
Bit  
Bit  
Bit  
Bit  
Bit  
Bit  
Bit  
Range  
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1  
24/16/8/0  
r-1  
—
r-1  
r-1  
—
r-1  
r-1  
—
r-1  
r-1  
—
r-1  
r-1  
—
r-1  
r-1  
—
r-1  
r-1  
—
r-1  
r-1  
—
r-1  
31:24  
23:16  
15:8  
7:0  
—
R/P  
—
R/P  
—
R/P  
—
R/P  
—
R/P  
—
R/P  
—
R/P  
—
R/P  
USERID<15:8>  
R/P  
R/P  
R/P  
R/P  
R/P  
R/P  
R/P  
R/P  
USERID<7:0>  
Legend:  
R = Readable bit  
W = Writable bit  
P = Programmable bit  
r = Reserved bit  
U = Unimplemented bit  
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)  
bit 31-16 Reserved: Write ‘1’  
bit 15-0 USERID<15:0>: This is a 16-bit value that is user defined and is readable via ICSP™ and JTAG  
REGISTER 26-5: DEVID: DEVICE AND REVISION ID REGISTER  
Bit  
Bit  
Bit  
Bit  
Bit  
Bit  
Bit  
Bit  
Bit  
Range  
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1  
24/16/8/0  
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
31:24  
23:16  
15:8  
7:0  
VER<3:0>(1)  
DEVID<27:24>(1)  
R
R
R
R
R
R
R
R
R
R
R
DEVID<23:16>(1)  
R
R
DEVID<15:8>(1)  
R
R
DEVID<7:0>(1)  
Legend:  
R = Readable bit  
W = Writable bit  
P = Programmable bit  
r = Reserved bit  
U = Unimplemented bit  
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)  
bit 31-28 VER<3:0>: Revision Identifier bits(1)  
bit 27-0 DEVID<27:0>: Device ID(1)  
Note 1: See the “PIC32MX Flash Programming Specification” (DS61145) for a list of Revision and Device ID values.  
DS61143H-page 136  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
26.2 Watchdog Timer (WDT)  
This section describes the operation of the WDT and  
Power-Up Timer of the PIC32MX3XX/4XX.  
The WDT, when enabled, operates from the internal  
Low-Power Oscillator (LPRC) clock source and can be  
used to detect system software malfunctions by reset-  
ting the device if the WDT is not cleared periodically in  
software. Various WDT time-out periods can be  
selected using the WDT postscaler. The WDT can also  
be used to wake the device from Sleep or Idle mode.  
The following are some of the key features of the WDT  
module:  
• Configuration or software controlled  
• User-configurable time-out period  
• Can wake the device from Sleep or Idle  
FIGURE 26-1:  
WATCHDOG AND POWER-UP TIMER BLOCK DIAGRAM  
PWRT Enable  
WDT Enable  
LPRC  
Control  
PWRT Enable  
1:64 Output  
LPRC  
PWRT  
Oscillator  
1
Clock  
25-bit Counter  
25  
WDTCLR = 1  
WDT Enable  
Wake  
Device Reset  
0
1
WDT Counter Reset  
WDT Enable  
Reset Event  
NMI (Wake-up)  
Power Save  
Decoder  
FWDTPS<4:0>(DEVCFG1<20:16>)  
© 2011 Microchip Technology Inc.  
DS61143H-page 137  
PIC32MX3XX/4XX  
26.3.1  
ON-CHIP REGULATOR AND POR  
26.3 On-Chip Voltage Regulator  
When the voltage regulator is enabled, it takes fixed  
delay for it to generate output. During this time, desig-  
nated as TPU, code execution is disabled. TPU is applied  
every time the device resumes operation after any  
power-down, including Sleep mode.  
All PIC32MX3XX/4XX device’s core and digital logic  
are designed to operate at a nominal 1.8V. To simplify  
system  
designs,  
most  
devices  
in  
the  
PIC32MX3XX/4XX incorporate an on-chip regulator  
providing the required core logic voltage from VDD.  
If the regulator is disabled, a separate Power-up Timer  
(PWRT) is automatically enabled. The PWRT adds a  
fixed delay of TPWRT at device start-up. See  
Section 29.0 “Electrical Characteristics” for more  
information on TPU AND TPWRT.  
The internal 1.8V regulator is controlled by the  
ENVREG pin. Tying this pin to VDD enables the regu-  
lator, which in turn provides power to the core. A low  
ESR capacitor (such as tantalum) must be connected  
to the VCORE/VCAP pin (Figure 26-2). This helps to  
maintain the stability of the regulator. The recom-  
mended value for the filer capacitor is provided in  
Section 29.1 “DC Characteristics”.  
26.3.2  
When  
ON-CHIP REGULATOR AND BOR  
the on-chip regulator is enabled,  
PIC32MX3XX/4XX devices also have a simple brown-  
out capability. If the voltage supplied to the regulator is  
inadequate to maintain a regulated level, the regulator  
Reset circuitry will generate a Brown-out Reset. This  
event is captured by the BOR flag bit (RCON<1>). The  
brown-out voltage levels are specific in Section 29.1  
“DC Characteristics”.  
Note:  
It is important that the low ESR capacitor  
is placed as close as possible to the  
VCORE/VCAP pin.  
Tying the ENVREG pin to VSS disables the regulator. In  
this case, separate power for the core logic at a nomi-  
nal 1.8V must be supplied to the device on the  
VCORE/VCAP pin.  
26.3.3  
POWER-UP REQUIREMENTS  
Alternatively, the VCORE/VCAP and VDD pins can be tied  
together to operate at a lower nominal voltage. Refer to  
Figure 26-2 for possible configurations.  
The on-chip regulator is designed to meet the power-up  
requirements for the device. If the application does not  
use the regulator, then strict power-up conditions must  
be adhered to. While powering up, VCORE must never  
exceed VDD by 0.3 volts.  
FIGURE 26-2:  
CONNECTIONS FOR THE ON-CHIP REGULATOR  
Regulator Enabled (ENVREG tied to VDD):  
Regulator Disabled (ENVREG tied to ground):  
3.3V  
1.8V(1)  
3.3V(1)  
PIC32MX  
PIC32MX  
VDD  
VDD  
ENVREG  
ENVREG  
VCORE/VCAP  
VSS  
VCORE/VCAP  
VSS  
CEFC  
(10 μF typ)  
Note 1: These are typical operating voltages. Refer to Section 29.1 “DC Characteristics” for the full operating ranges of VDD  
and VCORE.  
DS61143H-page 138  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
26.4 Programming and Diagnostics  
PIC32MX3XX/4XX devices provide a complete range  
of programming and diagnostic features that can  
increase the flexibility of any application using them.  
These features allow system designers to include:  
• Simplified field programmability using two-wire In-  
Circuit Serial Programming™ (ICSP™) interfaces  
• Debugging using ICSP  
• Programming and debugging capabilities using  
the EJTAG extension of JTAG  
• JTAG boundary scan testing for device and board  
diagnostics  
PIC32MX devices incorporate two programming and  
diagnostic modules, and a trace controller, that provide  
a range of functions to the application developer.  
FIGURE 26-3:  
BLOCK DIAGRAM OF PROGRAMMING, DEBUGGING AND TRACE PORTS  
PGEC1  
PGED1  
ICSP™  
Controller  
PGEC2  
PGED2  
ICESEL  
TDI  
TDO  
JTAG  
Core  
Controller  
TCK  
TMS  
JTAGEN  
DEBUG<1:0>  
TRCLK  
TRD0  
TRD1  
TRD2  
TRD3  
Instruction Trace  
Controller  
DEBUG<1:0>  
© 2011 Microchip Technology Inc.  
DS61143H-page 139  
PIC32MX3XX/4XX  
REGISTER 26-6: DDPCON: DEBUG DATA PORT CONTROL REGISTER  
Bit  
Bit  
Bit  
Bit  
Bit  
Bit  
Bit  
Bit  
Bit  
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2  
25/17/9/1  
24/16/8/0  
r-x  
—
r-x  
—
r-x  
—
r-x  
r-x  
—
r-x  
—
r-x  
—
r-x  
—
r-x  
—
r-x  
—
r-x  
—
r-x  
—
r-x  
—
r-x  
—
31:24  
23:16  
15:8  
7:0  
—
r-x  
r-x  
r-x  
r-x  
r-x  
r-x  
—
—
—
—
—
—
r-x  
r-x  
r-x  
r-x  
r-x  
r-x  
—
—
—
—
—
—
R/W-0  
R/W-0  
R/W-0  
R/W-0  
R/W-1  
R/W-0  
DDPUSB  
DDPU1  
DDPU2  
DDPSPI1  
JTAGEN  
TROEN  
Legend:  
R = Readable bit  
W = Writable bit  
P = Programmable bit  
r = Reserved bit  
U = Unimplemented bit  
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)  
bit 31-8 Reserved: Write ‘0’; ignore read  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
DDPUSB: Debug Data Port Enable for USB bit  
1= USB peripheral ignores USBFRZ (U1CNFG1<5>) setting  
0= USB peripheral follows USBFRZ setting  
DDPU1: Debug Data Port Enable for UART1 bit  
1= UART1 peripheral ignores FRZ (U1MODE<14>) setting  
0= UART1 peripheral follows FRZ setting  
DDPU2: Debug Data Port Enable for UART2 bit  
1= UART2 peripheral ignores FRZ (U2MODE<14>) setting  
0= UART2 peripheral follows FRZ setting  
DDPSPI1: Debug Data Port Enable for SPI1 bit  
1= SPI1 peripheral ignores FRZ (SPI1CON<14>) setting  
0= SPI1 peripheral follows FRZ setting  
JTAGEN: JTAG Port Enable bit  
1= Enable JTAG Port  
0= Disable JTAG Port  
TROEN: Trace Output Enable bit  
1= Enable Trace Port  
0= Disable Trace Port  
bit 1-0 Reserved: Write ‘1’; ignore read  
DS61143H-page 140  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
Table 27-1 provides a summary of the instructions that  
are implemented by the PIC32MX3XX/4XX family  
core.  
27.0 INSTRUCTION SET  
The PIC32MX3XX/4XX family instruction set complies  
with the MIPS32 Release 2 instruction set architecture.  
PIC32MX does not support the following features:  
Note:  
Refer to “MIPS32® Architecture for Pro-  
grammers Volume II: The MIPS32®  
Instruction Set” at www.mips.com for  
more information.  
• CoreExtend instructions  
• Coprocessor 1 instructions  
• Coprocessor 2 instructions  
®
TABLE 27-1: MIPS32 INSTRUCTION SET  
Instruction  
ADD  
Description  
Function  
Integer Add  
Rd = Rs + Rt  
ADDI  
ADDIU  
ADDU  
AND  
Integer Add Immediate  
Unsigned Integer Add Immediate  
Unsigned Integer Add  
Logical AND  
Rt = Rs + Immed  
Rt = Rs +U Immed  
Rd = Rs +U Rt  
Rd = Rs & Rt  
ANDI  
B
Logical AND Immediate  
Rt = Rs & (016 || Immed)  
PC += (int)offset  
Unconditional Branch  
(Assembler idiom for: BEQ r0, r0, offset)  
BAL  
Branch and Link  
(Assembler idiom for: BGEZAL r0, offset)  
GPR[31] = PC + 8  
PC += (int)offset  
BEQ  
Branch on Equal  
if Rs == Rt  
PC += (int)offset  
BEQL  
Branch on Equal Likely(1)  
if Rs == Rt  
PC += (int)offset  
else  
Ignore Next Instruction  
BGEZ  
Branch on Greater Than or Equal to Zero  
if !Rs[31]  
PC += (int)offset  
BGEZAL  
Branch on Greater Than or Equal to Zero and Link  
GPR[31] = PC + 8  
if !Rs[31]  
PC += (int)offset  
BGEZALL  
BGEZL  
Branch on Greater Than or Equal to Zero and Link  
Likely(1)  
GPR[31] = PC + 8  
if !Rs[31]  
PC += (int)offset  
else  
Ignore Next Instruction  
Branch on Greater Than or Equal to Zero Likely(1)  
if !Rs[31]  
PC += (int)offset  
else  
Ignore Next Instruction  
BGTZ  
Branch on Greater Than Zero  
if !Rs[31] && Rs != 0  
PC += (int)offset  
BGTZL  
Branch on Greater Than Zero Likely(1)  
if !Rs[31] && Rs != 0  
PC += (int)offset  
else  
Ignore Next Instruction  
BLEZ  
Branch on Less Than or Equal to Zero  
if Rs[31] || Rs == 0  
PC += (int)offset  
Note 1: This instruction is deprecated and should not be used.  
© 2011 Microchip Technology Inc.  
DS61143H-page 141  
PIC32MX3XX/4XX  
®
TABLE 27-1: MIPS32 INSTRUCTION SET (CONTINUED)  
Instruction  
BLEZL  
Description  
Function  
Branch on Less Than or Equal to Zero Likely(1)  
if Rs[31] || Rs == 0  
PC += (int)offset  
else  
Ignore Next Instruction  
BLTZ  
Branch on Less Than Zero  
if Rs[31]  
PC += (int)offset  
BLTZAL  
Branch on Less Than Zero and Link  
GPR[31] = PC + 8  
if Rs[31]  
PC += (int)offset  
BLTZALL  
BLTZL  
Branch on Less Than Zero and Link Likely(1)  
Branch on Less Than Zero Likely(1)  
GPR[31] = PC + 8  
if Rs[31]  
PC += (int)offset  
else  
Ignore Next Instruction  
if Rs[31]  
PC += (int)offset  
else  
Ignore Next Instruction  
BNE  
Branch on Not Equal  
if Rs != Rt  
PC += (int)offset  
BNEL  
Branch on Not Equal Likely(1)  
if Rs != Rt  
PC += (int)offset  
else  
Ignore Next Instruction  
BREAK  
CLO  
Breakpoint  
Break Exception  
Count Leading Ones  
Count Leading Zeroes  
Return from Debug Exception  
Rd = NumLeadingOnes(Rs)  
Rd = NumLeadingZeroes(Rs)  
CLZ  
DERET  
PC = DEPC  
Exit Debug Mode  
DI  
Atomically Disable Interrupts  
Divide  
Rt = Status; StatusIE = 0  
DIV  
LO = (int)Rs / (int)Rt  
HI = (int)Rs % (int)Rt  
DIVU  
EHB  
Unsigned Divide  
LO = (uns)Rs / (uns)Rt  
HI = (uns)Rs % (uns)Rt  
Execution Hazard Barrier  
Stop instruction execution  
until execution hazards are  
cleared  
EI  
Atomically Enable Interrupts  
Return from Exception  
Rt = Status; StatusIE = 1  
ERET  
if StatusERL  
PC = ErrorEPC  
else  
PC = EPC  
StatusEXL = 0  
StatusERL = 0  
LL = 0  
EXT  
INS  
J
Extract Bit Field  
Insert Bit Field  
Rt = ExtractField(Rs, pos,  
size)  
Rt = InsertField(Rs, Rt, pos,  
size)  
Unconditional Jump  
PC = PC[31:28] || offset<<2  
Note 1: This instruction is deprecated and should not be used.  
DS61143H-page 142  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
®
TABLE 27-1: MIPS32 INSTRUCTION SET (CONTINUED)  
Instruction Description  
JAL  
Function  
Jump and Link  
GPR[31] = PC + 8  
PC = PC[31:28] || offset<<2  
JALR  
Jump and Link Register  
Rd = PC + 8  
PC = Rs  
JALR.HB  
Jump and Link Register with Hazard Barrier  
Like JALR, but also clears execution and  
instruction hazards  
JR  
Jump Register  
PC = Rs  
JR.HB  
Jump Register with Hazard Barrier  
Like JR, but also clears execution and  
instruction hazards  
LB  
Load Byte  
Rt = (byte)Mem[Rs+offset]  
Rt = (ubyte))Mem[Rs+offset]  
Rt = (half)Mem[Rs+offset]  
Rt = (uhalf)Mem[Rs+offset]  
LBU  
LH  
Unsigned Load Byte  
Load Halfword  
LHU  
LL  
Unsigned Load Halfword  
Load Linked Word  
Rt = Mem[Rs+offset>  
LLbit = 1  
LLAdr = Rs + offset  
LUI  
Load Upper Immediate  
Load Word  
Rt = immediate << 16  
Rt = Mem[Rs+offset]  
Rt = Mem[PC+offset]  
Re = Re MERGE Mem[Rs+offset]  
Re = Re MERGE Mem[Rs+offset]  
HI | LO += (int)Rs * (int)Rt  
HI | LO += (uns)Rs * (uns)Rt  
Rt = CPR[0, Rd, sel]  
Rd = HI  
LW  
LWPC  
LWL  
Load Word, PC relative  
Load Word Left  
LWR  
Load Word Right  
MADD  
MADDU  
MFC0  
MFHI  
MFLO  
MOVN  
Multiply-Add  
Multiply-Add Unsigned  
Move from Coprocessor 0  
Move from HI  
Move from LO  
Rd = LO  
Move Conditional on Not Zero  
if Rt ¼ 0 then  
Rd = Rs  
MOVZ  
Move Conditional on Zero  
if Rt = 0 then  
Rd = Rs  
MSUB  
MSUBU  
MTC0  
MTHI  
MTLO  
MUL  
Multiply-Subtract  
HI | LO -= (int)Rs * (int)Rt  
HI | LO -= (uns)Rs * (uns)Rt  
CPR[0, n, Sel] = Rt  
HI = Rs  
Multiply-Subtract Unsigned  
Move to Coprocessor 0  
Move to HI  
Move to LO  
LO = Rs  
Multiply with register write  
HI | LO =Unpredictable  
Rd = ((int)Rs * (int)Rt)31..0  
MULT  
MULTU  
NOP  
Integer Multiply  
HI | LO = (int)Rs * (int)Rd  
HI | LO = (uns)Rs * (uns)Rd  
Unsigned Multiply  
No Operation  
(Assembler idiom for: SLL r0, r0, r0)  
NOR  
OR  
Logical NOR  
Rd = ~(Rs | Rt)  
Rd = Rs | Rt  
Logical OR  
ORI  
RDHWR  
Logical OR Immediate  
Rt = Rs | Immed  
Re = HWR[Rd]  
Read Hardware Register (if enabled by HWREna  
Register)  
Note 1: This instruction is deprecated and should not be used.  
© 2011 Microchip Technology Inc.  
DS61143H-page 143  
PIC32MX3XX/4XX  
®
TABLE 27-1: MIPS32 INSTRUCTION SET (CONTINUED)  
Instruction  
RDPGPR  
Description  
Function  
Read GPR from Previous Shadow Set  
Rotate Word Right  
Rt = SGPR[SRSCtlPSS, Rd]  
Rd = Rtsa-1..0 || Rt31..sa  
Rd = RtRs-1..0 || Rt31..Rs  
(byte)Mem[Rs+offset] = Rt  
ROTR  
ROTRV  
SB  
Rotate Word Right Variable  
Store Byte  
SC  
Store Conditional Word  
if LLbit = 1  
mem[Rs+offset> = Rt  
Rt = LLbit  
SDBBP  
SEB  
SEH  
SH  
Software Debug Break Point  
Sign-Extend Byte  
Sign-Extend Half  
Trap to SW Debug Handler  
Rd = SignExtend (Rs-7...0)  
Rd = SignExtend (Rs-15...0)  
(half)Mem[Rs+offset> = Rt  
Rd = Rt << sa  
Store Half  
SLL  
SLLV  
SLT  
Shift Left Logical  
Shift Left Logical Variable  
Set on Less Than  
Rd = Rt << Rs[4:0]  
if (int)Rs < (int)Rt  
Rd = 1  
else  
Rd = 0  
SLTI  
SLTIU  
SLTU  
Set on Less Than Immediate  
if (int)Rs < (int)Immed  
Rt = 1  
else  
Rt = 0  
Set on Less Than Immediate Unsigned  
Set on Less Than Unsigned  
if (uns)Rs < (uns)Immed  
Rt = 1  
else  
Rt = 0  
if (uns)Rs < (uns)Immed  
Rd = 1  
else  
Rd = 0  
SRA  
Shift Right Arithmetic  
Shift Right Arithmetic Variable  
Shift Right Logical  
Rd = (int)Rt >> sa  
Rd = (int)Rt >> Rs[4:0]  
Rd = (uns)Rt >> sa  
Rd = (uns)Rt >> Rs[4:0]  
NOP  
SRAV  
SRL  
SRLV  
SSNOP  
SUB  
Shift Right Logical Variable  
Superscalar Inhibit No Operation  
Integer Subtract  
Rt = (int)Rs - (int)Rd  
Rt = (uns)Rs - (uns)Rd  
Mem[Rs+offset] = Rt  
Mem[Rs+offset] = Rt  
Mem[Rs+offset] = Rt  
SUBU  
SW  
Unsigned Subtract  
Store Word  
SWL  
Store Word Left  
SWR  
Store Word Right  
SYNC  
Synchronize  
Orders the cached coherent and  
uncached loads and stores for access to  
the shared memory  
SYSCALL  
TEQ  
System Call  
Trap if Equal  
SystemCallException  
if Rs == Rt  
TrapException  
TEQI  
Trap if Equal Immediate  
if Rs == (int)Immed  
TrapException  
Note 1: This instruction is deprecated and should not be used.  
DS61143H-page 144  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
®
TABLE 27-1: MIPS32 INSTRUCTION SET (CONTINUED)  
Instruction Description  
TGE Trap if Greater Than or Equal  
Function  
if (int)Rs >= (int)Rt  
TrapException  
TGEI  
TGEIU  
TGEU  
TLT  
Trap if Greater Than or Equal Immediate  
Trap if Greater Than or Equal Immediate Unsigned  
Trap if Greater Than or Equal Unsigned  
Trap if Less Than  
if (int)Rs >= (int)Immed  
TrapException  
if (uns)Rs >= (uns)Immed  
TrapException  
if (uns)Rs >= (uns)Rt  
TrapException  
if (int)Rs < (int)Rt  
TrapException  
TLTI  
TLTIU  
TLTU  
TNE  
Trap if Less Than Immediate  
Trap if Less Than Immediate Unsigned  
Trap if Less Than Unsigned  
if (int)Rs < (int)Immed  
TrapException  
if (uns)Rs < (uns)Immed  
TrapException  
if (uns)Rs < (uns)Rt  
TrapException  
Trap if Not Equal  
if Rs != Rt  
TrapException  
TNEI  
WAIT  
Trap if Not Equal Immediate  
Wait for Interrupt  
if Rs != (int)Immed  
TrapException  
Go to a low power mode and stall until  
interrupt occurs  
WRPGPR  
WSBH  
Write to GPR in Previous Shadow Set  
Word Swap Bytes Within Halfwords  
SGPR[SRSCtlPSS, Rd> = Rt  
Rd = Rt23..16 || Rt31..24 || Rt7..0  
|| Rt15..8  
XOR  
Exclusive OR  
Rd = Rs ^ Rt  
XORI  
Exclusive OR Immediate  
Rt = Rs ^ (uns)Immed  
Note 1: This instruction is deprecated and should not be used.  
© 2011 Microchip Technology Inc.  
DS61143H-page 145  
PIC32MX3XX/4XX  
NOTES:  
DS61143H-page 146  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
28.1 MPLAB Integrated Development  
Environment Software  
28.0 DEVELOPMENT SUPPORT  
The PIC® microcontrollers and dsPIC® digital signal  
controllers are supported with a full range of software  
and hardware development tools:  
The MPLAB IDE software brings an ease of software  
development previously unseen in the 8/16/32-bit  
microcontroller market. The MPLAB IDE is a Windows®  
operating system-based application that contains:  
• Integrated Development Environment  
- MPLAB® IDE Software  
• A single graphical interface to all debugging tools  
- Simulator  
• Compilers/Assemblers/Linkers  
- MPLAB C Compiler for Various Device  
Families  
- Programmer (sold separately)  
- In-Circuit Emulator (sold separately)  
- In-Circuit Debugger (sold separately)  
• A full-featured editor with color-coded context  
• A multiple project manager  
- HI-TECH C for Various Device Families  
- MPASMTM Assembler  
- MPLINKTM Object Linker/  
MPLIBTM Object Librarian  
- MPLAB Assembler/Linker/Librarian for  
Various Device Families  
• Customizable data windows with direct edit of  
contents  
• Simulators  
• High-level source code debugging  
• Mouse over variable inspection  
- MPLAB SIM Software Simulator  
• Emulators  
• Drag and drop variables from source to watch  
windows  
- MPLAB REAL ICE™ In-Circuit Emulator  
• In-Circuit Debuggers  
• Extensive on-line help  
• Integration of select third party tools, such as  
IAR C Compilers  
- MPLAB ICD 3  
- PICkit™ 3 Debug Express  
• Device Programmers  
- PICkit™ 2 Programmer  
- MPLAB PM3 Device Programmer  
The MPLAB IDE allows you to:  
• Edit your source files (either C or assembly)  
• One-touch compile or assemble, and download to  
emulator and simulator tools (automatically  
updates all project information)  
• Low-Cost Demonstration/Development Boards,  
Evaluation Kits, and Starter Kits  
• Debug using:  
- Source files (C or assembly)  
- Mixed C and assembly  
- Machine code  
MPLAB IDE supports multiple debugging tools in a  
single development paradigm, from the cost-effective  
simulators, through low-cost in-circuit debuggers, to  
full-featured emulators. This eliminates the learning  
curve when upgrading to tools with increased flexibility  
and power.  
© 2011 Microchip Technology Inc.  
DS61143H-page 147  
PIC32MX3XX/4XX  
28.2 MPLAB C Compilers for Various  
Device Families  
28.5 MPLINK Object Linker/  
MPLIB Object Librarian  
The MPLAB C Compiler code development systems  
are complete ANSI C compilers for Microchip’s PIC18,  
PIC24 and PIC32 families of microcontrollers and the  
dsPIC30 and dsPIC33 families of digital signal control-  
lers. These compilers provide powerful integration  
capabilities, superior code optimization and ease of  
use.  
The MPLINK Object Linker combines relocatable  
objects created by the MPASM Assembler and the  
MPLAB C18 C Compiler. It can link relocatable objects  
from precompiled libraries, using directives from a  
linker script.  
The MPLIB Object Librarian manages the creation and  
modification of library files of precompiled code. When  
a routine from a library is called from a source file, only  
the modules that contain that routine will be linked in  
with the application. This allows large libraries to be  
used efficiently in many different applications.  
For easy source level debugging, the compilers provide  
symbol information that is optimized to the MPLAB IDE  
debugger.  
28.3 HI-TECH C for Various Device  
Families  
The object linker/library features include:  
• Efficient linking of single libraries instead of many  
smaller files  
The HI-TECH C Compiler code development systems  
are complete ANSI C compilers for Microchip’s PIC  
family of microcontrollers and the dsPIC family of digital  
signal controllers. These compilers provide powerful  
integration capabilities, omniscient code generation  
and ease of use.  
• Enhanced code maintainability by grouping  
related modules together  
• Flexible creation of libraries with easy module  
listing, replacement, deletion and extraction  
28.6 MPLAB Assembler, Linker and  
Librarian for Various Device  
Families  
For easy source level debugging, the compilers provide  
symbol information that is optimized to the MPLAB IDE  
debugger.  
The compilers include a macro assembler, linker, pre-  
processor, and one-step driver, and can run on multiple  
platforms.  
MPLAB Assembler produces relocatable machine  
code from symbolic assembly language for PIC24,  
PIC32 and dsPIC devices. MPLAB C Compiler uses  
the assembler to produce its object file. The assembler  
generates relocatable object files that can then be  
archived or linked with other relocatable object files and  
archives to create an executable file. Notable features  
of the assembler include:  
28.4 MPASM Assembler  
The MPASM Assembler is a full-featured, universal  
macro assembler for PIC10/12/16/18 MCUs.  
The MPASM Assembler generates relocatable object  
files for the MPLINK Object Linker, Intel® standard HEX  
files, MAP files to detail memory usage and symbol  
reference, absolute LST files that contain source lines  
and generated machine code and COFF files for  
debugging.  
• Support for the entire device instruction set  
• Support for fixed-point and floating-point data  
• Command line interface  
• Rich directive set  
• Flexible macro language  
The MPASM Assembler features include:  
• Integration into MPLAB IDE projects  
• MPLAB IDE compatibility  
• User-defined macros to streamline  
assembly code  
• Conditional assembly for multi-purpose  
source files  
• Directives that allow complete control over the  
assembly process  
DS61143H-page 148  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
28.7 MPLAB SIM Software Simulator  
28.9 MPLAB ICD 3 In-Circuit Debugger  
System  
The MPLAB SIM Software Simulator allows code  
development in a PC-hosted environment by simulat-  
ing the PIC MCUs and dsPIC® DSCs on an instruction  
level. On any given instruction, the data areas can be  
examined or modified and stimuli can be applied from  
a comprehensive stimulus controller. Registers can be  
logged to files for further run-time analysis. The trace  
buffer and logic analyzer display extend the power of  
the simulator to record and track program execution,  
actions on I/O, most peripherals and internal registers.  
MPLAB ICD 3 In-Circuit Debugger System is Micro-  
chip's most cost effective high-speed hardware  
debugger/programmer for Microchip Flash Digital Sig-  
nal Controller (DSC) and microcontroller (MCU)  
devices. It debugs and programs PIC® Flash microcon-  
trollers and dsPIC® DSCs with the powerful, yet easy-  
to-use graphical user interface of MPLAB Integrated  
Development Environment (IDE).  
The MPLAB ICD 3 In-Circuit Debugger probe is con-  
nected to the design engineer's PC using a high-speed  
USB 2.0 interface and is connected to the target with a  
connector compatible with the MPLAB ICD 2 or MPLAB  
REAL ICE systems (RJ-11). MPLAB ICD 3 supports all  
MPLAB ICD 2 headers.  
The MPLAB SIM Software Simulator fully supports  
symbolic debugging using the MPLAB C Compilers,  
and the MPASM and MPLAB Assemblers. The soft-  
ware simulator offers the flexibility to develop and  
debug code outside of the hardware laboratory envi-  
ronment, making it an excellent, economical software  
development tool.  
28.10 PICkit 3 In-Circuit Debugger/  
Programmer and  
28.8 MPLAB REAL ICE In-Circuit  
Emulator System  
PICkit 3 Debug Express  
The MPLAB PICkit 3 allows debugging and program-  
ming of PIC® and dsPIC® Flash microcontrollers at a  
most affordable price point using the powerful graphical  
user interface of the MPLAB Integrated Development  
Environment (IDE). The MPLAB PICkit 3 is connected  
to the design engineer's PC using a full speed USB  
interface and can be connected to the target via an  
Microchip debug (RJ-11) connector (compatible with  
MPLAB ICD 3 and MPLAB REAL ICE). The connector  
uses two device I/O pins and the reset line to imple-  
ment in-circuit debugging and In-Circuit Serial Pro-  
gramming™.  
MPLAB REAL ICE In-Circuit Emulator System is  
Microchip’s next generation high-speed emulator for  
Microchip Flash DSC and MCU devices. It debugs and  
programs PIC® Flash MCUs and dsPIC® Flash DSCs  
with the easy-to-use, powerful graphical user interface of  
the MPLAB Integrated Development Environment (IDE),  
included with each kit.  
The emulator is connected to the design engineer’s PC  
using a high-speed USB 2.0 interface and is connected  
to the target with either a connector compatible with in-  
circuit debugger systems (RJ11) or with the new high-  
speed, noise tolerant, Low-Voltage Differential Signal  
(LVDS) interconnection (CAT5).  
The PICkit 3 Debug Express include the PICkit 3, demo  
board and microcontroller, hookup cables and CDROM  
with user’s guide, lessons, tutorial, compiler and  
MPLAB IDE software.  
The emulator is field upgradable through future firmware  
downloads in MPLAB IDE. In upcoming releases of  
MPLAB IDE, new devices will be supported, and new  
features will be added. MPLAB REAL ICE offers  
significant advantages over competitive emulators  
including low-cost, full-speed emulation, run-time  
variable watches, trace analysis, complex breakpoints, a  
ruggedized probe interface and long (up to three meters)  
interconnection cables.  
© 2011 Microchip Technology Inc.  
DS61143H-page 149  
PIC32MX3XX/4XX  
28.11 PICkit 2 Development  
Programmer/Debugger and  
PICkit 2 Debug Express  
28.13 Demonstration/Development  
Boards, Evaluation Kits, and  
Starter Kits  
The PICkit™ 2 Development Programmer/Debugger is  
a low-cost development tool with an easy to use inter-  
face for programming and debugging Microchip’s Flash  
families of microcontrollers. The full featured  
Windows® programming interface supports baseline  
A wide variety of demonstration, development and  
evaluation boards for various PIC MCUs and dsPIC  
DSCs allows quick application development on fully func-  
tional systems. Most boards include prototyping areas for  
adding custom circuitry and provide application firmware  
and source code for examination and modification.  
(PIC10F,  
PIC12F5xx,  
PIC16F5xx),  
midrange  
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,  
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit  
microcontrollers, and many Microchip Serial EEPROM  
products. With Microchip’s powerful MPLAB Integrated  
The boards support a variety of features, including LEDs,  
temperature sensors, switches, speakers, RS-232  
interfaces, LCD displays, potentiometers and additional  
EEPROM memory.  
Development Environment (IDE) the PICkit™  
2
enables in-circuit debugging on most PIC® microcon-  
trollers. In-Circuit-Debugging runs, halts and single  
steps the program while the PIC microcontroller is  
embedded in the application. When halted at a break-  
point, the file registers can be examined and modified.  
The demonstration and development boards can be  
used in teaching environments, for prototyping custom  
circuits and for learning about various microcontroller  
applications.  
In addition to the PICDEM™ and dsPICDEM™ demon-  
stration/development board series of circuits, Microchip  
has a line of evaluation kits and demonstration software  
The PICkit 2 Debug Express include the PICkit 2, demo  
board and microcontroller, hookup cables and CDROM  
with user’s guide, lessons, tutorial, compiler and  
MPLAB IDE software.  
®
for analog filter design, KEELOQ security ICs, CAN,  
IrDA®, PowerSmart battery management, SEEVAL®  
evaluation system, Sigma-Delta ADC, flow rate  
sensing, plus many more.  
28.12 MPLAB PM3 Device Programmer  
Also available are starter kits that contain everything  
needed to experience the specified device. This usually  
includes a single application and debug capability, all  
on one board.  
The MPLAB PM3 Device Programmer is a universal,  
CE compliant device programmer with programmable  
voltage verification at VDDMIN and VDDMAX for  
maximum reliability. It features a large LCD display  
(128 x 64) for menus and error messages and a modu-  
lar, detachable socket assembly to support various  
package types. The ICSP™ cable assembly is included  
as a standard item. In Stand-Alone mode, the MPLAB  
PM3 Device Programmer can read, verify and program  
PIC devices without a PC connection. It can also set  
code protection in this mode. The MPLAB PM3  
connects to the host PC via an RS-232 or USB cable.  
The MPLAB PM3 has high-speed communications and  
optimized algorithms for quick programming of large  
memory devices and incorporates an MMC card for file  
storage and data applications.  
Check the Microchip web page (www.microchip.com)  
for the complete list of demonstration, development  
and evaluation kits.  
DS61143H-page 150  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
29.0 ELECTRICAL CHARACTERISTICS  
This section provides an overview of PIC32MX3XX/4XX electrical characteristics. Additional information will be provided  
in future revisions of this document as it becomes available.  
Absolute maximum ratings for the PIC32MX3XX/4XX are listed below. Exposure to these maximum rating conditions  
for extended periods may affect device reliability. Functional operation of the device at these or any other conditions  
above the parameters indicated in the operation listings of this specification is not implied.  
Absolute Maximum Ratings  
(Note 1)  
Ambient temperature under bias.............................................................................................................-40°C to +105°C  
Storage temperature .............................................................................................................................. -65°C to +150°C  
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V  
Voltage on any pin that is not 5V tolerant, with respect to VSS (Note 3)......................................... -0.3V to (VDD + 0.3V)  
Voltage on any 5V tolerant pin with respect to VSS when VDD ≥ 2.3V (Note 3)........................................ -0.3V to +5.5V  
Voltage on any 5V tolerant pin with respect to VSS when VDD < 2.3V (Note 3)........................................ -0.3V to +3.6V  
Voltage on VCORE with respect to VSS ....................................................................................................... -0.3V to 2.0V  
Voltage on VBUS with respect to VSS ....................................................................................................... -0.3V to +5.5V  
Maximum current out of VSS pin(s).......................................................................................................................300 mA  
Maximum current into VDD pin(s) (Note 2)............................................................................................................300 mA  
Maximum output current sunk by any I/O pin..........................................................................................................25 mA  
Maximum output current sourced by any I/O pin ....................................................................................................25 mA  
Maximum current sunk by all ports .......................................................................................................................200 mA  
Maximum current sourced by all ports (Note 2)....................................................................................................200 mA  
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the  
device. This is a stress rating only and functional operation of the device at those or any other conditions  
above those indicated in the operation listings of this specification is not implied. Exposure to maximum  
rating conditions for extended periods may affect device reliability.  
2: Maximum allowable current is a function of device maximum power dissipation (see Table 29-2).  
3: See the “Pin Diagrams” section for the 5V tolerant pins.  
© 2011 Microchip Technology Inc.  
DS61143H-page 151  
PIC32MX3XX/4XX  
29.1 DC Characteristics  
TABLE 29-1: OPERATING MIPS VS. VOLTAGE  
Max. Frequency  
VDD Range  
(in Volts)  
Temp. Range  
Characteristic  
(in °C)  
PIC32MX3XX/4XX  
DC5  
2.3V-3.6V  
2.3V-3.6V  
-40°C to +85°C  
-40°C to +105°C  
80 MHz (Note 1)  
80 MHz (Note 1)  
DC5b  
Note 1: 40 MHz maximum for PIC32MX320F032H and PIC32MX420F032H devices.  
TABLE 29-2: THERMAL OPERATING CONDITIONS  
Rating  
Industrial Temperature Devices  
Symbol  
Min.  
Typical  
Max.  
Unit  
Operating Junction Temperature Range  
Operating Ambient Temperature Range  
TJ  
TA  
-40  
-40  
—
—
+125  
+85  
°C  
°C  
V-Temp Temperature Devices  
Operating Junction Temperature Range  
Operating Ambient Temperature Range  
TJ  
TA  
-40  
-40  
—
—
+140  
+105  
°C  
°C  
Power Dissipation:  
Internal Chip Power Dissipation:  
PINT = VDD x (IDD – S IOH)  
PD  
PINT + PI/O  
W
W
I/O Pin Power Dissipation:  
I/O = S ({VDD – VOH} x IOH) + S (VOL x IOL))  
Maximum Allowed Power Dissipation  
PDMAX  
(TJ – TA)/θJA  
TABLE 29-3: THERMAL PACKAGING CHARACTERISTICS  
Characteristics  
Symbol Typical  
Max.  
Unit  
Notes  
Package Thermal Resistance, 121-Pin XBGA (10x10x1.1 mm)  
Package Thermal Resistance, 100-Pin TQFP (12x12x1 mm)  
Package Thermal Resistance, 64-Pin TQFP (10x10x1 mm)  
Package Thermal Resistance, 64-Pin QFN (9x9x0.9 mm)  
θJA  
θJA  
θJA  
θJA  
40  
43  
47  
28  
—
—
—
—
°C/W  
°C/W  
°C/W  
°C/W  
1
1
1
1
Note 1: Junction to ambient thermal resistance, Theta-JA (θJA) numbers are achieved by package simulations.  
TABLE 29-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
DC CHARACTERISTICS  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
-40°C ≤TA ≤+105°C for V-Temp  
Param.  
No.  
Symbol  
Characteristics  
Min.  
Typical  
Max. Units  
Conditions  
Operating Voltage  
DC10  
DC12  
VDD  
VDR  
Supply Voltage  
2.3  
—
—
3.6  
—
V
V
—
—
RAM Data Retention Voltage  
(Note 1)  
1.75  
DC16  
DC17  
VPOR  
SVDD  
VDD Start Voltage  
to Ensure Internal  
Power-on Reset Signal  
1.75  
0.05  
—
—
1.95  
—
V
—
—
VDD Rise Rate  
V/ms  
to Ensure Internal  
Power-on Reset Signal  
Note 1: This is the limit to which VDD can be lowered without losing RAM data.  
DS61143H-page 152  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
TABLE 29-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
-40°C ≤TA ≤+105°C for V-Temp  
DC CHARACTERISTICS  
Param.  
Typical(3)  
No.  
Max.  
Units  
Conditions  
Operating Current (IDD)(1,2)  
-40ºC,  
+25ºC,  
+85ºC  
8.5  
13  
DC20  
mA  
Code executing from Flash  
—
4 MHz  
9
15  
—
32  
—
61  
—
+105ºC  
—
DC20c  
DC21  
4.0  
23.5  
16.4  
48  
mA  
mA  
mA  
mA  
mA  
Code executing from SRAM  
Code executing from Flash  
Code executing from SRAM  
Code executing from Flash  
Code executing from SRAM  
20 MHz  
(Note 4)  
—
—
—
—
DC21c  
DC22  
60 MHz  
(Note 4)  
DC22c  
45  
-40ºC,  
+25ºC,  
+85ºC  
55  
75  
DC23  
mA  
Code executing from Flash  
2.3V  
—
80 MHz  
60  
55  
—
100  
—
+105ºC  
—
DC23c  
DC24  
mA  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
Code executing from SRAM  
100  
130  
670  
850  
—
—
-40°C  
+25°C  
+85°C  
+105ºC  
-40°C  
+25°C  
+85°C  
+105ºC  
—
DC24a  
DC24b  
DC24c  
DC25  
—
—
2.3V  
—
—
—
—
94  
125  
302  
400  
71  
—
—
DC25a  
DC25b  
DC25d  
DC25c  
DC26  
—
—
3.3V  
—
LPRC (31 kHz)  
—
—
(Note 4)  
—
—
—
Code executing from SRAM  
110  
180  
700  
900  
—
—
—
—
-40°C  
+25°C  
+85°C  
+105ºC  
DC26a  
DC26b  
DC26c  
—
3.6V  
—
—
Note 1: A device’s IDD supply current is mainly a function of the operating voltage and frequency. Other factors,  
such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code  
execution pattern, execution from program Flash memory vs. SRAM, I/O pin loading and switching rate,  
oscillator type as well as temperature can have an impact on the current consumption.  
2: The test conditions for IDD measurements are as follows: Oscillator mode = EC+PLL with OSC1 driven by  
external square wave from rail to rail and PBCLK divisor = 1:8. CPU, Program Flash and SRAM data  
memory are operational, Program Flash memory Wait states = 7, program cache and prefetch are dis-  
abled and SRAM data memory Wait states = 1. All peripheral modules are disabled (ON bit = 0). WDT  
and FSCM are disabled. All I/O pins are configured as inputs and pulled to VSS. MCLR = VDD.  
3: Data in “Typical” column is at 3.3V, 25°C at specified operating frequency unless otherwise stated.  
Parameters are for design guidance only and are not tested.  
4: This parameter is characterized, but not tested in manufacturing.  
© 2011 Microchip Technology Inc.  
DS61143H-page 153  
PIC32MX3XX/4XX  
TABLE 29-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
-40°C ≤TA ≤+105°C for V-Temp  
DC CHARACTERISTICS  
Parameter  
Typical(2)  
No.  
Max.  
Units  
Conditions  
Idle Current (IIDLE): Core OFF, Clock ON Base Current (Note 1)  
DC30  
—
1.4  
—
—
—
13  
—
—
—
20  
—
—
—
24  
—
—
—
—
—
—
35  
65  
242  
350  
—
—
—
—
5
—
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
µA  
-40ºC, +25ºC, +85ºC  
-40ºC, +25ºC, +85ºC  
-40ºC, +25ºC, +85ºC  
+105ºC  
2.3V  
—
DC30a  
DC30b  
DC30c  
DC31  
4 MHz  
5
3.6V  
8
15  
—
-40ºC, +25ºC, +85ºC  
-40ºC, +25ºC, +85ºC  
-40ºC, +25ºC, +85ºC  
+105ºC  
2.3V  
—
DC31a  
DC31b  
DC31c  
DC32  
20 MHz  
(Note 3)  
17  
25  
22  
—
3.6V  
-40ºC, +25ºC, +85ºC  
-40ºC, +25ºC, +85ºC  
-40ºC, +25ºC, +85ºC  
+105ºC  
2.3V  
—
DC32a  
DC32b  
DC32c  
DC33  
60 MHz  
(Note 3)  
25  
32  
29  
—
3.6V  
-40ºC, +25ºC, +85ºC  
-40ºC, +25ºC, +85ºC  
-40ºC, +25ºC, +85ºC  
+105ºC  
2.3V  
—
DC33a  
DC33b  
DC33c  
DC34  
80 MHz  
32  
40  
36  
62  
392  
550  
—
3.6V  
-40°C  
DC34a  
DC34b  
DC34c  
DC35  
µA  
+25°C  
2.3V  
µA  
+85°C  
µA  
+105ºC  
µA  
-40°C  
DC35a  
DC35b  
DC35c  
DC36  
—
µA  
+25°C  
LPRC (31 kHz)  
3.3V  
3.6V  
(Note 3)  
—
µA  
+85°C  
—
µA  
+105ºC  
43  
106  
414  
600  
µA  
-40°C  
DC36a  
DC36b  
DC36c  
µA  
+25°C  
µA  
+85°C  
µA  
+105ºC  
Note 1: The test conditions for base IDLE current measurements are as follows: System clock is enabled and  
PBCLK divisor = 1:8. CPU in Idle mode (CPU core halted). Only digital peripheral modules are enabled  
(ON bit = 1) and being clocked. WDT and FSCM are disabled. All I/O pins are configured as inputs and  
pulled to VSS. MCLR = VDD.  
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance  
only and are not tested.  
3: This parameter is characterized, but not tested in manufacturing.  
DS61143H-page 154  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
TABLE 29-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)  
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
-40°C ≤TA ≤+105°C for V-Temp  
DC CHARACTERISTICS  
Parameter  
Typical(2)  
No.  
Max.  
Units  
Conditions  
Power-Down Current (IPD)(1)  
DC40  
7
30  
30  
μA  
μA  
μA  
µA  
μA  
μA  
μA  
μA  
μA  
µA  
-40°C  
+25°C  
+85°C  
+105ºC  
+25°C  
-40°C  
DC40a  
DC40b  
DC40h  
DC40c  
DC40d  
DC40e  
DC40g  
DC40f  
DC40i  
24  
2.3V  
3.3V  
Base Power-Down Current (Note 6)  
205  
450  
25  
300  
900  
—
Base Power-Down Current  
9
70  
25  
70  
+25°C  
+70°C  
+85°C  
+105ºC  
115  
200  
470  
200(5)  
400  
1200  
3.6V  
Base Power-Down Current  
Module Differential Current  
DC41  
—
—
—
—
5
10  
10  
10  
12  
—
10  
10  
12  
15  
10  
17  
37  
45  
—
10  
30  
44  
44  
μA  
μA  
μA  
µA  
μA  
μA  
μA  
μA  
µA  
μA  
μA  
μA  
µA  
μA  
μA  
μA  
μA  
µA  
-40°C  
+25°C  
+85°C  
+105ºC  
+25°C  
-40°C  
DC41a  
DC41b  
DC41g  
DC41c  
DC41d  
DC41e  
DC41f  
DC41h  
DC42  
2.3V  
3.3V  
3.6V  
Watchdog Timer Current: ΔIWDT (Notes 3, 6)  
Watchdog Timer Current: ΔIWDT (Note 3)  
Watchdog Timer Current: ΔIWDT (Note 3)  
—
—
—
—
—
—
—
—
23  
—
—
—
—
+25°C  
+85°C  
+105ºC  
-40°C  
DC42a  
DC42b  
DC42h  
DC42c  
DC42e  
DC42f  
DC42g  
DC42i  
+25°C  
+85°C  
+105ºC  
+25°C  
-40°C  
RTCC + Timer1 w/32 kHz Crystal: ΔIRTCC  
2.3V  
(Notes 3, 6)  
3.3V RTCC + Timer1 w/32 kHz Crystal: ΔIRTCC (Note 3)  
3.6V RTCC + Timer1 w/32 kHz Crystal: ΔIRTCC (Note 3)  
+25°C  
+85°C  
+105ºC  
Note 1: Base IPD is measured with all digital peripheral modules disabled. All I/Os are configured as inputs and  
pulled low. WDT and FSCM are disabled.  
2: Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance  
only and are not tested.  
3: The Δ current is the additional current consumed when the module is enabled. This current should be added  
to the base IPD current.  
4: Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled.  
5: Data is characterized at +70°C and not tested. Parameter is for design guidance only.  
6: This parameter is characterized, but not tested in manufacturing.  
© 2011 Microchip Technology Inc.  
DS61143H-page 155  
PIC32MX3XX/4XX  
TABLE 29-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED)  
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)  
DC CHARACTERISTICS  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
-40°C ≤TA ≤+105°C for V-Temp  
Parameter  
Typical(2)  
No.  
Max.  
Units  
Conditions  
Module Differential Current (Continued)  
DC43  
—
—
1100  
1100  
1000  
1200  
—
μA  
μA  
μA  
µA  
μA  
μA  
μA  
μA  
µA  
-40°C  
+25°C  
+85°C  
+105ºC  
—
DC43a  
DC43b  
DC43h  
DC43c  
DC43e  
DC43f  
DC43g  
DC43i  
2.5V  
—
ADC: ΔIADC (Notes 3, 4, 6)  
ADC: ΔIADC (Notes 3, 4)  
ADC: ΔIADC (Notes 3, 4)  
—
—
880  
—
1100  
1100  
1000  
1200  
-40°C  
+25°C  
+85°C  
+105ºC  
—
3.6V  
—
—
Note 1: Base IPD is measured with all digital peripheral modules disabled. All I/Os are configured as inputs and  
pulled low. WDT and FSCM are disabled.  
2: Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance  
only and are not tested.  
3: The Δ current is the additional current consumed when the module is enabled. This current should be added  
to the base IPD current.  
4: Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled.  
5: Data is characterized at +70°C and not tested. Parameter is for design guidance only.  
6: This parameter is characterized, but not tested in manufacturing.  
DS61143H-page 156  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
TABLE 29-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS  
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise  
stated)  
DC CHARACTERISTICS  
Operating temperature  
-40°C ≤TA ≤+85°C for Industrial  
-40°C ≤TA ≤+105°C for V-Temp  
Param.  
No.  
Symbol  
Characteristics  
Min.  
Typical(1)  
Max.  
Units  
Conditions  
VIL  
Input Low Voltage  
I/O pins:  
DI10  
VSS  
VSS  
—
—
0.15 VDD  
0.2 VDD  
V
V
with TTL Buffer  
with Schmitt Trigger Buffer  
MCLR  
(Note 4)  
(Note 4)  
(Note 4)  
(Note 4)  
(Note 4)  
DI15  
DI16  
DI17  
DI18  
VSS  
VSS  
VSS  
VSS  
—
—
—
—
0.2 VDD  
0.2 VDD  
0.2 VDD  
0.3 VDD  
V
V
V
V
OSC1 (XT mode)  
OSC1 (HS mode)  
SDAx, SCLx  
SMBus disabled  
(Note 4)  
DI19  
DI20  
SDAx, SCLx  
VSS  
—
0.8  
V
SMBus enabled  
(Note 4)  
VIH  
Input High Voltage  
I/O pins:  
with Analog Functions  
0.8 VDD  
0.8 VDD  
—
—
—
—
VDD  
V
V
V
V
(Note 4)  
(Note 4)  
(Note 4)  
(Note 4)  
(Note 4)  
(Note 4)  
(Note 4)  
Digital Only  
0.25VDD + 0.8V  
0.8 VDD  
5.5  
5.5  
with TTL Buffer  
with Schmitt Trigger Buffer  
MCLR  
DI25  
DI26  
DI27  
DI28  
0.8 VDD  
0.7 VDD  
0.7 VDD  
0.7 VDD  
—
—
—
—
VDD  
VDD  
VDD  
5.5  
V
V
V
V
OSC1 (XT mode)  
OSC1 (HS mode)  
SDAx, SCLx  
SMBus disabled  
(Note 4)  
DI29  
DI30  
SDAx, SCLx  
2.1  
50  
—
5.5  
V
SMBus enabled,  
2.3V ≤VPIN ≤5.5  
(Note 4)  
ICNPU CNxx Pull up Current  
250  
400  
μA VDD = 3.3V, VPIN = VSS  
IIL  
Input Leakage Current  
(Note 3)  
DI50  
DI51  
I/O Ports  
—
—
—
—
+1  
+1  
μA VSS ≤VPIN ≤VDD,  
Pin at high-impedance  
Analog Input Pins  
μA VSS ≤VPIN ≤VDD,  
Pin at high-impedance  
DI55  
DI56  
MCLR  
OSC1  
—
—
—
—
+1  
+1  
μA VSS ≤VPIN ≤VDD  
μA VSS ≤VPIN ≤VDD,  
XT and HS modes  
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only  
and are not tested.  
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified  
levels represent normal operating conditions. Higher leakage current may be measured at different input  
voltages.  
3: Negative current is defined as current sourced by the pin.  
4: This parameter is characterized, but not tested in manufacturing.  
© 2011 Microchip Technology Inc.  
DS61143H-page 157  
PIC32MX3XX/4XX  
TABLE 29-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS  
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise  
stated)  
Operating temperature  
DC CHARACTERISTICS  
-40°C ≤TA ≤+85°C for Industrial  
-40°C ≤TA ≤+105°C for V-Temp  
Param.  
No.  
Symbol  
Characteristics  
Min.  
Typical  
Max. Units  
Conditions  
VOL  
Output Low Voltage  
DO10  
DO16  
I/O Ports  
—
—
—
—
—
—
—
—
0.4  
0.4  
0.4  
0.4  
V
V
V
V
IOL = 7 mA, VDD = 3.6V  
IOL = 6 mA, VDD = 2.3V  
IOL = 3.5 mA, VDD = 3.6V  
IOL = 2.5 mA, VDD = 2.3V  
OSC2/CLKO  
VOH  
Output High Voltage  
DO20  
DO26  
I/O Ports  
2.4  
1.4  
2.4  
1.4  
—
—
—
—
—
—
—
—
V
V
V
V
IOH = -12 mA, VDD = 3.6V  
IOH = -12 mA, VDD = 2.3V  
IOH = -12 mA, VDD = 3.6V  
IOH = -12 mA, VDD = 2.3V  
OSC2/CLKO  
TABLE 29-10: ELECTRICAL CHARACTERISTICS: BROWN-OUT RESET (BOR)  
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise  
stated)  
Operating temperature  
DC CHARACTERISTICS  
-40°C ≤TA ≤+85°C for Industrial  
-40°C ≤TA ≤+105°C for V-Temp  
Param.  
No.  
Symbol  
Characteristics  
Min.  
Typical  
Max. Units  
2.3  
Conditions  
BO10  
VBOR  
BOR Event on VDD  
transition high-to-low  
2.0  
—
V
—
DS61143H-page 158  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
(3)  
TABLE 29-11: DC CHARACTERISTICS: PROGRAM MEMORY  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
-40°C ≤TA ≤+105°C for V-Temp  
DC CHARACTERISTICS  
Param.  
Symbol  
No.  
Characteristics  
Min. Typical(1) Max. Units  
Conditions  
Program Flash Memory  
Cell Endurance  
D130  
D131  
D132  
D134  
D135  
EP  
1000  
VMIN  
3.0  
—
—
—
—
10  
—
3.6  
3.6  
—
E/W  
V
—
—
—
—
—
VPR  
VDD for Read  
VPEW  
TRETD  
IDDP  
VDD for Erase or Write  
Characteristic Retention  
V
20  
Year  
mA  
Supply Current during  
Programming  
—
—
TWW  
TRW  
Word Write Cycle Time  
Row Write Cycle Time(2)  
(128 words per row)  
20  
3
—
40  
—
μs  
—
—
D136  
D137  
4.5  
ms  
TPE  
TCE  
Page Erase Cycle Time  
Chip Erase Cycle Time  
20  
80  
—
—
—
—
—
—
6
ms  
ms  
μs  
—
—
—
D138  
LVDstartup Flash LVD Delay  
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.  
2: The minimum SYSCLK for row programming is 4 MHz. Care should be taken to minimize bus activities  
during row programming, such as suspending any memory-to-memory DMA operations. If heavy bus  
loads are expected, selecting Bus Matrix Arbitration mode 2 (rotating priority) may be necessary. The  
default Arbitration mode is mode 1 (CPU has lowest priority).  
3: Refer to the “PIC32MX Flash Programming Specification” (DS61145) for operating conditions during  
programming and erase cycles.  
TABLE 29-12: PROGRAM FLASH MEMORY WAIT STATE CHARACTERISTICS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
DC CHARACTERISTICS  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
-40°C ≤TA ≤+105°C for V-Temp  
Required Flash wait states  
SYSCLK  
Units  
Comments  
0 Wait State  
1 Wait State  
2 Wait States  
0 to 30  
31 to 60  
61 to 80  
—
MHz  
Note 1: 40 MHz maximum for PIC32MX320F032H and PIC32MX420F032H devices.  
© 2011 Microchip Technology Inc.  
DS61143H-page 159  
PIC32MX3XX/4XX  
TABLE 29-13: COMPARATOR SPECIFICATIONS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
-40°C ≤TA ≤+105°C for V-Temp  
DC CHARACTERISTICS  
Param.  
Symbol  
No.  
Characteristics  
Input Offset Voltage  
Min. Typical Max.  
Units  
Comments  
D300  
—
0
±7.5  
—
±25  
VDD  
mV  
AVDD = VDD,  
AVSS = VSS  
VIOFF  
D301  
VICM  
Input Common Mode Voltage  
V
AVDD = VDD,  
AVSS = VSS  
(Note 2)  
D302  
D303  
CMRR  
TRESP  
Common Mode Rejection Ratio  
Response Time  
55  
—
—
—
dB  
ns  
Max VICM = (VDD - 1)V  
(Note 2)  
150  
400  
AVDD = VDD,  
AVSS = VSS  
(Notes 1,2)  
D304  
ON2OV  
Comparator Enabled to Output  
Valid  
—
—
10  
μs  
Comparator module is  
configured before setting  
the comparator ON bit.  
(Note 2)  
D305  
IVREF  
Internal Voltage Reference  
0.57  
0.6  
0.63  
V
—
Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions  
from VSS to VDD.  
2: These parameters are characterized but not tested.  
TABLE 29-14: VOLTAGE REFERENCE SPECIFICATIONS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
DC CHARACTERISTICS  
-40°C ≤TA ≤+105°C for V-Temp  
Param.  
No.  
Symbol  
Characteristics  
Resolution  
Min. Typical Max.  
Units  
Comments  
D310  
D311  
D312  
VRES  
VRAA  
TSET  
VDD/24  
—
—
—
—
VDD/32  
1/2  
LSb  
LSb  
μs  
—
—
—
Absolute Accuracy  
Settling Time(1)  
—
10  
Note 1: Settling time measured while CVRR = 1and CVR3:CVR0 transitions from ‘0000’ to ‘1111’. This  
parameter is characterized, but not tested in manufacturing.  
TABLE 29-15: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
DC CHARACTERISTICS  
-40°C ≤TA ≤+105°C for V-Temp  
Param.  
No.  
Symbol  
Characteristics  
Min. Typical Max. Units  
Comments  
D320  
D321  
VCORE  
CEFC  
Regulator Output Voltage  
1.62  
8
1.80  
10  
1.98  
—
V
—
External Filter Capacitor Value  
μF  
Capacitor must be low series  
resistance (< 1 Ohm)  
D322  
TPWRT  
Power-up Timer Period  
—
64  
—
ms ENVREG = 0  
DS61143H-page 160  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
29.2 AC Characteristics and Timing  
Parameters  
The information contained in this section defines  
PIC32MX3XX/4XX AC characteristics and timing  
parameters.  
FIGURE 29-1:  
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS  
Load Condition 1 – for all pins except OSC2  
Load Condition 2 – for OSC2  
VDD/2  
CL  
RL  
Pin  
VSS  
CL  
Pin  
RL = 464Ω  
CL = 50 pF for all pins  
50 pF for OSC2 pin (EC mode)  
VSS  
TABLE 29-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
AC CHARACTERISTICS  
-40°C ≤TA ≤+105°C for V-Temp  
Param.  
No.  
Symbol  
Characteristics  
Min. Typical(1) Max. Units  
Conditions  
DO56  
DO58  
CIO  
CB  
All I/O pins and OSC2  
SCLx, SDAx  
—
—
—
—
50  
pF EC mode  
pF In I2C™ mode  
400  
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only  
and are not tested.  
FIGURE 29-2:  
EXTERNAL CLOCK TIMING  
OS30  
OS31  
OS20  
OSC1  
OS31  
OS30  
© 2011 Microchip Technology Inc.  
DS61143H-page 161  
PIC32MX3XX/4XX  
TABLE 29-17: EXTERNAL CLOCK TIMING REQUIREMENTS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
-40°C ≤TA ≤+105°C for V-Temp  
AC CHARACTERISTICS  
Param.  
Symbol  
No.  
Characteristics  
Min.  
Typical(1)  
Max.  
Units  
Conditions  
OS10  
FOSC  
External CLKI Frequency  
(External clocks allowed only  
in EC and ECPLL modes)  
DC  
4
—
—
50(3)  
50(5)  
MHz EC (Note 5)  
MHz ECPLL (Note 4)  
OS11  
OS12  
Oscillator Crystal Frequency  
3
4
—
—
10  
10  
MHz XT (Note 5)  
MHz XTPLL  
(Notes 4, 5)  
OS13  
OS14  
10  
10  
—
—
25  
25  
MHz HS (Note 5)  
MHz HSPLL  
(Notes 4, 5)  
OS15  
OS20  
32  
—
32.768  
—
100  
—
kHz SOSC (Note 5)  
(2)  
TOSC  
TOSC = 1/FOSC = TCY  
—
See parameter  
OS10 for FOSC  
value  
OS30  
OS31  
OS40  
TOSL,  
TOSH  
External Clock In (OSC1)  
High or Low Time  
0.45 x TOSC  
—
—
—
0.05 x TOSC  
—
ns  
ns  
EC (Note 5)  
TOSR,  
TOSF  
External Clock In (OSC1)  
Rise or Fall Time  
—
—
EC (Note 5)  
TOST  
Oscillator Start-up Timer Period  
(Only applies to HS, HSPLL,  
XT, XTPLL and SOSC Clock  
Oscillator modes)  
1024  
TOSC (Note 5)  
OS41  
OS42  
TFSCM  
GM  
Primary Clock Fail Safe  
Time-out Period  
—
—
2
—
—
ms  
(Note 5)  
External Oscillator  
Transconductance  
12  
mA/V VDD = 3.3V  
TA = +25°C  
(Note 5)  
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are characterized but are  
not tested.  
2: Instruction cycle period (TCY) equals the input oscillator time base period. All specified values are based on  
characterization data for that particular oscillator type under standard operating conditions with the device  
executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or  
higher than expected current consumption. All devices are tested to operate at “min.” values with an  
external clock applied to the OSC1/CLKI pin.  
3: 40 MHz maximum for PIC32MX320F032H and PIC32MX420F032H devices.  
4: PLL input requirements: 4 MHZ ≤FPLLIN ≤5 MHZ (use PLL prescaler to reduce FOSC). This parameter is  
characterized, but tested at 10 MHz only at manufacturing.  
5: This parameter is characterized, but not tested in manufacturing.  
DS61143H-page 162  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
TABLE 29-18: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.3V TO 3.6V)  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
-40°C ≤TA ≤+105°C for V-Temp  
AC CHARACTERISTICS  
Param.  
Symbol  
No.  
Characteristics(1)  
Min.  
Typical  
Max. Units  
Conditions  
OS50  
FPLLI  
PLL Voltage Controlled  
Oscillator (VCO) Input  
Frequency Range  
4
—
5
MHz ECPLL, HSPLL, XTPLL,  
FRCPLL modes  
OS51  
FSYS  
On-Chip VCO System  
Frequency  
60  
—
120  
MHz  
—
—
OS52  
OS53  
TLOCK  
DCLK  
PLL Start-up Time (Lock Time)  
CLKO Stability(2)  
(Period Jitter or Cumulative)  
—
—
—
2
ms  
%
-0.25  
+0.25  
Measured over 100 ms  
period  
Note 1: These parameters are characterized, but not tested in manufacturing.  
2: This jitter specification is based on clock-cycle by clock-cycle measurements. To get the effective jitter for  
individual time-bases on communication clocks, use the following formula:  
DCLK  
EffectiveJitter = --------------------------------------------------------------  
SYSCLK  
---------------------------------------------------------  
CommunicationClock  
For example, if SYSCLK = 80 MHz and SPI bit rate = 20 MHz, the effective jitter is as follows:  
DCLK  
DCLK  
EffectiveJitter = ------------- = -------------  
2
80  
-----  
20  
TABLE 29-19: INTERNAL FRC ACCURACY  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
-40°C ≤TA ≤+105°C for V-Temp  
AC CHARACTERISTICS  
Param.  
Characteristics  
Min. Typical Max.  
Units  
Conditions  
No.  
Internal FRC Accuracy @ 8.00 MHz(1)  
F20 FRC  
-2  
—
+2  
%
—
Note 1: Frequency calibrated at 25°C and 3.3V. TUN bits can be used to compensate for temperature drift.  
TABLE 29-20: INTERNAL RC ACCURACY  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
AC CHARACTERISTICS  
-40°C ≤TA ≤+105°C for V-Temp  
Param.  
Characteristics  
Min. Typical Max.  
Units  
Conditions  
No.  
LPRC @ 31.25 kHz(1)  
F21 LPRC  
-15  
—
+15  
%
—
Note 1: Change of LPRC frequency as VDD changes.  
© 2011 Microchip Technology Inc.  
DS61143H-page 163  
PIC32MX3XX/4XX  
FIGURE 29-3:  
I/O TIMING CHARACTERISTICS  
I/O Pin  
(Input)  
DI35  
DI40  
I/O Pin  
(Output)  
DO31  
DO32  
Note: Refer to Figure 29-1 for load conditions.  
TABLE 29-21: I/O TIMING REQUIREMENTS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
-40°C ≤TA ≤+105°C for V-Temp  
AC CHARACTERISTICS  
Param.  
Symbol  
No.  
Characteristics(2)  
Min.  
Typical(1)  
Max.  
Units  
Conditions  
DO31  
TIOR  
Port Output Rise Time  
Port Output Fall Time  
—
—
—
—
10  
2
5
5
15  
10  
15  
10  
—
—
ns  
ns  
VDD < 2.5V  
VDD > 2.5V  
VDD < 2.5V  
VDD > 2.5V  
—
DO32  
TIOF  
5
ns  
5
ns  
DI35  
DI40  
TINP  
INTx Pin High or Low Time  
—
—
ns  
TRBP  
CNx High or Low Time (input)  
TSYSCLK  
—
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.  
2: This parameter is characterized, but not tested in manufacturing.  
DS61143H-page 164  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
FIGURE 29-4:  
POWER-ON RESET TIMING CHARACTERISTICS  
Internal Voltage Regulator Enabled  
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)  
VDD  
VPOR  
(TSYSDLY)  
SY02  
Power Up Sequence  
(Note 2)  
CPU starts fetching code  
SY00  
(TPU)  
(Note 1)  
Internal Voltage Regulator Enabled  
Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC)  
VDD  
VPOR  
(TSYSDLY)  
SY02  
Power Up Sequence  
(Note 2)  
CPU starts fetching code  
SY00  
(TPU)  
SY10  
(TOST)  
(Note 1)  
External VCORE Provided  
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)  
VDD  
VCORE  
VPOR  
(TSYSDLY)  
SY02  
Power Up Sequence  
(Note 3)  
CPU starts fetching code  
SY01  
(TPWRT)  
(Note 1)  
Note 1: The Power-up period will be extended if the power-up sequence completes before the device  
exits from BOR (VDD < VDDMIN).  
2: Includes interval voltage regulator stabilization delay.  
3: Power-up Timer (PWRT); only active when the internal voltage regulator is disabled.  
© 2011 Microchip Technology Inc.  
DS61143H-page 165  
PIC32MX3XX/4XX  
FIGURE 29-5:  
EXTERNAL RESET TIMING CHARACTERISTICS  
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)  
MCLR  
BOR  
TMCLR  
(SY20)  
TBOR  
(SY30)  
(TSYSDLY)  
SY02  
Reset Sequence  
CPU starts fetching code  
Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC)  
(TSYSDLY)  
SY02  
Reset Sequence  
CPU starts fetching code  
TOST  
(SY10)  
TABLE 29-22: RESETS TIMING  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
-40°C ≤TA ≤+105°C for V-Temp  
AC CHARACTERISTICS  
Param.  
Symbol  
No.  
Characteristics(1)  
Power-up Period  
Min.  
—
Typical(2)  
Max.  
600  
80  
Units  
Conditions  
SY00  
TPU  
μs  
-40°C to +85°C  
400  
Internal Voltage Regulator Enabled  
SY01  
TPWRT  
Power-up Period  
External Vcore Applied  
(Power-Up-Timer Active)  
48  
64  
ms  
—
-40°C to +85°C  
-40°C to +85°C  
—
—
SY02  
TSYSDLY System Delay Period:  
Time required to reload Device  
1 μs  
+
Configuration Fuses plus SYSCLK  
delay before first instruction is  
fetched.  
8 SYSCLK  
cycles  
—
—
—
—
SY20  
SY30  
TMCLR  
TBOR  
MCLR Pulse Width (low)  
BOR Pulse Width (low)  
2
1
μs  
μs  
-40°C to +85°C  
-40°C to +85°C  
Note 1: These parameters are characterized, but not tested in manufacturing.  
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Characterized by design but not tested.  
DS61143H-page 166  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
FIGURE 29-6:  
TIMER1, 2, 3, 4, 5 EXTERNAL CLOCK TIMING CHARACTERISTICS  
TxCK  
Tx11  
Tx10  
Tx15  
Tx20  
OS60  
TMRx  
Note: Refer to Figure 29-1 for load conditions.  
(1)  
TABLE 29-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
-40°C ≤TA ≤+105°C for V-Temp  
AC CHARACTERISTICS  
Param.  
Symbol  
No.  
Characteristics(2)  
Min.  
Typical Max. Units  
Conditions  
[(12.5 ns or 1TPB)/N]  
+ 25 ns  
TA10  
TA11  
TA15  
TTXH  
TTXL  
TTXP  
TxCK Synchronous,  
High Time with prescaler  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns Must also meet  
parameter TA15.  
Asynchronous,  
with prescaler  
10  
ns  
—
TxCK  
Synchronous, [(12.5 ns or 1TPB)/N]  
ns Must also meet  
parameter TA15.  
Low Time  
with prescaler  
+ 25 ns  
Asynchronous,  
with prescaler  
10  
ns  
ns  
ns  
ns  
ns  
—
TxCK  
Synchronous,  
[(Greater of 25 ns or  
2TPB)/N] + 30 ns  
VDD > 2.7V  
VDD < 2.7V  
Input Period with prescaler  
[(Greater of 25 ns or  
2TPB)/N] + 50 ns  
Asynchronous,  
with prescaler  
20  
50  
32  
VDD > 2.7V  
(Note 3)  
VDD < 2.7V  
(Note 3)  
OS60 FT1  
SOSC1/T1CK Oscillator  
Input Frequency Range  
(oscillator enabled by  
setting TCS bit  
100 kHz  
—
(T1CON<1>))  
TA20  
TCKEXTMRL Delay from External TxCK  
Clock Edge to Timer  
—
1
TPB  
—
Increment  
Note 1: Timer1 is a Type A.  
2: This parameter is characterized, but not tested in manufacturing.  
3: N = prescale value (1, 8, 64, 256)  
© 2011 Microchip Technology Inc.  
DS61143H-page 167  
PIC32MX3XX/4XX  
TABLE 29-24: TIMER2, 3, 4, 5 EXTERNAL CLOCK TIMING REQUIREMENTS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
AC CHARACTERISTICS  
-40°C ≤TA ≤+105°C for V-Temp  
Param.  
No.  
Symbol  
TTXH  
Characteristics(1)  
Min.  
Max. Units  
Conditions  
N = prescale  
ns Must also meet  
[(12.5 ns or 1TPB)/N]  
+ 25 ns  
TB10  
TxCK  
High  
Time  
Synchronous,  
with prescaler  
—
value  
(1, 2, 4, 8, 16,  
32, 64, 256)  
parameter  
TB15.  
TB11  
TB15  
TTXL  
TTXP  
TxCK  
Low  
[(12.5 ns or 1TPB)/N]  
+ 25 ns  
—
ns Must also meet  
parameter  
Synchronous,  
with prescaler  
Time  
TB15.  
TxCK  
Input  
[(Greater of 25 ns or  
2 TPB)/N] + 30 ns  
—
—
1
ns VDD > 2.7V  
ns VDD < 2.7V  
Synchronous,  
with prescaler  
Period  
[(Greater of 25 ns or  
2 TPB)/N] + 50 ns  
—
TB20  
TCKEXTMRL Delay from External  
TxCK Clock Edge to  
—
TPB  
—
Timer Increment  
Note 1: These parameters are characterized, but not tested in manufacturing.  
DS61143H-page 168  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
FIGURE 29-7:  
INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS  
ICx  
IC10  
IC11  
IC15  
Note: Refer to Figure 29-1 for load conditions.  
TABLE 29-25: INPUT CAPTURE MODULE TIMING REQUIREMENTS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
AC CHARACTERISTICS  
-40°C ≤TA ≤+105°C for V-Temp  
Param.  
No.  
Symbol  
Characteristics(1)  
Min.  
Max. Units  
Conditions  
IC10  
TCCL  
ICx Input Low Time  
[(12.5 ns or 1TPB)/N]  
+ 25 ns  
N = prescale  
value (1, 4, 16)  
—
—
—
ns  
ns  
ns  
Must also  
meet  
parameter  
IC15.  
IC11  
IC15  
TCCH  
ICx Input High Time  
[(12.5 ns or 1TPB)/N]  
+ 25 ns  
Must also  
meet  
parameter  
IC15.  
TCCP  
ICx Input Period  
[(25 ns or 2TPB)/N]  
+ 50 ns  
—
Note 1: These parameters are characterized, but not tested in manufacturing.  
FIGURE 29-8:  
OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS  
OCx  
(Output Compare  
or PWM Mode)  
OC10  
OC11  
Note: Refer to Figure 29-1 for load conditions.  
TABLE 29-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
-40°C ≤TA ≤+105°C for V-Temp  
AC CHARACTERISTICS  
Param.  
Symbol  
Characteristics(1)  
Min.  
Typical(2)  
Max.  
Units  
Conditions  
No.  
OC10  
OC11  
TCCF  
TCCR  
OCx Output Fall Time  
OCx Output Rise Time  
—
—
—
—
—
—
ns  
ns  
See parameter DO32.  
See parameter DO31.  
Note 1: These parameters are characterized, but not tested in manufacturing.  
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only  
and are not tested.  
© 2011 Microchip Technology Inc.  
DS61143H-page 169  
PIC32MX3XX/4XX  
FIGURE 29-9:  
OCFA/OCFB  
OCx  
OC/PWM MODULE TIMING CHARACTERISTICS  
OC20  
OC15  
OCx is tri-stated  
Note: Refer to Figure 29-1 for load conditions.  
TABLE 29-27: SIMPLE OC/PWM MODE TIMING REQUIREMENTS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
-40°C ≤TA ≤+105°C for V-Temp  
AC CHARACTERISTICS  
Param  
Symbol  
No.  
Characteristics(1)  
Min  
Typical(2)  
Max  
Units  
Conditions  
OC15  
OC20  
TFD  
Fault Input to PWM I/O Change  
Fault Input Pulse Width  
—
—
—
25  
—
ns  
ns  
—
—
TFLT  
50  
Note 1: These parameters are characterized, but not tested in manufacturing.  
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only  
and are not tested.  
DS61143H-page 170  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
FIGURE 29-10:  
SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS  
SCKx  
(CKP = 0)  
SP11  
SP10  
SP21  
SP20  
SCKx  
(CKP = 1)  
SP35  
SP31  
SP21  
LSb  
SP20  
Bit 14 - - - - - -1  
MSb  
SDOx  
SDIx  
SP30  
MSb In  
SP40  
LSb In  
Bit 14 - - - -1  
SP41  
Note: Refer to Figure 29-1 for load conditions.  
TABLE 29-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
-40°C ≤TA ≤+105°C for V-Temp  
AC CHARACTERISTICS  
Param.  
Symbol  
No.  
Characteristics(1)  
Min.  
Typical(2) Max. Units  
Conditions  
SCKx Output Low Time(3)  
SCKx Output High Time(3)  
SCKx Output Fall Time(4)  
SCKx Output Rise Time(4)  
SDOx Data Output Fall Time(4)  
SDOx Data Output Rise Time(4)  
SP10  
SP11  
SP20  
SP21  
SP30  
SP31  
SP35  
TSCL  
TSCH  
TSCF  
TSCR  
TDOF  
TDOR  
TSCK/2  
TSCK/2  
—
—
—
—
—
—
—
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
—
—
See parameter DO32  
See parameter DO31  
See parameter DO32  
See parameter DO31  
VDD > 2.7V  
—
—
—
—
—
—
—
—
—
—
15  
20  
—
—
—
TSCH2DOV, SDOx Data Output Valid after  
TSCL2DOV SCKx Edge  
—
—
VDD < 2.7V  
SP40  
SP41  
TDIV2SCH, Setup Time of SDIx Data Input  
—
10  
TDIV2SCL  
TSCH2DIL, Hold Time of SDIx Data Input  
TSCL2DIL to SCKx Edge  
Note 1: These parameters are characterized, but not tested in manufacturing.  
to SCKx Edge  
—
—
ns  
—
10  
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only  
and are not tested.  
3: The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not  
violate this specification.  
4: Assumes 50 pF load on all SPIx pins.  
© 2011 Microchip Technology Inc.  
DS61143H-page 171  
PIC32MX3XX/4XX  
FIGURE 29-11:  
SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS  
SP36  
SCKX  
(CKP = 0)  
SP11  
SP10  
SP21  
SP20  
SP20  
SP21  
SCKX  
(CKP = 1)  
SP35  
LSb  
MSb  
Bit 14 - - - - - -1  
SDOX  
SDIX  
SP30,SP31  
MSb In  
SP41  
Bit 14 - - - -1  
LSb In  
SP40  
Note: Refer to Figure 29-1 for load conditions.  
TABLE 29-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
AC CHARACTERISTICS  
-40°C ≤TA ≤+105°C for V-Temp  
Param.  
No.  
Symbol  
TSCL  
Characteristics(1)  
Min.  
Typical(2) Max. Units  
Conditions  
SCKx Output Low Time(3)  
SCKx Output High Time(3)  
SCKx Output Fall Time(4)  
SCKx Output Rise Time(4)  
SDOx Data Output Fall Time(4)  
SDOx Data Output Rise Time(4)  
SP10  
SP11  
SP20  
SP21  
SP30  
SP31  
SP35  
TSCK/2  
TSCK/2  
—
—
—
—
—
—
—
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
—
TSCH  
TSCF  
TSCR  
TDOF  
TDOR  
—
See parameter DO32  
See parameter DO31  
See parameter DO32  
See parameter DO31  
VDD > 2.7V  
—
—
—
—
—
—
—
—
—
—
15  
20  
—
—
—
TSCH2DOV, SDOx Data Output Valid after  
TSCL2DOV SCKx Edge  
—
—
VDD < 2.7V  
SP36  
SP40  
TDOV2SC, SDOx Data Output Setup to  
TDOV2SCL First SCKx Edge  
—
15  
TDIV2SCH, Setup Time of SDIx Data Input  
TDIV2SCL to SCKx Edge  
—
—
—
—
—
—
—
—
ns  
ns  
ns  
ns  
VDD > 2.7V  
VDD < 2.7V  
VDD > 2.7V  
VDD < 2.7V  
15  
20  
15  
20  
SP41  
TSCH2DIL, Hold Time of SDIx Data Input  
TSCL2DIL  
to SCKx Edge  
Note 1: These parameters are characterized, but not tested in manufacturing.  
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only  
and are not tested.  
3: The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not  
violate this specification.  
4: Assumes 50 pF load on all SPIx pins.  
DS61143H-page 172  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
FIGURE 29-12:  
SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS  
SSX  
SP52  
SP50  
SCKX  
(CKP = 0)  
SP71  
SP70  
SP72  
SP73  
SP72  
SCKX  
(CKP = 1)  
SP35  
SP73  
LSb  
MSb  
SDOX  
SDIX  
Bit 14 - - - - - -1  
SP51  
SP30,SP31  
Bit 14 - - - -1  
MSb In  
SP41  
LSb In  
SP40  
Note: Refer to Figure 29-1 for load conditions.  
TABLE 29-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
AC CHARACTERISTICS  
-40°C ≤TA ≤+105°C for V-Temp  
Param.  
No.  
Symbol  
TSCL  
Characteristics(1)  
Min.  
Typical(2) Max. Units  
Conditions  
SCKx Input Low Time(3)  
SCKx Input High Time(3)  
SCKx Input Fall Time  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
—
TSCK/2  
TSCK/2  
—
SP70  
SP71  
SP72  
SP73  
SP30  
SP31  
TSCH  
TSCF  
TSCR  
TDOF  
TDOR  
—
See parameter DO32  
See parameter DO31  
See parameter DO32  
See parameter DO31  
VDD > 2.7V  
SCKx Input Rise Time  
—
SDOx Data Output Fall Time(4)  
SDOx Data Output Rise Time(4)  
—
—
SP35 TSCH2DOV, SDOx Data Output Valid after  
TSCL2DOV SCKx Edge  
—
15  
20  
—
—
VDD < 2.7V  
SP40 TDIV2SCH, Setup Time of SDIx Data Input  
TDIV2SCL to SCKx Edge  
—
10  
SP41 TSCH2DIL, Hold Time of SDIx Data Input  
—
—
—
—
—
—
25  
—
ns  
ns  
ns  
ns  
10  
—
—
—
—
TSCL2DIL  
to SCKx Edge  
SP50 TSSL2SCH, SSx ↓to SCKx ↑ or SCKx Input  
175  
TSSL2SCL  
SP51 TSSH2DOZ SSx ↑ to SDOx Output  
5
High-Impedance(3)  
SP52  
TSCH2SSH SSx after SCKx Edge  
TSCL2SSH  
TSCK + 20  
Note 1: These parameters are characterized, but not tested in manufacturing.  
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance  
only and are not tested.  
3: The minimum clock period for SCKx is 40 ns.  
4: Assumes 50 pF load on all SPIx pins.  
© 2011 Microchip Technology Inc.  
DS61143H-page 173  
PIC32MX3XX/4XX  
FIGURE 29-13:  
SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS  
SP60  
SSx  
SP50  
SP52  
SCKx  
(CKP = 0)  
SP71  
MSb  
SP70  
SP72  
SP73  
SP73  
SCKx  
(CKP = 1)  
SP35  
SP72  
LSb  
Bit 14 - - - - - -1  
SDOx  
SDIx  
SP30,SP31  
Bit 14 - - - -1  
SP51  
MSb In  
SP41  
LSb In  
SP40  
Note: Refer to Figure 29-1 for load conditions.  
TABLE 29-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
AC CHARACTERISTICS  
-40°C ≤TA ≤+105°C for V-Temp  
Param.  
No.  
Symbol  
TSCL  
Characteristics(1)  
Min.  
Typical(2) Max.  
Units  
Conditions  
SCKx Input Low Time(3)  
SCKx Input High Time(3)  
SCKx Input Fall Time  
—
—
5
—
—
10  
10  
—
—
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
—
—
—
—
TSCK/2  
TSCK/2  
—
SP70  
SP71  
SP72  
SP73  
SP30  
SP31  
SP35  
TSCH  
TSCF  
TSCR  
TDOF  
TDOR  
SCKx Input Rise Time  
—
5
SDOx Data Output Fall Time(4)  
SDOx Data Output Rise Time(4)  
—
—
—
—
—
—
See parameter DO32  
See parameter DO31  
VDD > 2.7V  
—
TSCH2DOV, SDOx Data Output Valid after  
TSCL2DOV SCKx Edge  
—
20  
30  
—
—
VDD < 2.7V  
SP40  
SP41  
SP50  
SP51  
SP52  
SP60  
TDIV2SCH, Setup Time of SDIx Data Input  
TDIV2SCL to SCKx Edge  
—
10  
10  
175  
5
TSCH2DIL, Hold Time of SDIx Data Input  
TSCL2DIL  
—
—
—
—
—
—
—
25  
—
25  
ns  
ns  
ns  
ns  
ns  
—
—
—
—
—
to SCKx Edge  
TSSL2SCH, SSx ↓to SCKx ↓or SCKx ↑  
TSSL2SCL Input  
TSSH2DOZ SSx ↑ to SDOX Output  
High-Impedance(4)  
TSCH2SSH SSx ↑ after SCKx Edge  
TSCL2SSH  
TSCK +  
20  
TSSL2DOV SDOx Data Output Valid after  
SSx Edge  
—
Note 1: These parameters are characterized, but not tested in manufacturing.  
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only  
and are not tested.  
3: The minimum clock period for SCKx is 40 ns.  
4: Assumes 50 pF load on all SPIx pins.  
DS61143H-page 174  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
FIGURE 29-14:  
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)  
SCLx  
IM31  
IM34  
IM30  
IM33  
SDAx  
Stop  
Condition  
Start  
Condition  
Note: Refer to Figure 29-1 for load conditions.  
FIGURE 29-15:  
I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)  
IM20  
IM21  
IM11  
IM10  
SCLx  
IM11  
IM26  
IM10  
IM33  
IM25  
SDAx  
In  
IM45  
IM40  
IM40  
SDAx  
Out  
Note: Refer to Figure 29-1 for load conditions.  
© 2011 Microchip Technology Inc.  
DS61143H-page 175  
PIC32MX3XX/4XX  
TABLE 29-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
-40°C ≤TA ≤+105°C for V-Temp  
AC CHARACTERISTICS  
Param.  
Symbol  
No.  
Characteristics  
Min.(1)  
Max.  
Units  
Conditions  
IM10  
TLO:SCL Clock Low Time 100 kHz mode  
400 kHz mode  
TPB * (BRG + 2)  
—
—
μs  
μs  
μs  
μs  
μs  
μs  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
μs  
μs  
μs  
μs  
μs  
μs  
μs  
μs  
μs  
μs  
μs  
μs  
ns  
ns  
ns  
ns  
ns  
ns  
μs  
μs  
μs  
TPB * (BRG + 2)  
—
1 MHz mode(2)  
—
TPB * (BRG + 2)  
IM11  
THI:SCL Clock High Time 100 kHz mode  
—
TPB * (BRG + 2)  
400 kHz mode  
1 MHz mode(2)  
—
TPB * (BRG + 2)  
—
—
TPB * (BRG + 2)  
IM20  
IM21  
IM25  
IM26  
IM30  
TF:SCL  
TR:SCL  
SDAx and SCLx 100 kHz mode  
—
300  
300  
100  
1000  
300  
300  
—
CB is specified to be  
from 10 to 400 pF.  
Fall Time  
400 kHz mode  
1 MHz mode(2)  
20 + 0.1 CB  
—
SDAx and SCLx 100 kHz mode  
—
CB is specified to be  
from 10 to 400 pF.  
Rise Time  
400 kHz mode  
1 MHz mode(2)  
100 kHz mode  
400 kHz mode  
1 MHz mode(2)  
100 kHz mode  
400 kHz mode  
1 MHz mode(2)  
20 + 0.1 CB  
—
TSU:DAT Data Input  
Setup Time  
250  
100  
—
—
—
100  
—
THD:DAT Data Input  
Hold Time  
0
—
0
0.9  
0.3  
—
0
TSU:STA Start Condition 100 kHz mode  
Only relevant for  
Repeated Start  
condition.  
TPB * (BRG + 2)  
TPB * (BRG + 2)  
TPB * (BRG + 2)  
TPB * (BRG + 2)  
TPB * (BRG + 2)  
TPB * (BRG + 2)  
TPB * (BRG + 2)  
TPB * (BRG + 2)  
TPB * (BRG + 2)  
TPB * (BRG + 2)  
TPB * (BRG + 2)  
TPB * (BRG + 2)  
—
Setup Time  
400 kHz mode  
—
1 MHz mode(2)  
—
IM31  
IM33  
IM34  
THD:STA Start Condition 100 kHz mode  
—
After this period, the  
first clock pulse is  
generated.  
Hold Time  
400 kHz mode  
—
1 MHz mode(2)  
—
TSU:STO Stop Condition 100 kHz mode  
—
Setup Time  
400 kHz mode  
—
—
1 MHz mode(2)  
—
THD:STO Stop Condition  
Hold Time  
100 kHz mode  
400 kHz mode  
1 MHz mode(2)  
100 kHz mode  
400 kHz mode  
1 MHz mode(2)  
—
—
—
—
—
IM40  
IM45  
TAA:SCL Output Valid  
from Clock  
3500  
1000  
350  
—
—
—
TBF:SDA Bus Free Time 100 kHz mode  
4.7  
The amount of time the  
bus must be free  
before a new  
400 kHz mode  
1 MHz mode(2)  
1.3  
—
0.5  
—
transmission can start.  
IM50  
IM51  
CB  
Bus Capacitive Loading  
Pulse Gobbler Delay(3)  
—
400  
312  
pF  
ns  
—
—
TPGD  
52  
Note 1: BRG is the value of the I2C™ Baud Rate Generator.  
2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).  
3: The typical value for this parameter is 104 ns.  
DS61143H-page 176  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
FIGURE 29-16:  
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)  
SCLx  
IS34  
IS31  
IS30  
IS33  
SDAx  
Stop  
Condition  
Start  
Condition  
Note: Refer to Figure 29-1 for load conditions.  
FIGURE 29-17:  
I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)  
IS20  
IS21  
IS11  
IS10  
SCLx  
IS30  
IS26  
IS31  
IS33  
IS25  
SDAx  
In  
IS45  
IS40  
IS40  
SDAx  
Out  
Note: Refer to Figure 29-1 for load conditions.  
© 2011 Microchip Technology Inc.  
DS61143H-page 177  
PIC32MX3XX/4XX  
TABLE 29-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
-40°C ≤TA ≤+105°C for V-Temp  
AC CHARACTERISTICS  
Param.  
Symbol  
No.  
Characteristics  
Min.  
Max. Units  
Conditions  
IS10  
IS11  
TLO:SCL Clock Low Time 100 kHz mode  
400 kHz mode  
4.7  
—
—
μs  
μs  
PBCLK must operate at a  
minimum of 800 KHz.  
1.3  
PBCLK must operate at a  
minimum of 3.2 MHz.  
1 MHz mode(1)  
0.5  
4.0  
—
—
μs  
μs  
—
THI:SCL  
Clock High Time 100 kHz mode  
PBCLK must operate at a  
minimum of 800 KHz.  
400 kHz mode  
0.6  
—
μs  
PBCLK must operate at a  
minimum of 3.2 MHz.  
1 MHz mode(1)  
0.5  
—
300  
300  
100  
1000  
300  
300  
—
μs  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
μs  
μs  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
μs  
μs  
μs  
pF  
—
IS20  
IS21  
IS25  
IS26  
IS30  
IS31  
IS33  
IS34  
IS40  
IS45  
IS50  
TF:SCL  
TR:SCL  
SDAx and SCLx 100 kHz mode  
—
CB is specified to be from  
10 to 400 pF.  
Fall Time  
400 kHz mode  
1 MHz mode(1)  
20 + 0.1 CB  
—
—
SDAx and SCLx 100 kHz mode  
Rise Time  
CB is specified to be from  
10 to 400 pF.  
400 kHz mode  
1 MHz mode(1)  
100 kHz mode  
400 kHz mode  
1 MHz mode(1)  
100 kHz mode  
400 kHz mode  
1 MHz mode(1)  
100 kHz mode  
400 kHz mode  
1 MHz mode(1)  
100 kHz mode  
400 kHz mode  
1 MHz mode(1)  
100 kHz mode  
400 kHz mode  
1 MHz mode(1)  
100 kHz mode  
400 kHz mode  
1 MHz mode(1)  
20 + 0.1 CB  
—
TSU:DAT Data Input  
Setup Time  
250  
100  
100  
0
—
—
—
—
THD:DAT Data Input  
Hold Time  
—
0
0.9  
0.3  
—
0
TSU:STA Start Condition  
Setup Time  
4700  
600  
250  
4000  
600  
250  
4000  
600  
600  
4000  
600  
250  
0
Only relevant for Repeated  
Start condition.  
—
—
THD:STA Start Condition  
Hold Time  
—
After this period, the first  
clock pulse is generated.  
—
—
TSU:STO Stop Condition  
Setup Time  
—
—
—
—
—
—
THD:STO Stop Condition  
Hold Time  
—
—
TAA:SCL  
Output Valid from 100 kHz mode  
3500  
1000  
350  
—
Clock  
400 kHz mode  
1 MHz mode(1)  
100 kHz mode  
400 kHz mode  
1 MHz mode(1)  
0
0
TBF:SDA Bus Free Time  
4.7  
The amount of time the bus  
must be free before a new  
transmission can start.  
1.3  
—
0.5  
—
CB  
Bus Capacitive Loading  
—
400  
—
Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).  
DS61143H-page 178  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
TABLE 29-34: ADC MODULE SPECIFICATIONS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
-40°C ≤TA ≤+105°C for V-Temp  
AC CHARACTERISTICS  
Param.  
Symbol  
Characteristics  
Min.  
Typical  
Max.  
Units  
Conditions  
No.  
Device Supply  
AD01  
AVDD  
Module VDD Supply  
Module VSS Supply  
Greater of  
VDD – 0.3  
or 2.5  
—
Lesser of  
VDD + 0.3  
or 3.6  
V
V
—
—
AD02  
AVSS  
VSS  
—
VSS + 0.3  
Reference Inputs  
AD05  
AD05a  
AD06  
VREFH  
Reference Voltage High AVSS + 2.0  
2.5  
—
—
—
AVDD  
3.6  
V
V
V
(Note 1)  
VREFH = AVDD (Note 3)  
VREFL  
VREF  
Reference Voltage Low  
AVSS  
VREFH –  
2.0  
(Note 1)  
AD07  
AD08  
Absolute Reference  
Voltage  
2.0  
—
AVDD  
V
(Note 3)  
(VREFH – VREFL)  
IREF  
Current Drain  
—
250  
—
400  
3
μA ADC operating  
μA ADC off  
Analog Input  
AD12 VINH-VINL Full-Scale Input Span  
VREFL  
—
—
VREFH  
V
V
—
—
AD13  
AD14  
AD15  
VINL  
Absolute VINL Input  
Voltage  
AVSS – 0.3  
AVDD/2  
VIN  
Absolute Input Voltage  
AVSS – 0.3  
—
—
AVDD +  
0.3  
V
—
—
Leakage Current  
±0.001  
±0.610  
μA VINL = AVSS = VREFL = 0V,  
AVDD = VREFH = 3.3V  
Source Impedance = 10KΩ  
AD17  
RIN  
Recommended  
—
—
5K  
Ω
(Note 1)  
Impedance of Analog  
Voltage Source  
ADC Accuracy – Measurements with External VREF+/VREF-  
AD20c Nr  
Resolution  
10 data bits  
—
bits  
—
AD21c INL  
Integral Nonlinearity  
—
—
<±1  
<±1  
LSb VINL = AVSS = VREFL = 0V,  
AVDD = VREFH = 3.3V  
AD22c DNL  
Differential Nonlinearity  
—
LSb VINL = AVSS = VREFL = 0V,  
AVDD = VREFH = 3.3V  
(Note 2)  
AD23c GERR  
AD24n EOFF  
Gain Error  
—
—
—
—
—
—
<±1  
<±1  
—
LSb VINL = AVSS = VREFL = 0V,  
AVDD = VREFH = 3.3V  
Offset Error  
LSb VINL = AVSS = 0V,  
AVDD = 3.3V  
AD25c  
—
Monotonicity  
—
Guaranteed  
Note 1: These parameters are not characterized or tested in manufacturing.  
2: With no missing codes.  
3: These parameters are characterized, but not tested in manufacturing.  
4: Characterized with 1 kHz sinewave.  
© 2011 Microchip Technology Inc.  
DS61143H-page 179  
PIC32MX3XX/4XX  
TABLE 29-34: ADC MODULE SPECIFICATIONS (CONTINUED)  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
-40°C ≤TA ≤+105°C for V-Temp  
AC CHARACTERISTICS  
Param.  
Symbol  
Characteristics  
Min.  
Typical  
Max.  
Units  
Conditions  
No.  
ADC Accuracy – Measurements with Internal VREF+/VREF-  
AD20d Nr  
AD21d INL  
Resolution  
10 data bits  
—
bits (Note 3)  
Integral Nonlinearity  
—
—
—
—
—
<±1  
<±1  
<±4  
<±2  
—
LSb VINL = AVSS = 0V,  
AVDD = 2.5V to 3.6V  
(Note 3)  
AD22d DNL  
AD23d GERR  
AD24d EOFF  
Differential Nonlinearity  
Gain Error  
—
—
—
—
LSb VINL = AVSS = 0V,  
AVDD = 2.5V to 3.6V  
(Notes 2,3)  
LSb VINL = AVSS = 0V,  
AVDD = 2.5V to 3.6V  
(Note 3)  
Offset Error  
LSb VINL = AVSS = 0V,  
AVDD = 2.5V to 3.6V  
(Note 3)  
AD25d  
—
Monotonicity  
—
Guaranteed  
Dynamic Performance  
AD31b  
SINAD Signal to Noise and  
55  
58.5  
9.5  
—
—
dB (Notes 3, 4)  
bits (Notes 3, 4)  
Distortion  
AD34b  
ENOB Effective Number of Bits  
9.0  
Note 1: These parameters are not characterized or tested in manufacturing.  
2: With no missing codes.  
3: These parameters are characterized, but not tested in manufacturing.  
4: Characterized with 1 kHz sinewave.  
DS61143H-page 180  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
(2)  
TABLE 29-35: 10-BIT ADC CONVERSION RATE PARAMETERS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
-40°C ≤TA ≤+105°C for V-Temp  
TAD  
Sampling  
ADC Speed  
RS Max  
VDD  
ADC Channels Configuration  
Minimum Time Min  
1 MIPS to 400 ksps(1)  
65 ns  
132 ns  
500Ω 3.0V to 3.6V  
VREF- VREF+  
CH  
X
ANx  
SHA  
ADC  
Up to 400 ksps  
200 ns  
200 ns  
5.0 kΩ 2.5V to 3.6V  
V
REF  
-
V
REF  
+
or  
or  
AVSS AVDD  
CHX  
ANx  
SHA  
ADC  
ANx or VREF  
-
Up to 300 ksps  
200 ns  
200 ns  
5.0 kΩ 2.5V to 3.6V  
V
REF- VREF+  
or  
or  
AVSS AVDD  
CHX  
ANx  
SHA  
ADC  
ANx or VREF  
-
Note 1: External VREF- and VREF+ pins must be used for correct operation.  
2: These parameters are characterized, but not tested in manufacturing.  
© 2011 Microchip Technology Inc.  
DS61143H-page 181  
PIC32MX3XX/4XX  
TABLE 29-36: ANALOG-TO-DIGITAL CONVERSION TIMING REQUIREMENTS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
AC CHARACTERISTICS  
-40°C ≤TA ≤+105°C for V-Temp  
Param.  
No.  
Symbol  
Characteristics  
Min.  
Typical(1) Max.  
Units  
Conditions  
Clock Parameters  
AD50  
AD51  
TAD  
TRC  
Analog-to-Digital Clock Period  
65  
—
—
—
—
ns  
ns  
See Table 29-35 and  
Note 2  
Analog-to-Digital Internal RC  
Oscillator Period  
250  
See Note 3  
Conversion Rate  
AD55  
AD56  
TCONV  
FCNV  
Conversion Time  
—
—
12 TAD  
—
—
1000  
400  
—
—
—
Throughput Rate  
(Sampling Speed)  
KSPS AVDD = 3.0V to 3.6V  
KSPS AVDD = 2.5V to 3.6V  
—
—
AD57  
TSAMP  
Sample Time  
1 TAD  
—
—
TSAMP must be ≥ 132  
ns.  
Timing Parameters  
AD60  
TPCS  
Conversion Start from Sample  
Trigger  
—
1.0 TAD  
—
—
Auto-Convert Trigger  
(SSRC<2:0> = 111)  
not selected.  
See Note 3  
AD61  
AD62  
AD63  
TPSS  
TCSS  
TDPU  
Sample Start from Setting  
Sample (SAMP) bit  
0.5 TAD  
—
—
0.5 TAD  
—
1.5 TAD  
—
—
μs  
—
See Note 3  
See Note 3  
Conversion Completion to  
Sample Start (ASAM = 1)  
—
2
Time to Stabilize Analog Stage  
from Analog-to-Digital OFF to  
Analog-to-Digital ON  
—
Note 1: These parameters are characterized, but not tested in manufacturing.  
2: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity  
performance, especially at elevated temperatures.  
3: Characterized by design but not tested.  
DS61143H-page 182  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
FIGURE 29-18:  
ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS  
(CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000)  
AD50  
ADCLK  
Instruction  
Execution  
Set SAMP  
Clear SAMP  
SAMP  
ch0_dischrg  
ch0_samp  
ch1_dischrg  
ch1_samp  
eoc  
AD61  
AD60  
TSAMP  
AD55  
AD55  
CONV  
ADxIF  
Buffer(0)  
Buffer(1)  
1
2
3
4
5
6
7
8
5
6
7
8
– Software sets ADxCON. SAMP to start sampling.  
1
2
– Sampling starts after discharge period. TSAMP is described in Section 17. “10-bit Analog-to-Digital Converter (ADC)”  
(DS61104) of the “PIC32 Family Reference Manual”.  
– Software clears ADxCON. SAMP to start conversion.  
– Sampling ends, conversion sequence starts.  
– Convert bit 9.  
3
4
5
6
7
8
– Convert bit 8.  
– Convert bit 0.  
– One TAD for end of conversion.  
© 2011 Microchip Technology Inc.  
DS61143H-page 183  
PIC32MX3XX/4XX  
FIGURE 29-19:  
ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS  
(CHPS<1:0> = 01, SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)  
AD50  
ADCLK  
Instruction  
Execution  
Set ADON  
SAMP  
ch0_dischrg  
ch0_samp  
ch1_dischrg  
ch1_samp  
eoc  
TSAMP  
TSAMP  
AD55  
AD55  
TCONV  
CONV  
ADxIF  
Buffer(0)  
Buffer(1)  
1
2
3
4
5
6
7
3
4
5
6
8
3
4
– Software sets ADxCON. ADON to start AD operation.  
1
2
TSAMP is described in Section 17. “10-bit Analog-to-Digital Converter (ADC)”  
– Sampling starts after discharge period.  
(DS61104) of the “PIC32 Family Reference Manual”.  
– Convert bit 9.  
3
4
5
6
7
8
– Convert bit 8.  
– Convert bit 0.  
– One TAD for end of conversion.  
– Begin conversion of next channel.  
– Sample for time specified by SAMC<4:0>.  
DS61143H-page 184  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
FIGURE 29-20:  
PARALLEL SLAVE PORT TIMING  
CS  
PS5  
RD  
PS6  
WR  
PS4  
PS7  
PMD<7:0>  
PS1  
PS3  
PS2  
TABLE 29-37: PARALLEL SLAVE PORT REQUIREMENTS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
-40°C ≤TA ≤+105°C for V-Temp  
AC CHARACTERISTICS  
Param.  
Symbol  
No.  
Characteristics(1)  
Min.  
Typical Max. Units  
Conditions  
PS1  
PS2  
PS3  
PS4  
TdtV2wrH Data In Valid before WR or CS  
Inactive (setup time)  
20  
—
—
—
—
—
—
60  
10  
ns  
ns  
ns  
ns  
—
TwrH2dtI WR or CS Inactive to Data –  
In Invalid (hold time)  
40  
—
0
—
—
—
TrdL2dtV RD and CS Active to Data –  
Out Valid  
TrdH2dtI RD Active or CS Inactive to Data –  
Out Invalid  
PS5  
PS6  
PS7  
Tcs  
CS Active Time  
WR Active Time  
RD Active Time  
TPB + 40  
TPB + 25  
TPB + 25  
—
—
—
—
—
—
ns  
ns  
ns  
—
—
—
TWR  
TRD  
Note 1: These parameters are characterized, but not tested in manufacturing.  
© 2011 Microchip Technology Inc.  
DS61143H-page 185  
PIC32MX3XX/4XX  
FIGURE 29-21:  
PARALLEL MASTER PORT READ TIMING DIAGRAM  
TPB  
TPB  
TPB  
TPB  
TPB  
TPB  
TPB  
TPB  
PB Clock  
PM4  
Address  
PMA<13:18>  
PMD<7:0>  
PM6  
Data  
Address<7:0>
PM2  
PM7  
PM3  
PMRD  
PM5  
PMWR  
PM1  
PMALL/PMALH  
PMCS<2:1>  
TABLE 29-38: PARALLEL MASTER PORT READ TIMING REQUIREMENTS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
-40°C ≤TA ≤+105°C for V-Temp  
AC CHARACTERISTICS  
Param.  
Symbol  
No.  
Characteristics(1)  
Min.  
Typical  
Max.  
Units  
Conditions  
PM1  
PM2  
TLAT  
PMALL/PMALH Pulse Width  
—
—
1 TPB  
2 TPB  
—
—
—
—
—
—
TADSU  
Address Out Valid to PMALL/PMALH  
Invalid (address setup time)  
PM3  
PM4  
TADHOLD PMALL/PMALH Invalid to Address  
Out Invalid (address hold time)  
—
5
1 TPB  
—
—
—
—
ns  
—
—
TAHOLD  
PMRD Inactive to Address Out  
Invalid  
(address hold time)  
PM5  
PM6  
TRD  
PMRD Pulse Width  
—
1 TPB  
—
—
—
—
ns  
—
—
TDSU  
PMRD or PMENB Active to Data In  
Valid (data setup time)  
15  
PM7  
TDHOLD PMRD or PMENB Inactive to Data In  
Invalid (data hold time)  
—
80  
—
ns  
—
Note 1: These parameters are characterized, but not tested in manufacturing.  
DS61143H-page 186  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
FIGURE 29-22:  
PARALLEL MASTER PORT WRITE TIMING DIAGRAM  
TPB  
TPB  
TPB  
TPB  
TPB  
TPB  
TPB  
TPB  
PB Clock  
Address  
PMA<13:18>  
PM2 + PM3  
Address<7:0>  
PMD<7:0>  
Data  
PM12  
PM13  
PMRD  
PMWR  
PM11  
PM1  
PMALL/PMALH  
PMCS<2:1>  
TABLE 29-39: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
-40°C ≤TA ≤+105°C for V-Temp  
AC CHARACTERISTICS  
Param.  
Symbol  
No.  
Characteristics(1)  
PMWR Pulse Width  
Min.  
Typical  
Max.  
Units  
Conditions  
PM11  
TWR  
—
—
1 TPB  
2 TPB  
—
—
—
—
—
—
PM12 TDVSU  
Data Out Valid before PMWR or  
PMENB goes Inactive (data setup  
time)  
PM13 TDVHOLD PMWR or PMEMB Invalid to Data  
Out Invalid (data hold time)  
—
1 TPB  
—
—
—
Note 1: These parameters are characterized, but not tested in manufacturing.  
© 2011 Microchip Technology Inc.  
DS61143H-page 187  
PIC32MX3XX/4XX  
TABLE 29-40: OTG ELECTRICAL SPECIFICATIONS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
-40°C ≤TA ≤+105°C for V-Temp  
AC CHARACTERISTICS  
Param.  
Symbol  
No.  
Characteristics(1)  
USB Voltage  
Min.  
Typ  
Max.  
Units  
Conditions  
USB313 VUSB  
3.0  
—
3.6  
V
Voltage on VUSB must  
be in this range for  
proper USB operation.  
USB315 VILUSB Input Low Voltage for USB Buffer  
USB316 VIHUSB Input High Voltage for USB Buffer  
—
2.0  
—
—
—
—
0.8  
—
V
V
V
—
—
USB318 VDIFS  
Differential Input Sensitivity  
0.2  
The difference  
between D+ and D-  
must exceed this value  
while VCM is met.  
USB319 VCM  
USB320 ZOUT  
USB321 VOL  
Differential Common Mode Range  
Driver Output Impedance  
Voltage Output Low  
0.8  
28.0  
0.0  
—
—
—
2.5  
44.0  
0.3  
V
Ω
V
—
—
1.5 kΩ load connected  
to 3.6V.  
USB322 VOH  
Voltage Output High  
2.8  
—
3.6  
V
1.5 kΩ load connected  
to ground.  
Note 1: These parameters are characterized, but not tested in manufacturing.  
DS61143H-page 188  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
FIGURE 29-23:  
EJTAG TIMING CHARACTERISTICS  
TTCKeye  
TTCKhigh  
TTCKlow  
Trf  
TCK  
Trf  
TMS  
TDI  
Trf  
TTsetup TThold  
Trf  
TDO  
TRST*  
TTRST*low  
TTDOout  
TTDOzstate  
Undefined  
Defined  
Trf  
TABLE 29-41: EJTAG TIMING REQUIREMENTS  
AC CHARACTERISTICS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤TA ≤+85°C for Industrial  
-40°C ≤TA ≤+105°C for V-Temp  
Param.  
No.  
Symbol  
Description(1)  
TCK Cycle Time  
Min.  
Max. Units  
Conditions  
EJ1  
TTCKCYC  
TTCKHIGH  
TTCKLOW  
TTSETUP  
25  
10  
10  
5
—
—
—
—
ns  
ns  
ns  
ns  
—
—
—
—
EJ2  
EJ3  
EJ4  
TCK High Time  
TCK Low Time  
TAP Signals Setup Time Before  
Rising TCK  
EJ5  
EJ6  
EJ7  
TTHOLD  
TAP Signals Hold Time After  
Rising TCK  
3
—
5
ns  
ns  
ns  
—
—
—
TTDOOUT  
TDO Output Delay Time from  
Falling TCK  
—
—
TTDOZSTATE TDO 3-State Delay Time from  
Falling TCK  
5
EJ8  
EJ9  
TTRSTLOW  
TRF  
TRST Low Time  
25  
—
—
—
ns  
ns  
—
—
TAP Signals Rise/Fall Time, All  
Input and Output  
Note 1: These parameters are characterized, but not tested in manufacturing.  
© 2011 Microchip Technology Inc.  
DS61143H-page 189  
PIC32MX3XX/4XX  
NOTES:  
DS61143H-page 190  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
30.0 PACKAGING INFORMATION  
30.1 Package Marking Information  
64-Lead TQFP (10x10x1 mm)  
Example  
PIC32MX360F  
512H-80I/PT  
XXXXXXXXXX  
XXXXXXXXXX  
XXXXXXXXXX  
YYWWNNN  
e
3
0510017  
100-Lead TQFP (12x12x1 mm)  
Example  
PIC32MX360F  
256L-80I/PT  
XXXXXXXXXXXX  
XXXXXXXXXXXX  
YYWWNNN  
e
3
0510017  
64-Lead QFN (9x9x0.9 mm)  
Example  
XXXXXXXXXX  
XXXXXXXXXX  
XXXXXXXXXX  
PIC32MX360F  
512H-80I/MR  
e
3
YYWWNNN  
0510017  
121-Lead XBGA (10x10x1.1 mm)  
Example  
XXXXXXXXXX  
XXXXXXXXXX  
XXXXXXXXXX  
YYWWNNN  
PIC32MX460F  
512L-80I/BG  
e
3
0510017  
Legend: XX...X Customer-specific information  
Y
YY  
WW  
NNN  
Year code (last digit of calendar year)  
Year code (last 2 digits of calendar year)  
Week code (week of January 1 is week ‘01’)  
Alphanumeric traceability code  
Pb-free JEDEC designator for Matte Tin (Sn)  
*
This package is Pb-free. The Pb-free JEDEC designator ( 
e
3
can be found on the outer packaging for this package.  
Note: In the event the full Microchip part number cannot be marked on one line, it will  
be carried over to the next line, thus limiting the number of available  
characters for customer-specific information.  
© 2011 Microchip Technology Inc.  
DS61143H-page 191  
PIC32MX3XX/4XX  
30.2 Package Details  
The following sections give the technical details of the packages.  
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢏꢌꢐꢇꢑꢒꢅꢆꢇꢓꢉꢅꢋꢔꢅꢍꢕꢇꢖꢈꢎꢗꢇꢘꢇꢙꢚꢛꢙꢚꢛꢙꢇꢜꢜꢇꢝꢞꢆꢟꢠꢇꢡꢢꢚꢚꢇꢜꢜꢇꢣꢎꢑꢓꢈꢤ  
ꢥꢞꢋꢄꢦ ꢭꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢛꢉꢖꢮꢉꢥꢌꢅꢋꢐꢉꢗꢃꢄꢥꢇꢓꢅꢛꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢡꢃꢖꢐꢕꢖꢘꢃꢛꢅꢂꢉꢖꢮꢉꢥꢃꢄꢥꢅꢧꢛꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ  
ꢘꢏꢏꢛꢪꢯꢯꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢛꢁꢖꢕꢑꢯꢛꢉꢖꢮꢉꢥꢃꢄꢥ  
D
D1  
E
e
E1  
N
b
1 2 3  
NOTE 1  
c
NOTE 2  
α
A
φ
A2  
A1  
β
L
L1  
ꢰꢄꢃꢏꢇ  
ꢡꢱꢲꢲꢱꢡꢠꢫꢠꢬꢧ  
ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢅꢲꢃꢑꢃꢏꢇ  
ꢡꢱꢳ  
ꢳꢴꢡ  
ꢶꢤ  
ꢢꢁꢣꢢꢅꢩꢧꢚ  
ꢸ
ꢀꢁꢢꢢ  
ꢸ
ꢡꢦꢵ  
ꢳꢈꢑꢔꢌꢐꢅꢕꢎꢅꢲꢌꢉꢋꢇ  
ꢲꢌꢉꢋꢅꢂꢃꢏꢖꢘ  
ꢴꢆꢌꢐꢉꢊꢊꢅꢷꢌꢃꢥꢘꢏ  
ꢡꢕꢊꢋꢌꢋꢅꢂꢉꢖꢮꢉꢥꢌꢅꢫꢘꢃꢖꢮꢄꢌꢇꢇ  
ꢧꢏꢉꢄꢋꢕꢎꢎꢅꢅ  
ꢭꢕꢕꢏꢅꢲꢌꢄꢥꢏꢘ  
ꢳ
ꢌ
ꢦ
ꢦꢙ  
ꢦꢀ  
ꢲ
ꢸ
ꢀꢁꢙꢢ  
ꢀꢁꢢꢣ  
ꢢꢁꢀꢣ  
ꢢꢁꢺꢣ  
ꢢꢁꢹꢣ  
ꢢꢁꢢꢣ  
ꢢꢁꢤꢣ  
ꢢꢁꢶꢢ  
ꢭꢕꢕꢏꢛꢐꢃꢄꢏ  
ꢭꢕꢕꢏꢅꢦꢄꢥꢊꢌ  
ꢲꢀ  
ꢀ
ꢀꢁꢢꢢꢅꢬꢠꢭ  
ꢞꢁꢣꢻ  
ꢢꢻ  
ꢺꢻ  
ꢴꢆꢌꢐꢉꢊꢊꢅꢼꢃꢋꢏꢘ  
ꢴꢆꢌꢐꢉꢊꢊꢅꢲꢌꢄꢥꢏꢘ  
ꢠ
ꢟ
ꢠꢀ  
ꢟꢀ  
ꢖ
ꢀꢙꢁꢢꢢꢅꢩꢧꢚ  
ꢀꢙꢁꢢꢢꢅꢩꢧꢚ  
ꢀꢢꢁꢢꢢꢅꢩꢧꢚ  
ꢀꢢꢁꢢꢢꢅꢩꢧꢚ  
ꢸ
ꢡꢕꢊꢋꢌꢋꢅꢂꢉꢖꢮꢉꢥꢌꢅꢼꢃꢋꢏꢘ  
ꢡꢕꢊꢋꢌꢋꢅꢂꢉꢖꢮꢉꢥꢌꢅꢲꢌꢄꢥꢏꢘ  
ꢲꢌꢉꢋꢅꢫꢘꢃꢖꢮꢄꢌꢇꢇ  
ꢲꢌꢉꢋꢅꢼꢃꢋꢏꢘ  
ꢡꢕꢊꢋꢅꢟꢐꢉꢎꢏꢅꢦꢄꢥꢊꢌꢅꢫꢕꢛ  
ꢡꢕꢊꢋꢅꢟꢐꢉꢎꢏꢅꢦꢄꢥꢊꢌꢅꢩꢕꢏꢏꢕꢑ  
ꢢꢁꢢꢹ  
ꢢꢁꢀꢺ  
ꢀꢀꢻ  
ꢢꢁꢙꢢ  
ꢢꢁꢙꢺ  
ꢀꢞꢻ  
ꢔ
ꢁ
ꢢꢁꢙꢙ  
ꢀꢙꢻ  
ꢀꢙꢻ  
ꢂ
ꢀꢀꢻ  
ꢀꢞꢻ  
ꢥꢞꢋꢄꢊꢦ  
ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃꢇꢈꢉꢊꢅꢃꢄꢋꢌꢍꢅꢎꢌꢉꢏꢈꢐꢌꢅꢑꢉꢒꢅꢆꢉꢐꢒꢓꢅꢔꢈꢏꢅꢑꢈꢇꢏꢅꢔꢌꢅꢊꢕꢖꢉꢏꢌꢋꢅꢗꢃꢏꢘꢃꢄꢅꢏꢘꢌꢅꢘꢉꢏꢖꢘꢌꢋꢅꢉꢐꢌꢉꢁ  
ꢙꢁ ꢚꢘꢉꢑꢎꢌꢐꢇꢅꢉꢏꢅꢖꢕꢐꢄꢌꢐꢇꢅꢉꢐꢌꢅꢕꢛꢏꢃꢕꢄꢉꢊꢜꢅꢇꢃꢝꢌꢅꢑꢉꢒꢅꢆꢉꢐꢒꢁ  
ꢞꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢇꢅꢟꢀꢅꢉꢄꢋꢅꢠꢀꢅꢋꢕꢅꢄꢕꢏꢅꢃꢄꢖꢊꢈꢋꢌꢅꢑꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢛꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢁꢅꢡꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢛꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢅꢇꢘꢉꢊꢊꢅꢄꢕꢏꢅꢌꢍꢖꢌꢌꢋꢅꢢꢁꢙꢣꢅꢑꢑꢅꢛꢌꢐꢅꢇꢃꢋꢌꢁ  
ꢤꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢥꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢥꢅꢛꢌꢐꢅꢦꢧꢡꢠꢅꢨꢀꢤꢁꢣꢡꢁ  
ꢩꢧꢚꢪ ꢩꢉꢇꢃꢖꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢁꢅꢫꢘꢌꢕꢐꢌꢏꢃꢖꢉꢊꢊꢒꢅꢌꢍꢉꢖꢏꢅꢆꢉꢊꢈꢌꢅꢇꢘꢕꢗꢄꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢇꢁ  
ꢬꢠꢭꢪ ꢬꢌꢎꢌꢐꢌꢄꢖꢌꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢓꢅꢈꢇꢈꢉꢊꢊꢒꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢓꢅꢎꢕꢐꢅꢃꢄꢎꢕꢐꢑꢉꢏꢃꢕꢄꢅꢛꢈꢐꢛꢕꢇꢌꢇꢅꢕꢄꢊꢒꢁ  
ꢡꢃꢖꢐꢕꢖꢘꢃꢛ ꢫꢌꢖꢘꢄꢕꢊꢕꢥꢒ ꢟꢐꢉꢗꢃꢄꢥ ꢚꢢꢤꢽꢢꢾꢣꢩ  
DS61143H-page 192  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
© 2011 Microchip Technology Inc.  
DS61143H-page 193  
PIC32MX3XX/4XX  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
DS61143H-page 194  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
© 2011 Microchip Technology Inc.  
DS61143H-page 195  
PIC32MX3XX/4XX  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
DS61143H-page 196  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
ꢙꢚꢚꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢏꢌꢐꢇꢑꢒꢅꢆꢇꢓꢉꢅꢋꢔꢅꢍꢕꢇꢖꢈꢎꢗꢇꢘꢇꢙꢡꢛꢙꢡꢛꢙꢇꢜꢜꢇꢝꢞꢆꢟꢠꢇꢡꢢꢚꢚꢇꢜꢜꢇꢣꢎꢑꢓꢈꢤ  
ꢥꢞꢋꢄꢦ ꢭꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢛꢉꢖꢮꢉꢥꢌꢅꢋꢐꢉꢗꢃꢄꢥꢇꢓꢅꢛꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢡꢃꢖꢐꢕꢖꢘꢃꢛꢅꢂꢉꢖꢮꢉꢥꢃꢄꢥꢅꢧꢛꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ  
ꢘꢏꢏꢛꢪꢯꢯꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢛꢁꢖꢕꢑꢯꢛꢉꢖꢮꢉꢥꢃꢄꢥ  
D
D1  
e
E
E1  
N
b
123  
NOTE 2  
NOTE 1  
c
α
A
φ
L
A1  
β
A2  
L1  
ꢰꢄꢃꢏꢇ  
ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢅꢲꢃꢑꢃꢏꢇ  
ꢡꢱꢲꢲꢱꢡꢠꢫꢠꢬꢧ  
ꢳꢴꢡ  
ꢡꢱꢳ  
ꢡꢦꢵ  
ꢳꢈꢑꢔꢌꢐꢅꢕꢎꢅꢲꢌꢉꢋꢇ  
ꢲꢌꢉꢋꢅꢂꢃꢏꢖꢘ  
ꢴꢆꢌꢐꢉꢊꢊꢅꢷꢌꢃꢥꢘꢏ  
ꢳ
ꢌ
ꢦ
ꢀꢢꢢ  
ꢢꢁꢤꢢꢅꢩꢧꢚ  
ꢸ
ꢸ
ꢀꢁꢙꢢ  
ꢀꢁꢢꢣ  
ꢢꢁꢀꢣ  
ꢢꢁꢺꢣ  
ꢡꢕꢊꢋꢌꢋꢅꢂꢉꢖꢮꢉꢥꢌꢅꢫꢘꢃꢖꢮꢄꢌꢇꢇ  
ꢧꢏꢉꢄꢋꢕꢎꢎꢅꢅ  
ꢭꢕꢕꢏꢅꢲꢌꢄꢥꢏꢘ  
ꢦꢙ  
ꢦꢀ  
ꢲ
ꢢꢁꢹꢣ  
ꢢꢁꢢꢣ  
ꢢꢁꢤꢣ  
ꢀꢁꢢꢢ  
ꢸ
ꢢꢁꢶꢢ  
ꢭꢕꢕꢏꢛꢐꢃꢄꢏ  
ꢭꢕꢕꢏꢅꢦꢄꢥꢊꢌ  
ꢲꢀ  
ꢀ
ꢀꢁꢢꢢꢅꢬꢠꢭ  
ꢞꢁꢣꢻ  
ꢢꢻ  
ꢺꢻ  
ꢴꢆꢌꢐꢉꢊꢊꢅꢼꢃꢋꢏꢘ  
ꢴꢆꢌꢐꢉꢊꢊꢅꢲꢌꢄꢥꢏꢘ  
ꢠ
ꢟ
ꢠꢀ  
ꢟꢀ  
ꢖ
ꢀꢤꢁꢢꢢꢅꢩꢧꢚ  
ꢀꢤꢁꢢꢢꢅꢩꢧꢚ  
ꢀꢙꢁꢢꢢꢅꢩꢧꢚ  
ꢀꢙꢁꢢꢢꢅꢩꢧꢚ  
ꢸ
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© 2011 Microchip Technology Inc.  
DS61143H-page 197  
PIC32MX3XX/4XX  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
DS61143H-page 198  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
© 2011 Microchip Technology Inc.  
DS61143H-page 199  
PIC32MX3XX/4XX  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
DS61143H-page 200  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
© 2011 Microchip Technology Inc.  
DS61143H-page 201  
PIC32MX3XX/4XX  
NOTES:  
DS61143H-page 202  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
Revision F (June 2009)  
APPENDIX A: REVISION HISTORY  
Revision E (July 2008)  
This revision includes minor typographical and  
formatting changes throughout the data sheet text.  
• Updated the PIC32MX340F128H features in  
Table 1 to include 4 programmable DMA  
channels.  
Global changes include:  
• Changed all instances of OSCI to OSC1 and  
OSCO to OSC2  
• Changed all instances of VDDCORE and  
VDDCORE/VCAP to VCAP/VDDCORE  
• Deleted registers in most sections, refer to the  
related section of the “PIC32 Family Reference  
Manual” (DS61132).  
The other changes are referenced by their respective  
section in the following table.  
TABLE A-1:  
MAJOR SECTION UPDATES  
Section Name  
Update Description  
“High-Performance, General  
Purpose and USB 32-bit Flash  
Microcontrollers”  
Added a “Packages” column to Table 1 and Table 2.  
Corrected all pin diagrams to update the following pin names.  
• Changed PGC1/EMUC1 to PGEC1  
• Changed PGD1/EMUD1 to PGED1  
• Changed PGC2/EMUC2 to PGEC2  
• Changed PGD2/EMUD2 to PGED2  
Shaded appropriate pins in each diagram to indicate which pins are 5V tolerant.  
Added 64-Lead QFN package pin diagrams, one for General Purpose and one  
for USB.  
Section 1.0 “Device Overview” Reconstructed Figure 1-1 to include Timers, ADC and RTCC in the block  
diagram.  
Section 2.0 “Guidelines for  
Getting Started with 32-bit  
Microcontrollers”  
Added a new section to the data sheet that provides the following information:  
• Basic Connection Requirements  
• Capacitors  
• Master Clear Pin  
• ICSP™ Pins  
• External Oscillator Pins  
• Configuration of Analog and Digital Pins  
• Unused I/Os  
Section 4.0 “Memory  
Organization”  
Updated the memory maps, Figure 4-1 through Figure 4-6.  
All summary peripheral register maps were relocated to Section 4.0 “Memory  
Organization”.  
Section 7.0 “Interrupt  
Controller”  
Removed the “Address” column from Table 7-1.  
Section 12.0 “I/O Ports”  
Added a second paragraph in Section 12.1.3 “Analog Inputs” to clarify that all  
pins that share ANx functions are analog by default, because the AD1PCFG  
register has a default value of 0x0000.  
© 2011 Microchip Technology Inc.  
DS61143H-page 203  
PIC32MX3XX/4XX  
TABLE A-1:  
MAJOR SECTION UPDATES (CONTINUED)  
Update Description  
Section Name  
Section 26.0 “Special Features” Modified bit names and locations in Register 26-5 “DEVID: Device and  
Revision ID Register”.  
Replaced “TSTARTUP” with “TPU”, and “64-ms nominal delay” with “TPWRT”, in  
Section 26.3.1 “On-Chip Regulator and POR”.  
The information that appeared in the Watchdog Timer and the Programming and  
Diagnostics sections of 61143E version of this data sheet has been incorporated  
into the Special Features section:  
• Section 26.2 “Watchdog Timer (WDT)”  
• Section 26.4 “Programming and Diagnostics”  
Section 29.0 “Electrical  
Characteristics”  
Added the 64-Lead QFN package to Table 29-3.  
Updated data in Table 29-5.  
Updated data in Table 29-7.  
Updated data in Table 29-4, Table 29-5, Table 29-7 and Table 29-8.  
Updated data in Table 29-11.  
Added OS42 parameter to Table 29-17.  
Replaced Table 29-23.  
Replaced Table 29-24.  
Replaced Table 29-25.  
Updated Table 29-36.  
Section 30.0 “Packaging  
Information”  
Added 64-Lead QFN package marking information to Section 30.1 “Package  
Marking Information”.  
Added the 64-Lead QFN (MR) package drawing and land pattern to  
Section 30.2 “Package Details”.  
“Product Identification System” Added the MR package designator for the 64-Lead (9x9x0.9) QFN.  
DS61143H-page 204  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
This revision also includes minor typographical and  
formatting changes throughout the data sheet text.  
Major updates are referenced by their respective  
section in the following table.  
Revision G (April 2010)  
The revision includes the following global update:  
• Added Note 2 to the shaded table that appears at  
the beginning of each chapter. This new note  
provides information regarding the availability of  
registers and their associated bits.  
TABLE A-2:  
MAJOR SECTION UPDATES  
Section Name  
Update Description  
“High-Performance, General Purpose Updated the crystal oscillator range to 3 MHz to 25 MHz (see Peripheral  
and USB 32-bit Flash  
Microcontrollers”  
Features:)  
Added the 121-pin Ball Grid Array (XBGA) pin diagram.  
Updated Table 1: “PIC32MX General Purpose – Features” and Table 2:  
“PIC32MX USB – Features”  
Added the following tables:  
- Table 3: “Pin Names: PIC32MX320F128L, PIC32MX340F128L,  
and PIC32MX360F128L, and PIC32MX360F512L Devices”,  
- Table 4: “Pin Names: PIC32MX440F128L, PIC32MX460F256L  
and PIC32MX460F512L Devices”  
Updated the following pins as 5V tolerant:  
- 64-pin QFN (USB): Pin 34 (VBUS), Pin 36 (D-/RG3) and Pin 37  
(D+/RG2)  
- 64-pin TQFP (USB): Pin 34 (Vbus), Pin 36 (D-/RG3), Pin 37  
(D+/RG2) and Pin 42 (IC1/RTCC/INT1/RD8)  
- 100-pin TQFP (USB): Pin 54 (VBUS), Pin 56 (D-/RG3) and Pin 57  
(D+/RG2)  
Section 1.0 “Device Overview”  
Updated the Pinout I/O Descriptions table to include the device pin  
numbers (see Table 1-1)  
Section 2.0 “Guidelines for Getting  
Updated the Ohm value for the low-ESR capacitor from less than 5 to less  
Started with 32-bit Microcontrollers” than 1 (see Section 2.3.1 “Internal Regulator Mode”).  
Labeled the capacitor on the VCAP/VDDCORE pin as CEFC in Figure 2-1.  
Changed 10 µF capacitor to CEFC capacitor in Section 2.3 “Capacitor on  
Internal Voltage Regulator (VCAP/VCORE)”.  
Section 4.0 “Memory Organization”  
Section 12.0 “I/O Ports”  
Updated all register map tables to include the “All Resets” column.  
Separated the PORT register maps into individual tables (see Table 4-21  
through Table 4-34).  
In addition, formatting changes were made to improve readability.  
Updated the second paragraph of Section 12.1.2 “Digital Inputs” and  
removed Table 12-1.  
Section 22.0 “10-bit Analog-to-Digital Updated the ADC Conversion Clock Period Block Diagram (see Figure 22-  
Converter (ADC)”  
2).  
Section 26.0 “Special Features”  
Extensive updates were made to Section 26.2 “Watchdog Timer (WDT)”  
and Section 26.3 “On-Chip Voltage Regulator”.  
© 2011 Microchip Technology Inc.  
DS61143H-page 205  
PIC32MX3XX/4XX  
TABLE A-2:  
MAJOR SECTION UPDATES (CONTINUED)  
Section Name  
Update Description  
Section 29.0 “Electrical  
Characteristics”  
Updated the Absolute Maximum Ratings and added Note 3.  
Added Thermal Packaging Characteristics for the 121-pin XBGA package  
(see Table 29-3).  
Updated the conditions for parameters DC20, DC21, DC22 and DC23 in  
Table 29-5.  
Updated the comments for parameter D321 (CEFC) in Table 29-15.  
Updated the SPIx Module Slave Mode (CKE = 1) Timing Characteristics,  
changing SP52 to SP35 between the MSb and Bit 14 on SDOx (see  
Figure 29-13).  
Section 30.0 “Packaging Information” Added the 121-pin XBGA package marking information and package  
details.  
“Product Identification System”  
Added the definition for BG (121-lead 10x10x1.1 mm, XBGA).  
Added the definition for Speed.  
DS61143H-page 206  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
Revision H (May 2011)  
The revision includes the following global update:  
• All references to VDDCORE/VCAP have been  
changed to: VCORE/VCAP  
• Added references to the new V-Temp temperature  
range: -40ºC to +105ºC  
This revision also includes minor typographical and  
formatting changes throughout the data sheet text.  
Major updates are referenced by their respective  
section in the following table.  
TABLE A-3:  
MAJOR SECTION UPDATES  
Section Name  
Update Description  
Section 1.0 “Device Overview”  
Updated the VBUS description in Table 1-1: “Pinout I/O Descriptions”.  
Section 4.0 “Memory Organization”  
Added Note 2 and changed the RIPL<2:0> bits to SRIPL<2:0> in the  
Interrupt Register Map tables (see Table 4-2 through Table 4-6.  
Added Note 2 to the Timer1-5 Register Map (see Table 4-7).  
Updated the All Resets value for I2C1CON<15:0> and I2C2CON<15:0>  
in the I2C1 and I2C2 Register Map (see Table 4-10).  
Updated the All Resets value for SPI1STAT<15:0> and SPI2STAT<15:0>  
in the SPI1 and SPI2 Register Map (see Table 4-12).  
Updated the All Resets value for CM1CON<15:0> and CM2CON<15:0>  
in the Comparator Register Map (see Table 4-17).  
Renamed the RCDIV<2:0> bits to FRCDIV<2:0> and the LOCK bit to  
SLOCK in the OSCCON register, and added Note 3 and the  
SYSKEYregister to the System Control Registers Map (see Table 4-20).  
Updated the All Resets value for the PMSTAT register in the Parallel  
Master Port Register Map (see Table 4-37).  
Updated the All Resets value for CHECON<15:0> and CHETAG<15:0>  
in the Prefetch Register Map (see Table 4-39).  
Renamed FUPLLEN, FUPLLIDIV, and FPLLMULT in the DEVCFG2  
register to: UPLLEN, UPLLIDIV, and FPLLMUL, respectively in the  
Device Configuration Word Summary (see Table 4-41).  
Added Notes 1 through 4 to the USB Register Map (see Table 4-43).  
Added a note on Flash LVD Delay and Example 5-1.  
Section 5.0 “Flash Program Memory”  
Section 8.0 “Oscillator Configuration” Updated the PIC32MX3XX/4XX Family Clock Diagram (see Figure 8-1).  
Section 11.0 “USB On-The-Go (OTG)”  
Updated the PIC32MX3XX/4XX Family USB Interface Diagram (see  
Figure 11-1).  
Section 16.0 “Output Compare”  
Updated the Output Compare Module Block Diagram (see Figure 16-1).  
Section 22.0 “10-bit Analog-to-Digital  
Converter (ADC)”  
Updated the ADC Conversion Clock Period Block Diagram (see  
Figure 22-2).  
Section 26.0 “Special Features”  
Renamed FUPLLEN, FUPLLIDIV, and FPLLMULT in the DEVCFG2  
register to: UPLLEN, UPLLIDIV, and FPLLMUL, respectively (see  
Register 26-3).  
© 2011 Microchip Technology Inc.  
DS61143H-page 207  
PIC32MX3XX/4XX  
TABLE A-3:  
MAJOR SECTION UPDATES (CONTINUED)  
Section Name  
Update Description  
Section 29.0 “Electrical  
Characteristics”  
Added the new V-Temp temperature range (-40ºC to +105ºC) to the  
heading of all specification tables.  
Updated the Ambient temperature under bias, updated the Voltage on  
any 5V tolerant pin with respect to VSS when VDD < 2.3V, and added  
Voltage on VBUS with respect to Vss in Absolute Maximum Ratings.  
Added the characteristic, DC5a to Operating MIPS vs. Voltage (see  
Table 29-1).  
Updated or added the following parameters to the Operating Current  
(IDD) DC Characteristics: DC20, DC23, DC24c, DC25d, DC26c (see  
Table 29-5).  
Added the following parameters to the Idle Current (IIDLE) DC  
Characteristics: DC30c, DC31c, DC32c, DS33c, DC34c, DC35c, and  
DC36c (see Table 29-6).  
Added the following parameters to the Power-down Current (IPD) DC  
Characteristics: DC40g, DC40h, DC40i, DC41g, DC41h, DC42g, DC42h,  
DC42i, DC43h, and DC43i (see Table 29-7).  
Added the Brown-out Reset (BOR) Electrical Characteristics (see  
Table 29-10).  
Removed all Conditions from the Program Memory DC Characteristics  
(see Table 29-11).  
Removed the AC Characteristics voltage reference table (Table 29-15).  
Added Note 2 to the PLL Clock Timing Specifications (see Table 29-18).  
Updated the OC/PWM Module Timing Characteristics (see Figure 29-9).  
Added parameter IM51 and Note 3 to the I2Cx Bus Data Timing  
Requirements (Master Mode) (see Table 29-32).  
Added parameter numbers (AD13, AD14, and AD15) to the ADC Module  
Specifications (see Table 29-34).  
Updated the 10-bit ADC Conversion Rate Parameters (see Table 29-35).  
Updated parameter AD57 (TSAMP) in the Analog-to-Digital Conversion  
Timing Requirements (see Table 29-36).  
Updated the Conditions for parameters USB313, USB318, and USB319  
in the OTG Electrical Specifications (see Table 29-40).  
Section 30.0 “Packaging Information” Updated the 64-Lead Plastic Quad Flat, No Lead Package (MR) –  
9x9x0.9 mm Body [QFN] packing diagram.  
Product Identification System  
Added the new V-Temp (V) temperature information.  
DS61143H-page 208  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
INDEX  
A
M
AC Characteristics ............................................................ 161  
Internal RC Accuracy................................................ 163  
AC Electrical Specifications  
Parallel Master Port Read Requirements ................. 186  
Parallel Master Port Write Requirements.................. 187  
Parallel Slave Port Requirements............................. 185  
Assembler  
Microchip Internet Web Site.............................................. 209  
MPLAB ASM30 Assembler, Linker, Librarian................... 148  
MPLAB Integrated Development Environment Software.. 147  
MPLAB PM3 Device Programmer .................................... 150  
MPLAB REAL ICE In-Circuit Emulator System ................ 149  
MPLINK Object Linker/MPLIB Object Librarian................ 148  
P
MPASM Assembler................................................... 148  
Packaging......................................................................... 191  
Details....................................................................... 192  
Marking..................................................................... 191  
PIC32 Family USB Interface Diagram .............................. 100  
Pinout I/O Descriptions (table)............................................ 22  
Power-on Reset (POR)  
B
Block Diagrams  
ADC Module.............................................................. 123  
Comparator I/O Operating Modes............................. 125  
Comparator Voltage Reference ................................ 127  
Connections for On-Chip Voltage Regulator............. 138  
Input Capture ............................................................ 107  
JTAG Compliant Application Showing  
and On-Chip Voltage Regulator ............................... 138  
R
Reader Response............................................................. 210  
Daisy-Chaining of Components ........................ 139  
Output Compare Module........................................... 109  
Reset System.............................................................. 87  
RTCC........................................................................ 121  
Type B Timer ................................................ 37, 95, 105  
UART ........................................................................ 115  
WDT.......................................................................... 137  
Brown-out Reset (BOR)  
S
Serial Peripheral Interface (SPI)... 87, 97, 111, 119, 121, 130  
Software Simulator (MPLAB SIM) .................................... 149  
Special Features............................................................... 131  
T
Timer1 Module.............................................. 89, 95, 103, 105  
Timing Diagrams  
and On-Chip Voltage Regulator................................ 138  
C
10-bit Analog-to-Digital Conversion (CHPS<1:0> = 01,  
SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000) .. 183  
10-bit Analog-to-Digital Conversion (CHPS<1:0> = 01,  
SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111,  
SAMC<4:0> = 00001)....................................... 184  
I2Cx Bus Data (Master Mode).................................. 175  
I2Cx Bus Data (Slave Mode).................................... 177  
I2Cx Bus Start/Stop Bits (Master Mode)................... 175  
I2Cx Bus Start/Stop Bits (Slave Mode)..................... 177  
Input Capture (CAPx) ............................................... 169  
OC/PWM .................................................................. 170  
Output Compare (OCx) ............................................ 169  
Parallel Master Port Write................................. 186, 187  
Parallel Slave Port.................................................... 185  
SPIx Master Mode (CKE = 0) ................................... 171  
SPIx Master Mode (CKE = 1) ................................... 172  
SPIx Slave Mode (CKE = 0)..................................... 173  
SPIx Slave Mode (CKE = 1)..................................... 174  
Timer1, 2, 3, 4, 5 External Clock .............................. 167  
Transmission (8-bit or 9-bit Data)............................. 116  
UART Reception with Receive Overrun ................... 117  
Timing Requirements  
C Compilers  
MPLAB C18 .............................................................. 148  
Comparator  
Operation .................................................................. 126  
Comparator Voltage Reference  
Configuring................................................................ 128  
CPU Module.................................................................. 31, 37  
Customer Change Notification Service............................. 209  
Customer Notification Service........................................... 209  
Customer Support............................................................. 209  
D
DC Characteristics............................................................ 152  
I/O Pin Input Specifications....................................... 157  
I/O Pin Output Specifications.................................... 158  
Idle Current (IIDLE) .................................................... 154  
Operating Current (IDD)............................................. 153  
Power-Down Current (IPD)........................................ 155  
Program Memory ...................................................... 159  
Temperature and Voltage Specifications.................. 152  
Development Support ....................................................... 147  
CLKO and I/O........................................................... 164  
Timing Specifications  
E
Electrical Characteristics................................................... 151  
AC............................................................................. 161  
Errata .................................................................................. 19  
I2Cx Bus Data Requirements (Master Mode)........... 175  
I2Cx Bus Data Requirements (Slave Mode)............. 178  
Output Compare Requirements................................ 169  
Simple OC/PWM Mode Requirements..................... 170  
SPIx Master Mode (CKE = 0) Requirements............ 171  
SPIx Master Mode (CKE = 1) Requirements............ 172  
SPIx Slave Mode (CKE = 1) Requirements.............. 174  
F
Flash Program Memory ...................................................... 85  
RTSP Operation.......................................................... 85  
I
V
I/O Ports.................................................................... 101, 115  
Parallel I/O (PIO)....................................................... 102  
Internet Address................................................................ 209  
VCORE/VCAP Pin ............................................................... 138  
Voltage Reference Specifications..................................... 160  
Voltage Regulator (On-Chip) ............................................ 138  
© 2011 Microchip Technology Inc.  
DS61143H-page 209  
PIC32MX3XX/4XX  
W
Watchdog Timer  
Operation ..................................................................137  
WWW Address..................................................................209  
WWW, On-Line Support......................................................19  
DS61143H-page 210  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
THE MICROCHIP WEB SITE  
CUSTOMER SUPPORT  
Microchip provides online support via our WWW site at  
www.microchip.com. This web site is used as a means  
to make files and information easily available to  
customers. Accessible by using your favorite Internet  
browser, the web site contains the following  
information:  
Users of Microchip products can receive assistance  
through several channels:  
• Distributor or Representative  
• Local Sales Office  
• Field Application Engineer (FAE)  
• Technical Support  
• Product Support – Data sheets and errata,  
application notes and sample programs, design  
resources, user’s guides and hardware support  
documents, latest software releases and archived  
software  
• Development Systems Information Line  
Customers  
should  
contact  
their  
distributor,  
representative or field application engineer (FAE) for  
support. Local sales offices are also available to help  
customers. A listing of sales offices and locations is  
included in the back of this document.  
• General Technical Support – Frequently Asked  
Questions (FAQs), technical support requests,  
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program member listing  
Technical support is available through the web site  
at: http://microchip.com/support  
• Business of Microchip – Product selector and  
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CUSTOMER CHANGE NOTIFICATION  
SERVICE  
Microchip’s customer notification service helps keep  
customers current on Microchip products. Subscribers  
will receive e-mail notification whenever there are  
changes, updates, revisions or errata related to a  
specified product family or development tool of interest.  
To register, access the Microchip web site at  
www.microchip.com. Under “Support”, click on  
“Customer Change Notification” and follow the  
registration instructions.  
© 2011 Microchip Technology Inc.  
DS61143H-page 211  
PIC32MX3XX/4XX  
READER RESPONSE  
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip  
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our  
documentation can better serve you, please FAX your comments to the Technical Publications Manager at  
(480) 792-4150.  
Please list the following information, and use this outline to provide us with your comments about this document.  
TO:  
RE:  
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Reader Response  
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Telephone: (_______) _________ - _________  
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Application (optional):  
Would you like a reply?  
Y
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PIC32MX3XX/4XX  
DS61143H  
Literature Number:  
Device:  
Questions:  
1. What are the best features of this document?  
2. How does this document meet your hardware and software development needs?  
3. Do you find the organization of this document easy to follow? If not, why?  
4. What additions to the document do you think would enhance the structure and subject?  
5. What deletions from the document could be made without affecting the overall usefulness?  
6. Is there any incorrect or misleading information (what and where)?  
7. How would you improve this document?  
DS61143H-page 212  
© 2011 Microchip Technology Inc.  
PIC32MX3XX/4XX  
Product Identification System  
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.  
Examples:  
PIC32 MX 3XX F 512 H T - 80 I / PT - XXX  
PIC32MX320F032H-40I/PT:  
General purpose PIC32MX,  
32 KB program memory,  
64-pin, Industrial temperature,  
TQFP package.  
Microchip Brand  
Architecture  
Product Groups  
Flash Memory Family  
Program Memory Size (KB)  
Pin Count  
PIC32MX360F256L-80I/PT:  
General purpose PIC32MX,  
256 KB program memory,  
100-pin, Industrial temperature,  
TQFP package.  
Tape and Reel Flag (if applicable)  
Speed  
Temperature Range  
Package  
Pattern  
Flash Memory Family  
Architecture  
MX = 32-bit RISC MCU core  
Product Groups  
Flash Memory Family  
3XX = General purpose microcontroller family  
4XX= USB  
F
= Flash program memory  
Program Memory Size 32 = 32K  
64 = 64K  
128 = 128K  
256 = 256K  
512 = 512K  
Speed  
40 = 40 MHz  
80 = 80 MHz  
Pin Count  
H
L
= 64-pin  
= 100-pin  
Temperature Range  
Package  
I
V
= -40°C to +85° C (Industrial)  
= -40°C to +105° C (V-Temp)  
PT = 64-Lead (10x10x1 mm) TQFP (Thin Quad Flatpack)  
PT = 100-Lead (12x12x1 mm) TQFP (Thin Quad Flatpack)  
MR = 64-Lead (9x9x0.9 mm) QFN (Plastic Quad Flat)  
BG = 121-Lead (10x10x1.1 mm) XBGA (Plastic Thin Profile Ball Grid Array)  
Pattern  
Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise)  
ES = Engineering Sample  
© 2011 Microchip Technology Inc.  
DS61143H-page 213  
Worldwide Sales and Service  
AMERICAS  
ASIA/PACIFIC  
ASIA/PACIFIC  
EUROPE  
Corporate Office  
2355 West Chandler Blvd.  
Chandler, AZ 85224-6199  
Tel: 480-792-7200  
Fax: 480-792-7277  
Technical Support:  
http://www.microchip.com/  
support  
Asia Pacific Office  
Suites 3707-14, 37th Floor  
Tower 6, The Gateway  
Harbour City, Kowloon  
Hong Kong  
Tel: 852-2401-1200  
Fax: 852-2401-3431  
India - Bangalore  
Tel: 91-80-3090-4444  
Fax: 91-80-3090-4123  
Austria - Wels  
Tel: 43-7242-2244-39  
Fax: 43-7242-2244-393  
Denmark - Copenhagen  
Tel: 45-4450-2828  
Fax: 45-4485-2829  
India - New Delhi  
Tel: 91-11-4160-8631  
Fax: 91-11-4160-8632  
France - Paris  
Tel: 33-1-69-53-63-20  
Fax: 33-1-69-30-90-79  
India - Pune  
Tel: 91-20-2566-1512  
Fax: 91-20-2566-1513  
Australia - Sydney  
Tel: 61-2-9868-6733  
Fax: 61-2-9868-6755  
Web Address:  
www.microchip.com  
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Tel: 49-89-627-144-0  
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Tel: 81-45-471- 6166  
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Tel: 678-957-9614  
Fax: 678-957-1455  
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Tel: 86-10-8569-7000  
Fax: 86-10-8528-2104  
Italy - Milan  
Tel: 39-0331-742611  
Fax: 39-0331-466781  
Korea - Daegu  
Tel: 82-53-744-4301  
Fax: 82-53-744-4302  
China - Chengdu  
Tel: 86-28-8665-5511  
Fax: 86-28-8665-7889  
Boston  
Westborough, MA  
Tel: 774-760-0087  
Fax: 774-760-0088  
Netherlands - Drunen  
Tel: 31-416-690399  
Fax: 31-416-690340  
Korea - Seoul  
China - Chongqing  
Tel: 86-23-8980-9588  
Fax: 86-23-8980-9500  
Tel: 82-2-554-7200  
Fax: 82-2-558-5932 or  
82-2-558-5934  
Chicago  
Itasca, IL  
Tel: 630-285-0071  
Fax: 630-285-0075  
Spain - Madrid  
Tel: 34-91-708-08-90  
Fax: 34-91-708-08-91  
China - Hangzhou  
Tel: 86-571-2819-3180  
Fax: 86-571-2819-3189  
Malaysia - Kuala Lumpur  
Tel: 60-3-6201-9857  
Fax: 60-3-6201-9859  
UK - Wokingham  
Tel: 44-118-921-5869  
Fax: 44-118-921-5820  
Cleveland  
Independence, OH  
Tel: 216-447-0464  
Fax: 216-447-0643  
China - Hong Kong SAR  
Tel: 852-2401-1200  
Fax: 852-2401-3431  
Malaysia - Penang  
Tel: 60-4-227-8870  
Fax: 60-4-227-4068  
Dallas  
Addison, TX  
Tel: 972-818-7423  
Fax: 972-818-2924  
China - Nanjing  
Tel: 86-25-8473-2460  
Fax: 86-25-8473-2470  
Philippines - Manila  
Tel: 63-2-634-9065  
Fax: 63-2-634-9069  
China - Qingdao  
Tel: 86-532-8502-7355  
Fax: 86-532-8502-7205  
Singapore  
Tel: 65-6334-8870  
Fax: 65-6334-8850  
Detroit  
Farmington Hills, MI  
Tel: 248-538-2250  
Fax: 248-538-2260  
China - Shanghai  
Tel: 86-21-5407-5533  
Fax: 86-21-5407-5066  
Taiwan - Hsin Chu  
Tel: 886-3-6578-300  
Fax: 886-3-6578-370  
Indianapolis  
Noblesville, IN  
Tel: 317-773-8323  
Fax: 317-773-5453  
China - Shenyang  
Tel: 86-24-2334-2829  
Fax: 86-24-2334-2393  
Taiwan - Kaohsiung  
Tel: 886-7-213-7830  
Fax: 886-7-330-9305  
Los Angeles  
China - Shenzhen  
Tel: 86-755-8203-2660  
Fax: 86-755-8203-1760  
Taiwan - Taipei  
Tel: 886-2-2500-6610  
Fax: 886-2-2508-0102  
Mission Viejo, CA  
Tel: 949-462-9523  
Fax: 949-462-9608  
China - Wuhan  
Tel: 86-27-5980-5300  
Fax: 86-27-5980-5118  
Thailand - Bangkok  
Tel: 66-2-694-1351  
Fax: 66-2-694-1350  
Santa Clara  
Santa Clara, CA  
Tel: 408-961-6444  
Fax: 408-961-6445  
China - Xian  
Tel: 86-29-8833-7252  
Fax: 86-29-8833-7256  
Toronto  
Mississauga, Ontario,  
Canada  
China - Xiamen  
Tel: 905-673-0699  
Fax: 905-673-6509  
Tel: 86-592-2388138  
Fax: 86-592-2388130  
China - Zhuhai  
Tel: 86-756-3210040  
Fax: 86-756-3210049  
05/02/11  
DS61143H-page 214  
© 2011 Microchip Technology Inc.  

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