USB5926C/KD [MICROCHIP]
6-Port USB 3.2 Gen 1 SmartHubTM with Support for Multiple USB Type-C® UFP and DFP;
| 型号： | USB5926C/KD |
| 厂家： | 
MICROCHIP |
| 描述： | 6-Port USB 3.2 Gen 1 SmartHubTM with Support for Multiple USB Type-C® UFP and DFP |
| 文件： | 总66页 (文件大小：2714K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
USB5926
TM
6-Port USB 3.2 Gen 1 SmartHub
®
with Support for Multiple USB Type-C UFP and DFP
• Supports battery charging of most popular battery
powered devices on all ports
Highlights
• USB Hub Feature Controller Hub with:
-
USB-IF Battery Charging rev. 1.2 support
(DCP, CDP, SDP)
-
-
-
-
2 USB 3.1 Gen 1 USB Type-C® downstream ports
2 USB 3.1 Gen 1 legacy downstream ports
2 USB 2.0 legacy downstream ports
USB Type-C upstream port
-
-
-
-
-
Apple® portable product charger emulation
Chinese YD/T 1591-2006 charger emulation
Chinese YD/T 1591-2009 charger emulation
European Union universal mobile charger support
Support for Microchip UCS100x family of battery
charging controllers
• USB-IF Battery Charger revision 1.2 support on
up & downstream ports (DCP, CDP, SDP)
• Internal Hub Feature Controller device enables:
-
-
USB to I2C/SPI/GPIO bridge endpoint support
-
Supports additional portable devices
USB to internal hub register write and read
• Smart port controller operation
• USB Link Power Management (LPM) support
-
Firmware handling of companion port power
controllers
• Enhanced OEM configuration options available
through either OTP or SPI ROM
• On-chip microcontroller
-
manages I/Os, VBUS, and other signals
• USB-IF certified , supporting latest Engineering
Change Notices for compliance with USB-IF logo
testing for new USB Type-C®
• 8 KB RAM, 64 KB ROM
• 8 KB One-Time-Programmable (OTP) ROM
industry initiative (Revision C or newer only)
-
Includes on-chip charge pump
- Header Packet Timer (TD7.9, TD7.11, TD7.26)
• Configuration programming via OTP ROM,
SPI ROM, or SMBus
- Power Management Timer (TD7.18, TD7.20, TD7.23)
- Unacknowledged Connect and Remote
Wake Test Failure (TD10.25)
• PortSwap
-
Configurable USB 2.0 differential pair signal swap
• PHYBoostTM
• Available in 100-pin (12mm x 12mm) VQFN
RoHS compliant package
-
Programmable USB transceiver drive strength for
• Commercial and industrial grade temperature
support
recovering signal integrity
-
USB 2.0 Hi-Speed disconnect threshold adjust
(Revision C or newer only)
Target Applications
• Standalone USB Hubs
• Laptop Docks
• PC Motherboards
• PC Monitor Docks
• VariSenseTM
-
Programmable USB receive sensitivity
• Port Split
-
USB2.0 and USB 3.2 Gen1 port operation can be
split for custom applications using embedded
USB3.x devices in parallel with USB2.0 devices.
• Multi-function USB 3.2 Gen 1 Peripherals
• USB Power Delivery Billboard Device Support
Key Benefits
• USB 3.2 Gen 1 compliant 5 Gbps, 480 Mbps,
12 Mbps, and 1.5Mbps operation
-
Internal port can enumerate as a Power Delivery
Billboard device to communicate Power Delivery
Alternate Mode negotiation failure cases to USB
host
-
-
-
5V tolerant USB 2.0 pins
1.32V tolerant USB 3.2 Gen 1 pins
Integrated termination and pull-up/down resistors
• Compatible with Microsoft Windows 10, 8, 7, XP,
Apple OS X 10.4+, and Linux hub drivers
• Native USB Type-C Support
• Optimized for low-power operation and low ther-
mal dissipation
-
Integrated Multiplexer on USB Type-C enabled
ports
• Package
-
USB 3.1 Gen 1 PHYs are disabled until a valid
USB Type-C attach is detected, saving idle power
-
100-pin VQFN (12mm x 12mm)
2016-2021 Microchip Technology Inc.
DS00002234E-page 1
USB5926
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
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Register on our web site at www.microchip.com to receive the most current information on all of our products.
DS00002234E-page 2
2016-2021 Microchip Technology Inc.
USB5926
TABLE OF CONTENTS
Introduction ........................................................................................................................................................................................... 7
Pin Descriptions and Configuration ....................................................................................................................................................... 6
Functional Descriptions ......................................................................................................................................................................... 9
Operational Characteristics................................................................................................................................................................. 13
System Application ............................................................................................................................................................................. 19
Package Outlines ................................................................................................................................................................................ 26
Revision History................................................................................................................................................................................... 29
The Microchip Web Site ...................................................................................................................................................................... 30
Customer Change Notification Service ............................................................................................................................................... 30
Customer Support ............................................................................................................................................................................... 30
Product Identification System ............................................................................................................................................................. 31
2016-2021 Microchip Technology Inc.
DS00002234E-page 3
USB5926
1.0
1.1
PREFACE
General Terms
TABLE 1-1:
GENERAL TERMS
Term
Description
ADC
Analog-to-Digital Converter
Byte
8 bits
CDC
Communication Device Class
Control and Status Registers
32 bits
CSR
DWORD
EOP
End of Packet
EP
Endpoint
FIFO
First In First Out buffer
Full-Speed
FS
FSM
Finite State Machine
General Purpose I/O
Hi-Speed
GPIO
HS
HSOS
High Speed Over Sampling
Hub Feature Controller
The Hub Feature Controller, sometimes called a Hub Controller for short is the internal
processor used to enable the unique features of the USB Controller Hub. This is not to
be confused with the USB Hub Controller that is used to communicate the hub status
back to the Host during a USB session.
I2C
Inter-Integrated Circuit
Low-Speed
LS
lsb
Least Significant Bit
Least Significant Byte
Most Significant Bit
Most Significant Byte
Not Applicable
LSB
msb
MSB
N/A
NC
No Connect
OTP
PCB
PCS
PHY
PLL
One Time Programmable
Printed Circuit Board
Physical Coding Sublayer
Physical Layer
Phase Lock Loop
RESERVED
Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must
always be zero for write operations. Unless otherwise noted, values are not guaran-
teed when reading reserved bits. Unless otherwise noted, do not read or write to
reserved addresses.
SDK
Software Development Kit
System Management Bus
Universally Unique IDentifier
16 bits
SMBus
UUID
WORD
DS00002234E-page 4
2016-2021 Microchip Technology Inc.
USB5926
1.2
Reference Documents
1. UNICODE UTF-16LE For String Descriptors USB Engineering Change Notice, December 29th, 2004, http://
www.usb.org
2. Universal Serial Bus Revision 3.2 Specification, http://www.usb.org/developers/docs/
3. Battery Charging Specification, Revision 1.2, Dec. 07, 2010, http://www.usb.org
4. I2C-Bus Specification, Version 1.1, http://www.nxp.com
5. System Management Bus Specification, Version 1.0, http://smbus.org/specs
2016-2021 Microchip Technology Inc.
DS00002234E-page 5
USB5926
2.0
2.1
INTRODUCTION
General Description
The Microchip USB5926 hub is a low-power, OEM configurable, USB 3.2 Gen 1 hub controller with 6 downstream ports
and advanced features for embedded USB applications. The USB5926 is fully compliant with the Universal Serial Bus
Revision 3.2 Specification and USB 2.0 Link Power Management Addendum. The USB5926 supports 5 Gbps Super-
Speed (SS), 480 Mbps Hi-Speed (HS), 12 Mbps Full-Speed (FS), and 1.5 Mbps Low-Speed (LS) USB downstream
devices on all enabled downstream ports.
The USB5926 supports the legacy USB speeds (HS/FS/LS) through a dedicated USB 2.0 hub controller that is the cul-
mination of five generations of Microchip hub controller design and experience with proven reliability, interoperability,
and device compatibility. The SuperSpeed hub controller operates in parallel with the USB 2.0 hub controller, decoupling
the 5 Gbps SS data transfers from bottlenecks due to the slower USB 2.0 traffic.
The USB5926 hub feature controller enables OEMs to configure their system using “Configuration Straps.” These straps
simplify the configuration process, assigning default values to USB 3.2 Gen 1 ports and GPIOs. OEMs can disable ports,
enable battery charging, and define GPIO functions as default assignments on power-up, removing the need for OTP
or external SPI ROM.
The USB5926 supports downstream battery charging via the integrated battery charger detection circuitry, which sup-
ports the USB-IF Battery Charging (BC1.2) detection method and most Apple devices. The USB5926 provides the bat-
tery charging handshake and supports the following USB-IF BC1.2 charging profiles:
• DCP: Dedicated Charging Port (Power brick with no data)
• CDP: Charging Downstream Port (1.5A with data)
• SDP: Standard Downstream Port (0.5A with data)
• Custom profiles loaded via SMBus or OTP
Additionally, the USB5926 includes many powerful and unique features such as:
The Hub Feature Controller, which provides an internal USB device dedicated for use as a USB to I2C/UART/SPI/
GPIO interface, allowing external circuits or devices to be monitored, controlled, or configured via the USB interface.
PortSwap, which adds per-port programmability to USB differential-pair pin locations. PortSwap allows direct alignment
of USB signals (D+/D-) to connectors to avoid uneven trace length or crossing of the USB differential signals on the
PCB.
PHYBoost, which provides programmable levels of Hi-Speed USB signal drive strength
in the downstream port transceivers. PHYBoost attempts to restore USB signal integrity
in a compromised system environment. The graphic on the right shows an example of
Hi-Speed USB eye diagrams before and after PHYBoost signal integrity restoration. in
a compromised system environment.
VariSense, which controls the USB receiver sensitivity enabling programmable levels of USB signal receive sensitivity.
This capability allows operation in a sub-optimal system environment, such as when a captive USB cable is used.
Port Split, which allows for the USB 3.2 Gen1 and USB2.0 portions of downstream ports 3 and 4 to operate inde-
pendently and enumerate two separate devices in parallel in special applications.
USB Power Delivery Billboard Device, which allows an internal device to enumerate as a Billboard class device when
a Power Delivery Alternate Mode negotiation has failed. The Billboard device will enumerate temporarily to the host PC
when a failure occurs, as indicated by a digital signal from an external Power Delivery controller.
The USB5926 can be configured for operation through internal default settings. Custom OEM configurations are sup-
ported through external SPI ROM or OTP ROM. All port control signal pins are under firmware control in order to allow
for maximum operational flexibility, and are available as GPIOs for customer specific use.
The USB5926 is available in commercial (0°C to +70°C) and industrial (-40°C to +85°C) temperature ranges. An internal
block diagram of the USB5926 is shown in Figure 2-1.
DS00002234E-page 6
2016-2021 Microchip Technology Inc.
USB5926
FIGURE 2-1:
INTERNAL BLOCK DIAGRAM
P0‘C’
I2C from Master
+3.3 V
+1.2 V
I2C/SMB
AFE0 AFE0 AFE0
USB3 USB2
Hub Controller Logic
25 Mhz
AFE1 AFE1 AFE1
AFE3 AFE3
AFE4 AFE4
AFE5
AFE6
AFE7
AFE2 AFE2 AFE2
OTP
Hub Feature
Controller
GPIO SMB SPI
P3
‘A’
P5
‘A’
P6
‘A’
P1
‘C’
P2
‘C’
P4
‘A’
2016-2021 Microchip Technology Inc.
DS00002234E-page 7
USB5926
3.0
3.1
PIN DESCRIPTIONS
Pin Diagram
FIGURE 3-1:
PIN ASSIGNMENTS (TOP VIEW)
76
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
C_ATTACH0/ATTACHMUX0A/GPIO64
SUSP_IND/GPIO68
VDD12
AB1/ATTACHMUX1B/GPIO65
USB3DN_RXDM3
USB3DN_RXDP3
VDD12
77
78
79
NC
80
81
82
83
84
NC
USB3DN_TXDM3
USB3DN_TXDP3
USB2DN_DM3/PRT_DIS_M3
USB2DN_DP3/PRT_DIS_P3
VDD33
USB3UP_TXDPB
USB3UP_TXDMB
VDD12
USB3UP_RXDPB
USB3UP_RXDMB
USB2DN_DP4/PRT_DIS_P4
USB2DN_DM4/PRT_DIS_M4
USB3DN_TXDP4
USB3DN_TXDM4
VDD12
85
86
87
USB3DN_RXDM2B
USB3DN_RXDP2B
VDD12
Microchip
88
89
90
91
92
93
94
95
96
97
98
99
100
USB3DN_TXDM2B
USB3DN_TXDP2B
USB2DN_DM6/ PRT_DIS_M6
USB2DN_DP6/PRT_DIS_P6
USB3DN_RXDM2A
USB3DN_RXDP2A
VDD12
USB5926
(Top View 100-VQFN)
USB3DN_RXDP4
USB3DN_RXDM4
VDD33
USB2UP_DP
thermal slug connects to VSS
USB2UP_DM
USB3DN_TXDM2A
USB3DN_TXDP2A
USB2DN_DM2/PRT_DIS_M2
USB2DN_DP2/PRT_DIS_P2
VDD33
USB3UP_TXDPA
USB3UP_TXDMA
VDD12
USB3UP_RXDPA
USB3UP_RXDMA
VDD12
Note 1: Configuration straps are identified by an underlined symbol name. Signals that function as configuration
straps must be augmented with an external resistor when connected to a load. Refer to Section 3.5, Con-
figuration Straps and Programmable Functions
DS00002234E-page 8
2016-2021 Microchip Technology Inc.
USB5926
3.2
Pin Symbols
Pin Num.
Pin Name
Reset Pin Num.
Pin Name
Reset
1
RBIAS
VDD33
A/P
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
PRT_CTL4/GPIO22
PRT_CTL3/GPIO21
HOST_TYPE0/GPIO23
VDD33
PD-50k
2
A/P
PD-50k
3
XTALI/CLKIN
XTALO
A/P
PD-50k
4
A/P
A/P
5
VDD33
A/P
HOST_TYPE1/GPIO67
C_ATTACH2/ATTACHMUX2A/GPIO2
PRT_CTL6/GANG_PWR/GPIO20
PRT_CTL2/GPIO19
VDD12
Z
6
USB2DN_DP1/PRT_DIS_P1
USB2DN_DM1/PRT_DIS_M1
USB3DN_TXDP1A
USB3DN_TXDM1A
VDD12
PD-15k
Z
7
PD-15k
PD-50k
8
Z
PD-50k
9
Z
A/P
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
A/P
AB0/ATTACHMUX0B/GPIO3
CC_POL/GPIO71
PRT_CTL5/GPIO18
ALT_MUX_EN/GPIO70
VDD33
Z
USB3DN_RXDP1A
USB3DN_RXDM1A
USB2DN_DP5/PRT_DIS_P5
USB2DN_DM5/PRT_DIS_M5
USB3DN_TXDP1B
USB3DN_TXDM1B
VDD12
Z
Z
Z
PD-50k
PD-15k
Z
PD-15k
A/P
Z
SPI_CLK/GPIO4
SPI_DO/GPIO5
Z
Z
PD-50k
A/P
SPI_DI/GPIO9/CFG_BC_EN
SPI_CE_N/GPIO7/CFG_NON_REM
GPIO69
Z
USB3DN_RXDP1B
USB3DN_RXDM1B
GPIO12/CFG_STRAP
NC
Z
PU-50k
Z
Z
Z
PRT_CTL1/GPIO17
AB2/ATTACHMUX2B/GPIO66
VDD33
PD-50k
Z
Z
NC
Z
A/P
TESTEN
Z
C_ATTACH1/ATTACHMUX1A/GPIO1
SMBDATA/GPIO6
SMBCLK/GPIO8
C_ATTACH0/ATTACHMUX0A/GPIO64
SUSP_IND/GPIO68
VDD12
Z
VBUS_DET
Z
Z
RESET_N
R
Z
VDD12
A/P
Z
VDD33
A/P
Z
USB2DN_DP2/PRT_DIS_P2
USB2DN_DM2/PRT_DIS_M2
USB3DN_TXDP2A
USB3DN_TXDM2A
VDD12
PD-15k
A/P
PD-15k
NC
PD-15k
Z
NC
PD-15k
Z
USB3UP_TXDPB
USB3UP_TXDMB
VDD12
Z
A/P
Z
USB3DN_RXDP2A
USB3DN_RXDM2A
USB2DN_DP6/PRT_DIS_P6
USB2DN_DM6/PRT_DIS_M6
USB3DN_TXDP2B
USB3DN_TXDM2B
VDD12
Z
A/P
Z
USB3UP_RXDPB
USB3UP_RXDMB
USB2DN_DP4/PRT_DIS_P4
USB2DN_DM4/PRT_DIS_M4
USB3DN_TXDP4
USB3DN_TXDM4
VDD12
Z
PD-15k
Z
PD-15k
PD-15k
Z
PD-15k
Z
Z
A/P
Z
USB3DN_RXDP2B
USB3DN_RXDM2B
VDD33
Z
A/P
Z
USB3DN_RXDP4
USB3DN_RXDM4
VDD33
Z
A/P
Z
A/P
PD-1M
PD-1M
Z
USB2DN_DP3/PRT_DIS_P3
USB2DN_DM3/PRT_DIS_M3
USB3DN_TXDP3
USB3DN_TXDM3
VDD12
PD-15k
PD-15k
USB2UP_DP
Z
Z
USB2UP_DM
USB3UP_TXDPA
USB3UP_TXDMA
VDD12
A/P
Z
Z
USB3DN_RXDP3
USB3DN_RXDM3
AB1/ATTACHMUX1B/GPIO65
A/P
Z
Z
USB3UP_RXDPA
USB3UP_RXDMA
Z
Z
2016-2021 Microchip Technology Inc.
DS00002234E-page 9
USB5926
The pin reset state definitions are detailed in Table 3-1.
TABLE 3-1:
Symbol
PIN RESET STATE LEGEND
Description
A/P
R
Analog/Power Input
Reset Control Input
Z
Hardware disables output driver (high impedance)
PU-50k Hardware enables internal 50kΩ pull-up
PD-50k Hardware enables internal 50kΩ pull-down
PD-15k Hardware enables internal 15kΩ pull-down
PD-1M
Hardware enables internal 1M pull-down
3.3
USB5926 Pin Descriptions
This section contains descriptions of the various USB5926 pins. The pin descriptions have been broken into functional
groups as follows:
• USB 3.2 Gen 1 Pin Descriptions
• USB 2.0 Pin Descriptions
• Port Control Pin Descriptions
• SPI Interface
• USB Type-C Connector Controls
• Miscellaneous Pin Descriptions
• Configuration Strap Pin Descriptions
• Power and Ground Pin Descriptions
The “_N” symbol in the signal name indicates that the active, or asserted, state occurs when the signal is at a low voltage
level. For example, RESET_N indicates that the reset signal is active low. When “_N” is not present after the signal
name, the signal is asserted when at the high voltage level.
The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of
“active low” and “active high” signal. The term assert, or assertion, indicates that a signal is active, independent of
whether that level is represented by a high or low voltage. The term negate, or negation, indicates that a signal is inac-
tive.
TABLE 3-2:
Name
USB 3.2 GEN 1 PIN DESCRIPTIONS
Buffer
Symbol
Type
Description
USB 3.1 Gen 1
Upstream A
D+ TX
USB3UP_TXDPA
USB3UP_TXDMA
USB3UP_RXDPA
I/O-U
I/O-U
I/O-U
Upstream USB Type-C “Orientation A” USB 3.1 Gen 1
Transmit Data Plus
USB 3.1 Gen 1
Upstream A
D- TX
Upstream USB Type-C “Orientation A” USB 3.1 Gen 1
Transmit Data Minus
USB 3.1 Gen 1
Upstream A
D+ RX
Upstream USB Type-C “Orientation A” USB 3.1 Gen 1
Receive Data Plus
DS00002234E-page 10
2016-2021 Microchip Technology Inc.
USB5926
TABLE 3-2:
USB 3.2 GEN 1 PIN DESCRIPTIONS (CONTINUED)
Buffer
Type
Name
Symbol
Description
USB 3.1 Gen 1
Upstream A
D- RX
USB3UP_RXDMA
I/O-U
I/O-U
I/O-U
I/O-U
I/O-U
I/O-U
I/O-U
I/O-U
I/O-U
I/O-U
I/O-U
I/O-U
I/O-U
I/O-U
Upstream USB Type-C “Orientation A” USB 3.1 Gen 1
Receive Data Minus
USB 3.1 Gen 1
Upstream B
D+ TX
USB3UP_TXDPB
USB3UP_TXDMB
Upstream USB Type-C “Orientation B” USB 3.1 Gen 1
Transmit Data Plus
USB 3.1 Gen 1
Upstream B
D- TX
Upstream USB Type-C “Orientation B” USB 3.1 Gen 1
Transmit Data Minus
USB 3.1 Gen 1
Upstream B
D+ RX
USB3UP_RXDPB
Upstream USB Type-C “Orientation B” USB 3.1 Gen 1
Receive Data Plus
USB 3.1 Gen 1
Upstream B
D- RX
USB3UP_RXDMB
Upstream USB Type-C “Orientation B” USB 3.1 Gen 1
Receive Data Minus
USB 3.2 Gen 1
Ports 4-3
USB3DN_TXDP[4:3]
USB3DN_TXDM[4:3]
USB3DN_RXDP[4:3]
USB3DN_RXDM[4:3]
USB3DN_TXDP[2:1]A
USB3DN_TXDM[2:1]A
USB3DN_RXDP[2:1]A
USB3DN_RXDM[2:1]A
USB3DN_TXDP[2:1]B
Downstream Super Speed Transmit Data Plus,
ports 4 through 3.
D+ TX
USB 3.2 Gen 1
Ports 4-3
D- TX
Downstream Super Speed Transmit Data Minus,
ports 4 through 3.
USB 3.2 Gen 1
Ports 4-3
Downstream Super Speed Receive Data Plus,
ports 4 through 3.
D+ RX
USB 3.2 Gen 1
Ports 4-3
Downstream Super Speed Receive Data Minus,
ports 4 through 3.
D- RX
USB 3.1 Gen 1
Ports 2-1 A
D+ TX
Downstream USB Type-C “Orientation A” Super Speed
Transmit Data Plus, ports 2 through 1.
USB 3.1 Gen 1
Ports 2-1 A
D- TX
Downstream USB Type-C “Orientation A” Super Speed
Transmit Data Minus, ports 2 through 1.
USB 3.1 Gen 1
Ports 2-1 A
D+ RX
Downstream USB Type-C “Orientation A” Super Speed
Receive Data Plus, ports 2 through 1.
USB 3.1 Gen 1
Ports 2-1 A
D- RX
Downstream USB Type-C “Orientation A” Super Speed
Receive Data Minus, ports 2 through 1.
USB 3.1 Gen 1
Ports 2-1 B
D+ TX
Downstream USB Type-C “Orientation B” Super Speed
Transmit Data Plus, ports 2 through 1.
2016-2021 Microchip Technology Inc.
DS00002234E-page 11
USB5926
TABLE 3-2:
USB 3.2 GEN 1 PIN DESCRIPTIONS (CONTINUED)
Buffer
Type
Name
Symbol
Description
USB 3.1 Gen 1
Ports 2-1 B
D- TX
USB3DN_TXDM[2:1]B
I/O-U
I/O-U
I/O-U
Downstream USB Type-C “Orientation B” Super Speed
Transmit Data Minus, ports 2 through 1.
USB 3.1 Gen 1
Ports 2-1 B
D+ RX
USB3DN_RXDP[2:1]B
USB3DN_RXDM[2:1]B
Downstream USB Type-C “Orientation B” Super Speed
Receive Data Plus, ports 2 through 1.
USB 3.1 Gen 1
Ports 2-1 B
D- RX
Downstream USB Type-C “Orientation B” Super Speed
Receive Data Minus, ports 2 through 1.
TABLE 3-3:
Name
USB 2.0 PIN DESCRIPTIONS
Buffer
Symbol
Description
Type
USB 2.0
Upstream
D+
USB2UP_DP
I/O-U
Upstream USB 2.0 Data Plus (D+)
USB 2.0
Upstream
D-
USB2UP_DM
I/O-U
Upstream USB 2.0 Data Minus (D-)
USB 2.0
Ports 6 D+
USB2DN_DP[6:1]
USB2DN_DM[6:1]
VBUS_DET
I/O-U
I/O-U
IS
Downstream USB 2.0 Ports 6-1 Data Plus (D+)
Downstream USB 2.0 Ports 6-1 Data Minus (D-)
This signal detects the state of the upstream bus power.
USB 2.0
Ports 6 D-
VBUS Detect
When designing a detachable hub, this pin must be con-
nected to the VBUS power pin of the upstream USB port
through a resistor divider (50 kΩ by 100 kΩ) to provide
3.3 V.
For self-powered applications with a permanently
attached host, this pin must be connected to either 3.3 V
or 5.0 V through a resistor divider to provide 3.3 V.
In embedded applications, VBUS_DET may be controlled
(toggled) when the host desires to renegotiate a connec-
tion without requiring a full reset of the device.
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USB5926
TABLE 3-4:
Name
PORT CONTROL PIN DESCRIPTIONS
Buffer
Type
Symbol
Description
Port 6
Power Enable /
Overcurrent
Sense
PRT_CTL6
I/OD12 Port 6 Power Enable / Overcurrent Sense.
(PU)
When the downstream port is enabled, this pin is set as
an input with an internal pull-up resistor applied. The
internal pull-up enables power to the downstream port
while the pin monitors for an active low overcurrent signal
assertion from an external current monitor on USB port 6.
This pin will change to an output and be driven low when
the port is disabled by configuration or by the host con-
trol.
Port 5
Power Enable /
Overcurrent
Sense
PRT_CTL5
PRT_CTL4
PRT_CTL3
I/OD12 Port 5 Power Enable / Overcurrent Sense.
(PU)
When the downstream port is enabled, this pin is set as
an input with an internal pull-up resistor applied. The
internal pull-up enables power to the downstream port
while the pin monitors for an active low overcurrent signal
assertion from an external current monitor on USB port 5.
This pin will change to an output and be driven low when
the port is disabled by configuration or by the host con-
trol.
Port 4
Power Enable /
Overcurrent
Sense
I/OD12 Port 4 Power Enable / Overcurrent Sense.
(PU)
When the downstream port is enabled, this pin is set as
an input with an internal pull-up resistor applied. The
internal pull-up enables power to the downstream port
while the pin monitors for an active low overcurrent signal
assertion from an external current monitor on USB port 4.
This pin will change to an output and be driven low when
the port is disabled by configuration or by the host con-
trol.
Port 3
Power Enable /
Overcurrent
Sense
I/OD12 Port 3 Power Enable / Overcurrent Sense.
(PU)
When the downstream port is enabled, this pin is set as
an input with an internal pull-up resistor applied. The
internal pull-up enables power to the downstream port
while the pin monitors for an active low overcurrent signal
assertion from an external current monitor on USB port 3.
This pin will change to an output and be driven low when
the port is disabled by configuration or by the host con-
trol.
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USB5926
TABLE 3-4:
PORT CONTROL PIN DESCRIPTIONS (CONTINUED)
Buffer
Type
Name
Symbol
Description
Port 2
Power Enable /
Overcurrent
Sense
PRT_CTL2
I/OD12 Port 2 Power Enable / Overcurrent Sense.
(PU)
When the downstream port is enabled, this pin is set as
an input with an internal pull-up resistor applied. The
internal pull-up enables power to the downstream port
while the pin monitors for an active low overcurrent signal
assertion from an external current monitor on USB port 2.
This pin will change to an output and be driven low when
the port is disabled by configuration or by the host con-
trol.
Port 1
Power Enable /
Overcurrent
Sense
PRT_CTL1
I/OD12 Port 1 Power Enable / Overcurrent Sense.
(PU)
When the downstream port is enabled, this pin is set as
an input with an internal pull-up resistor applied. The
internal pull-up enables power to the downstream port
while the pin monitors for an active low overcurrent signal
assertion from an external current monitor on USB port 1.
This pin will change to an output and be driven low when
the port is disabled by configuration or by the host con-
trol.
Gang Power
GANG_PWR
I
GANG_PWR becomes the port control (PRTCTL) pin for
all downstream ports when the hub is configured for
ganged port power control mode. All port power control-
lers should be controlled from this pin when the hub is
configured for ganged port power mode.
TABLE 3-5:
SPI INTERFACE
Buffer
Type
Name
Symbol
Description
SPI Chip Enable
SPI_CE_N
I/O12
This is the active low SPI chip enable output. If the SPI
interface is enabled, this pin must be driven high in
power-down states.
SPI Clock
SPI_CLK
I/O-U
This is the SPI clock out to the serial ROM. If the SPI
interface is disabled, by setting the SPI_DIS-ABLE bit in
the UTIL_CONFIG1 register, this pin becomes GPIO4. If
the SPI interface is enabled this pin must be driven low
during reset.
SPI Data Output
SPI Data Input
SPI_DO
SPI_DI
I/O-U
I/O-U
SPI data output, when configured for SPI operation.
SPI data input, when configured for SPI operation.
Note:
If SPI memory device is not used, these pins may not be simply floated. These pins must be handled per
their respective alternate pin functions descriptions (CFG_BC_EN and CFG_NON_REM).
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USB5926
TABLE 3-6:
Name
USB TYPE-C CONNECTOR CONTROLS
Buffer
Type
Symbol
Description
USB Type-C
Attach Control
Input 0-2
C_ATTACH[0:2]
I
“Type-C Control Mode 1” USB Type-C attach control
input.
(PD)
This pin indicates to the hub when a valid USB Type-C
attach has been detected. This pin is used by the hub to
enable the USB 3.2 Gen 1 PHY when a Type-C connec-
tion is present. When there is no USB Type-C connection
present, the USB 3.2 Gen 1 PHY is disabled to reduce
power consumption.
The polarity of this input is controlled via the CC_POL
pin. If CC_POL is low, this pin behaves as follows:
- 1: USB Type-C attach detected, turn respective
USB 3.2 Gen 1 PHY on.
- 0: No USB Type-C attach detected, turn respec-
tive USB 3.2 Gen 1 PHY off.
If CC_POL is high, this pin behaves as follows:
- 1: No USB Type-C attach detected, turn respec-
tive USB3.1 Gen 1 PHY off.
- 0: USB Type-C attach detected, turn respective
USB3.1 Gen 1 PHY on.
When using legacy USB Type-A and Type-B connectors,
pull these pins to 3.3V to permanently enable all USB 3.2
PHYs.
USB Type-C
Orientation
AB[0:2]
I
“Type-C Control Mode 1” USB Type-C orientation control
input.
(PD)
Control Input 0-2
This pin signals to the hub the orientation of the USB
Type-C connector. The hub enables the appropriate USB
3.1 Gen 1 PHY based upon the polarity of this signal, and
the assertion of the associated C_ATTACH[0:2] pin.
The polarity of this input is controlled via the CC_POL
pin. If CC_POL is low, this pin behaves as follows:
- 1: Enable USB 3.1 Gen 1 PHY B.
- 0: Enable USB 3.1 Gen 1 PHY A.
If CC_POL is high, this pin behaves as follows:
- 1: Enable USB 3.1 Gen 1 PHY A.
- 0: Enable USB 3.1 Gen 1 PHY B.
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USB5926
TABLE 3-6:
USB TYPE-C CONNECTOR CONTROLS (CONTINUED)
Buffer
Type
Name
Symbol
Description
USB Type-C
Alternative
Orientation A
Attach 0-2
ATTACH_MUX[0:2]A
I
“Type-C Control Mode 2” Alternative USB Type-C attach
for “Orientation A” USB Type-C connections.
(PD)
This mode of control is an alternative to the C_AT-
TACH[0:2] and AB[0:2] pins. To select this mode, the
ALT_MUX_EN pin must be high.
When this pin asserted, the hub enables the “Orientation
A” USB 3.1 Gen 1 PHY of the associated port. When
there is no USB Type-C connection present and this pin
is not asserted, the associated USB 3.1 Gen 1 PHY is
disabled to reduce power consumption.
The polarity of this input is controlled via the CC_POL
pin.
If CC_POL is low, this pin behaves as follows:
- 1: USB Type-C attach detected, turn respective
“Orientation A” USB 3.1 Gen 1 PHY on.
- 0: No USB Type-C attach detected, turn respec-
tive “Orientation A” USB 3.1 Gen 1 PHY off.
If CC_POL is high, this pin behaves as follows:
- 1: No USB Type-C attach detected, turn respec-
tive “Orientation A” USB 3.1 Gen 1 PHY off.
- 0: USB Type-C attach detected, turn respective
“Orientation A” USB 3.1 Gen 1 PHY on.
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USB5926
TABLE 3-6:
USB TYPE-C CONNECTOR CONTROLS (CONTINUED)
Buffer
Type
Name
Symbol
Description
USB Type-C
Alternative
ATTACH_MUX[0:2]B
I
“Type-C Control Mode 2” USB Type-C attach for “Orienta-
tion B” USB Type-C connections.
(PD)
Orientation B
Attach 0-2
This mode of control is an alternative to the C_AT-
TACH[0:2] and AB[0:2] pins.To select this mode, the
ALT_MUX_EN pin must be high.
When this pin asserted, the hub enables the “Orientation
B” USB 3.1 Gen 1 PHY of the associated port. When
there is no USB Type-C connection present and this pin
is not asserted, the associated USB 3.1 Gen 1 PHY is
disabled to reduce power consumption.
The polarity of this input is controlled via the CC_POL
pin.
If CC_POL is low, this pin behaves as follows:
- 1: USB Type-C attach detected, turn respective
“Orientation B” USB 3.1 Gen 1 PHY on.
- 0: No USB Type-C attach detected, turn respec-
tive “Orientation B” USB 3.1 Gen 1 PHY off.
If CC_POL is high, this pin behaves as follows:
- 1: No USB Type-C attach detected, turn respec-
tive “Orientation B” USB 3.1 Gen 1 PHY off.
- 0: USB Type-C attach detected, turn respective
“Orientation A” USB 3.1 Gen 1 PHY on.
Attach Polarity
Control
CC_POL
I
USB C_ATTACH polarity control input.
(PD)
If this pin is low, the C_ATTACH[0:2], AB[0:2],
ATTACH_MUX[0:2]A, and ATTACH_MUX[0:2]B pins
are active high.
If this pin is high, the C_ATTACH[0:2], AB[0:2],
ATTACH_MUX[0:2]A, and ATTACH_MUX[0:2]B pins
are active low.
This pin has an internal pull-down enabled. If the desired
strapping is to pull this pin low, then this pin may be left
unconnected.
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USB5926
TABLE 3-6:
USB TYPE-C CONNECTOR CONTROLS (CONTINUED)
Buffer
Type
Name
Symbol
Description
USB Type-C
Control Mode
Selection
ALT_MUX_EN
I
USB Type-C control mode selection.
(PD)
If this pin is low, the hub operates in “Type-C Control
Mode 1”. In “Type-C Control Mode 1”, the C_AT-
TACH[0:2] and AB[0:2] pin functions are used.
If this pin is high, the hub operates in “Type-C Control
Mode 2”. In “Type-C Control Mode 2”, the
ATTACH_MUX[0:2]A and ATTACH_MUX[0:2]B pin
functions are used.
This pin has an internal pull-down enabled. If the desired
mode is “Type-C Control Mode 1”, then this pin may be
left unconnected.
TABLE 3-7:
Name
MISCELLANEOUS PIN DESCRIPTIONS
Buffer
Symbol
Type
Description
SMBus/I2C
Clock
SMBCLK
I/O12
I/O12
O12
SMBus/I2C Clock
The SMBus/I2C interface acts as SMBus slave or I2C
bridge dependent on the device configuration.
For information on how to configure this interface refer to
Section 3.5.1, CFG_STRAP Configuration.
SMBus/I2C Data
SMBDATA
SMBus/I2C Data
The SMBus/I2C interface acts as SMBus slave or I2C
bridge dependent on the device configuration.
For information on how to configure this interface refer to
Section 3.5.1, CFG_STRAP Configuration.
USB Host
Port 1-0
HOST_TYPE_[1:0]
USB Host Port Speed Indicator
Speed Indicator
Tri-state: Not connected
0: USB 3.2 Gen 1
1: USB 2.0 / USB 1.1
General
Purpose I/O
GPIO[1:9],
GPIO12,
GPIO[17:23],
GPIO[64:71]
I/O12
(PU/
PD)
General Purpose Inputs/Outputs
Refer to Section 3.5.5, General Purpose input/Output
Configuration (GPIOx) for details.
USB 2.0
Suspend State
Indicator
SUSP_IND
O12
USB 2.0 Suspend State Indicator
SUSP_IND can be used as a sideband remote wakeup
signal for the host when in USB 2.0 suspend.
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USB5926
TABLE 3-7:
MISCELLANEOUS PIN DESCRIPTIONS (CONTINUED)
Buffer
Type
Name
Symbol
Description
Reset Control
Input
RESET_N
IS
Reset Control Input
This pin places the hub into Reset Mode when pulled low.
Bias Resistor
RBIAS
I-R
A 12.0 kΩ (+/- 1%) resistor is attached from ground to
this pin to set the transceiver’s internal bias settings.
Place the resistor as close to the device as possible with
a dedicated, low impedance connection to the GND
plane.
External 25 MHz
Crystal Input
XTALI
CLKIN
ICLK
ICLK
External 25 MHz crystal input
External 25 MHz
Reference Clock
Input
External reference clock input.
The device may alternatively be driven by a single-ended
clock oscillator. When this method is used, XTALO
should be left unconnected.
External 25 MHz
Crystal Output
XTALO
OCLK
I/O12
External 25 MHz crystal output
Test
TESTEN
Test pin.
This signal is used for test purposes and must always be
connected to ground.
No Connect
NC
-
No connect.
For proper operation, this signal must be left uncon-
nected.
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USB5926
TABLE 3-8:
Name
CONFIGURATION STRAP PIN DESCRIPTIONS
Buffer
Type
Symbol
Description
Device Mode
CFG_STRAP
I
Device Mode Configuration Strap.
Configuration
Strap
This configuration strap is used to set the device mode.
Refer to Section 3.5.1, CFG_STRAP Configuration for
details.
See Note 2
Port 6-1 D+
Disable
PRT_DIS_P[6:1]
I
Port 6-1 D+ Disable Configuration Strap.
Configuration
Strap
These configuration straps are used in conjunction with
the corresponding PRT_DIS_M[6:1] straps to disable the
related port (6-1). Refer to Section Section 3.5.2, Port
Disable Configuration (PRT_DIS_P[6:1] /
PRT_DIS_M[6:1]) for more information.
See Note 2
Port 6-1 D-
Disable
PRT_DIS_M[6:1]
I
Port 6-1 D- Disable Configuration Strap.
Configuration
Strap
These configuration straps are used in conjunction with
the corresponding PRT_DIS_P[6:1] straps to disable the
related port (6-1). Refer to Section 3.5.2, Port Disable
Configuration (PRT_DIS_P[6:1] / PRT_DIS_M[6:1]) for
more information.
See Note 2
Non-Removable
Ports
Configuration
Strap
CFG_NON_REM
CFG_BC_EN
I
I
Configuration strap to control number of reported non-
removal ports. See Section 3.5.3, Non-Removable Port
Configuration (CFG_NON_REM)
See Note 2
BatteryCharging
Configuration
Strap
Configuration strap to control number of BC 1.2 enabled
downstream ports. See Section 3.5.4, Battery Charging
Configuration (CFG_BC_EN)
See Note 2
Note 2:Configuration strap values are latched on Power-On Reset (POR) and the rising edge of RESET_N
(external chip reset). Configuration straps are identified by an underlined symbol name. Signals that function
as configuration straps must be augmented with an external resistor when connected to a load. Refer to
Section 3.5, Configuration Straps and Programmable Functions for additional information.
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USB5926
TABLE 3-9:
Name
POWER AND GROUND PIN DESCRIPTIONS
Buffer
Type
Symbol
Description
+3.3V Power
Supply Input
VDD33
P
P
P
+3.3 V power and internal regulator input
Refer to Section 4.1, Power Connections for power con-
nection information
+1.2V Core
Power Supply
Input
VDD12
GND
+1.2 V core power
Refer to Section 4.1, Power Connections for power con-
nection information.
Ground
Common ground.
This exposed pad must be connected to the ground plane
with a via array.
3.4
Buffer Type Descriptions
TABLE 3-10: USB5926 BUFFER TYPE DESCRIPTIONS
BUFFER
DESCRIPTION
I
Input.
IS
Input with Schmitt trigger.
O12
OD12
PU
Output buffer with 12 mA sink and 12 mA source.
Open-drain output with 12 mA sink
50 μA (typical) internal pull-up. Unless otherwise noted in the pin description, internal
pull-ups are always enabled.
Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on
internal resistors to drive signals external to the device. When connected to a load that
must be pulled high, an external resistor must be added.
PD
50 μA (typical) internal pull-down. Unless otherwise noted in the pin description,
internal pull-downs are always enabled.
Internal pull-down resistors prevent unconnected inputs from floating. Do not rely on
internal resistors to drive signals external to the device. When connected to a load that
must be pulled low, an external resistor must be added.
ICLK
OCLK
I/O-U
I-R
Crystal oscillator input pin
Crystal oscillator output pin
Analog input/output defined in USB specification.
RBIAS.
Note:
Refer to Section 10.5, DC Specifications for individual buffer DC electrical characteristics.
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USB5926
3.5
Configuration Straps and Programmable Functions
Configuration straps are multi-function pins that are used during Power-On Reset (POR) or external chip reset
(RESET_N) to determine the default configuration of a particular feature. The state of the signal is latched following de-
assertion of the reset. Configuration straps are identified by an underlined symbol name. This section details the various
device configuration straps and associated programmable pin functions.
Note:
The system designer must guarantee that configuration straps meet the timing requirements specified in
Section 10.6.2, Power-On and Configuration Strap Timing and Section 10.6.3, Reset and Configuration
Strap Timing. If configuration straps are not at the correct voltage level prior to being latched, the device
may capture incorrect strap values.
3.5.1
CFG_STRAP CONFIGURATION
The CFG_STRAP pin is used to place the hub into preset modes of operation. The resistor options are a 200 kΩ pull-
down, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, 10 Ω pull-down, and 10 Ω pull-up as shown in Table 3-11.
TABLE 3-11: CFG_STRAP RESISTOR ENCODING
CFG_STRAP
Resistor Value
Config
Setting
200 kΩ Pull-Down
CONFIG1
I2C Bridging Mode
The SMBus interface will operate in Master Mode for use with USB to I2C bridg-
ing function. For more information on USB to I2C bridging with the USB5806,
refer to the “USB to I2C Using Microchip USB 3.1 Gen 1 Hubs” application note.
200 kΩ Pull-Up
CONFIG2
SMBus Slave Mode
The SMBus interface will operate in Slave Mode for use with hub configuration.
10 kΩ Pull-Down
10 kΩ Pull-Up
10 Ω Pull-Down
10 Ω Pull-Up
CONFIG3
CONFIG4
CONFIG5
CONFIG6
Unused, Reserved
Unused, Reserved
Unused, Reserved
Unused, Reserved
3.5.2
PORT DISABLE CONFIGURATION (PRT_DIS_P[6:1] / PRT_DIS_M[6:1])
The PRT_DIS_P[6:1] and PRT_DIS_M[6:1] configuration straps are used in conjunction to disable the related port (6-1).
For PRT_DIS_Px (where x is the corresponding port 6-1):
0 = Port x D+ Enabled
1 = Port x D+ Disabled
For PRT_DIS_Mx (where x is the corresponding port 6-1):
0 = Port x D- Enabled
1 = Port x D- Disabled
Note:
Both PRT_DIS_Px and PRT_DIS_Mx (where x is the corresponding port) must be tied to 3.3 V to disable
the associated downstream port. Disabling the USB 2.0 port will also disable the corresponding USB 3.2
Gen 1 port.
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USB5926
3.5.3
NON-REMOVABLE PORT CONFIGURATION (CFG_NON_REM)
The CFG_NON_REM configuration strap is used to configure the non-removable port settings of the device to one of
five settings. These modes are selected by the configuration of an external resistor on the CFG_NON_REM pin. The
resistor options are a 200 kΩ pull-down, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, 10 Ω pull-down and 10 Ω pull-
up as shown in Table 3-12.
TABLE 3-12: CFG_NON_REM RESISTOR ENCODING
CFG_NON_REM Resistor Value
200 kΩ Pull-Down
Setting
All ports removable
200 kΩ Pull-Up
10 kΩ Pull-Down
10 kΩ Pull-Up
10 Ω Pull-Down
10 Ω Pull-Up
Port 3 non-removable
Port 3, 4 non-removable
Port 3, 4, 5, non-removable
Port 3, 4, 5, 6 non-removable
Reserved
3.5.4
BATTERY CHARGING CONFIGURATION (CFG_BC_EN)
The CFG_BC_EN configuration strap is used to configure the battery charging port settings of the device to one of five
settings. These modes are selected by the configuration of an external resistor on the CFG_BC_EN pin. The resistor
options are a 200 kΩ pull-down, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, 10 Ω pull-down and 10 Ω pull-up as
shown in Table 3-13.
TABLE 3-13: CFG_BC_EN RESISTOR ENCODING
CFG_BC_EN Resistor Value
200 kΩ Pull-Down
Setting
No battery charging
200 kΩ Pull-Up
10 kΩ Pull-Down
10 kΩ Pull-Up
10 Ω Pull-Down
10 Ω Pull-Up
Port 1 battery charging
Port 1, 2 battery charging
Port 1, 2, 3, battery charging
Port 1, 2, 3, 4 battery charging
Port 1, 2, 3, 4, 5, 6 battery charging
3.5.5
GENERAL PURPOSE INPUT/OUTPUT CONFIGURATION (GPIOx)
General Purpose Inputs/Outputs may be used for application specific purposes. Any given GPIO may operate as an
input or an output. Inputs can apply an internal 50kΩ pull-down or pull-up resistor. Outputs may drive low or drive high
(3.3V). GPIOs may be configured and manipulated during runtime (while enumerated to a host) in one of two ways:
• SMBus configuration
• USB to GPIO bridging
3.5.5.1
SMBus configuration
The SMBus slave interface may be used to write to internal registers that configure the state of the GPIO. Refer to the
“Configuration Options for Microchip USB58xx and USB59xx Hubs” application note for additional details.
3.5.5.2
USB to GPIO Bridging
USB to GPIO Bridging may be used to write to internal registers that configure the state of the GPIO. USB to GPIO
bridging operates via host communication to the hub’s internal Hub Feature Controller. Refer to the “USB to GPIO Bridg-
ing for Microchip USB 3.2 Gen 1 Hubs” application note for additional details.
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USB5926
4.0
4.1
DEVICE CONNECTIONS
Power Connections
Figure 4-1 illustrates the device power connections.
FIGURE 4-1:
DEVICE POWER CONNECTIONS
+3.3V
Supply
+1.2V
Supply
VDD33
VDD12
3.3V Internal Logic
1.2V Internal Logic
VSS
USB5926
4.2
SPI ROM Connections
Figure 4-2 illustrates the device SPI ROM connections. Refer to Section 7.1 “SPI Master Interface” for additional infor-
mation on this device interface.
FIGURE 4-2:
SPI ROM CONNECTIONS
SPI_CE_N
SPI_CLK
CE#
CLK
SPI ROM
USB5926
SPI_DO
DI
SPI_DI
DO
4.3
SMBus Slave Connections
Figure 4-3 illustrates the device SMBus slave connections. Refer to Section 7.2 “SMBus Slave Interface” for addi-
tional information on this device interface.
FIGURE 4-3:
SMBUS SLAVE CONNECTIONS
+3.3V
10K
SMCLK
Clock
Data
SMBus
Master
+3.3V
10K
USB5926
SMDAT
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USB5926
5.0
MODES OF OPERATION
The device provides two main modes of operation: Standby Mode and Hub Mode. These modes are controlled via the
RESET_N pin, as shown in Table 5-1.
TABLE 5-1:
MODES OF OPERATION
RESET_N Input
0
Summary
Standby Mode: This is the lowest power mode of the device. No functions are active
other than monitoring the RESET_N input. All port interfaces are high impedance and
the PLL is halted. Refer to Section 8.3.2, External Chip Reset (RESET_N) for additional
information on RESET_N.
1
Hub (Normal) Mode: The device operates as a configurable USB hub with battery
charger detection. This mode has various sub-modes of operation, as detailed in
Figure 5-1. Power consumption is based on the number of active ports, their speed,
and amount of data transferred.
The flowchart in Figure 5-1 details the modes of operation and how the device traverses through the Hub Mode stages
(shown in bold). The remaining sub-sections provide more detail on each stage of operation.
FIGURE 5-1:
HUB BOOT FLOWCHART
RESET_N deasserted
SPI
Signature
Present?
YES
Run from
External ROM
NO
(SPI_INIT)
Load Config from
External ROM
Load Config from
Internal ROM
Modify Config
Based on psuedo-
OTP
Modify Config
Based on OTP
(Ext_CFG
_RD)
(CFG_RD)
YES
Do SMBus or I2C
initialization
CFG_STRAP for
SMBus Slave?
NO
(STRAP)
No
SOC Done?
YES
Combine OTP
Config Data
(SOC_CFG)
(OTP_CFG)
Hub Connect
NORMAL operation
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USB5926
5.1
Standby Mode
If the RESET_N pin is asserted, the hub will be in Standby Mode. This mode provides a very low power state for maxi-
mum power efficiency when no signaling is required. This is the lowest power state. In Standby Mode all downstream
ports are disabled, the USB data pins are held in a high-impedance state, all transactions immediately terminate (no
states saved), all internal registers return to their default state, the PLLis halted, and core logic is powered down in order
to minimize power consumption. Because core logic is powered off, no configuration settings are retained in this mode
and must be re-initialized after RESET_N is negated high.
5.2
SPI Initialization Stage (SPI_INIT)
The first stage, the initialization stage, occurs on the deassertion of RESET_N. In this stage, the internal logic is reset,
the PLL locks if a valid clock is supplied, and the configuration registers are initialized to their default state. The internal
firmware then checks for an external SPI ROM. The firmware looks for an external SPI flash device that contains a valid
signature of “2DFU” (device firmware upgrade) beginning at address 0xFFFA. If a valid signature is found, then the
external ROM is enabled and the code execution begins at address 0x0000 in the external SPI device. If a valid signa-
ture is not found, then execution continues from internal ROM (CFG_RD stage).
When using an external SPI ROM, a 1 Mbit, 60 MHz or faster ROM must be used. Both 1- and 2-bit SPI operation are
supported. For optimum throughput, a 2-bit SPI ROM is recommended. Both mode 0 and mode 3 SPI ROMs are also
supported.
If the system is not strapped for SPI Mode, code execution will continue from internal ROM (CFG_RD stage).
5.3
Configuration Read Stage (CFG_RD)
In this stage, the internal firmware loads the default values from the internal ROM and then uses the configuration strap-
ping options to override the default values. Refer to Section 3.5, Configuration Straps and Programmable Functions for
information on usage of the various device configuration straps.
5.4
Strap Read Stage (STRAP)
In this stage, the firmware registers the configuration strap settings and checks the state of CFG_STRAP. If
CFG_STRAP is set for CONFIG2, then the hub will check the state of the SMBDATA and SMBCLK pins. If 10k pull-up
resistors are detected on both pins, the device will enter the SOC_CFG stage. If 10k pull-up resistors are not detected
on both pins, the hub will transition to the OTP_CFG stage instead.
5.5
SOC Configuration Stage (SOC_CFG)
In this stage, the SOC can modify any of the default configuration settings specified in the integrated ROM, such as USB
device descriptors and port electrical settings.
There is no time limit on this mode. In this stage the firmware will wait indefinitely for the SMBus/I2C configuration. When
the SOC has completed configuring the device, it must write to register 0xFF to end the configuration.
5.6
OTP Configuration Stage (OTP_CFG)
Once the SOC has indicated that it is done with configuration, all configuration data is combined in this stage. The
default data, the SOC configuration data, and the OTP data are all combined in the firmware and the device is pro-
grammed.
After the device is fully configured, it will go idle and then into suspend if there is no VBUS or Hub.Connect present.
Once VBUS is present, and battery charging is enabled, the device will transition to the Battery Charger Detection
Stage. If VBUS is present, and battery charging is not enabled, the device will transition to the Connect stage.
5.7
Hub Connect Stage (Hub.Connect)
Once the CHGDET stage is completed, the device enters the Hub Connect stage. USB connect can be initiated by
asserting the VBUS pin function high. The device will remain in the Hub Connect stage indefinitely until the VBUS pin
function is deasserted.
DS00002234E-page 26
2016-2021 Microchip Technology Inc.
USB5926
5.8
Normal Mode
Lastly, the hub enters Normal Mode of operation. In this stage full USB operation is supported under control of the USB
Host on the upstream port. The device will remain in the normal mode until the operating mode is changed by the sys-
tem.
2016-2021 Microchip Technology Inc.
DS00002234E-page 27
USB5926
6.0
DEVICE CONFIGURATION
The device supports a large number of features (some mutually exclusive), and must be configured in order to correctly
function when attached to a USB host controller. The hub can be configured either internally or externally depending on
the implemented interface.
Microchip provides a comprehensive software programming tool, Pro-Touch2, for configuring the USB5926 functions,
registers and OTP memory. All configuration is to be performed via the Pro-Touch2 programming tool. For additional
information on the Pro-Touch2 programming tool, refer to Software Libraries within Microchip USB5926 product page
at www.microchip.com/USB5926.
Note:
Device configuration straps and programmable pins are detailed in Section 3.5, Configuration Straps and
Programmable Functions.
Refer to Section 7.0, Device Interfaces for detailed information on each device interface.
6.1
Customer Accessible Functions
The following functions are available to the customer via the Pro-Touch2 Programming Tool.
Note:
For additional programming details, refer to the Pro-Touch2 programming tool User’s Guide.
6.1.1
6.1.1.1
USB ACCESSIBLE FUNCTIONS
I2C Bridging Access over USB
Access to I2C devices is performed as a pass-through operation from the USB Host. The device firmware has no knowl-
edge of the operation of the attached I2C device. For more information, refer to the Microchip USB5926 product page
and Pro-Touch2 at www.microchip.com/USB5926.
Note:
Refer to Section 7.3, I2C Bridge Interface for additional information on the I2C interface.
SPI Access over USB
6.1.1.2
Access to an attached SPI device is performed as a pass-through operation from the USB Host. The device firmware
has no knowledge of the operation of the attached SPI device. For more information, refer to the Microchip USB5926
product page and SDK at www.microchip.com/USB5926.
Note:
Refer to Section 7.1, SPI Master Interface for additional information on the SPI.
OTP Access
6.1.1.3
The OTP ROM in the device is accessible via the USB bus during normal runtime operation or SMBus during the
SOC_CFG stage. For more information, refer to the Microchip USB5926 product page or the Pro-Touch2 User’s Guide.
6.1.1.4
Battery Charging Access over USB
The Battery charging behavior of the device can be dynamically changed by the USB Host when something other than
the preprogrammed or OTP programmed behavior is desired. For more information, refer to the Microchip USB5926
product page or the Pro-Touch2 User’s Guide.
6.1.2
SMBUS ACCESSIBLE FUNCTIONS
OTP access and configuration of specific device functions are possible via the USB5926 SMBus slave interface. All OTP
parameters can be modified via the SMBus Host. For more information refer to the Microchip USB5926 product page.
DS00002234E-page 28
2016-2021 Microchip Technology Inc.
USB5926
7.0
DEVICE INTERFACES
The USB5926 provides multiple interfaces for configuration and external memory access. This section details the vari-
ous device interfaces and their usage:
• SPI Master Interface
• SMBus Slave Interface
• I2C Bridge Interface
Note:
For details on how to enable each interface, refer to Section 3.5, Configuration Straps and Programmable
Functions.
For information on device connections, refer to Section 4.0, Device Connections. For information on device
configuration, refer to Section 6.0, Device Configuration.
Microchip provides a comprehensive software programming tool, Pro-Touch2, for configuring the USB5926
functions, registers and OTP memory. All configuration is to be performed via the Pro-Touch2 programming
tool. For additional information on the Pro-Touch2 programming tool, refer to Software Libraries within
Microchip USB5926 product page at www.microchip.com/USB5926.
7.1
SPI Master Interface
The device is capable of code execution from an external SPI ROM. When configured for SPI Mode, on power up the
firmware looks for an external SPI flash device that contains a valid signature of 2DFU (device firmware upgrade) begin-
ning at address 0xFFFA. If a valid signature is found, then the external ROM is enabled and the code execution begins
at address 0x0000 in the external SPI device. If a valid signature is not found, then execution continues from internal
ROM.
Note:
For SPI timing information, refer to Section 10.6.7, SPI Timing.
7.2
SMBus Slave Interface
The device includes an integrated SMBus slave interface, which can be used to access internal device run time registers
or program the internal OTP memory. SMBus slave detection is accomplished by setting the CFG_STRAP in the correct
configuration followed by detection of pull-up resistors on both the SMDAT and SMCLK signals during the hub’s boot-
up sequence. Refer to Section 3.5.1, CFG_STRAP Configuration for additional information.
Note:
All configuration is to be performed via the Pro-Touch2 programming tool. For additional information on the
Pro-Touch2 programming tool, refer to Software Libraries within Microchip USB5926 product page at
www.microchip.com/USB5926.
7.3
I2C Bridge Interface
The I2C Bridge interface implements a subset of the I2C Master Specification (Please refer to the Philips Semiconductor
Standard I2C-Bus Specification for details on I2C bus protocols). The I2C Bridge conforms to the Fast-Mode I2C Spec-
ification (400 kbit/s transfer rate and 7-bit addressing) for protocol and electrical compatibility. The device acts as the
master and generates the serial clock SCL, controls the bus access (determines which device acts as the transmitter
and which device acts as the receiver), and generates the START and STOP conditions. The I2C Bridge interface fre-
quency is configurable through the I2C Bridging commands. I2C Bridge frequencies are derived from the formula
626KHz/n, where n is any integer from 1 to 256. Refer to Section 3.5.1, CFG_STRAP Configuration for additional infor-
mation.
Note:
Extensions to the I2C Specification are not supported.
All configuration is to be performed via the Pro-Touch2 programming tool. For additional information on the
Pro-Touch2 programming tool, refer to Software Libraries within Microchip USB5926 product page at
www.microchip.com/USB5926.
2016-2021 Microchip Technology Inc.
DS00002234E-page 29
USB5926
8.0
FUNCTIONAL DESCRIPTIONS
This section details various USB5926 functions, including:
• USB Type-C Receptacle Support
• Battery Charging
• Resets
• Link Power Management (LPM)
• Remote Wakeup Indicator
• Port Control Interface
• Port Split
8.1
USB Type-C Receptacle Support
The USB5926 has built-in support for the USB Type-C receptacle. There are 3 fundamental configurations:
• External USB 3.2 Gen 1 Multiplexer
• Internal USB3.1 Gen 1 Multiplexer, “Type-C Control Mode 1”
• Internal USB 3.1 Gen 1 Multiplexer, “Type-C Control Mode 2”
8.1.1
EXTERNAL USB 3.2 GEN 1 MULTIPLEXER
C_ATTACH[0:2] pins are used to signal to the hub when a valid USB Type-C connection has been detected. This func-
tionality requires an external USB Type-C controller such as a Microchip UTC2000 to monitor the USB Type-C recep-
tacle for a valid attach. This signal is used to enable and disable clocking to the USB 3.2 Gen 1 PHY in order to reduce
power consumption when there is no USB Type-C attach.
The polarity of the C_ATTACH[0:2] pins are controlled by the CC_POL pin. See Table 3-6 for details.
A diagram of a USB Type-C Downstream Facing Port with a USB5926, Microchip UTC2000, and external multiplexer
is shown in Figure 8-1.
FIGURE 8-1:
DFP TYPE-C PORT WITH MICROCHIP UTC2000 AND EXTERNAL MUX
USB Type-C
GENERIC
PO WER
USB Type-C
®
PORT PWR
CTLR
External Mux
Downstream Port
VBUS
OCS
SSTXA+
SSTXA-
SSTXA+
SSTXA-
SSTX+
SSTX-
SSRXA+
SSRXA-
SSTX+
SSTX-
SSRXA+
SSRXA-
MUX
SSRX+
SSRX-
SSTXB+
SSTXB-
SSRX+
SSRX-
SSTXB+
SSTXB-
SSRXB+
SSRXB-
SSRXB+
SSRXB-
A/B
D+
D-
D+
D-
ENABLE
OCS#
PRTCTL
3.3V
PLUG_OR#
PPC_EN
CC1
CC2
CC1
CC2
C_ATTACH
ALT_MUX_EN
CC_POL
UTC2000
DFP Mode
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2016-2021 Microchip Technology Inc.
USB5926
8.1.2
INTERNAL USB3.1 GEN 1 MULTIPLEXER, “TYPE-C CONTROL MODE 1”
“Type-C Control Mode 1” is enabled by setting the ALT_MUX_EN signal low or leaving it floating. While in “Type-C Con-
trol Mode 1”, the C_ATTACH[0:2] and AB[0:2] pins are used together to signal to the hub when a valid USB Type-C
connection has been detected and in what orientation the connection has been detected. This functionality requires an
external USB Type-C controller such as a Microchip UTC2000 to monitor the USB Type-C receptacle for a valid attach.
These signal are used to enable/disable the USB 3.1 Gen 1 PHYs appropriately according to the detected Type-C attach
and orientation. Unused USB 3.1 Gen 1 PHYs are disabled to conserve power.
The polarity of the C_ATTACH[0:2] pins and AB[0:2] are controlled by the CC_POL pin. See Table 3-6 for details.
A diagram of a USB Type-C Downstream Facing Port with the USB5916USB5926, Microchip UTC2000, and internal
multiplexer operating in “Type-C Control Mode 1” is shown in Figure 8-2.
A diagram of a USB Type-C Upstream Facing Port with the USB5926, Microchip UTC2000, and internal multiplexer
operating in “Type-C Control Mode 1” is shown in Figure 8-3.
FIGURE 8-2:
DFP TYPE-C PORT WITH MICROCHIP UTC2000 & INTERNAL MUX (MODE 1)
USB Type-C
GENERIC
PORT PWR
CTLR
POWER
USB Type-C®
Internal Mux
Downstream Port
VBUS
OCS
SSTXA+
SSTXA-
SSRXA+
SSRXA-
SSTXA+
SSTXA-
SSRXA+
SSRXA-
SSTXB+
SSTXB-
SSRXB+
SSRXB-
SSTXB+
SSTXB-
SSRXB+
SSRXB-
D+
D-
D+
D-
PRTCTL
3.3V
ENABLE
OCS#
CC1
CC2
CC1
CC2
AB
C_ATTACH
PLUG_OR#
PPC_EN
USB Type-C
ALT_MUX_EN
Control Mode 1
CC_POL
UTC2000
UFP Mode
2016-2021 Microchip Technology Inc.
DS00002234E-page 31
USB5926
FIGURE 8-3:
UFP TYPE-C PORT WITH MICROCHIP UTC2000 & EXTERNAL MUX (MODE 1)
USB Type-C
USB Type-C
®
External Mux
Upstream Port
VBUS
SSTXA+
SSTXA-
VBUS_DET
SSTXA+
SSTXA-
SSRXA+
SSRXA-
SSRXA+
SSRXA-
SSTX+
SSTX-
SSTX+
SSTX-
MUX
SSTXB+
SSTXB-
SSTXB+
SSTXB-
SSRX+
SSRX-
SSRX+
SSRX-
SSRXB+
SSRXB-
SSRXB+
SSRXB-
A/B
D+
D-
D+
D-
3.3V
3.3V
PLUG_
ORIENTATION#
C_ATTACH0
CONNECTED#
CC1
CC2
CC1
CC2
3.3V
UTC2000
UFP Mode
CC_POL
ALT_MUX_EN
8.1.3
INTERNAL USB 3.1 GEN 1 MULTIPLEXER, “TYPE-C CONTROL MODE 2”
“Type-C Control Mode 2” is enabled by setting the ALT_MUX_EN signal high. While in “Type-C Control Mode 2”, the
ATTACH_MUX[0:2]A and ATTACH_MUX[0:2]B pins are used to signal to the hub when a valid USB Type-C connec-
tion has been detected and in what orientation the connection has been detected. This functionality requires an external
USB Type-C controller (this mode not directly supported by UTC2000) to monitor the USB Type-C receptacle for a valid
attach. These signal are used to enable/disable the USB 3.1 Gen 1 PHYs appropriately according to the detected Type-
C attach and orientation. Unused USB 3.1 Gen 1 PHYs are disabled to conserve power.
The polarity of the ATTACH_MUX[0:2]A pins and ATTACH_MUX[0:2]B are controlled by the CC_POL pin. See
Table 3-6 for details.
A diagram of a USB Type-C Downstream Facing Port with internal multiplexer operating in “Type-C Control Mode 2”
with the USB5916USB5926 is shown in Figure 8-4.
A diagram of a USB Type-C Upstream Facing Port with internal multiplexer operating in “Type-C Control Mode 2” with
the USB5926 is shown in Figure 8-5.
DS00002234E-page 32
2016-2021 Microchip Technology Inc.
USB5926
FIGURE 8-4:
DFP TYPE-C PORT WITH GENERIC TYPE-C CONTROLLER AND INTERNAL MUX
(MODE 2)
USB Type-C
GENERIC
PO WER
USB Type-C
®
PORT PWR
CTLR
Internal Mux
VBUS
OCS
Downstream Port
SSTXA+
SSTXA-
SSRXA+
SSRXA-
SSTXA+
SSTXA-
SSRXA+
SSRXA-
SSTXB+
SSTXB-
SSRXB+
SSRXB-
SSTXB+
SSTXB-
SSRXB+
SSRXB-
D+
D-
D+
D-
PRTCTL
3.3V
ENABLE
OCS#
CC1
CC2
CC1
CC2
AB
PLUG_OR#
PPC_EN
C_ATTACH
ALT_MUX_EN
CC_POL
UTC2000
UFP Mode
FIGURE 8-5:
UFP TYPE-C PORT WITH GENERIC TYPE-C CONTROLLER & INTERNAL MUX
(MODE 2)
USB Type-C
USB Type-C
®
Internal Mux
VBUS
VB US_DET
Upstream Port
SSTXA+
SSTXA-
SSRXA+
SSRXA-
SSTXA+
SSTXA-
SS RX A+
SS RX A-
SSTXB+
SSTXB-
SSRXB+
SSRXB-
SSTXB+
SSTXB-
SS RX B+
SS RX B-
D+
D-
D+
D-
3.3V
UTC2000
UFP Mode
ATTACH_MUXA
AB
CC1
CC2
CC1
CC2
3.3V
CONNECTED#
PLUG_OR#
3.3V
ALT_MUX_EN
CC_POL
2016-2021 Microchip Technology Inc.
DS00002234E-page 33
USB5926
8.2
Battery Charging
The device can be configured by an OEM to have any of the downstream ports support battery charging. The hub’s role
in battery charging is to provide acknowledgment to a device’s query as to whether the hub system supports USB battery
charging. The hub silicon does not provide any current or power FETs or any additional circuitry to actually charge the
device. Those components must be provided externally by the OEM.
FIGURE 8-6:
BATTERY CHARGING EXTERNAL POWER SUPPLY
DC Power
Microchip
Hub
VBUS[n]
If the OEM provides an external supply capable of supplying current per the battery charging specification, the hub can
be configured to indicate the presence of such a supply from the device. This indication, via the PRT_CTL[6:1] pins, is
on a per port basis. For example, the OEM can configure two ports to support battery charging through high current
power FETs and leave the other two ports as standard USB ports.
For additional information, refer to the Microchip USB5926 Battery Charging application note on the Microchip.com
USB5926 product page www.microchip.com/USB5926.
8.3
Resets
• Power-On Reset (POR)
• External Chip Reset (RESET_N)
• USB Bus Reset
8.3.1
POWER-ON RESET (POR)
A power-on reset occurs whenever power is initially supplied to the device, or if power is removed and reapplied to the
device. A timer within the device will assert the internal reset per the specifications listed in Section 10.6.2, Power-On
and Configuration Strap Timing.
8.3.2
EXTERNAL CHIP RESET (RESET_N)
A valid hardware reset is defined as assertion of RESET_N, after all power supplies are within operating range, per the
specifications in Section 10.6.3, Reset and Configuration Strap Timing. While reset is asserted, the device (and its asso-
ciated external circuitry) enters Standby Mode and consumes minimal current.
Assertion of RESET_N causes the following:
1. The PHY is disabled and the differential pairs will be in a high-impedance state.
2. All transactions immediately terminate; no states are saved.
3. All internal registers return to the default state.
4. The external crystal oscillator is halted.
5. The PLL is halted.
Note:
All power supplies must have reached the operating levels mandated in Section 10.2, Operating Condi-
tions**, prior to (or coincident with) the assertion of RESET_N.
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2016-2021 Microchip Technology Inc.
USB5926
8.3.3
USB BUS RESET
In response to the upstream port signaling a reset to the device, the device performs the following:
1. Sets default address to 0.
2. Sets configuration to Unconfigured.
3. Moves device from suspended to active (if suspended).
4. Complies with the USB Specification for behavior after completion of a reset sequence.
The host then configures the device in accordance with the USB Specification.
Note:
The device does not propagate the upstream USB reset to downstream devices.
8.4
Link Power Management (LPM)
The device supports the L0 (On), L1 (Sleep), and L2 (Suspend) link power management states. These supported LPM
states offer low transitional latencies in the tens of microseconds versus the much longer latencies of the traditional USB
suspend/resume in the tens of milliseconds. The supported LPM states are detailed in Table 8-1.
TABLE 8-1:
LPM STATE DEFINITIONS
State
L2
Description
Entry/Exit Time to L0
Suspend
Entry: ~3 ms
Exit: ~2 ms (from start of RESUME)
L1
L0
Sleep
Entry: <10 us
Exit: <50 us
Fully Enabled (On)
-
8.5
Remote Wakeup Indicator
The remote wakeup indicator feature uses SUSP_IND as a side band signal to wake up the host when in USB 2.0 sus-
pend. This feature is enabled and disabled via the HUB_RESUME_INHIBIT configuration bit in the hub configuration
space register HUB_CFG_3. The only way to control the bit is by configuration EEPROM, SMBus or internal ROM
default setting. The state is only modified during a power on reset, or hardware reset. No dynamic reconfiguring of this
capability is possible.
When HUB_RESUME_INHIBIT = ‘0’, Normal Resume Behavior per the USB 2.0 specification
When HUB_RESUME_INHIBIT = ‘1’, Modified Resume Behavior is enabled
Note:
The SUSP_IND signal only indicates the USB2.0 state.
8.6
Port Control Interface
Port power and over-current sense share the same pin (PRT_CTLx) for each port. These functions can be controlled
directly from the USB hub, or via the processor. Additionally, smart port controllers can be controlled via the I2C inter-
face.
The device can be configured into one of the two following port control modes:
• Ganged Mode - A single GANG_PWR pin controls power and detects over-current events for all downstream
ports.
• Individual Mode - Each port has an individual PRT_CTLx pin for independent port power control and over-current
detection.
Port connection in various modes are detailed in the following subsections.
2016-2021 Microchip Technology Inc.
DS00002234E-page 35
USB5926
8.6.1
PORT CONNECTION IN GANGED MODE
Ganged Mode is enabled via SMBus or OTP configuration. GANG_PWR becomes the port control (PRTCTL) pin for all
downstream ports when the hub is configured for ganged port power control mode. All port power controllers should be
controlled from this pin when the hub is configured for ganged port power mode. While in this mode of operation, an
over-current event on any single downstream port will cause all downstream ports to be flagged for over-current.
8.6.2
PORT CONNECTION IN INDIVIDUAL MODE
Port Power Control using USB Power Switch
8.6.2.1
Individual mode is the default mode of operation. When operating in individual mode, the device will have one port power
control and over-current sense pin for each downstream port. When disabling port power, the driver will actively drive a
'0'. To avoid unnecessary power dissipation, the pull-up resistor will be disabled at that time. When port power is
enabled, it will disable the output driver and enable the pull-up resistor, making it an open drain output. If there is an
over-current situation, the USB Power Switch will assert the open drain OCS signal. The Schmidt trigger input will rec-
ognize that as a low. The open drain output does not interfere. The over-current sense filter handles the transient con-
ditions such as low voltage while the device is powering up.
FIGURE 8-7:
PORT POWER CONTROL WITH USB POWER SWITCH
Pull‐Up Enable
50k
5V
PRT_CTLx
OCS
USB Power
Switch
EN
PRTPWR
USB
Device
FILTER
OCS
When the port is enabled, the PRT_CTLx pin input is constantly sampled. Overcurrent events can be detected in one
of two ways:
• Single, continuous low pulse (consecutive low samples over tocs_single), as shown in Figure 8-8.
• Two short low pulses within a rolling window (two groupings of 1 or more low samples over tocs_double), as shown
in Figure 8-9.
FIGURE 8-8:
SINGLE LOW PULSE OVERCURRENT DETECTION
PRT_CTLx
IS VIL
tocs_single
DS00002234E-page 36
2016-2021 Microchip Technology Inc.
USB5926
FIGURE 8-9:
DOUBLE LOW PULSE OVERCURRENT DETECTION
PRT_CTLx
IS VIL
tocs_double
To maximize compatibility with various port power control topologies, the parameters tocs_single and tocs_double are con-
figurable via the Overcurrent Minimum Pulse Width Register and Overcurrent Inactive Timer Register.
The pin also has a turn-on “lockout” feature where the state of the pin is ignored for a configured amount of time imme-
diately after port power is turned on. This prevents slow ramp times due to parasitic resistance/capacitance attached to
the pin from triggering false overcurrent detections. This parameter is configurable via the Overcurrent Lockout Timer
Register.
TABLE 8-2:
OVERCURRENT MINIMUM PULSE WIDTH REGISTER
OCS_MIN_WIDTH
Overcurrent Detection Pulse Window
(30EAh)
BIT
Name
R/W
Description
7:4
Reserved
R
Reserved
3:0
OCS_MIN_WIDTH
R/W
The minimum overcurrent detection pulse width (tocs_single) is config-
ured in this register.
The range can be configured in 1ms increments from 0ms to 5ms.
0000 - 0ms minimum overcurrent detection pulse width
0001 - 1ms minimum overcurrent detection pulse width
0010 - 2ms minimum overcurrent detection pulse width
0011 - 3ms minimum overcurrent detection pulse width
0100 - 4ms minimum overcurrent detection pulse width
0101 - 5ms minimum overcurrent detection pulse width [Default]
TABLE 8-3:
OVERCURRENT INACTIVE TIMER REGISTER
OCS_INACTIVE_TIMER
Overcurrent Inactive Timer After First Overcurrent Detection
(30EBh)
BIT
7:0
Name
R/W
Description
OCS_INACTIVE_TIMER
R/W
This register configures the timer within which a double low pulse trig-
gers an overcurrent detection event (tocs_double).
The timer can be incremented in 1ms steps. The default value is
20ms (14h).
Note:
This register should never be set to 00h.
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DS00002234E-page 37
USB5926
TABLE 8-4:
OVERCURRENT LOCKOUT TIMER REGISTER
START_LOCKOUT_TIMER_REG
Start Lockout Timer Register
Description
(30E1h)
BIT
Name
R/W
7:0
START_LOCKOUT_TIMER_REG
R/W
The “start lockout timer” blocks an overcurrent event from
being detected immediately after port power is turned on.
Any overcurrent event within this timer value is ignored.
The timer can be incremented in 1ms steps. The default
value is 10ms (0Ah).
Note:
This register should never be set to 00h.
8.6.2.2
Port Power Control using Poly Fuse
When using the device with a poly fuse, there is no need for an output power control. To maintain consistency, the same
circuit will be used. A single port power control and over-current sense for each downstream port is still used from the
Hub's perspective. When disabling port power, the driver will actively drive a '0'. This will have no effect as the external
diode will isolate pin from the load. When port power is enabled, it will disable the output driver and enable the pull-up
resistor. This means that the pull-up resistor is providing 3.3 volts to the anode of the diode. If there is an over-current
situation, the poly fuse will open. This will cause the cathode of the diode to go to 0 volts. The anode of the diode will
be at 0.7 volts, and the Schmidt trigger input will register this as a low resulting in an over-current detection. The open
drain output does not interfere.
Note:
The USB 2.0 and USB 3.2 Gen 1 bPwrOn2PwrGood descriptors must be set to 0 when using poly-fuse
mode. Refer to the “Configuration Options for the USB58xx and USB59xx” Microchip application note for
details on how to change these values.
FIGURE 8-10:
PORT POWER CONTROL USING A POLY FUSE
5V
Pull-Up Enable
50k
Poly Fuse
PRT_CTLx
USB
Device
PRTPWR
FILTER
OCS
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2016-2021 Microchip Technology Inc.
USB5926
8.6.2.3
Port Power Control with Single Poly Fuse and Multiple Loads
Many customers use a single poly fuse to power all their devices. For the ganged situation, all power control pins must
be tied together.
FIGURE 8-11:
PORT POWER CONTROL WITH GANGED CONTROL WITH POLY FUSE
5V
Pull-Up Enable
50k
Poly Fuse
PRT_CTLz
Pull-Up Enable
50k
PRT_CTLy
Pull-Up Enable
50k
PRT_CTLx
USB
USB
USB
Device
Device
Device
PRTPWR
OCS
8.6.3
PORT CONTROLLER CONNECTION EXAMPLE
FIGURE 8-12:
GENERIC PORT POWER CONTROLLERS
Port x
Connector
(High Current)
POWER
PRT_CTLx
OCS
VBUS
(BC Enabled)
D+
Generic Port
Power Controller
D+
D-
D-
Port y
Connector
POWER
PRT_CTLy
OCS
VBUS
(BC Enabled)
D+
D-
Generic Port
Power Controller
D+
D-
Note:
The CFG_BC_EN configuration strap must be properly configured to enable battery charging on the appro-
priate ports. For more information on the CFG_BC_EN configuration strap, refer to Section 3.5.4, Battery
Charging Configuration (CFG_BC_EN).
2016-2021 Microchip Technology Inc.
DS00002234E-page 39
USB5926
8.7
Port Split
8.7.1
FEATURE OVERVIEW
This feature allows the USB 2.0 and USB 3.2 Gen 1 PHYs associated with any downstream port to be operationally
separated. The intention of this feature is to allow a system designer to connect an embedded USB 3.x device to the
USB 3.2 Gen 1 PHY, while allowing the USB 2.0 PHY to be used as either a standard USB 2.0 port or with a separate
embedded USB 2.0 device.
This feature operates outside of the provisions of the USB specifications. Operation is intended for specialized applica-
tions only. Contact your local sales representative for additional information.
In order to maintain a positive end user experience, it is recommended that only permanently attached, embedded USB
3.x devices be connected to the USB 3.2 Gen 1 PHY when enabling the Port Split feature. This prevents end users from
attempting to connect USB High-Speed, Full-Speed, or Low-Speed devices to an exposed USB port which only has USB
3.2 Gen 1 connections.
FIGURE 8-13:
RECOMMENDED PORT SPLITTING CONFIGURATIONS
PRTPWRx_USB3_SPLIT
(GPIOxx)
Embedded
USB3.x Device
EN
5V
USB58xx/
USB59xx
USB
Power
Switch
USB2.0
Device
PRTCTLx
OCS
EN
VBUS
PRTPWRx_USB3_SPLIT
(GPIOxx)
Embedded
USB3.x Device
EN
EN
USB58xx/
USB59xx
Embedded
USB2.0 Device
PRTCTLx
8.7.2
PORT SPLITTING CONFIGURATION
Downstream ports 3 and 4 may be configured for Port Splitting. Port Splitting is configured via register configuration
through SMBus during the hub configuration stage (SOC_CFG) or via the hub’s internal OTP memory.
When Port Splitting is enabled, the existing PRT_CTLx pin associated with that port will continue to control the USB 2.0
portion of the port in an identical matter. A new pin function assigned to a GPIOx pin will be activated and configured to
control the USB 3.2 Gen 1 portion of the port. This new pin is named PRTPWRx_USB3_SPLIT where x indicates the
respective port. Note that overcurrent detection is not supported on the PRTPWRx_USB3_SPLIT pin. These new pins
are assigned as shown in Table 8-5.
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2016-2021 Microchip Technology Inc.
USB5926
TABLE 8-5:
PORT SPLIT PRTPWRX_USB3_SPLIT PIN ASSIGNMENT
GPIOx Pin
Port Split Assignment
PRTPWR3_USB3_SPLIT Option A
GPIO66
GPIO6
GPIO5
GPIO4
PRTPWR4_USB3_SPLIT Option A
PRTPWR3_USB3_SPLIT Option B
PRTPWR4_USB3_SPLIT Option B
8.7.2.1
Enabling Port Splitting
In order to enable the Port Splitting feature on downstream ports 3 and/or 4, the following configuration settings must
be made.
Enabling Port Splitting on Port 3:
• Write 0x42 to register 0x416E to select GPIO66 for Option A
• Write 0x05 to register 0x416E to select GPIO5 for Option B
• Set bit 5 of the USB3_PORT_SPLIT_EN (0x3C48 = 0x20)
• Set bit 0 of the PORTSPLITENABLEFLAG (0x4141 = 0x01)
Enabling Port Splitting on Port 4:
• Write 0x06 to register 0x416F to select GPIO6 for Option A
• Write 0x04 to register 0x416F to select GPIO4 for Option B
• Set bit 6 of the USB3_PORT_SPLIT_EN (0x3C48 = 0x40)
• Set bit 0 of the PORTSPLITENABLEFLAG (0x4141 = 0x01)
TABLE 8-6:
USB 3.0 PORT SPLIT ENABLE REGISTER
USB3_PORT_SPLIT_EN
(0x3C48 - RESET = 0x00)
USB 3.0 Port Split Enable
Description
BIT
Name
R/W
7:1
PORT_SPLIT_EN[7:1]
R/W
0 = Port Splitting on the specified port is disabled
1 = Port Splitting on the specified port is enabled
Bit
[1] - Reserved
[2] - Reserved
[3] - Reserved
[4] - Reserved
[5] - Port 3
[6] - Port 4
[7] - Reserved
0
Reserved
R
Reserved
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DS00002234E-page 41
USB5926
TABLE 8-7:
GLOBAL PORT SPLIT ENABLE REGISTER
PORTSPLITENABLEFLAG
(0x4141 - RESET = 0x00)
Global Port Split Enable
Description
BIT
Name
R/W
7:1
0
Reserved
R
Reserved
GLOBAL_PORT_SPLIT_EN
R/W
0 = Port Split feature global disable
1 = Port Split feature global enable
8.7.2.2
Link Timeout Reset
Port Splitting is intended for use with embedded USB 3.x devices only. When Port Splitting is enabled, the hub constantly
monitors the USB 3.2 Gen 1 Link to see if a valid USB 3.2 Gen 1 Link is established. If there is no valid USB 3.2 Gen 1
Link for a configured amount of time (see below), then the hub will toggle assertion of the associated “PRTPWRx-
_USB3_SPLIT” pin in an attempt to reset the embedded USB 3.2 Gen 1 device and re-establish the USB 3.2 Gen 1 Link.
The timer is always reset and restarted whenever the timeout occurs.
A valid USB 3.2 Gen 1 link is qualified by the LTSSM_STATE register status for the port. A normal Link will actively
switch through many Link states.
If the hub detects that the Link is staying in one of the following Link states the entire duration of the timeout timer, then
the Link is stuck in an invalid state and PRTPWRx_USB3_SPLIT will be toggled in order to attempt to re-establish the
Link.
• SIS.Disabled(0x4)
• Rx.Detect(0x5)
• SS.Inactive(0x6)
• Polling(0x7)
• Recovery(0x8)
• HotReset (0x9)
The Link Timeout Reset value is configured via register 0x4171 and can be overridden by OTP. The default value is
0x05, which selects a Timeout value of 1 second. Setting the register to 0x00 will disable the Link Timeout Reset feature.
The duration of the Link reset (time which PRTPWRx_USB3_SPLIT signal stays low) can be configured in register
0x4176. The default duration is 400ms with a configurable range of 350ms to 2.9s.
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USB5926
8.8
USB Billboard Device Class Support
TABLE 8-8:
USB 3.X PORT SPLIT LINK TIMEOUT REGISTER
USB3_PORT_SPLIT_TIMEOUT
(0X4171 - RESET=0X05)
USB 3.X PORT SPLIT LINK TIMEOUT REGISTER
DESCRIPTION
BIT
NAME
R/W
[7:3]
[2:0]
Reserved
R/W
R/W
Always read ‘0’
PORT_SPLIT_TIMEOUT[
2:0]
Global USB Port Splitting Link Timeout Value
If Port Splitting is enabled on a port and there is no valid USB 3.x
Link for the configured amount of time, then the associated
“PRTPWRx_USB3_SPLIT” pin will be toggled in an attempt to reset
the embedded USB 3.x device and re-establish the USB 3.x Link.
The timer is always reset and restarted whenever the timeout
occurs.
000b - No Timeout, never toggle PRTPWRx_USB3_SPLIT
001b - 100ms
010b - 250ms
011b - 500ms
100b - 750ms
101b - 1 second
110b - 2 second
111b - Reserved
TABLE 8-9:
USB 3.X PORT SPLIT TOGGLE TIME REGISTER
USB3_PORT_SPLIT_TOGGLE_TIME
(0X4176 - RESET=0X05)
USB 3.X PORT SPLIT TOGGLE TIME REGISTER
DESCRIPTION
BIT
NAME
R/W
[7:0]
PORT_SPLIT_TOGGLE_
TIME[7:0]
R/W
The PORT_SPLIT_TOGGLE_TIME is used to control the length of
time port power is toggled off. This is specific to the
“PRTPWRx_USB3_SPLIT” pin, and is only used in conjunction with
0X4171. The timer is always reset whenever the toggle completes.
The minimum toggle time is 350ms and is represented by
00000000b.
Each incremental value will add 10ms to the 350ms minimum value.
USB Billboard is supported by the USB5926 in conjunction with an external USB Power Delivery capable controller that
supports the USB PD stack and alternate mode negotiation.
When a USB Type-C enabled product supports alternate modes for enhanced capability beyond what is available
through USB connectivity alone, that product must support a USB Billboard endpoint so that a user will be notified by
an operating system when the enhanced capability is not enabled due to an alternate mode mismatch.
A good example of alternate mode functionality is support for a DisplayPort monitor that many docking stations provide.
In this case, the docking station offers DisplayPort (DP) capability over the USB-C connector as an alternate mode.The
DP monitor will only function correctly when a successful alternate mode negotiation occurs between the docking station
and the notebook PC (this is the USB-C to USB-C connection). In order for the alternate mode negotiation to succeed,
the Notebook and the Docking Station must both support DP over USB-C, and have the DP messaging capability
enabled to support alternate mode negotiation. If the alternate mode negotiation is successful, then the notebook and
the Docking Station both change their multiplexers to enable DP signaling over USB Type-C. In this case, no USB Bill-
board messages need to be displayed.
2016-2021 Microchip Technology Inc.
DS00002234E-page 43
USB5926
If the above example instead uses a notebook that doesn’t support DP over USB-C, then the alternate mode negotiation
will fail. The docking station will not have a way to enable the DP monitor capability, reducing functionality for the cus-
tomer. For this is the reason, USB Billboard capability is mandated. In this case, a USB Billboard device class endpoint
must appear on a hub port within the Docking Station, and it must provide text and or a web site link which will provide
information to the user regarding the corrective steps required to use the feature.
In the case of the USB5926, all of the above mentioned negotiation capability will occur outside of the USB5926 via an
external USB Power Delivery capable device that contains a full USB PD stack and can communicate via USB PD mes-
saging. In an alternate mode failure case, the USB5926 will provide that message by allowing the USB host to enumer-
ate an internal USB Billboard Device Class just after the failure in response to a signal from the external USB PD
controller. The Billboard Device descriptors will contain the failure message to the USB Host. The message itself will be
prerecorded in the device’s OTP memory.
8.8.1
BILLBOARD ENABLE IN OTP AND GPIOx PIN USE
Any of the GPIOx pins may be selected to use as the BILLBOARD_EN input. By default, GPIO68 is selected when the
Billboard feature is enabled.
The BILLBOARD_EN input signal is active low. When the pin is driven low by a Power Delivery controller to indicate
an alternate mode negotiation failure, the Billboard functionality will activate.
TABLE 8-10: USB BILLBOARD CONTROL
USBBILLBOARDCNTL
USB BILLBOARD CONTROL
(OTP ADDR4 - RESET=0X14)
BIT
NAME
R/W
DESCRIPTION
[7:6]
[5:1]
Reserved
R/W
R/W
Always read ‘0’
BILLBOARD_EN Pin
Select
00000= GPIO64
00001= GPIO1
00010= GPIO2
00011= GPIO3
00100= GPIO65
00101= GPIO66
00110= GPIO67
00111= GPIO23
01000= GPIO10
01001= Reserved
01010= GPIO68 (default)
01011= GPIO6
01100= GPIO69
01101= GPIO70
01110= GPIO71
01111= GPIO5
10000= GPIO4
[0]
Billboard Support Enable
R/W
0 = Billboard support disabled
1 = Billboard support enabled
DS00002234E-page 44
2016-2021 Microchip Technology Inc.
USB5926
8.8.2
BILLBOARD ENDPOINT FUNCTIONALITY
When the applicable GPIOx pin is 0, which indicates that Billboard device must be displayed, the following sequence
of events will occur:
1. USB5926 will force the Hub Feature Controller internal device to disconnect from the USB Hub port (emulating
a physical detach)
2. USB5926 will force the Hub Feature Controller to re-connect with descriptors that will show the Hub Feature Con-
troller endpoint is a Billboard device, compliant to version 1.1 of the Billboard device class specification.
3. USB5926 will start a timer (Timer A) when the Host sets the Hub Feature Controller USB address. This timer will
be used to ensure that the Billboard endpoint will not remain permanently attached if it is never accessed. The
default Timer A timeout is 20 seconds.
4. This implementation will only support Billboard when a failure occurs, therefore the Device Container uses a
static list of device capabilities and will only expose the Billboard Device on failure to enter into Modal Operation
and will set the bmConfigured descriptor field to “Unspecified Error” (00b) by default.
5. The Hub Feature Controller will Provide the iAlternateModeString when the host requests it, and will start a timer
(Timer B). The default Timer B timeout is 20 seconds.
6. When either timer expires, the USB5926 will force the Hub Feature Controller internal device to disconnect from
the USB Hub port (emulating a physical detach).
7. USB5926 will force the Hub Feature Controller to re-connect with the standard Hub Feature Controller Function-
ality.
TABLE 8-11: TIMER A: BILLBOARD DETACH TIMER LSB
DETACH_TIMER_A_LSB
Billboard Detach Timer A LSB
(413Ch)
BIT
Name
R/W
Description
7:0
TIMEOUT
R/W
Timer A is started as soon as the Hub Feature Controller’s Billboard
Class Device address is set by the host. Once the timer expires, the
Billboard Class Device will automatically detach from the host and re-
attach as the default WinUSB device.
Increments of 10ms can be set.
The default value of 413Ch = D0h, 413Dh = 07h is equivalent to a 20s
timeout. (07D0h = 2000d)
TABLE 8-12: TIMER A: BILLBOARD DETACH TIMER MSB
DETACH_TIMER_A_MSB
Billboard Detach Timer A MSB
(413Dh)
BIT
Name
R/W
Description
7:0
TIMEOUT
R/W
Timer A is started as soon as the Hub Feature Controller’s Billboard
Class Device address is set by the host. Once the timer expires, the
Billboard Class Device will automatically detach from the host and re-
attach as the default WinUSB device.
Increments of 10ms can be set.
Note:
The default value of 413Ch = D0h, 413Dh = 07h is equiv-
alent to a 20s timeout. (07D0h = 2000d)
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DS00002234E-page 45
USB5926
TABLE 8-13: TIMER B: BILLBOARD DETACH TIMER LSB
DETACH_TIMER_B_LSB
Billboard Detach Timer B LSB
(413Eh)
BIT
Name
R/W
Description
7:0
TIMEOUT
R/W
Timer B is started as soon as the host requests iAlternateModeString.
Once the timer expires, the Billboard Class Device will automatically
detach from the host and re-attach as the default WinUSB device.
Increments of 10ms can be set.
The default value of 413Ch = D0h, 413Dh = 07h is equivalent to a 20s
timeout. (07D0h = 2000d)
TABLE 8-14: TIMER B: BILLBOARD DETACH TIMER MSB
DETACH_TIMER_B_MSB
Billboard Detach Timer A MSB
(413Fh)
BIT
Name
R/W
Description
7:0
TIMEOUT
R/W
Timer B is started as soon as the host requests iAlternateModeString.
Once the timer expires, the Billboard Class Device will automatically
detach from the host and re-attach as the default WinUSB device.
Increments of 10ms can be set.
Note:
The default value of 413Ch = D0h, 413Dh = 07h is equiv-
alent to a 20s timeout. (07D0h = 2000d)
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USB5926
8.8.3
BILLBOARD DEVICE DESCRIPTORS
The AlternateModeString and iAdditionalInfoURL descriptors can be configured in the hub to provide the user with addi-
tional information about the Alternate Mode failure.
TABLE 8-15: BILLBOARD DEVICE DESCRIPTORS
Offset: 0
Offset: +1
Offset: +2
Offset: +3
iAdditionalInfoURL
Default = 01h
bNumberOfAlternate-
bPreferredAlternateMode
VCONN Power[0]
VCONN Power[1]
Modes
Default = 00h
Default = 00h
Default = 80h
Default = 01h
bmConfigured[0]
bmConfigured[1]
bmConfigured[2]
bmConfigured[3]
Default = 00h
Default = 00h
Default = 00h
Default = 00h
bmConfigured[4]
bmConfigured[5]
bmConfigured[6]
bmConfigured[7]
Default = 00h
Default = 00h
Default = 00h
Default = 00h
bmConfigured[8]
bmConfigured[9]
bmConfigured[10]
bmConfigured[11]
Default = 00h
Default = 00h
Default = 00h
Default = 00h
bmConfigured[12]
bmConfigured[13]
bmConfigured[14]
bmConfigured[15]
Default = 00h
Default = 00h
Default = 00h
Default = 00h
bmConfigured[16]
bmConfigured[17]
bmConfigured[18]
bmConfigured[19]
Default = 00h
Default = 00h
Default = 00h
Default = 00h
bmConfigured[20]
bmConfigured[21]
bmConfigured[22]
bmConfigured[23]
Default = 00h
Default = 00h
Default = 00h
Default = 00h
bmConfigured[24]
bmConfigured[25]
bmConfigured[26]
bmConfigured[27]
Default = 00h
Default = 00h
Default = 00h
Default = 00h
bmConfigured[28]
bmConfigured[29]
bmConfigured[30]
bmConfigured[31]
Default = 00h
Default = 00h
Default = 00h
Default = 00h
bcdVersion[0]
bcdVersion[1]
bAdditonalFailureInfo
bReserved
Default = 10h
Default = 01h
Default = 00h
Default = 00h
wSVID[0]
wSVID[1]
bAlternateMode
Default = 00h
Default = FFh
Default = 00h
2016-2021 Microchip Technology Inc.
DS00002234E-page 47
USB5926
9.0
COMPLIANCE UPDATE
In order to be USB-IF certified , silicon revision C and newer of the USB5926 supports the USB 3.2 Engineering Change
Notices (ECNs) included in the Universal Serial Bus Revision 3.2 Specification. This allows the latest revision of the
USB5926 to be certified in compliance with USB-IF logo testing for the new USB Type-C® industry initiative. The follow-
ing compliance updates are supported:
• Pending Header Packet (HP) Timer (TD7.9, TD7.11, TD7.26)
• Power Management (PM) Timer (TD7.18, TD7.20, TD7.23)
• Unacknowledged Connect and Remote Wake Test Failure (TD10.25)
These USB 3.2 ECNs can be found as part of the Universal Serial Bus Revision 3.2 Specification zip file, which can be
downloaded from the USB developers website (http://www.usb.org/developers/docs/).
9.1
Pending Header Packet (HP) Timer (TD7.9, TD7.11, TD7.26)
A turn around time is defined between the communication of a Host and Device (Link Partners) for an acknowledgment
of a USB connection. The time is budgeted between a number of steps (Transmit/Receive data path of the initiator, the
delay in the cable, and the response time of the responder). If the time is exceeded, no USB communication is initiated.
The ECN calls to relax the timing from 3us to 10us at the link and PHY layers to allow for an extended propagation delay
to account for the usage of active cables and retimers in new SuperSpeed Plus designs.
Impact to Legacy Systems:
• A new host with a retimer connected to an active cable AND a legacy device
• A legacy host connected to an active cable and a new device with or without a retimer
9.2
Power Management (PM) Timer (TD7.18, TD7.20, TD7.23)
There are three timers for link power management: PM_LC_TIMER, PM_ENTRY_TIMER, and Ux_EXIT_TIMER. The
PM_LC_TIMER is used for a port initiating an entry request to a low power link state. The PM_ENTRY_TIMER is used
for a port accepting the entry request to a low power link state. Ux_EXIT_TIMER is used for a port to initiate the exit
from U1 or U2 to a low power state.
The ECN calls to increase the maximum timeout values to accommodate for the new connectivity models with retimers
and active cables beyond the standard USB-IF transmission lengths.
Impact to Legacy Systems:
• No impact to USB 3.0 or early USB 3.2 ecosystems
9.3
Unacknowledged Connect and Remote Wake Test Failure (TD10.25)
If a USB3 port with a connected device is placed into Suspend and RemoteWake is set but the RemoteWake mask
(C_PORT_CONNECTION bit) has not been cleared, the USB3 hub will automatically issue a wake up signal to the host.
In legacy systems, if a USB3 port with a connected device was placed into Suspend and RemoteWake is set without
the mask bit being cleared, the USB3 hub would NOT issue a wake up signal to the host.
Impact to Legacy Systems:
• No impact – with the new implementation, a remote wake is automatically initiated if the mask bit is not set. In
older systems the remote wake may or may not have been executed.
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USB5926
10.0 OPERATIONAL CHARACTERISTICS
10.1 Absolute Maximum Ratings*
+1.2 V Supply Voltage (VDD12) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +1.32 V
+3.3 V Supply Voltage (VDD33) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +4.6 V
Positive voltage on input signal pins, with respect to ground (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.6 V
Negative voltage on input signal pins, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V
Positive voltage on XTALI/CLKIN, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+3.63 V
Positive voltage on USB DP/DM signal pins, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6.0 V
Positive voltage on USB 3.2 Gen 1 USB3UP_xxxx and USB3DN_xxxx signal pins, with respect to ground . . . . .1.32 V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +150oC
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125oC
Lead Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Refer to JEDEC Spec. J-STD-020
HBM ESD Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 kV
Note 1: When powering this device from laboratory or system power supplies, it is important that the absolute max-
imum ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on
their outputs when AC power is switched on or off. In addition, voltage transients on the AC power line may
appear on the DC output. If this possibility exists, it is suggested to use a clamp circuit.
Note 2: This rating does not apply to the following pins: All USB DM/DP pins, XTAL1/CLKIN, and XTALO
*Stresses exceeding those listed in this section could cause permanent damage to the device. This is a stress rating
only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Functional
operation of the device at any condition exceeding those indicated in Section 10.2, Operating Conditions**,
Section 10.5, DC Specifications, or any other applicable section of this specification is not implied.
10.2 Operating Conditions**
+1.2 V Supply Voltage (VDD12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.08 V to +1.32 V
+3.3 V Supply Voltage (VDD33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.0 V to +3.6 V
Input Signal Pins Voltage (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +3.6 V
XTALI/CLKIN Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +3.6 V
USB 2.0 DP/DM Signal Pins Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +5.5 V
USB 3.2 Gen 1 USB3UP_xxxx and USB3DN_xxxx Signal Pins Voltage . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +1.32 V
Ambient Operating Temperature in Still Air (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Note 3
+1.2 V Supply Voltage Rise Time (TRT in Figure 10-1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 µs
+3.3 V Supply Voltage Rise Time (TRT in Figure 10-1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 µs
Note 3: 0oC to +70oC for commercial version, -40oC to +85oC for industrial version.
**Proper operation of the device is guaranteed only within the ranges specified in this section.
Note:
Do not drive input signals without power supplied to the device.
2016-2021 Microchip Technology Inc.
DS00002234E-page 49
USB5926
FIGURE 10-1:
SUPPLY RISE TIME MODEL
Voltage
TRT
3.3 V
1.2 V
100%
100%
VDD33
90%
90%
VDD12
VSS
10%
t90%
Time
t10%
Note:
The rise time for the 3.3 V supply can be extended to 100ms max if RESET_N is actively driven low, typi-
cally by another IC, until 1 µs after all supplies are within operating range.
10.3 Package Thermal Specifications
TABLE 10-1: PACKAGE THERMAL PARAMETERS
Symbol
°C/W
Velocity (Meters/s)
19
16
0
1
0
1
0
1
JA
0.1
0.1
1.4
1.4
JT
JC
Note:
Thermal parameters are measured or estimated for devices in a multi-layer 2S2P PCB per JESDN51.
TABLE 10-2: MAXIMUM POWER DISSIPATION
Parameter
Value
1.75
Units
PD(max)
W
DS00002234E-page 50
2016-2021 Microchip Technology Inc.
USB5926
10.4 Power Consumption
The values shown below represent typical power consumption as measured during various modes of operation. Power
dissipation is determined by temperature, supply voltage, and external source/sink requirements.
The following measurements were taken with VDD33 equal to 3.3V, VDD12 equal to 1.2V, at an ambient temperature
of 25°C.
Note:
A USB 3.x hub operates both the USB 3.x and USB 2.0 interfaces in parallel on it’s upstream port connec-
tion. A port operating under the SS/HS condition indicates that a USB 3.x hub was connected to it.
TABLE 10-3: DEVICE POWER CONSUMPTION
Typical (mA)
Typical Power
(mW)
VDD33
VDD12
Reset
1.0
4.0
4.0
83
10.5
8.0
16
23
No VBUS
Global Suspend
4 SS Ports + 2 HS Port
4 SS/HS Ports/2 HS Port
8.0
23
685
693
1,096
1,238
123
Note:
Actual power consumption will vary depending on the capabilities of the USB host, the devices connected,
data type, and data bus utilization. The published data represents typical power consumption of the hub at
nominal ambient temperature and supply voltage while large file transfers are active between USB host and
USB Mass Storage class devices on all downstream ports.
Typical power consumption for specific use cases can be estimated using the formulas below:
IVDD33(mA) = 35 + (NPORTSFS)(1)* +(NPORTSHS)(10) + (NPORTSSS)(7)
IVDD12(mA) = 245+ (NPORTSFS)(0.1)* +(NPORTSHS)(2) + (NPORTSSS)(109)
PTOTAL(mW) = 409.5+ (NPORTSFS)(3.42)* +(NPORTSHS)(35.4) + (NPORTSSS)(153.9)
10.5 DC Specifications
TABLE 10-4: I/O DC ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Min
Typical
Max
Units
Notes
I Type Input Buffer
Low Input Level
VIL
0.9
V
V
High Input Level
VIH
2.1
IS Type Input Buffer
Low Input Level
VIL
VIH
0.9
40
V
V
High Input Level
1.9
9
Schmitt Trigger Hysteresis
VHYS
20
mV
(VIHT - VILT
)
O6 Type Output Buffer
Low Output Level
VOL
VOH
0.4
V
V
IOL = 6 mA
High Output Level
VDD33-0.4
IOH = -6 mA
2016-2021 Microchip Technology Inc.
DS00002234E-page 51
USB5926
TABLE 10-4: I/O DC ELECTRICAL CHARACTERISTICS (CONTINUED)
Parameter
Symbol
Min
Typical
Max
Units
Notes
O12 Type Output Buffer
Low Output Level
VOL
VOH
0.4
V
V
IOL = 12 mA
High Output Level
VDD33-0.4
IOH = -12 mA
OD12 Type Output Buffer
Low Output Level
VOL
0.4
V
IOL = 12 mA
Note 4
ICLK Type Input Buffer
(XTALI Input)
Low Input Level
VIL
0.50
V
V
High Input Level
VIH
0.85
VDD33
IO-U Type Buffer
Note 5
(See Note 5)
Note 4: XTALI can optionally be driven from a 25 MHz singled-ended clock oscillator.
Note 5: Refer to the USB 3.2 Gen 1 Specification for USB DC electrical characteristics.
10.6 AC Specifications
This section details the various AC timing specifications of the device.
10.6.1
POWER SUPPLY AND RESET_N SEQUENCE TIMING
Figure 10-2 illustrates the recommended power supply sequencing and timing for the device. VDD33 should rise after
or at the same rate as VDD12. Similarly, RESET_N and/or VBUS_DET should rise after or at the same rate as VDD33.
VBUS_DET and RESET_N do not have any other timing dependencies.
FIGURE 10-2:
POWER SUPPLY AND RESET_N SEQUENCE TIMING
VDD12
tVDD33
VDD33
treset
RESET_N/
VBUS_DET
TABLE 10-5: POWER SUPPLY AND RESET_N SEQUENCE TIMING
Symbol
Description
VDD12 to VDD33 rise time
VDD33 to RESET_N/VBUS_DET rise time
Min
Typ
Max
Units
tVDD33
treset
0
0
ms
ms
DS00002234E-page 52
2016-2021 Microchip Technology Inc.
USB5926
10.6.2
POWER-ON AND CONFIGURATION STRAP TIMING
Figure 10-3 illustrates the configuration strap valid timing requirements in relation to power-on, for applications where
RESET_N is not used at power-on. In order for valid configuration strap values to be read at power-on, the following
timing requirements must be met. The operational levels (Vopp) for the external power supplies are detailed in
Section 10.2, Operating Conditions**.
FIGURE 10-3:
POWER-ON CONFIGURATION STRAP VALID TIMING
All External
Power Supplies
Vopp
Configuration
Straps
TABLE 10-6: POWER-ON CONFIGURATION STRAP LATCHING TIMING
Symbol
Description
Min
Typ
Max
Units
tcsh
Configuration strap hold after external power supplies at opera-
1
ms
tional levels
Device configuration straps are also latched as a result of RESET_N assertion. Refer to Section 10.6.3, Reset and Con-
figuration Strap Timing for additional details.
10.6.3
RESET AND CONFIGURATION STRAP TIMING
Figure 10-4 illustrates the RESET_N pin timing requirements and its relation to the configuration strap pins. Assertion
of RESET_N is not a requirement. However, if used, it must be asserted for the minimum period specified. Refer to
Section 8.3, Resets for additional information on resets. Refer to Section 3.5, Configuration Straps and Programmable
Functions for additional information on configuration straps.
FIGURE 10-4:
RESET_N CONFIGURATION STRAP TIMING
trstia
RESET_N
tcsh
Configuration
Straps
TABLE 10-7: RESET_N CONFIGURATION STRAP TIMING
Symbol
Description
RESET_N input assertion time
Min
Typ
Max
Units
trstia
tcsh
5
1
s
Configuration strap pins hold after RESET_N deassertion
ms
Note:
The clock input must be stable prior to RESET_N deassertion.
Configuration strap latching and output drive timings shown assume that the Power-On reset has finished
first otherwise the timings in Section 10.6.2, Power-On and Configuration Strap Timing apply.
2016-2021 Microchip Technology Inc.
DS00002234E-page 53
USB5926
10.6.4
USB TIMING
All device USB signals confirm to the voltage, power, and timing characteristics/specifications as set forth in the Univer-
sal Serial Bus Specification. Please refer to the Universal Serial Bus Revision 3.2 Specification, available at http://
www.usb.org/developers/docs.
10.6.5
I2C TIMING
All device I2C signals confirm to the 100KHz Standard Mode (Sm) voltage, power, and timing characteristics/specifica-
tions as set forth in the I2C-Bus Specification. Please refer to the I2C-Bus Specification, available at http://www.nxp.com/
documents/user_manual/UM10204.pdf.
10.6.6
SMBUS TIMING
All device SMBus signals confirm to the voltage, power, and timing characteristics/specifications as set forth in the Sys-
tem Management Bus Specification. Please refer to the System Management Bus Specification, Version 1.0, available
at http://smbus.org/specs.
10.6.7
SPI TIMING
This section specifies the SPI timing requirements for the device.
FIGURE 10-5:
SPI TIMING
tceh
SPI_CE_N
SPI_CLK
SPI_DI
tfc
tcel
tclq
tdh
tos toh
tov
toh
SPI_DO
TABLE 10-8: SPI TIMING (30 MHZ OPERATION)
Symbol
Description
Min
Typ
Max
Units
tfc
tceh
tclq
tdh
Clock frequency
30
MHz
ns
Chip enable (SPI_CE_EN) high time
Clock to input data
100
13
ns
Input data hold time
0
5
ns
tos
Output setup time
ns
toh
Output hold time
5
ns
tov
Clock to output valid
4
ns
tcel
tceh
Chip enable (SPI_CE_EN) low to first clock
Last clock to chip enable (SPI_CE_EN) high
12
12
ns
ns
DS00002234E-page 54
2016-2021 Microchip Technology Inc.
USB5926
TABLE 10-9: SPI TIMING (60 MHZ OPERATION)
Symbol
Description
Min
Typ
Max
Units
tfc
tceh
tclq
tdh
Clock frequency
60
MHz
ns
Chip enable (SPI_CE_EN) high time
Clock to input data
50
9
ns
Input data hold time
0
5
ns
tos
Output setup time
ns
toh
Output hold time
5
ns
tov
Clock to output valid
4
ns
tcel
tceh
Chip enable (SPI_CE_EN) low to first clock
Last clock to chip enable (SPI_CE_EN) high
12
12
ns
ns
10.7 Clock Specifications
The device can accept either a 25MHz crystal or a 25MHz single-ended clock oscillator (±50ppm) input. If the single-
ended clock oscillator method is implemented, XTALO should be left unconnected and XTALI/CLKIN should be driven
with a nominal 0-3.3V clock signal. The input clock duty cycle is 40% minimum, 50% typical and 60% maximum.
It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals
(XTALI/XTALO). The following circuit design (Figure 10-6) and specifications (Table 10-10) are required to ensure
proper operation.
FIGURE 10-6:
25MHZ CRYSTAL CIRCUIT
XTALO
Y1
XTALI
C1
C2
10.7.1
CRYSTAL SPECIFICATIONS
It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals
(XTALI/XTALO). Refer to Table 10-10 for the recommended crystal specifications.
TABLE 10-10: CRYSTAL SPECIFICATIONS
PARAMETER
Crystal Cut
SYMBOL
MIN
NOM
MAX
UNITS
NOTES
AT, typ
Crystal Oscillation Mode
Crystal Calibration Mode
Frequency
Frequency Tolerance @ 25oC
Frequency Stability Over Temp
Frequency Deviation Over Time
Fundamental Mode
Parallel Resonant Mode
Ffund
Ftol
-
25.000
-
MHz
PPM
PPM
PPM
-
-
-
-
±50
±50
-
Ftemp
Fage
-
±3 to 5
Note 6
2016-2021 Microchip Technology Inc.
DS00002234E-page 55
USB5926
TABLE 10-10: CRYSTAL SPECIFICATIONS (CONTINUED)
PARAMETER
SYMBOL
MIN
NOM
MAX
UNITS
NOTES
Total Allowable PPM Budget
Shunt Capacitance
-
-
7 typ
20 typ
-
±100
PPM
pF
Note 7
CO
CL
-
-
Load Capacitance
-
-
pF
Drive Level
PW
R1
100
-
uW
Equivalent Series Resistance
Operating Temperature Range
XTALI/CLKIN Pin Capacitance
XTALO Pin Capacitance
-
-
60
Ω
Note 7
-
Note 8
oC
pF
-
-
3 typ
3 typ
-
-
Note 9
Note 9
pF
Note 6: Frequency Deviation Over Time is also referred to as Aging.
Note 7: 0 °C for commercial version, -40 °C for industrial version.
Note 8: +70 °C for commercial version, +85 °C for industrial version.
Note 9: This number includes the pad, the bond wire and the lead frame. PCB capacitance is not included in this
value. The XTALI/CLKIN pin, XTALO pin and PCB capacitance values are required to accurately calculate
the value of the two external load capacitors. These two external load capacitors determine the accuracy of
the 25.000 MHz frequency.
10.7.2
EXTERNAL REFERENCE CLOCK (CLKIN)
When using an external reference clock, the following input clock specifications are suggested:
• 25 MHz
• 50% duty cycle ±10%, ±100 ppm
• Jitter < 100 ps RMS
DS00002234E-page 56
2016-2021 Microchip Technology Inc.
USB5926
11.0 PACKAGE INFORMATION
11.1 Package Marking Information
100-VQFN (12x12 mm)
PIN 1
USB5926i
e3
Rnnn e3
YYWWNNN
Legend:
i
R
Temperature range designator (Blank = commercial, i = industrial)
Product revision
nnn
e3
YY
Internal code
Pb-free JEDEC® designator for Matte Tin (Sn)
Year code (last two digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Note:
In the event the full Microchip part number cannot be marked on one line, it
will be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
* Standard device marking consists of Microchip part number, year code, week code and traceability code.
For device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.
For QTP devices, any special marking adders are included in QTP price.
2016-2021 Microchip Technology Inc.
DS00002234E-page 57
USB5926
11.2 Package Drawings
Note:
For the most current package drawings, see the Microchip Packaging Specification at:
http://www.microchip.com/packaging.
FIGURE 11-1:
100-VQFN PACKAGE (DRAWING)
6((
'(7$,/ꢆ$
'
$
%
(
127(ꢆꢂ
1
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ꢈ
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ꢈ;
ꢀꢁꢂꢀ &
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ꢀꢁꢂꢀ
& $ %
6($7,1*
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& $ %
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DS00002234E-page 58
2016-2021 Microchip Technology Inc.
USB5926
FIGURE 11-2:
100-VQFN PACKAGE (DIMENSIONS)
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8QLWV
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0,//,0(7(56
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7HUPLQDOꢆ7KLFNQHVV
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1
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Notes:
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ꢈꢁ 3DFNDJHꢆLVꢆVDZꢆVLQJXODWHG
ꢌꢁ 'LPHQVLRQLQJꢆDQGꢆWROHUDQFLQJꢆSHUꢆ$60(ꢆ<ꢂꢉꢁꢄ0
%6&ꢏꢆ%DVLFꢆ'LPHQVLRQꢁꢆ7KHRUHWLFDOO\ꢆH[DFWꢆYDOXHꢆVKRZQꢆZLWKRXWꢆWROHUDQFHVꢁ
5()ꢏꢆ5HIHUHQFHꢆ'LPHQVLRQꢐꢆXVXDOO\ꢆZLWKRXWꢆWROHUDQFHꢐꢆIRUꢆLQIRUPDWLRQꢆSXUSRVHVꢆRQO\ꢁ
0LFURFKLSꢆ7HFKQRORJ\ꢆ'UDZLQJꢆꢆ&ꢀꢉꢊꢉꢀꢃꢆ5HYꢆ%ꢆ6KHHWꢆꢈꢆRIꢆꢈ
2016-2021 Microchip Technology Inc.
DS00002234E-page 59
USB5926
FIGURE 11-3:
100-VQFN PACKAGE (LAND PATTERN)
C1
X2
EV
100
1
2
ØV
C2 Y2
EV
G1
Y1
X1
SILK SCREEN
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
MILLIMETERS
NOM
0.40 BSC
MIN
0.20
MAX
Contact Pitch
Optional Center Pad Width
Optional Center Pad Length
Contact Pad Spacing
X2
Y2
C1
C2
X1
Y1
G1
V
8.10
8.10
11.70
11.70
Contact Pad Spacing
Contact Pad Width (X100)
Contact Pad Length (X100)
Contact Pad to Center Pad (X100)
Thermal Via Diameter
0.20
1.05
0.33
1.20
Thermal Via Pitch
EV
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-2407A
DS00002234E-page 60
2016-2021 Microchip Technology Inc.
USB5926
APPENDIX A: REVISION HISTORY
TABLE A-1:
REVISION HISTORY
Revision Level & Date
Section/Figure/Entry
Correction
• Updated figures
Figure 8-1, Figure 8-2, Figure 8-3,
Figure 8-4, Figure 8-5
DS00002234E (07-06-21)
• Updated USB 3.1 to USB 3.2 throughout
the document.
Table 10-3
Cover
• Updated Power Numbers: Reset, No
VBUS and Global Suspend
• Added new Highlight bullet/sub-bullets
regarding USB-IF ECN support (Revision
C or newer only).
• Added sub-bullet under PHYBoost: “USB
2.0 Hi-Speed disconnect threshold adjust
(Revision C or newer only)”
Section 1.2, Reference Documents
Section 3.0, Pin Descriptions
Updated USB specification reference.
• Removed GPIO10 and GPIO72 from pins
21 and 22. Replaced with NC (No Con-
nect).
• Removed GPIO16 from pin 24.
Section 9.0, Compliance Update
Added new compliance update section.
Section 10.1, Absolute Maximum Rat- Updated HBM ESD Performance to 2.5 kV
ings*
Product Identification System
• Added “C” to part number ordering codes/
examples.
• Added note 2: Devices prior to silicon
revision C do not include upgrades
described in Chapter 9: Compliance
Updates.
• Added direction of unreeling diagram
Section 8.7.2.1, Enabling Port Split-
ting, Table 8-7
• Updated procedure with additional step to
set the global Port Split enable bit in the
Global Port Split Enable Register.
• Added Global Port Split Enable Register
definition.
Table 3-6
Table 3-6
Added pull-down (PD) to buffer type of C_AT-
TACH[0:2], AB[0:2], CC_POL, ALT_MUX-
_EN, ATTACH_MUX[0:2]A,
DS00002234D (05-11-18)
ATTACH_MUX[0:2]B pins.
Corrected the AB[0:2] 0 and 1 state descrip-
tions.
Section 8.7.2.1, Enabling Port Split-
Updated section and added
ting
USB3_PORT_SPLIT_EN register information.
DS00002234C (08-18-17) Figure 11-1, Figure 11-2, Figure 11-3 Updated package drawings.
Cover, Section 2.1, General Descrip- Removed references to FlexConnect.
tion, Section 8.0, Functional Descrip-
tions
Section 3.2, Pin Symbols, Figure 3-1, Removed references to FLEX_CMD and
Table 3-4
FLEX_STATE pins.
Section 3.2, Pin Symbols, Figure 3-1, Removed references to PRT_CTL0 pin.
Table 3-4
2016-2021 Microchip Technology Inc.
DS00002234E-page 61
USB5926
TABLE A-1:
REVISION HISTORY (CONTINUED)
Revision Level & Date
Section/Figure/Entry
Table 10-10
Correction
Updated max equivalent series resistance to
60Ω.
Table 10-3
Updated values.
Figure 4-2, SPI ROM Connections
Modified drawing by changing position of DO
to DI and DI to DO
DS00002234B (01-20-17)
Table 10-3, Device Power Consump- Typical power consumption formula added
tion
below table.
Section 8.7.2.1, Enabling Port Split-
Options A and B added.
ting
Throughout data sheet
Changed 62kOhm to 50kOhm
Table 3-1, Pin Reset State Legend
In PD-15k, changed “Hardware enables inter-
nal 62kOhm pull-down” to “Hardware enables
internal 15kOhm pull-down”
Section 3.2, Pin Symbols
Updated pin names for pin numbers:
51, 52, 57, 58 and 62
Figure 3-1 Pin Assignments (Top
View)
Modified Figure titles 8-1 and 8-4.
Initial Release
DS00002234A (10-03-16) All
DS00002234E-page 62
2016-2021 Microchip Technology Inc.
USB5926
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are
committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection
feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or
other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication is provided for the sole purpose of designing with and using Microchip products. Information regarding device
applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your applica-
tion meets with your specifications.
THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND
WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT
NOT LIMITED TO ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE.
IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE,
COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP
HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW,
MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THEAMOUNT
OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION. Use of Microchip devices in life support and/or
safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages,
claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights
unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo,
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch,
MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo,
PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero,
motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux,
TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the
U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM,
ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain,
Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net,
PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher,
SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in
other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other
countries.
All other trademarks mentioned herein are property of their respective companies.
© 2016-2021, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 9781522444114
For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.
2016-2021 Microchip Technology Inc.
DS00002234E-page 63
USB5926
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
[X](1)
PART NO.
/XX
[-X]
Examples:
Device Tape and Reel
Option
Temperature
Range
Package
a)
b)
USB5926C/KD
Tray, Commercial temp., 100-pin VQFN
USB5926C-I/KD
Tray, Industrial temp., 100-pin VQFN
c)
d)
USB5926CT/KD
Tape & reel, Commercial temp., 100-pin VQFN
Device:
USB5926C
USB5926CT-I/KD
Tape & reel, Industrial temp., 100-pin VQFN
Tape and Reel
Option:
Blank = Standard packaging (tube or tray)
T
= Tape and Reel(1)
Temperature
Range:
Blank
I
=
=
0C to +70C (Commercial)
-40C to +85C (Industrial)
Note 1:
Note 2:
Tape and Reel identifier only appears in the
catalog part number description. This
identifier is used for ordering purposes and is
not printed on the device package. Check
with your Microchip Sales Office for package
availability with the Tape and Reel option.
Devices prior to silicon revision C do not
include the upgrades described in
Package:
KD
=
100-pin VQFN
Section 9.0, Compliance Update.
DS00002234E-page 64
2016-2021 Microchip Technology Inc.
USB5926
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make
files and information easily available to customers. Accessible by using your favorite Internet browser, the web site con-
tains the following information:
• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
guides and hardware support documents, latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion
groups, Microchip consultant program member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of semi-
nars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive
e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or
development tool of interest.
To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notifi-
cation” and follow the registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales
offices are also available to help customers. A listing of sales offices and locations is included in the back of this docu-
ment.
Technical support is available through the web site at: http://microchip.com/support
2016-2021 Microchip Technology Inc.
DS00002234E-page 65
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Australia - Sydney
Tel: 61-2-9868-6733
India - Bangalore
Tel: 91-80-3090-4444
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
China - Beijing
Tel: 86-10-8569-7000
India - New Delhi
Tel: 91-11-4160-8631
Denmark - Copenhagen
Tel: 45-4485-5910
Fax: 45-4485-2829
China - Chengdu
Tel: 86-28-8665-5511
India - Pune
Tel: 91-20-4121-0141
Finland - Espoo
Tel: 358-9-4520-820
China - Chongqing
Tel: 86-23-8980-9588
Japan - Osaka
Tel: 81-6-6152-7160
Web Address:
www.microchip.com
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
China - Dongguan
Tel: 86-769-8702-9880
Japan - Tokyo
Tel: 81-3-6880- 3770
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
China - Guangzhou
Tel: 86-20-8755-8029
Korea - Daegu
Tel: 82-53-744-4301
Germany - Garching
Tel: 49-8931-9700
China - Hangzhou
Tel: 86-571-8792-8115
Korea - Seoul
Tel: 82-2-554-7200
Germany - Haan
Tel: 49-2129-3766400
Austin, TX
Tel: 512-257-3370
China - Hong Kong SAR
Tel: 852-2943-5100
Malaysia - Kuala Lumpur
Tel: 60-3-7651-7906
Germany - Heilbronn
Tel: 49-7131-72400
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
China - Nanjing
Tel: 86-25-8473-2460
Malaysia - Penang
Tel: 60-4-227-8870
Germany - Karlsruhe
Tel: 49-721-625370
China - Qingdao
Philippines - Manila
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Tel: 86-532-8502-7355
Tel: 63-2-634-9065
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
China - Shanghai
Tel: 86-21-3326-8000
Singapore
Tel: 65-6334-8870
Germany - Rosenheim
Tel: 49-8031-354-560
China - Shenyang
Tel: 86-24-2334-2829
Taiwan - Hsin Chu
Tel: 886-3-577-8366
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Israel - Ra’anana
Tel: 972-9-744-7705
China - Shenzhen
Tel: 86-755-8864-2200
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
China - Suzhou
Tel: 86-186-6233-1526
Taiwan - Taipei
Tel: 886-2-2508-8600
Detroit
Novi, MI
Tel: 248-848-4000
China - Wuhan
Tel: 86-27-5980-5300
Thailand - Bangkok
Tel: 66-2-694-1351
Italy - Padova
Tel: 39-049-7625286
Houston, TX
Tel: 281-894-5983
China - Xian
Tel: 86-29-8833-7252
Vietnam - Ho Chi Minh
Tel: 84-28-5448-2100
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Tel: 317-536-2380
China - Xiamen
Tel: 86-592-2388138
Norway - Trondheim
Tel: 47-7288-4388
China - Zhuhai
Tel: 86-756-3210040
Poland - Warsaw
Tel: 48-22-3325737
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Tel: 951-273-7800
Romania - Bucharest
Tel: 40-21-407-87-50
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Raleigh, NC
Tel: 919-844-7510
Sweden - Gothenberg
Tel: 46-31-704-60-40
New York, NY
Tel: 631-435-6000
Sweden - Stockholm
Tel: 46-8-5090-4654
San Jose, CA
Tel: 408-735-9110
Tel: 408-436-4270
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
2016-2021 Microchip Technology Inc.
DS00002234E-page 66
02/28/20
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