VP2450N3-G [MICROCHIP]
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| 型号： | VP2450N3-G |
| 厂家： | 
MICROCHIP |
| 描述： | 暂无描述 |
| 文件： | 总14页 (文件大小：1035K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VP2450
P-Channel Enhancement-Mode Vertical DMOS FET
Features
General Description
• Free from Secondary Breakdown
• Low Power Drive Requirement
• Ease of Paralleling
The VP2450 is a low-threshold, Enhancement-mode
(normally-off) transistor that utilizes
a
vertical
Double-diffused Metal-Oxide Semiconductor (DMOS)
structure and a well-proven silicon gate manufacturing
process. This combination produces a device with the
power handling capabilities of bipolar transistors and
the high input impedance and positive temperature
coefficient inherent in MOS devices. Characteristic of
all MOS structures, this device is free from thermal
runaway and thermally induced secondary breakdown.
• Low CISS and Fast Switching Speeds
• High Input Impedance and High Gain
• Excellent Thermal Stability
• Integral Source-drain Diode
Applications
This Vertical DMOS Field-Effect Transistor (FET) is
ideally suited to a wide range of switching and
amplifying applications where very low threshold
voltage, high breakdown voltage, high input
impedance, low input capacitance, and fast switching
speeds are desired.
• Motor Controls
• Converters
• Amplifiers
• Switches
• Power Supply Circuits
• Drivers: Relays, Hammers, Solenoids, Lamps,
Memory, Displays, Bipolar Transistors, etc.
Package Types
TO-92
SOT-89
DRAIN
SOURCE
DRAIN
GATE
DRAIN
SOURCE
GATE
See Table 3-1 for pin information.
2016 Microchip Technology Inc.
DS20005569A-page 1
VP2450
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Drain-to-source Voltage.........................................................................................................................................BVDSS
Drain-to-gate Voltage ............................................................................................................................................BVDGS
Gate-to-source Voltage ........................................................................................................................................... ±20V
Operating and Storage Temperatures.................................................................................................. –55°C to +150°C
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions above those
indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
Electrical Specifications: For all specifications, TA = TJ = +25°C unless otherwise noted.
Parameter
Sym.
Min. Typ. Max.
Unit
Conditions
DC PARAMETER (Note 1 unless otherwise stated)
Drain-to-source Breakdown Voltage
Gate Threshold Voltage
BVDSS –500
—
—
—
—
—
—
V
V
VGS = 0V, ID = –250 µA
VGS = VDS, ID = –1 mA
VGS(th)
∆VGS(th)
IGSS
–1.5
—
–3.5
Change in VGS(th) with Temperature
Gate Body Leakage Current
–4.8 mV/°C VGS = VDS, ID = –1 mA (Note 2)
—
–100
–10
nA
µA
VGS = ±20V, VDS = 0V
—
VGS = 0V, VDS = Maximum Rating
Zero Gate Voltage Drain Current
On-state Drain Current
IDSS
VDS = 0.8 Maximum Rating,
VGS = 0V, TA = 125°C (Note 2)
—
—
–1
mA
mA
–75
–200
—
—
—
—
—
—
—
35
30
VGS = –4.5V, VDS = –15V
ID(ON)
V
GS = –10V, VDS = –15V
VGS = –4.5V, ID = –50 mA
VGS = –10V, ID = –100 mA
Static Drain-to-source On-state
Resistance
RDS(ON)
Ω
—
Change in RDS(ON) with Temperature
VGS = –10V, ID = –100 mA
(Note 2)
∆RDS(ON)
—
—
0.75 %/°C
AC PARAMETER (Note 2)
Forward Transconductance
Input Capacitance
GFS
CISS
COSS
CRSS
td(ON)
tr
150
—
—
—
—
—
—
—
320
—
—
—
—
—
—
—
—
190
75
20
10
25
45
25
mmho VDS = –15V, ID = –100 mA
Common Source Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
pF
VGS = 0V, VDS = –25V, f = 1 MHz
Rise Time
VDD = –25V, ID = –200 mA,
RGEN = 25ꢀ
ns
Turn-off Delay Time
td(OFF)
tf
Fall Time
DIODE PARAMETER
VGS = 0V, ISD = –100 mA
(Note 1)
Diode Forward Voltage Drop
Reverse Recovery Time
VSD
trr
—
—
—
–1.8
—
V
VGS = 0V, ISD = –100 mA
(Note 2)
300
ns
Note 1: All DC parameters are 100% tested at 25°C unless otherwise stated.
(Pulse test: 300 µs pulse, 2% duty cycle)
2: Specification is obtained by characterization and is not 100% tested.
DS20005569A-page 2
2016 Microchip Technology Inc.
VP2450
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise noted, for all specifications TA =TJ = +25°C.
Parameter
Sym.
Min.
Typ.
Max.
Unit
Conditions
TEMPERATURE RANGE
Operating Temperature
Storage Temperature
PACKAGE THERMAL RESISTANCE
TO-92
TA
TS
–55
–55
—
—
+150
+150
°C
°C
JA
JA
—
—
132
133
—
—
°C/W
°C/W
SOT-89
THERMAL CHARACTERISTICS
ID (Note 1)
(Continuous)
(mA)
ID
Power Dissipation at
IDR (Note 1)
IDRM
(mA)
Package
(Pulsed)
(mA)
TA= 25°C
(W)
(mA)
TO-92
SOT-89
–100
–160
–300
–800
0.74
–100
–160
–300
–800
1.6 (Note 2)
Note 1: ID (continuous) is limited by maximum TJ.
2: Mounted on FR5 board, 25 mm x 25 mm X 1.57 mm
2016 Microchip Technology Inc.
DS20005569A-page 3
VP2450
2.0
TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g. outside specified power supply range) and therefore outside the warranted range.
1.2
80
60
40
20
0
1.1
1.0
0.9
0.8
VGS = -4.5V
V
GS = -10V
-50
0
50
100
150
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
Tj (OC)
ID (amperes)
FIGURE 2-1:
Te m pe ra tu re .
-1.2
BV
Variation with
DSS
FIGURE 2-4:
Current.
1.5
On-resistance vs. Drain
TA = -55OC
2.2
VDS = -20V
-1.0
-0.8
-0.6
-0.4
-0.2
0
1.3
1.8
1.4
1.0
0.6
25OC
VTH @ -1.0 mA
1.1
0.9
0.7
125OC
RDS(ON) @ -10V, -0.1A
0
-1.0
-2.0
-3.0
-4.0
-50
0
50
100
150
VGS (volts)
Tj (OC)
FIGURE 2-2:
Transfer Characteristics.
FIGURE 2-5:
V
and R
GS(th)
DS(ON)
Variation with Temperature.
400
-10
ID = -100mA
f = 1.0 MHz
-8.0
300
200
100
VDS = -20V
V
DS = -40V
-6.0
-4.0
-2.0
0
CISS
COSS
CRSS
-10
0
0
-20
-30
-40
0
1.0
2.0
3.0
VDS (volts)
QG (nanocoulombs)
FIGURE 2-3:
Drain-to-source Voltage.
Capacitance vs.
FIGURE 2-6:
Characteristics.
Gate Drive Dynamic
DS20005569A-page 4
2016 Microchip Technology Inc.
VP2450
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
-1.0
-0.8
-0.6
-0.4
-0.2
0
VGS = -10V
VGS = -4.5V
VGS = -10V
V
GS = -6.0V
VGS = -6.0V
V
GS = -4.5V
VGS = -3.5V
V
GS = -3.5V
0
-2.0
-4.0
-6.0
-8.0
-10
0
-10
-20
-30
-40
-50
VDS (volts)
VDS (volts)
FIGURE 2-7:
Output Characteristics.
FIGURE 2-10:
Saturation Characteristics.
1.0
2.0
VDS = -20V
TO-243AA
0.8
0.6
0.4
0.2
1.5
1.0
0.5
0
TA = -55OC
25OC
TO-92
125OC
0
0
0
25
50
75
100
125
150
-100
-200
-300
-400
-500
TC (OC)
ID (milliamperes)
FIGURE 2-8:
Current.
-1.0
Transconductance vs. Drain
FIGURE 2-11:
Temperature.
1.0
Power Dissipation vs. Case
TO-243AA (pulsed)
TO-92 (pulsed)
0.8
0.6
0.4
0.2
TO-243AA (DC)
-0.1
-0.01
TO-243AA
PDA = 1.6W
TO-92 (DC)
T
= 25OC
TO-92
T
= 25OC
PCD = 1.0W
TA = 25OC
0
-0.001
0.001
0.01
0.1
1.0
10
-1.0
-10
-100
-1000
tP (seconds)
VDS (volts)
FIGURE 2-9:
Maximum Rated Safe
FIGURE 2-12:
Thermal Response
Operating Area.
Characteristics.
2016 Microchip Technology Inc.
DS20005569A-page 5
VP2450
3.0
PIN DESCRIPTION
The details on the pins of VP2450 (TO-92 and SOT-89)
are listed on Table 3-1. Refer to Package Types for the
location of pins.
TABLE 3-1:
PIN FUNCTION TABLE
SOT-89
TO-92
Pin Number
Pin Number
Pin Name
Description
1
2
3
3
1
Source
Gate
Source
Gate
2,4
Drain
Drain
DS20005569A-page 6
2016 Microchip Technology Inc.
VP2450
4.0
FUNCTIONAL DESCRIPTION
Figure 4-1 illustrates the switching waveforms and test
circuit for VP2450.
0V
Pulse
10%
Generator
INPUT
RGEN
90%
t(OFF)
-10V
t(ON)
td(ON)
D.U.T.
tr
td(OFF)
tf
INPUT
OUTPUT
0V
RL
90%
90%
OUTPUT
10%
10%
VDD
VDD
FIGURE 4-1:
Switching Waveforms and Test Circuit.
PRODUCT SUMMARY
RDS(ON)
(Maximum)
(Ω)
ID(ON)
(Minimum)
(mA)
VGS(th)
(Maximum)
(V)
BVDSS/BVDGS
(V)
–500
30
–200
–0.4
2016 Microchip Technology Inc.
DS20005569A-page 7
VP2450
5.0
5.1
PACKAGING INFORMATION
Package Marking Information
3-lead TO-92
Example
VP2450
XXXXXX
e3
e3
XXXX
N3
YWWNNN
616343
3-lead SOT-89
Example
XXXXYWW
VP4E612
NNN
343
Legend: XX...X Product Code or Customer-specific information
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( )
e
3
*
e
3
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for product code or customer-specific information. Package may or
not include the corporate logo.
DS20005569A-page 8
2016 Microchip Technology Inc.
VP2450
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
2016 Microchip Technology Inc.
DS20005569A-page 9
VP2450
3-Lead TO-243AA (SOT-89) Package Outline (N8)
D
D1
C
H
E
E1
1
2
3
L
b
b1
A
e
e1
Top View
Side View
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
Symbol
A
1.40
-
b
0.44
-
b1
0.36
-
C
0.35
-
D
4.40
-
D1
1.62
-
E
2.29
-
E1
2.00†
-
e
e1
H
3.94
-
L
0.73†
-
MIN
NOM
MAX
Dimensions
(mm)
1.50
BSC
3.00
BSC
1.60
0.56
0.48
0.44
4.60
1.83
2.60
2.29
4.25
1.20
JEDEC Registration TO-243, Variation AA, Issue C, July 1986.
† This dimension differs from the JEDEC drawing
Drawings not to scale.
DS20005569A-page 10
2016 Microchip Technology Inc.
VP2450
APPENDIX A: REVISION HISTORY
Revision A (September 2016)
• Converted Supertex Doc# DSFP-VP2450 to
Microchip DS20005569A.
• Changed the “TO-243AA (SOT-89)” package to
“SOT-89.”
• Limited package options to TO-92 (1000/Bag) and
SOT-89 (2000/Reel).
• Made minor text changes throughout the docu-
ment.
DS20005569A-page 11
2016 Microchip Technology Inc.
VP2450
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
Examples:
XX
PART NO.
Device
-
X
-
X
a) VP2450N3-G:
P-Channel Enhancement-Mode
Vertical DMOS FET, 3-lead
TO-92 Package, 1000/Bag
Package
Options
Environmental
Media Type
b) VP2450N8-G:
P-Channel Enhancement-Mode
Vertical DMOS FET, 3-lead
SOT-89 Package, 2000/Reel
Device:
VP2450
=
P-Channel Enhancement-Mode Vertical
DMOS FET
Packages:
N3
N8
=
=
3-lead TO-92
3-lead SOT-89
Environmental:
Media Type:
G
=
=
Lead (Pb)-free/RoHS-compliant Package
(Blank)
1000/Bag for an N3 Package
2000/Reel for an N8 Package
2016 Microchip Technology Inc.
DS20005569A-page 12
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
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suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
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are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
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ETHERSYNCH, Hyper Speed Control, HyperLight Load,
IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut,
BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
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EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip
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SQTP is a service mark of Microchip Technology Incorporated
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Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
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All other trademarks mentioned herein are property of their
respective companies.
QUALITYꢀMANAGEMENTꢀꢀSYSTEMꢀ
CERTIFIEDꢀBYꢀDNVꢀ
© 2016, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0991-5
== ISO/TSꢀ16949ꢀ==ꢀ
2016 Microchip Technology Inc.
DS20005569A-page 13
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06/23/16
DS20005569A-page 14
2016 Microchip Technology Inc.
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