ZL40219LDG1 [MICROCHIP]
Low Skew Clock Driver, 4000/14000/40000 Series, 16 True Output(s), 0 Inverted Output(s), CMOS;
| 型号： | ZL40219LDG1 |
| 厂家： | 
MICROCHIP |
| 描述： | Low Skew Clock Driver, 4000/14000/40000 Series, 16 True Output(s), 0 Inverted Output(s), CMOS 驱动 逻辑集成电路 |
| 文件： | 总23页 (文件大小：539K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ZL40219
Precision 1:8 LVDS Fanout Buffer
with On-Chip Input Termination
Data Sheet
April 2014
Features
Ordering Information
ZL40219LDG1 32 Pin QFN
Trays
Tape and Reel
Inputs/Outputs
ZL40219LDF1
32 Pin QFN
•
Accepts differential or single-ended input
LVPECL, LVDS, CML, HCSL, LVCMOS
Matte Tin
Package size: 5 x 5 mm
•
-40oC to +85oC
•
On-chip input termination and biasing for AC
coupled inputs
•
•
Eight precision LVDS outputs
Applications
Operating frequency up to 750 MHz
•
•
•
•
•
General purpose clock distribution
Low jitter clock trees
Power
•
•
•
Options for 2.5 V or 3.3 V power supply
Logic translation
Current consumption of 112 mA
Clock and data signal restoration
On-chip Low Drop Out (LDO) Regulator for superior
power supply rejection
Wired communications: OTN, SONET/SDH, GE,
10 GE, FC and 10G FC
Performance
•
•
•
PCI Express generation 1/2/3 clock distribution
Wireless communications
•
Ultra low additive jitter of 135 fs RMS
High performance microprocessor clock
distribution
out0_p
out0_n
out1_p
out1_n
out2_p
out2_n
ctrl
vt
Termination
and Bias
out3_p
out3_n
clk_p
clk_n
Buffer
out4_p
out4_n
out5_p
out5_n
out6_p
out6_n
out7_p
out7_n
Figure 1 - Functional Block Diagram
1
Microsemi Corporation
Copyright 2014, Microsemi Corporation. All Rights Reserved.
ZL40219
Data Sheet
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Change Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.0 Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Clock Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 Device Additive Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.1 Sensitivity to power supply noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.2 Power supply filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.3 PCB layout considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.0 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.0 Performance Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.0 Typical Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.0 Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.0 Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2
Microsemi Corporation
ZL40219
Data Sheet
List of Figures
Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3 - Simplified Diagram of Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4 - Clock Input - LVPECL - DC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5 - Clock Input - LVPECL - AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6 - Clock Input - LVDS - DC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7 - Clock Input - LVDS - AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8 - Clock Input - CML- AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9 - Clock Input - HCSL- AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 10 - Clock Input - AC-coupled Single-Ended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 11 - Clock Input - DC-coupled 3.3V CMOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 12 - Simplified LVDS Output Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 13 - LVDS DC Coupled Termination (Internal Receiver Termination) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 14 - LVDS DC Coupled Termination (External Receiver Termination) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 15 - LVDS AC Coupled Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 16 - LVDS AC Output Termination for CML Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 17 - Additive Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 18 - Decoupling Connections for Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 19 - Differential Output Voltage Parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 20 - Input To Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3
Microsemi Corporation
ZL40219
Data Sheet
Change Summary
Below are the changes from the February 2013 issue to the April 2014 issue:
Page
Item
Change
Added PCI Express clock distribution.
Added exposed pad to Pin Description.
1
6
8
Applications
Pin Description
Figure 4 and Figure 5
Removed 22 Ohm series resistors from Figure 4 and 5. These
resistors are not required; however there is no impact to
performance if the resistors are included.
16
18
Power supply filtering
Figure 19
Corrected typo of 0.3 ohm to 0.15 ohm.
Clarification of V and V
.
OD
ID
Below are the changes from the November 2012 issue to the February 2013 issue:
Page
Item
Change
8
Figure 4
Changed text to indicate the circuit is not recommended for
VDD_driver=2.5V.
12
Figure 12
Changed gate values to +/+ on the left and -/- on the right.
4
Microsemi Corporation
ZL40219
Data Sheet
1.0 Package Description
The device is packaged in a 32 pin QFN
24
22
20
18
16
out5_p
out5_n
out6_p
out6_n
out7_p
out7_n
NC
out2_n
out2_p
out1_n
out1_p
out0_n
out0_p
NC
26
14
12
28
30
32
gnd (E-pad)
10
vdd
vdd
2
4
6
8
Figure 2 - Pin Connections
5
Microsemi Corporation
ZL40219
Data Sheet
2.0 Pin Description
Pin #
Name
Description
3, 6
clk_p, clk_n, Differential Input (Analog Input). Differential (or single ended) input signals.
For single-ended inputs see See “Clock Inputs” on page 7
30, 29, out0_p, out0_n Differential Output (Analog Output). Differential outputs.
28, 27, out1_p, out1_n
26, 25, out2_p, out2_n
24, 23, out3_p, out3_n
18, 17, out4_p, out4_n
16, 15, out5_p, out5_n
14, 13, out6_p, out6_n
12, 11 out7_p, out7_n
9, 19,
vdd
Positive Supply Voltage. 2.5 V or 3.3 V nominal.
DC DC
22, 32
1, 8
vdd_core
gnd
Positive Supply Voltage. 2.5 V or 3.3 V nominal.
DC DC
2, 7,
Ground. 0 V.
20, 21
4
5
vt
On-Chip Input Termination Node (Analog). Center tap between internal 50 Ohm
termination resistors.
The use of this pin is detailed in section “Clock Inputs” on page 7, for various input signal
types.
ctrl
Digital Control for On-Chip Input Termination (Input). Selects differential input mode;
0: DC coupled LVPECL or LVDS modes
1: AC coupled differential modes
This pin is internally pulled down to GND. The use of this pin is detailed in section “Clock
Inputs” on page 7, for various input signal types.
10, 31
NC
No Connection. Leave unconnected.
Device GND.
Exposed Pad
6
Microsemi Corporation
ZL40219
Data Sheet
3.0 Functional Description
he ZL40219 is an LVDS clock fanout buffer with eight output clock drivers capable of operating at frequencies up to
750MHz.
The ZL40219 provides an internal input termination network for DC and AC coupled inputs; optional input biasing
for AC coupled inputs is also provided. The ZL40219 can accept DC coupled LVPECL or LVDS and AC coupled
LVPECL and LVDS input signals, AC coupled CML or HCSL input signals, and single ended signals. A pin
compatible device with external termination is also available.
The ZL40219 is designed to fan out low-jitter reference clocks for wired or optical communications applications
while adding minimal jitter to the clock signal. An internal linear power supply regulator and bulk capacitors
minimize additive jitter due to power supply noise. The device operates from 2.5V+/-5% or 3.3V+/-5% supply. Its
operation is guaranteed over the industrial temperature range -40°C to +85°C.
The device block diagram is shown in Figure 1; its operation is described in the following sections.
3.1 Clock Inputs
The device has a differential input equipped with two on-chip 50 Ohm termination resistors arranged in series with a
center tap. The input can accept many differential and single-ended signals with AC or DC coupling as appropriate.
A control pin is available to enable internal biasing for AC coupled inputs. A block diagram of the input stage is in
Figure 3.
clk_p
50
Receiver
50
clk_n
Vt
Bias
ctrl
Figure 3 - Simplified Diagram of Input Stage
This following figures give the components values and configuration for the various circuits compatible with the
input stage and the use of the Vt and ctrl pins in each case.
In the following diagrams where the ctrl pin is logically one and the Vt pin is not connected, the Vt pin can be
instead connected to VDD with a capacitor. A capacitor can also help in Figure 4 between Vt and VDD. This
capacitor will minimize the noise at the point between the two internal termination resistors and improve the overall
performance of the device.
7
Microsemi Corporation
ZL40219
Data Sheet
VDD_driver
VDD
Zo = 50 Ohms
clk_p
LVPECL
Driver
clk_n
Vt
Zo = 50 Ohms
Ctrl
“0”
R
For 3.3V R=50 ohms
Not recommended for VDD_driver=2.5V
Figure 4 - Clock Input - LVPECL - DC Coupled
VDD_driver
VDD
Zo = 50 Ohms
Zo = 50 Ohms
clk_p
LVPECL
Driver
clk_n
Vt
NC
“1”
R
R
Ctrl
For 3.3V: R=150 ohms
For 2.5V: R=85 ohms
Figure 5 - Clock Input - LVPECL - AC Coupled
8
Microsemi Corporation
ZL40219
Data Sheet
VDD_driver
VDD
Zo = 50 Ohms
clk_p
LVDS
Driver
clk_n
Vt
Zo = 50 Ohms
NC
Ctrl
“0”
Figure 6 - Clock Input - LVDS - DC Coupled
VDD_driver
VDD
Zo = 50 Ohms
clk_p
LVDS
Driver
R
clk_n
Vt
Zo = 50 Ohms
NC
Ctrl
“1”
For VDD_driver = 3.3 V: R= 900 Ohms
For VDD_driver = 2.5 V: R = 680 Ohms
Figure 7 - Clock Input - LVDS - AC Coupled
9
Microsemi Corporation
ZL40219
Data Sheet
VDD_driver
VDD
R
R
Zo = 50 Ohms
clk_p
CML
Driver
clk_n
Vt
Zo = 50 Ohms
NC
Ctrl
“1”
R= 50 Ohms
Figure 8 - Clock Input - CML- AC Coupled
VDD_driver
VDD
Zo = 50 Ohms
clk_p
HCSL
Driver
clk_n
Vt
Zo = 50 Ohms
NC
R
R
Ctrl
“1”
R= 50 Ohms
Figure 9 - Clock Input - HCSL- AC Coupled
10
Microsemi Corporation
ZL40219
Data Sheet
VDD_driver
VDD
CMOS
Driver
Zo = 50 Ohms
clk_p
clk_n
Vt
Ctrl
“1”
Figure 10 - Clock Input - AC-coupled Single-Ended
VDD_driver
VDD
CMOS
Driver
Zo = 50 Ohms
clk_p
clk_n
Vt
NC
Ctrl
“1”
Figure 11 - Clock Input - DC-coupled 3.3V CMOS
11
Microsemi Corporation
ZL40219
Data Sheet
3.2 Clock Outputs
LVDS has lower signal swing than LVPECL which results in a low power consumption. A simplified diagram for the
LVDS output stage is shown in Figure 12.
VDD
3 mA
+
+
‐
‐
Output
Figure 12 - Simplified LVDS Output Driver
The methods to terminate the ZL40219 drivers are shown in the following figures.
VDD_Rx
VDD
ZL40219
Zo = 50 Ohms
clk_p
LVDS
Receiver
clk_n
Zo = 50 Ohms
Figure 13 - LVDS DC Coupled Termination (Internal Receiver Termination)
12
Microsemi Corporation
ZL40219
Data Sheet
VDD_Rx
VDD
ZL40219
Zo = 50 Ohms
Zo = 50 Ohms
clk_p
LVDS
Receiver
100 Ohms
clk_n
Figure 14 - LVDS DC Coupled Termination (External Receiver Termination)
VDD_Rx
VDD_Rx
VDD
R1
R1
ZL40219
Zo = 50 Ohms
Zo = 50 Ohms
clk_p
LVDS
Receiver
100 Ohms
R2
clk_n
R2
Note: R1 and R2 values and need for external termination
depend on the specification of the LVDS receiver
Figure 15 - LVDS AC Coupled Termination
13
Microsemi Corporation
ZL40219
Data Sheet
VDD_Rx
VDD
50 Ohms
50 Ohms
ZL40219
Zo = 50 Ohms
clk_p
CML
Receiver
clk_n
Zo = 50 Ohms
Figure 16 - LVDS AC Output Termination for CML Inputs
14
Microsemi Corporation
ZL40219
Data Sheet
3.3 Device Additive Jitter
The ZL40219 clock fanout buffer is not intended to filter clock jitter. The jitter performance of this type of device is
characterized by its additive jitter. Additive jitter is the jitter the device would add to a hypothetical jitter-free clock as
it passes through the device. The additive jitter of the ZL40219 is random and as such it is not correlated to the jitter
of the input clock signal.
The square of the resultant random RMS jitter at the output of the ZL40219 is equal to the sum of the squares of the
various random RMS jitter sources including: input clock jitter; additive jitter of the buffer; and additive jitter due to
power supply noise. There may be additional deterministic jitter sources, but they are not shown in Figure 17.
2
2
Jadd
Jps
2
2
Jout2= Jin +Jadd2+Jps
2
Jin
+
+
Jin
Jadd
Jps
= Random input clock jitter (RMS)
= Additive jitter due to the device (RMS)
= Additive jitter due to power supply noise (RMS)
= Resultant random output clock jitter (RMS)
Jout
Figure 17 - Additive Jitter
15
Microsemi Corporation
ZL40219
Data Sheet
3.4 Power Supply
This device operates employing either a 2.5V supply or 3.3V supply.
3.4.1 Sensitivity to power supply noise
Power supply noise from sources such as switching power supplies and high-power digital components such as
FPGAs can induce additive jitter on clock buffer outputs. The ZL40219 is equipped with an on-chip linear power
regulator and on-chip bulk capacitors to minimize additive jitter due to power supply noise. The on-chip regulation,
recommended power supply filtering, and good PCB layout all work together to minimize the additive jitter from
power supply noise.
3.4.2 Power supply filtering
Jitter levels may increase when noise is present on the power pins. For optimal jitter performance, the device
should be isolated from the power planes connected to its power supply pins as shown in Figure •.
•
•
•
•
10 µF capacitors should be size 0603 or size 0805 X5R or X7R ceramic, 6.3 V minimum rating
0.1 µF capacitors should be size 0402 X5R ceramic, 6.3 V minimum rating
Capacitors should be placed next to the connected device power pins
A 0.15 ohm resistor is recommended
1
vdd_core
0.1 µF
8
0.1 µF
0.15 Ω
ZL40219
9
vdd
10 µF
19
0.1 µF
22
0.1 µF
32
10 µF
Figure 18 - Decoupling Connections for Power Pins
3.4.3 PCB layout considerations
The power nets in Figure 18 can be implemented either as a plane island or routed power topology without effect
overall jitter performance of the device.
16
Microsemi Corporation
ZL40219
4.0 AC and DC Electrical Characteristics
Data Sheet
Absolute Maximum Ratings*
Parameter
Sym.
Min.
Max.
4.6
Units
1
2
3
4
5
6
7
Supply voltage
VDD_R
-0.5
-0.5
V
Voltage on any digital pin
Soldering temperature
Storage temperature
Junction temperature
Voltage on input pin
V
V
V
PIN
DD
T
260
°C
°C
°C
V
T
-55
125
125
ST
T
j
V
V
DD
input
Input capacitance each pin
C
500
fF
p
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
* Voltages are with respect to ground (GND) unless otherwise stated
Recommended Operating Conditions*
Characteristics
Sym.
Min.
Typ.
Max.
Units
1
2
3
Supply voltage 2.5 V mode
Supply voltage 3.3 V mode
Operating temperature
VDD25
VDD33
TA
2.375
3.135
-40
2.5
3.3
25
2.625
3.465
85
V
V
°C
* Voltages are with respect to ground (GND) unless otherwise stated
DC Electrical Characteristics - Current Consumption
Characteristics
Sym.
Min. Typ. Max. Units
Notes
Notes
1
Supply current LVDS drivers - loaded
(all outputs are active)
Idd_load
112
mA
DC Electrical Characteristics - Inputs and Outputs - for 2.5/3.3 V Supply
Characteristics
Sym.
Min.
Typ.
Max.
Units
1
2
3
CMOS control logic high-level input
CMOS control logic low-level input
VCIH
VCIL
IIL
0.7*V
V
V
DD
0.3*V
DD
CMOS control logic Input leakage
current
1
µA
V = V or 0 V
I DD
4
5
Differential input common mode
voltage
VICM
VICM
1.1
1.1
1.6
2.0
1
V
V
for 2.5 V
for 3.3 V
Differential input common mode
voltage
6
7
8
9
Differential input voltage difference
Differential input resistance
VID
VIR
0.25
80
V
ohm
V
100
0.30
1.25
120
0.40
LVDS output differential voltage*
LVDS Common Mode voltage
VOD
VCM
0.25
1.1
1.375
V
* The VOD parameter was measured between 125 and 750 MHz
17
Microsemi Corporation
ZL40219
Data Sheet
clk_p
outx_p
VID
VOD
clk_n
GND
outx_n
GND
VICM
VCM
outx_p – outx_n
clk_p – clk_n
0
0
2*VID
2*VOD
Figure 19 - Differential Output Voltage Parameter
AC Electrical Characteristics* - Inputs and Outputs (see Figure 20) - for 2.5/3.3 V Supply.
Characteristics
Sym.
1/t
Min.
Typ.
Max.
Units
Notes
1
2
3
4
5
6
Maximum Operating Frequency
Input to output clock propagation delay
Output to output skew
750
2
MHz
ns
p
t
0
1
80
120
0
pd
t
150
300
5
ps
out2out
Part to part output skew
t
ps
part2part
Output clock Duty Cycle degradation
LVDS Output slew rate
t
/ t
-5
Percent
V/ns
PWH PWL
r
0.55
SL
* Supply voltage and operating temperature are as per Recommended Operating Conditions
t
P
t
t
PWL
PWH
Input
t
pd
Output
Figure 20 - Input To Output Timing
18
Microsemi Corporation
ZL40219
Data Sheet
5.0 Performance Characterization
Additive Jitter at 2.5 V*
Jitter
Measurement
Filter
Typical
Output Frequency (MHz)
Notes
RMS (fs)
1
2
3
4
5
6
7
125
12 kHz - 20 MHz
184
174
157
152
139
138
135
212.5
311.04
425
12 kHz - 20 MHz
12 kHz - 20 MHz
12 kHz - 20 MHz
12 kHz - 20 MHz
12 kHz - 20 MHz
12 kHz - 20 MHz
500
622.08
750
*The values in this table were taken with an approximate slew rate of 0.8 V/ns.
Additive Jitter at 3.3 V*
Jitter
Measurement
Filter
Typical
Output Frequency (MHz)
Notes
RMS (fs)
1
2
3
4
5
6
7
125
12 kHz - 20 MHz
187
176
156
153
140
139
137
212.5
311.04
425
12 kHz - 20 MHz
12 kHz - 20 MHz
12 kHz - 20 MHz
12 kHz - 20 MHz
12 kHz - 20 MHz
12 kHz - 20 MHz
500
622.08
750
*The values in this table were taken with an approximate slew rate of 0.8 V/ns.
Additive Jitter from a Power Supply Tone*
Carrier frequency
Parameter
Typical
Units
Notes
125MHz
750MHz
25 mV at 100 kHz
25 mV at 100 kHz
33
33
fs RMS
fs RMS
* The values in this table are the additive periodic jitter caused by an interfering tone typically caused by a switching power supply. For this test,
measurements were taken over the full temperature and voltage range for VDD = 3.3 V. The magnitude of the interfering tone is measured at the
DUT.
19
Microsemi Corporation
ZL40219
Data Sheet
6.0 Typical Behavior
0.35
0.2
0.15
0.1
0.34
0.33
0.32
0.31
0.3
0.05
0
-0.05
-0.1
-0.15
-0.2
0
5
10
15
20
0
100
200
300
400
500
600
700
800
Time (ns)
Frequency (MHz)
Typical Waveform at 155.52 MHz
VOD vs Frequency
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-60
125 MHz
212.5 MHz
-65
425 MHz
750 MHz
-70
-75
-80
-85
-90
125 MHz
212.5 MHz
425 MHz
750 MHz
20
30
40
50
60
70
80
90
100
100
150
200
250
300
350
400
450
500
Tone Magnitude (mV)
Tone Frequency (kHz)
Power Supply Tone Frequency versus PSRR
Power Supply Tone Magnitude versus PSRR
0.9
0.85
0.8
0.75
0.7
0.65
0.6
-40
-20
0
20
40
60
80
100
Temperature ( C)
Propagation Delay versus Temperature
Note: This is for a single device. For more details, see the
characterization section.
20
Microsemi Corporation
ZL40219
Data Sheet
7.0 Package Characteristics
Thermal Data
Parameter
Symbol
Test Condition
Value
Unit
Junction to Ambient Thermal Resistance
ΘJA
Still Air
1 m/s
2 m/s
37.4
33.1
31.5
oC/W
Junction to Case Thermal Resistance
Junction to Board Thermal Resistance
Maximum Junction Temperature*
Maximum Ambient Temperature
ΘJC
ΘJB
Tjmax
TA
24.4
19.5
125
85
oC/W
oC/W
oC
oC
21
Microsemi Corporation
ZL40219
Data Sheet
8.0 Mechanical Drawing
22
Microsemi Corporation
Information relating to products and services furnished herein by Microsemi Corporation or its subsidiaries (collectively “Microsemi”) is
believed to be reliable. However, Microsemi assumes no liability for errors that may appear in this publication, or for liability otherwise
arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual
property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase
of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by
Microsemi or licensed from third parties by Microsemi, whatsoever. Purchasers of products are also hereby notified that the use of
product in certain ways or in combination with Microsemi, or non-Microsemi furnished goods or services may infringe patents or other
intellectual property rights owned by Microsemi.
This publication is issued to provide information only and (unless agreed by Microsemi in writing) may not be used, applied or
reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or
services concerned. The products, their specifications, services and other information appearing in this publication are subject to
change by Microsemi without notice. No warranty or guarantee express or implied is made regarding the capability, performance or
suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not
constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to
fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used
is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These
products are not suitable for use in any medical and other products whose failure to perform may result in significant injury or death to
the user. All products and materials are sold and services provided subject to Microsemi’s conditions of sale which are available on
request.
For more information about all Microsemi products
visit our website at
www.microsemi.com
TECHNICAL DOCUMENTATION – NOT FOR RESALE
Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor
and system solutions for communications, defense and security, aerospace and industrial
markets. Products include high-performance and radiation-hardened analog mixed-signal
integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and
synchronization devices and precise time solutions, setting the world’s standard for time; voice
processing devices; RF solutions; discrete components; security technologies and scalable
anti-tamper products; Power-over-Ethernet ICs and midspans; as well as custom design
capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif. and has
approximately 3,400 employees globally. Learn more at www.microsemi.com.
Microsemi Corporate Headquarters One
One Enterprise, Aliso Viejo CA 92656 USA
Within the USA: +1 (800) 713-4113
Outside the USA: +1 (949) 380-6100
Sales: +1 (949) 380-6136
© 2014 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of
Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.
Fax: +1 (949) 215-4996
E-mail: sales.support@microsemi.com
ZL40219
相关型号：
ZL40272
Low-Skew, Low Additive Jitter, 12 Output HCSL/LVDS/ LVPECL Fanout Buffer with Per-Output Enable Control
MICROCHIP
ZL40272LDF1
Low-Skew, Low Additive Jitter, 12 Output HCSL/LVDS/ LVPECL Fanout Buffer with Per-Output Enable Control
MICROCHIP
ZL40272LDG1
Low-Skew, Low Additive Jitter, 12 Output HCSL/LVDS/ LVPECL Fanout Buffer with Per-Output Enable Control
MICROCHIP
©2020 ICPDF网 联系我们和版权申明