MT48V4M32LFFC_技术文档

ADVANCE^‡

128Mb: x16, x32

MOBILE SDRAM

MT48LC8M16LFFF, MT48V8M16LFFF – 2 Meg x 16 x 4 banks

MT48LC4M32LFFC , MT48V4M32LFFC – 1 Meg x 32 x 4 banks

SYNCHRONOUS

DRAM

For the latest data sheet revisions, please refer to the Micron Web

site: www.micron.com/dramds

FEATURES

•

Temperature Compensated Self Refresh (TCSR)

Fully synchronous; all signals registered on positive

edge of system clock

Internal pipelined operation; column address can be

changed every clock cycle

PIN ASSIGNMENT (Top View)

54-Ball VFBGA

•

Internal banks for hiding row access/precharge

Programmable burst lengths: 1, 2, 4, 8, or full page

Auto Precharge, includes CONCURRENT AUTO

PRECHARGE, and Auto Refresh Modes

Self Refresh Mode; standard and low power

64ms, 4,096-cycle refresh

LVTTL-compatible inputs and outputs

Low voltage power supply

Partial Array Self Refresh power-saving mode

1

2

3

4

5

6

7

8

9

A

B

C

D

E

V

SS

DQ14

DQ12

DQ10

DQ8

DQ15

V

SS

Q

V

DDQ

DQ0

VDD

DQ13

DQ11

DQ9

NC

V

DD

Q

VSSQ

DQ2

DQ4

DQ6

LDQM

RAS#

BA1

A1

DQ1

DQ3

DQ5

DQ7

WE#

CS#

•

V

SS

Q

VDDQ

V

DD

Q

VSSQ

V

SS

VDD

•

Operating Temperature Range

Industrial (-40^oC to +85^oC)

UDQM

NC/A12

A8

CLK

A11

A7

CKE

A9

CAS#

BA0

A0

F

G

H

J

OPTIONS

•

MARKING

VDD/VDDQ

A6

A10

3.3V/3.3V

2.5V/2.5V or 1.8V

LC

V

SS

A5

A4

A3

A2

VDD

•

Configurations

8 Meg x 16 (2 Meg x 16 x 4 banks)

4 Meg x 32 (1 Meg x 32 x 4 banks)

8M16

4M32

Top View

(Ball Down)

•

Package/Ball out

Plastic Package

54-ball FBGA (8mm x 9mm)(x16 only)

90-ball FBGA (11mm x 13mm)

8 Meg x 16

4 Meg x 32

FF¹

FC¹

Configuration

Refresh Count

2 Meg x 16 x 4 banks 1 Meg x 32 x 4 banks

4K

Row Addressing

Bank Addressing

Column Addressing

4K (A0–A11)

4 (BA0, BA1)

512 (A0–A8)

4K (A0–A11)

4 (BA0, BA1)

256 (A0–A7)

Timing (Cycle Time)

8ns @ CL = 3 (125 MHz)

10ns @ CL = 3 (100 MHz)

-8

-10

Part Number Example:

KEY TIMING PARAMETERS

MT48V8M16LFFC-8

^tRCD ^tRP

NOTE: 1. See page 61 for FBGA/VFBGA Device Marking

SPEED

CLOCK

ACCESS TIME

Table.

GRADE FREQUENCY CL=1* CL=2* CL=3*

-8

-10

-8

125 MHz

100 MHz

83 MHz

50 MHz

40 MHz

–

7ns

–

20ns 20ns

–

8ns

–

-10

-8

–

19ns

22ns

–

-10

–

*CL = CAS (READ) latency

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1

^‡PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PUROPOSES ONLY AND ARE SUBJECT TO CHANGE BY

MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION AND DATA SHEET SPECIFICATIONS.

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

90-Ball FBGA PIN ASSIGNMENT

(Top View)

1

2

3

4

5

6

7

8

9

A

B

C

D

E

DQ26 DQ24

V

SS

V

DD

DQ23

DQ21

DQ19

DQ28

V

DDQ

V

SS

Q

VDD

Q

VSSQ

V

SS

Q

DQ27 DQ25

DQ29 DQ30

DQ22

DQ17

NC

DQ20

DQ18

DQ16

DQM2

A0

V

DD

Q

V

SS

DD

V

DD

Q

DQ31

DQM3

A5

NC

A3

A6

NC

A9

NC

VSSQ

F

V

SS

A2

VDD

G

H

J

A4

A7

A10

NC

A1

A8

BA1

A11

RAS#

DQM0

CLK

CKE

BA0

CAS#

CS#

K

L

DQM1

NC

WE#

DQ7

DQ5

DQ3

V

DD

Q

DQ8

DQ10

V

SS

V

DD

VSSQ

M

N

P

V

SS

Q

DQ9

DQ6

DQ1

V

DD

Q

V

SS

DQ12 DQ14

DD

DQ11

V

DDQ

VSS

Q

V

DD

Q

V

SSQ

DQ4

DQ2

R

DQ13 DQ15

V

SS

V

DD

DQ0

Ball and Array

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

2

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

128Mb SDRAM PART NUMBERS

PART NUMBER

VDD/VDDQ

ARCHITECTURE

8 Meg x 16

4 Meg x 32

PACKAGE

54-BALL VFBGA

90-BALL FBGA

MT48LC8M16LFFF-xx

MT48V8M16LFFF-xx

MT48LC4M32LFFC-xx

MT48V4M32LFFC-xx

3.3V / 3.3V

2.5V / 2.5V-1.8V

3.3V / 3.3V

2.5V / 2.5V-1.8V

GENERAL DESCRIPTION

®

The Micron 128Mb SDRAM is a high-speed CMOS,

dynamicrandom-accessmemorycontaining134,217,728

bits. It is internally configured as a quad-bank DRAM

withasynchronousinterface(allsignalsareregisteredon

the positive edge of the clock signal, CLK). Each of the

x16’s 33,554,432-bit banks is organized as 4,096 rows by

512 columns by 16 bits. Each of the x32’s 33,554,432-bit

banks is organized as 4,096 rows by 256 columns by 32

bits.

precharge that is initiated at the end of the burst se-

quence.

The 128Mb SDRAM uses an internal pipelined

architecture to achieve high-speed operation. This

architecture is compatible with the 2n rule of prefetch

architectures, but it also allows the column address to be

changed on every clock cycle to achieve a high-speed,

fully random access. Precharging one bank while access-

ing one of the other three banks will hide the precharge

cycles and provide seamless high-speed, random-access

operation.

The 128Mb SDRAM is designed to operate in 3.3V or

2.5V, low-power memory systems. An auto refresh mode

is provided, along with a power-saving, power-down

mode. All inputs and outputs are LVTTL-compatible.

SDRAMs offer substantial advances in DRAM operat-

ing performance, including the ability to synchronously

burst data at a high data rate with automatic column-

address generation, the ability to interleave between in-

ternal banks in order to hide precharge time and the

capabilitytorandomlychangecolumnaddressesoneach

clock cycle during a burst access.

Read and write accesses to the SDRAM are burst ori-

ented; accesses start at a selected location and continue

for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an AC-

TIVE command, which is then followed by a READ or

WRITE command. The address bits registered coinci-

dent with the ACTIVE command are used to select the

bank and row to be accessed (BA0, BA1 select the bank;

A0-A11 select the row). The address bits registered coin-

cident with the READ or WRITE command are used to

select the starting column location for the burst access.

The SDRAM provides for programmable READ or

WRITE burst lengths of 1, 2, 4, or 8 locations, or the full

page, with a burst terminate option. An auto precharge

function may be enabled to provide a self-timed row

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

3

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

TABLE OF CONTENTS

Functional Block Diagram – 8 Meg x 16 ................

Functional Block Diagram – 4 Meg x 32 ................

54-Ball Pin Descriptions .........................................

90-Ball Pin Descriptions .........................................

5

6

7

8

Truth Table 2 (CKE) ................................................ 30

Truth Table 3 (Current State, Same Bank) ..................... 31

Truth Table 4 (Current State, Different Bank) ................. 33

Absolute Maximum Ratings ................................... 35

DC Electrical Characteristics

Functional Description .........................................

Initialization ......................................................

Register Definition ............................................

mode register ................................................

Burst Length............................................

9

and Operating Conditions ................................... 35

AC Electrical Characteristics and Recommended

Operating Conditions (Timing Table) ............. 36

AC Functional Characteristics ................................ 37

IDD Specifications and Conditions ......................... 37

Capacitance ............................................................ 38

Burst Type ............................................... 10

CAS Latency ............................................ 11

Operating Mode ...................................... 11

Extended Mode Register ......................... 12

Timing Waveforms

Initialize and Load mode register...................... 40

Power-Down Mode ............................................ 41

Clock Suspend Mode ......................................... 42

Auto Refresh Mode ............................................ 43

Self Refresh Mode .............................................. 44

Reads

Read – Without Auto Precharge ................... 45

Read – With Auto Precharge ........................ 46

Single Read – Without Auto Precharge ........ 47

Single Read – With Auto Precharge ............. 48

Alternating Bank Read Accesses ................... 49

Read – Full-Page Burst .................................. 50

Read – DQM Operation ................................ 51

Writes

Temperature Compensated Self Refresh . 12

Partial Array Self Refresh......................... 13

Commands ............................................................. 14

Truth Table 1 (Commands and DQM Operation) ............ 14

Command Inhibit ............................................. 15

No Operation (NOP).......................................... 15

Load mode register ............................................ 15

Active ................................................................ 15

Read ................................................................ 15

Write ................................................................ 15

Precharge ........................................................... 15

Auto Precharge .................................................. 15

Burst Terminate ................................................. 15

Auto Refresh ...................................................... 16

Self Refresh ........................................................ 16

Operation................................................................ 17

Bank/Row Activation ........................................ 17

Reads ................................................................ 18

Writes ................................................................ 24

Precharge ........................................................... 26

Concurrent Auto Precharge .............................. 28

Power-Down ...................................................... 26

Clock Suspend ................................................... 27

Burst Read/Single Write .................................... 27

Write – Without Auto Precharge ................. 52

Write – With Auto Precharge ....................... 53

Single Write – Without Auto Precharge....... 54

Single Write – With Auto Precharge ............ 55

Alternating Bank Write Accesses ................. 56

Write – Full-Page Burst ................................. 57

Write – DQM Operation .............................. 58

54-Ball VFBGA Drawing ............................... 59

90-Ball FBGA Drawing ................................. 60

FBGA/VFBGA Device Marking ..................... 61

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

FUNCTIONAL BLOCK DIAGRAM

8 Meg x16 SDRAM

BA1

BA0

0

1

0

1

Bank

0

1

0

1

2

3

CKE

CLK

CONTROL

LOGIC

CS#

WE#

BANK3

CAS#

RAS#

BANK2

BANK1

REFRESH

COUNTER

12

MODE REGISTER

12

BANK0

ROW-

ADDRESS

LATCH

&

ROW-

ADDRESS

MUX

12

BANK0

MEMORY

ARRAY

2

4096

DQML,

DQMH

12

(4,096 x 512 x 16)

DECODER

DATA

OUTPUT

REGISTER

SENSE AMPLIFIERS

4096

16

DQ0-

DQ15

I/O GATING

2

16

DQM MASK LOGIC

READ DATA LATCH

WRITE DRIVERS

BANK

CONTROL

LOGIC

A0-A11,

BA0, BA1

ADDRESS

REGISTER

14

DATA

INPUT

REGISTER

2

16

512

(x16)

COLUMN

DECODER

COLUMN-

ADDRESS

COUNTER/

LATCH

9

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

5

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

FUNCTIONAL BLOCK DIAGRAM

4 Meg x 32 SDRAM

BA1

0

1

BA0

0

1

0

1

Bank

0

1

2

3

CKE

CLK

CONTROL

LOGIC

CS#

WE#

BANK3

CAS#

RAS#

BANK2

BANK1

BANK0

REFRESH

COUNTER

12

MODE REGISTER

12

BANK0

ROW-

ADDRESS

LATCH

&

ROW-

ADDRESS

MUX

12

BANK0

MEMORY

ARRAY

4

4096

DQM0–

DQM3

12

(4,096 x 256 x 32)

DECODER

DATA

OUTPUT

REGISTER

SENSE AMPLIFIERS

8192

32

DQ0–

DQ31

I/O GATING

2

32

DQM MASK LOGIC

READ DATA LATCH

WRITE DRIVERS

BANK

CONTROL

LOGIC

A0–A11,

BA0, BA1

ADDRESS

REGISTER

14

DATA

INPUT

REGISTER

2

32

256

(x32)

COLUMN

DECODER

COLUMN-

ADDRESS

COUNTER/

LATCH

8

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

6

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

BALL DESCRIPTIONS

54-BALL VFBGA

SYMBOL

TYPE

DESCRIPTION

F2

CLK

Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled

on the positive edge of CLK. CLK also increments the internal burst counter

and controls the output registers.

F3

CKE

Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.

Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH

operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or

CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous

except after the device enters power-down and self refresh modes, where

CKE becomes asynchronous until after exiting the same mode. The input

buffers, including CLK, are disabled during power-down and self refresh

modes, providing low standby power. CKE may be tied HIGH.

G9

CS#

Input Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the

command decoder. All commands are masked when CS# is registered HIGH.

CS# provides for external bank selection on systems with multiple banks. CS#

is considered part of the command code.

F7, F8, F9

E8, F1

CAS#, RAS#,

WE#

Input Command Inputs: CAS#, RAS#, and WE# (along with CS#) define the

command being entered.

LDQM,

UDQM

Input Input/Output Mask: DQM is sampled HIGH and is an input mask signal for

write accesses and an output enable signal for read accesses. Input data is

masked during a WRITE cycle. The output buffers are placed in a High-Z state

(two-clock latency) when during a READ cycle. LDQM corresponds to DQ0–

DQ7, UDQM corresponds to DQ8–DQ15. LDQM and UDQM are considered

same state when referenced as DQM.

G7, G8

BA0, BA1

A0–A11

Input Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ,

WRITE or PRECHARGE command is being applied. These pins also provide the

op-code during a LOAD MODE REGISTER command

H7, H8, J8, J7, J3, J2,

H3, H2, H1, G3, H9, G2,

Input Address Inputs: A0–A11 are sampled during the ACTIVE command (row-

address A0–A11) and READ/WRITE command (column-address A0–A8; with

A10 defining auto precharge) to select one location out of the memory array

in the respective bank. A10 is sampled during a PRECHARGE command to

determine if all banks are to be precharged (A10 HIGH) or bank selected by

BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD

MODE REGISTER command.

A8, B9, B8, C9, C8, D9,

D8, E9, E1, D2, D1, C2,

C1, B2, B1, A2

DQ0–DQ15

I/O

Data Input/Output: Data bus

E2, G1

NC

–

No Connect: These pins should be left unconnected.

G1 is a no connect for this part but may be used as A12 in future designs.

A7, B3, C7, D3

VDDQ

Supply DQ Power: Isolated power on the die to improve noise immunity.

A3, B7, C3, D7,

A9, E7, J9

VSSQ

VDD

Supply DQ Ground: Isolated power on the die to improve noise immunity.

Supply Power Supply: Voltage dependant on option.

A1, E3, J1

V^SS

Supply Ground.

128Mb: x16, x32 Mobile SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

7

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

BALL DESCRIPTIONS

90-BALL FBGA

SYMBOL

TYPE

DESCRIPTION

J1

CLK

Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled

on the positive edge of CLK. CLK also increments the internal burst counter

and controls the output registers.

J2

CKE

Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.

Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH

operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or

CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous

except after the device enters power-down and self refresh modes, where

CKE becomes asynchronous until after exiting the same mode. The input

buffers, including CLK, are disabled during power-down and self refresh

modes, providing low standby power. CKE may be tied HIGH.

J8

CS#

Input Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the

command decoder. All commands are masked when CS# is registered HIGH.

CS# provides for external bank selection on systems with multiple banks. CS#

is considered part of the command code.

J9, K7, K8

RAS#, CAS#

WE#

Input Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the

command being entered.

K9, K1, F8, F2

DQM0–3

Input Input/Output Mask: DQM is sampled HIGH and is an input mask signal for

write accesses and an output enable signal for read accesses. Input data is

masked during a WRITE cycle. The output buffers are placed in a High-Z state

(two-clock latency) when during a READ cycle. DQM0 corresponds to DQ0–

DQ7, DQM1 corresponds to DQ8–DQ15, DQM2 corresponds to DQ16–DQ23

and DQM3 corresponds to DQ24–DQ31. DQM0-3 are considered same state

when referenced as DQM.

J7, H8

BA0, BA1

A0–A11

Input Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ,

WRITE or PRECHARGE command is being applied. These pins also provide the

op-code during a LOAD MODE REGISTER command

G8, G9, F7, F3, G1, G2,

G3, H1, H2, J3, G7, H9

Input Address Inputs: A0–A11 are sampled during the ACTIVE command (row-

address A0–A11) and READ/WRITE command (column-address A0–A7; with

A10 defining auto precharge) to select one location out of the memory array

in the respective bank. A10 is sampled during a PRECHARGE command to

determine if all banks are to be precharged (A10 HIGH) or bank selected by

BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD

MODE REGISTER command.

R8, N7, R9, N8, P9, M8,

M7, L8, L2, M3, M2, P1, N2,

R1, N3, R2, E8, D7, D8, B9,

C8, A9, C7, A8, A2, C3, A1,

C2, B1, D2, D3, E2

DQ0–DQ31

I/O

Data Input/Output: Data bus

E3, E7, H3, H7, K2, K3

NC

–

No Connect: These pins should be left unconnected.

H7 and H9 are not connects for this part but may be used as A12 and A11 in

future designs.

B2, B7, C9, D9, E1,

L1, M9, N9, P2, P7

V^DDQ

V^SSQ

Supply DQ Power: Isolated power on the die to improve noise immunity.

B8, B3, C1, D1, E9,

L9, M1, N1, P3, P8

Supply DQ Ground: Isolated power on the die to improve noise immunity.

A7, F9, L7, R7

A3, F1, L3, R3

VDD

V^SS

Supply Power Supply: Voltage dependant on option.

Supply Ground.

128Mb: x16, x32 Mobile SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

8

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

FUNCTIONAL DESCRIPTION

Register Definition

In general, the 128Mb SDRAMs (2 Meg x16 x 4 banks

and 1 Meg x 32 x 4 banks) are quad-bank DRAMs that

operate at 3.3V or 2.5V and include a synchronous inter-

face (all signals are registered on the positive edge of the

clock signal, CLK). Each of the x16’s 33,554,432-bit banks

is organized as 4,096 rows by 512 columns by 16 bits.

Each of the x32’s 33,554,432-bit banks is organized as

4,096 rows by 256 columns by 32bits.

MODE REGISTER

In order to achieve low power consumption, there are

two mode registers in the Mobile component, Mode Reg-

isterandExtendedModeRegister. Forthissection, Mode

Register is referred to. Extended Mode register is dis-

cussedonpage12. Themoderegisterisusedtodefinethe

specific mode of operation of the SDRAM. This definition

includes the selection of a burst length, a burst type, a

CAS latency, an operating mode and a write burst mode,

as shown in Figure 1. The mode register is programmed

via the LOAD MODE REGISTER command and will retain

the stored information until it is programmed again or

the device loses power.

Mode Register bits M0-M2 specify the burst length,

M3 specifies the type of burst (sequential or interleaved),

M4-M6 specify the CAS latency, M7 and M8 specify the

operating mode, M9, M10, and M11 should be set to zero.

M12 and M13 should be set to zero to prevent extended

mode register.

Read and write accesses to the SDRAM are burst ori-

ented; accesses start at a selected location and continue

for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an AC-

TIVE command, which is then followed by a READ or

WRITEcommand. Theaddressbitsregisteredcoincident

with the ACTIVE command are used to select the bank

and row to be accessed (BA0 and BA1 select the bank, A0-

A11selecttherow). Theaddressbits(x16:A0-A8; x32:A0-

A7; ) registered coincident with the READ or WRITE com-

mand are used to select the starting column location for

the burst access.

The mode register must be loaded when all banks are

idle, and the controller must wait the specified time

before initiating the subsequent operation. Violating ei-

ther of these requirements will result in unspecified op-

eration.

Priortonormaloperation, theSDRAMmustbeinitial-

ized. The following sections provide detailed informa-

tion covering device initialization, register definition,

command descriptions and device operation.

Burst Length

Initialization

Read and write accesses to the SDRAM are burst ori-

ented, with the burst length being programmable, as

shown in Figure 1. The burst length determines the maxi-

mum number of column locations that can be accessed

for a given READ or WRITE command. Burst lengths of 1,

2, 4, or 8 locations are available for both the sequential

and the interleaved burst types, and a full-page burst is

available for the sequential type. The full-page burst is

used in conjunction with the BURST TERMINATE com-

mand to generate arbitrary burst lengths.

SDRAMs must be powered up and initialized in a

predefined manner. Operational procedures other than

those specified may result in undefined operation. Once

power is applied to VDD and VDDQ (simultaneously) and

the clock is stable (stable clock is defined as a signal

cycling within timing constraints specified for the clock

pin), the SDRAM requires a 100µs delay prior to issuing

anycommandotherthanaCOMMANDINHIBITorNOP.

Starting at some point during this 100µs period and con-

tinuing at least through the end of this period, COM-

MAND INHIBIT or NOP commands should be applied.

Once the 100µs delay has been satisfied with at least

one COMMAND INHIBIT or NOP command having been

applied, a PRECHARGE command should be applied. All

banks must then be precharged, thereby placing the

device in the all banks idle state.

Reserved states should not be used, as unknown op-

eration or incompatibility with future versions may re-

sult.

WhenaREADorWRITEcommandisissued, ablockof

columns equal to the burst length is effectively selected.

All accesses for that burst take place within this block,

meaning that the burst will wrap within the block if a

boundary is reached. The block is uniquely selected by

A1-A8 (x16) or A1-A7 (x32) when the burst length is set to

two; by A2-A8 (x16) or A2-A7 (x32) when the burst length

is set to four; and by A3-A8 (x16) or A3-A7 (x32) when the

burst length is set to eight. The remaining (least signifi-

cant) address bit(s) is (are) used to select the starting

location within the block. Full-page bursts wrap within

the page if the boundary is reached.

Once in the idle state, two AUTO REFRESH cycles

must be performed. After the AUTO REFRESH cycles are

complete, the SDRAM is ready for mode register pro-

gramming. Because the mode register will power up in an

unknown state, it should be loaded prior to applying any

operational command.

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

9

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

Burst Type

Accesses within a given burst may be programmed to

be either sequential or interleaved; this is referred to as

the burst type and is selected via bit M3.

The ordering of accesses within a burst is determined

by the burst length, the burst type and the starting col-

umn address, as shown in Table 1.

Table 1

Burst Definition

Burst

Length

Starting Column Order of Accesses Within a Burst

Address

Type = Sequential Type = Interleaved

A0

0

1

0-1

1-0

0-1

1-0

2

4

A1 A0

Figure 1

Mode Register Definition

0

1

0

1

0

1

0-1-2-3

1-2-3-0

2-3-0-1

3-0-1-2

0-1-2-3

1-0-3-2

2-3-0-1

3-2-1-0

Address Bus

BA1 BA0 A11 A10 A9 A8

A7 A6 A5 A4

A3 A2 A1 A0

A2 A1 A0

M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0

13 12

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

2-3-4-5-6-7-0-1

3-4-5-6-7-0-1-2

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

6-7-0-1-2-3-4-5

7-0-1-2-3-4-5-6

Cn, Cn + 1, Cn + 2

Cn + 3, Cn + 4...

…Cn - 1,

0-1-2-3-4-5-6-7

1-0-3-2-5-4-7-6

2-3-0-1-6-7-4-5

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-4-7-6-1-0-3-2

6-7-4-5-2-3-0-1

7-6-5-4-3-2-1-0

9

8

6

5

4

1

11 10

7

3

2

0

Mode Register (Mx)

Reserved* WB Op Mode CAS Latency

BT

Burst Length

Reserved**

8

Burst Length

*Should program

M10 = “0, 0”

to ensure compatibility

with future devices.

M2 M1 M0

M3 = 0

M3 = 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

1

2

4

8

** BA1, BA0 = “0, 0”

to prevent Extended

Mode Register.

Full

Page

(y)

n = A0-A11

Reserved

Full Page

Reserved

Not Supported

(location 0-y)

Cn…

NOTE: 1. For full-page accesses: y = 512 (x16), y = 256

(x32).

Burst Type

M3

0

Sequential

Interleaved

2. For a burst length of two, A1-A8 (x16) or A1-A7

(x32) select the block-of-two burst; A0 selects

the starting column within the block.

3. For a burst length of four, A2-A8 (x16) or A2-A7

(x32) select the block-of-four burst; A0-A1 select

the starting column within the block.

4. For a burst length of eight, A3-A8 (x16) or A3-

A7 (x32) select the block-of-eight burst; A0-A2

select the starting column within the block.

5. For a full-page burst, the full row is selected

and A0-A8 (x16) or A0-A7 (x32) select the

starting column.

6. Whenever a boundary of the block is reached

within a given sequence above, the following

access wraps within the block.

1

CAS Latency

M6 M5 M4

Reserved

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

Reserved

M8

0

M7

0

M6-M0

Defined

-

Operating Mode

Standard Operation

All other states reserved

-

7. For a burst length of one, A0-A8 (x16) or A0-A7

(x32) select the unique column to be accessed,

and mode register bit M3 is ignored.

Write Burst Mode

M9

0

Programmed Burst Length

Single Location Access

1

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

10

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

CAS Latency

Operating Mode

The CAS latency is the delay, in clock cycles, between

the registration of a READ command and the availability

of the first piece of output data. The latency can be set to

one, two, or three clocks.

The normal operating mode is selected by setting M7

and M8 to zero; the other combinations of values for M7

and M8 are reserved for future use and/or test modes.

The programmed burst length applies to both READ and

WRITE bursts.

Test modes and reserved states should not be used

because unknown operation or incompatibility with fu-

ture versions may result.

If a READ command is registered at clock edge n, and

the latency is m clocks, the data will be available by clock

edge n + m. The DQs will start driving as a result of the

clock edge one cycle earlier (n + m - 1), and provided that

the relevant access times are met, the data will be valid by

clock edge n + m. For example, assuming that the clock

cycle time is such that all relevant access times are met,

if a READ command is registered at T0 and the latency is

programmed to two clocks, the DQs will start driving

after T1 and the data will be valid by T2, as shown in

Figure 2. Table 2 indicates the operating frequencies at

which each CAS latency setting can be used.

Reserved states should not be used as unknown op-

eration or incompatibility with future versions

may result.

Figure 2

CAS Latency

Table 2

CAS Latency

T0

T1

T2

CLK

ALLOWABLE OPERATING

FREQUENCY (MHz)

COMMAND

READ

NOP

t

CAS

t

LZ

OH

SPEED

- 8

LATENCY = 1 LATENCY = 2 LATENCY = 3

D

OUT

DQ

t

AC

≤ 50

≤ 40

≤ 100

≤ 83

≤ 125

≤ 100

- 10

CAS Latency = 1

T0

T1

T2

T3

CLK

COMMAND

READ

NOP

t

NOP

t

LZ

OH

D

OUT

DQ

t

AC

CAS Latency = 2

T0

T1

T2

T3

T4

CLK

COMMAND

READ

NOP

t

LZ

OH

D

OUT

DQ

t

AC

CAS Latency = 3

DON’T CARE

UNDEFINED

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

11

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

EXTENDED MODE REGISTER TABLE

BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus

M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0

13 12 11 10

9

8

7

6

5

4

3

2

1

0

Extended Mode

Register (Ex)

1

0

All must be set to "0"

TCSR

PASR

A4 A3 Maximum Case Temp

1

0

1

0

85˚C

70˚C

0

1

0

45˚C

15˚C

A2

0

A1

0

A0

0

Self Refresh Coverage

Four Banks

0

1

Two Banks (Bank 0,1)

0

1

0

One Bank (Bank 0)

RFU

0

1

0

1

0

1

0

1

Notes: 1. E13 and E12 (BA1 and BA0) must be “1, 0” to select the

Extended Mode Register (vs. the base Mode Register).

2. RFU: Reserved for Future Use

TEMPERATURE COMPENSATED SELF REFRESH

Temperature Compensated Self Refresh (TCSR) al-

lows the controller to program the Refresh interval dur-

ingSELFREFRESHmode, accordingtothecasetempera-

ture of the Mobile device. This allows great power savings

during SELF REFRESH during most operating tempera-

ture ranges. Only during extreme temperatures would

the controller have to select a TCSR level that will guaran-

tee data during SELF REFRESH.

Every cell in the DRAM requires refreshing due to the

capacitor losing its charge over time. The refresh rate is

dependent on temperature. At higher temperatures a

capacitor loses charge quicker than at lower tempera-

tures, requiring the cells to be refreshed more often.

Historically, during Self Refresh, the refresh rate has

been set to accomodate the worst case, or highest tem-

perature range expected.

EXTENDED MODE REGISTER

The Extended Mode Register controls the functions

beyond those controlled by the Mode Register. These

additional functions are special features of the Mobile

device. TheyincludeTemperatureCompensatedSelfRe-

fresh (TCSR) Control, and Partial Array Self Refresh

(PASR).

The Extended Mode Register is programmed via the

Mode Register Set command (BA1=1,BA0=0) and retains

the stored information until it is programmed again or

the device loses power.

The Extended Mode Register must be programmed

with M5 through M11 set to “0”. The Extended Mode

Register must be loaded when all banks are idle and no

bursts are in progress, and the controller must wait the

specified time before before initiating any subsequent

operation. Violating either of these requirements results

in unspecified operation.

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

12

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

Thus, during ambient temperatures, the power

consumed during refresh was unnecessarily high,

because the refresh rate was set to accommodate the

higher temperatures. Setting M4 and M3, allow the

DRAM to accomodate more specific temperature

regions during SELF REFRESH. There are four

temperature settings, which will vary the SELF

REFRESH current according to the selected tempera-

ture. This selectable refresh rate will save power when

the DRAM is operating at normal temperatures.

PARTIAL ARRAY SELF REFRESH

For further power savings during SELF REFRESH, the

Partial Array Self Refresh (PASR) feature allows the con-

troller to select the amount of memory that will be re-

freshed during SELF REFRESH. The refresh options are

all banks (banks 0, 1, 2, and 3); two banks(banks 0 and 1);

and one bank (bank 0). WRITE and READ commands

occur to any bank selected during standard operation,

but only the selected banks in PASR will be refreshed

during SELF REFRESH. It’s important to note that data

in banks 2 and 3 will be lost when the two bank option is

used. Data will be lost in banks 1, 2, and 3 when the one

bank option is used.

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

13

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

Commands

Truth Table 1 provides a quick reference of available

commands. This is followed by a written description of

each command. Three additional Truth Tables appear

following the Operation section; these tables provide

current state/next state information.

TRUTH TABLE 1 – COMMANDS AND DQM OPERATION

(Note: 1)

NAME (FUNCTION)

CS# RAS# CAS# WE# DQM

ADDR

X

DQs NOTES

COMMAND INHIBIT (NOP)

H

L

X

H

L

X

H

L

X

H

L

X

NO OPERATION (NOP)

X

ACTIVE (Select bank and activate row)

READ (Select bank and column, and start READ burst)

WRITE (Select bank and column, and start WRITE burst)

BURST TERMINATE

X

Bank/Row

Bank/Col

X

3

4

8

H

L

L/H

X

L

Bank/Col Valid

H

L

X

Code

X

Active

PRECHARGE (Deactivate row in bank or banks)

L

X

5

AUTO REFRESH or SELF REFRESH

(Enter self refresh mode)

L

H

X

6, 7

LOAD MODE REGISTER

L

–

L

–

L

–

L

–

X

L

Op-Code

X

2

8

Write Enable/Output Enable

Write Inhibit/Output High-Z

–

Active

High-Z

–

H

NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.

2. A0-A10 define the op-code written to the mode register.

3. A0-A11 provide row address, and BA0, BA1 determine which bank is made active.

4. A0-A8 (x16) or A0-A7 (x32) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent),

while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to.

5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t

Care.”

6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.

8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). DQM0 controls DQ0-

7, DQM1 controls DQ8-15, DQM2 controls DQ16-23, and DQM3 controls DQ24-31.

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

14

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

COMMAND INHIBIT

auto precharge is used. If auto precharge is selected, the

row being accessed will be precharged at the end of the

WRITE burst; if auto precharge is not selected, the row

will remain open for subsequent accesses. Input data

appearing on the DQs is written to the memory array

subject to the DQM input logic level appearing coinci-

dent with the data. If a given DQM signal is registered

LOW, the corresponding data will be written to memory;

if the DQM signal is registered HIGH, the corresponding

data inputs will be ignored, and a WRITE will not be

executed to that byte/column location.

TheCOMMANDINHIBITfunctionpreventsnewcom-

mands from being executed by the SDRAM, regardless of

whether the CLK signal is enabled. The SDRAM is effec-

tively deselected. Operations already in progress are not

affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to per-

form a NOP to an SDRAM which is selected (CS# is LOW).

This prevents unwanted commands from being regis-

tered during idle or wait states. Operations already in

progress are not affected.

PRECHARGE

The PRECHARGE command is used to deactivate the

openrowinaparticularbankortheopenrowinallbanks.

The bank(s) will be available for a subsequent row access

LOAD MODE REGISTER

The mode register is loaded via inputs A0, BA0, BA1.

See mode register heading in the Register Definition

section. The LOAD MODE REGISTER and LOAD EX-

TENDED MODE REGISTER commands can only be is-

sued when all banks are idle, and a subsequent execut-

t

a specified time ( RP) after the PRECHARGE command is

issued. Input A10 determines whether one or all banks

aretobeprecharged, andinthecasewhereonlyonebank

is to be precharged, inputs BA0, BA1 select the bank.

Otherwise BA0, BA1 are treated as “Don’t Care.” Once a

bank has been precharged, it is in the idle state and must

be activated prior to any READ or WRITE commands

being issued to that bank.

t

able command cannot be issued until MRD is met.

ACTIVE

The ACTIVE command is used to open (or activate) a

row in a particular bank for a subsequent access. The

value on the BA0, BA1 inputs selects the bank, and the

address provided on inputs A0-A11 selects the row. This

row remains active (or open) for accesses until a

PRECHARGE command is issued to that bank. A

PRECHARGE command must be issued before opening a

different row in the same bank.

AUTO PRECHARGE

Auto precharge is a feature which performs the same

individual-bank PRECHARGEfunction described above,

without requiring an explicit command. This is accom-

plished by using A10 to enable auto precharge in con-

junction with a specific READ or WRITE command. A

PRECHARGE of the bank/row that is addressed with the

READ or WRITE command is automatically performed

upon completion of the READ or WRITE burst, except in

the full-page burst mode, where auto precharge does not

apply. Auto precharge is nonpersistent in that it is either

enabled or disabled for each individual READ or WRITE

command.

READ

The READ command is used to initiate a burst read

access to an active row. The value on the BA0, BA1 inputs

selects the bank, and the address provided on inputs A0-

A8 (x16) or A0-A7 (x32) selects the starting column loca-

tion. The value on input A10 determines whether or not

auto precharge is used. If auto precharge is selected, the

row being accessed will be precharged at the end of the

READ burst; if auto precharge is not selected, the row will

remain open for subsequent accesses. Read data appears

on the DQs subject to the logic level on the DQM inputs

two clocks earlier. If a given DQM signal was registered

HIGH, the corresponding DQs will be High-Z two clocks

later; if the DQM signal was registered LOW, the DQs will

provide valid data.

Auto precharge ensures that the precharge is initiated

at the earliest valid stage within a burst. The user must

not issue another command to the same bank until the

t

precharge time ( RP) is completed. This is determined as

if an explicit PRECHARGE command was issued at the

earliest possible time, as described for each burst type in

the Operation section of this data sheet.

BURST TERMINATE

The BURST TERMINATE command is used to trun-

cate either fixed-length or full-page bursts. The most

recently registered READ or WRITE command prior to

the BURST TERMINATE command will be truncated, as

shown in the Operation section of this data sheet.

WRITE

The WRITE command is used to initiate a burst write

access to an active row. The value on the BA0, BA1 inputs

selects the bank, and the address provided on inputs A0-

A8 (x16) or A0-A7 (x32) selects the starting column loca-

tion. The value on input A10 determines whether or not

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

15

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

SELF REFRESH

AUTO REFRESH

The SELF REFRESH command can be used to retain

data in the SDRAM, even if the rest of the system is

powereddown.Whenintheselfrefreshmode,theSDRAM

retains data without external clocking. The SELF RE-

FRESH command is initiated like an AUTO REFRESH

command except CKE is disabled (LOW). Once the SELF

REFRESH command is registered, all the inputs to the

SDRAM become “Don’t Care” with the exception of CKE,

which must remain LOW.

AUTO REFRESH is used during normal operation of

the SDRAM and is analogous to CAS#-BEFORE-RAS#

(CBR) REFRESH in conventional DRAMs. This

command is nonpersistent, so it must be issued each

time a refresh is required. All active banks must be

PRECHARGED prior to issuing an AUTO REFRESH

command. The AUTO REFRESH command should not

be issued until the minimum RP has been met after the

PRECHARGE command as shown in the operation sec-

tion.

t

Once self refresh mode is engaged, the SDRAM pro-

vides its own internal clocking, causing it to perform its

own AUTO REFRESH cycles. The SDRAM must remain in

The addressing is generated by the internal refresh

controller. This makes the address bits “Don’t Care”

duringanAUTOREFRESHcommand.The128MbSDRAM

t

self refresh mode for a minimum period equal to RAS

t

and may remain in self refresh mode for an indefinite

period beyond that.

requires 4,096 AUTO REFRESH cycles every 64ms ( REF),

regardless of width option. Providing a distributed AUTO

REFRESH command every 15.625µs will meet the refresh

requirementandensurethateachrowisrefreshed. Alter-

natively, 4,096AUTOREFRESHcommandscanbeissued

The procedure for exiting self refresh requires a se-

quence of commands. First, CLK must be stable (stable

clock is defined as a signal cycling within timing con-

straints specified for the clock pin) prior to CKE going

back HIGH. Once CKE is HIGH, the SDRAM must have

NOP commands issued (a minimum of two clocks) for

t

in a burst at the minimum cycle rate ( RFC), once every

64ms.

t

XSR because time is required for the completion of any

internal refresh in progress.

Upon exiting the self refresh mode, AUTO REFRESH

commands must be issued every 15.625µs or less as both

SELF REFRESH and AUTO REFRESH utilize the row re-

fresh counter.

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

16

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

Operation

Figure 3

Activating a Specific Row in a

Specific Bank

BANK/ROW ACTIVATION

Before any READ or WRITE commands can be issued

to a bank within the SDRAM, a row in that bank must be

“opened.” This is accomplished via the ACTIVE com-

mand, which selects both the bank and the row to be

activated (see Figure 3).

CLK

CKE

CS#

HIGH

After opening a row (issuing an ACTIVE command), a

READ or WRITE command may be issued to that row,

t

subject to the RCD specification. RCD (MIN) should be

divided by the clock period and rounded up to the next

whole number to determine the earliest clock edge after

the ACTIVE command on which a READ or WRITE com-

RAS#

t

mand can be entered. For example, a RCD specification

of 20ns with a 125 MHz clock (8ns period) results in 2.5

clocks, rounded to 3. This is reflected in Figure 4, which

covers any case where 2 < RCD (MIN)/ CK ≤ 3. (The same

procedure is used to convert other specification limits

from time units to clock cycles.)

CAS#

WE#

t

A subsequent ACTIVE command to a different row in

the same bank can only be issued after the previous

active row has been “closed” (precharged). The mini-

mum time interval between successive ACTIVE com-

ROW

A0–A10, A11

BA0, BA1

ADDRESS

t

mands to the same bank is defined by RC.

BANK

ADDRESS

A subsequent ACTIVE command to another bank can

be issued while the first bank is being accessed, which

results in a reduction of total row-access overhead. The

minimumtimeintervalbetweensuccessiveACTIVEcom-

t

mands to different banks is defined by RRD.

Figure 4

t

≤

Example: Meeting RCD (MIN) When 2 < RCD (MIN)/ CK

3

T0

T1

T2

T3

T4

CLK

READ or

WRITE

COMMAND

ACTIVE

NOP

t

RCD

DON’T CARE

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

17

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

READs

READ bursts are initiated with a READ command, as

shown in Figure 5.

Upon completion of a burst, assuming no other com-

mands have been initiated, the DQs will go High-Z. A full-

page burst will continue until terminated. (At the end of

the page, it will wrap to column 0 and continue.)

Data from any READ burst may be truncated with a

subsequentREADcommand,anddatafromafixed-length

READ burst may be immediately followed by data from a

READcommand. Ineithercase, acontinuousflowofdata

can be maintained. The first data element from the new

burst follows either the last element of a completed burst

or the last desired data element of a longer burst that is

being truncated. The new READ command should be

issued x cycles before the clock edge at which the last

desired data element is valid, where x equals the CAS

latency minus one.

The starting column and bank addresses are provided

with the READ command, and auto precharge is either

enabledordisabledforthatburstaccess.Ifautoprecharge

is enabled, the row being accessed is precharged at the

completion of the burst. For the generic READ com-

mandsusedinthefollowingillustrations, autoprecharge

is disabled.

During READ bursts, the valid data-out element from

the starting column address will be available following

the CAS latency after the READ command. Each subse-

quent data-out element will be valid by the next positive

clock edge. Figure 6 shows general timing for each pos-

sible CAS latency setting.

Figure 5

READ Command

Figure 6

CAS Latency

T0

T1

T2

CLK

CKE

CS#

HIGH

COMMAND

READ

NOP

t

LZ

OH

DOUT

DQ

t

AC

CAS Latency = 1

RAS#

T0

T1

T2

T3

CAS#

WE#

CLK

COMMAND

READ

NOP

t

NOP

t

LZ

OH

DOUT

DQ

COLUMN

ADDRESS

t

A0-A8

AC

CAS Latency = 2

A9, A11

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

T0

T1

T2

T3

T4

A10

CLK

COMMAND

READ

NOP

t

BANK

ADDRESS

BA0,1

t

LZ

OH

DOUT

DQ

t

DON’T CARE

AC

CAS Latency = 3

DON’T CARE

UNDEFINED

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

18

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

This is shown in Figure 7 for CAS latencies of two and

three; data element n + 3 is either the last of a burst of four

or the last desired of a longer burst. The 128Mb SDRAM

uses a pipelined architecture and therefore does not

require the 2n rule associated with a prefetch architec-

ture. A READ command can be initiated on any clock

cycle following a previous READ command. Full-speed

random read accesses can be performed to the same

bank, as shown in Figure 8, or each subsequent READ

may be performed to a different bank.

Figure 7

Consecutive READ Bursts

T0

T1

T2

T3

T4

T5

CLK

READ

NOP

READ

NOP

COMMAND

X = 0 cycles

BANK,

COL n

BANK,

COL b

ADDRESS

DQ

D

OUT

D

n + 1

OUT

D

n + 2

OUT

DOUT

D

OUT

n

n + 3

b

CAS Latency = 1

T0

T1

T2

T3

T4

T5

T6

CLK

READ

NOP

READ

NOP

COMMAND

X = 1 cycle

BANK,

COL n

BANK,

COL b

ADDRESS

DQ

D

OUT

D

n + 1

OUT

DOUT

D

n + 3

OUT

D

OUT

n

n + 2

b

CAS Latency = 2

T1

T0

T2

T3

T4

T5

T6

T7

CLK

READ

NOP

READ

NOP

COMMAND

X = 2 cycles

BANK,

COL n

BANK,

COL b

ADDRESS

DQ

D

OUT

DOUT

D

n + 2

OUT

D

n + 3

OUT

DOUT

b

n

n + 1

CAS Latency = 3

NOTE: Each READ command may be to either bank. DQM is LOW.

DON’T CARE

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

19

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

Figure 8

Random READ Accesses

T0

T1

T2

T3

T4

CLK

COMMAND

ADDRESS

DQ

READ

NOP

BANK,

COL n

BANK,

COL a

BANK,

COL x

BANK,

COL m

DOUT

D

OUT

D

OUT

n

a

x

m

CAS Latency = 1

T0

T1

T2

T3

T4

T5

CLK

COMMAND

ADDRESS

DQ

READ

NOP

BANK,

COL n

BANK,

COL a

BANK,

COL x

BANK,

COL m

DOUT

D

OUT

D

OUT

n

a

x

m

CAS Latency = 2

T0

T1

T2

T3

T4

T5

T6

CLK

READ

NOP

COMMAND

ADDRESS

DQ

BANK,

COL n

BANK,

COL a

BANK,

COL x

BANK,

COL m

DOUT

D

OUT

D

OUT

D

OUT

n

a

x

m

CAS Latency = 3

NOTE: Each READ command may be to either bank. DQM is LOW.

DON’T CARE

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

20

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

Data from any READ burst may be truncated with a

subsequent WRITE command, and data from a fixed-

length READ burst may be immediately followed by data

from a WRITE command (subject to bus turnaround

limitations). The WRITE burst may be initiated on the

clock edge immediately following the last (or last de-

sired)dataelementfromtheREADburst, providedthatI/

O contention can be avoided. In a given system design,

there may be a possibility that the device driving the

input data will go Low-Z before the SDRAM DQs go High-

Z. In this case, at least a single-cycle delay should occur

between the last read data and the WRITE command.

The DQM input is used to avoid I/O contention, as

shown in Figures 9 and 10. The DQM signal must be

asserted (HIGH) at least two clocks prior to the WRITE

command (DQM latency is two clocks for output buffers)

to suppress data-out from the READ. Once the WRITE

command is registered, the DQs will go High-Z (or re-

main High-Z), regardless of the state of the DQM signal,

provided the DQM was active on the clock just prior to

the WRITE command that truncated the READ com-

mand. If not, the second WRITE will be an invalid WRITE.

For example, if DQM was LOW during T4 in Figure 10,

then the WRITEs at T5 and T7 would be valid, while the

WRITE at T6 would be invalid.

The DQM signal must be de-asserted prior to the

WRITE command (DQM latency is zero clocks for input

buffers) to ensure that the written data is not masked.

Figure 9 shows the case where the clock frequency allows

for bus contention to be avoided without adding a NOP

cycle, and Figure 10 shows the case where the additional

NOP is needed.

Figure 9

READ to WRITE

Figure 10

READ to WRITE With

Extra Clock Cycle

T0

T1

T2

T3

T4

T0

T1

T2

T3

T4

T5

CLK

DQM

READ

NOP

WRITE

COMMAND

ADDRESS

READ

NOP

WRITE

COMMAND

ADDRESS

BANK,

COL n

BANK,

COL b

BANK,

COL n

BANK,

COL b

t

CK

HZ

t

HZ

DOUT

n

DIN

b

DQ

t

D

OUT

n

DIN b

DS

DQ

t

DS

DON’T CARE

NOTE:

A CAS latency of three is used for illustration. The READ command

may be to any bank, and the WRITE command may be to any bank.

NOTE:

A CAS latency of three is used for illustration. The READ

command may be to any bank, and the WRITE command

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

21

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

A fixed-length READ burst may be followed by, or

truncated with, a PRECHARGE command to the same

bank (provided that auto precharge was not activated),

and a full-page burst may be truncated with a

PRECHARGE command to the same bank. The

PRECHARGE command should be issued x cycles before

the clock edge at which the last desired data element is

valid, where x equals the CAS latency minus one. This is

shown in Figure 11 for each possible CAS latency; data

element n + 3 is either the last of a burst of four or the last

desired of a longer burst. Following the PRECHARGE

command, a subsequent command to the same bank

cannotbeissueduntil RPismet. Notethatpartoftherow

precharge time is hidden during the access of the last

data element(s).

In the case of a fixed-length burst being executed to

completion, a PRECHARGE command issued at the opti-

mum time (as described above) provides the same op-

eration that would result from the same fixed-length

burst with auto precharge. The disadvantage of the

t

Figure 11

READ to PRECHARGE

T0

T1

T2

T3

T4

T5

T6

T7

CLK

t

RP

READ

NOP

PRECHARGE

NOP

ACTIVE

COMMAND

ADDRESS

DQ

X = 0 cycles

BANK

(a or all)

BANK a,

COL n

BANK a,

ROW

D

OUT

D

n + 1

OUT

DOUT

n

n + 2

n + 3

CAS Latency = 1

T0

T1

T2

T3

T4

T5

T6

T7

CLK

t

RP

READ

NOP

PRECHARGE

NOP

ACTIVE

COMMAND

ADDRESS

DQ

X = 1 cycle

BANK

(a or all)

BANK a,

ROW

COL

n

D

OUT

D

n + 1

OUT

DOUT

n + 3

n

n + 2

CAS Latency = 2

T0

T1

T2

T3

T4

T5

T6

T7

CLK

t

RP

READ

NOP

PRECHARGE

NOP

ACTIVE

COMMAND

ADDRESS

DQ

X = 2 cycles

BANK

(a or all)

BANK a,

ROW

COL

n

D

OUT

DOUT

D

n + 3

OUT

n

n + 1

n + 2

CAS Latency = 3

NOTE: DQM is LOW.

DON’T CARE

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

22

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

PRECHARGE command is that it requires that the com-

mand and address buses be available at the appropriate

time to issue the command; the advantage of the

PRECHARGE command is that it can be used to truncate

fixed-length or full-page bursts.

Full-page READ bursts can be truncated with the

BURST TERMINATE command, and fixed-length READ

burstsmaybetruncatedwithaBURSTTERMINATEcom-

mand, provided that auto precharge was not activated.

The BURST TERMINATE command should be issued x

cycles before the clock edge at which the last desired data

element is valid, where x equals the CAS latency minus

one. This is shown in Figure 12 for each possible CAS

latency; data element n + 3 is the last desired data ele-

ment of a longer burst.

Figure 12

Terminating a READ Burst

T0

T1

T2

T3

T4

T5

T6

CLK

BURST

TERMINATE

READ

NOP

COMMAND

ADDRESS

DQ

X = 0 cycles

BANK,

COL n

D

OUT

D

n + 1

OUT

D

n + 2

OUT

DOUT

n

n + 3

CAS Latency = 1

T0

T1

T2

T3

T4

T5

T6

CLK

BURST

TERMINATE

READ

NOP

COMMAND

ADDRESS

DQ

X = 1 cycle

BANK,

COL n

D

OUT

D

n + 1

OUT

DOUT

D

n + 3

OUT

n

n + 2

CAS Latency = 2

T1

T0

T2

T3

T4

T5

T6

T7

CLK

COMMAND

ADDRESS

DQ

BURST

TERMINATE

READ

NOP

X = 2 cycles

BANK,

COL n

D

OUT

DOUT

D

n + 2

OUT

D

n + 3

OUT

n

n + 1

CAS Latency = 3

NOTE: DQM is LOW.

DON’T CARE

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

23

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

WRITEs

WRITE bursts are initiated with a WRITE command,

as shown in Figure 13.

command applies to the new command. An example is

shown in Figure 15. Data n + 1 is either the last of a burst

of two or the last desired of a longer burst. The 128Mb

SDRAM uses a pipelined architecture and therefore does

not require the 2n rule associated with a prefetch archi-

tecture. A WRITE command can be initiated on any clock

cycle following a previous WRITE command. Full-speed

random write accesses within a page can be performed to

thesamebank, asshowninFigure16, oreachsubsequent

WRITE may be performed to a different bank.

The starting column and bank addresses are pro-

vided with the WRITE command, and auto precharge is

either enabled or disabled for that access. If auto

precharge is enabled, the row being accessed is

precharged at the completion of the burst. For the ge-

neric WRITE commands used in the following illustra-

tions, auto precharge is disabled.

During WRITE bursts, the first valid data-in element

will be registered coincident with the WRITE command.

Subsequent data elements will be registered on each

successive positive clock edge. Upon completion of a

fixed-length burst, assuming no other commands have

been initiated, the DQs will remain High-Z and any addi-

tional input data will be ignored (see Figure 14). A full-

page burst will continue until terminated. (At the end of

the page, it will wrap to column 0 and continue.)

Data for any WRITE burst may be truncated with a

subsequentWRITEcommand, anddataforafixed-length

WRITE burst may be immediately followed by data for a

WRITE command. The new WRITE command can be

issued on any clock following the previous WRITE com-

mand, and the data provided coincident with the new

Figure 14

WRITE Burst

T0

T1

T2

T3

CLK

WRITE

NOP

COMMAND

ADDRESS

DQ

BANK,

COL n

DIN

n + 1

n

Figure 13

WRITE Command

NOTE:

Burst length = 2. DQM is LOW.

CLK

CKE HIGH

Figure 15

WRITE to WRITE

CS#

T0

T1

T2

RAS#

CLK

CAS#

WE#

WRITE

NOP

WRITE

COMMAND

ADDRESS

DQ

COLUMN

A0-A8

ADDRESS

BANK,

COL n

BANK,

COL b

A9, A11

DIN

b

ENABLE AUTO PRECHARGE

n

n + 1

A10

DISABLE AUTO PRECHARGE

NOTE:

DQM is LOW. Each WRITE

command may be to any bank.

BANK

ADDRESS

BA0,1

DON’T CARE

VALID ADDRESS

DON’T CARE

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

24

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

Data for any WRITE burst may be truncated with a

subsequent READ command, and data for a fixed-length

WRITE burst may be immediately followed by a READ

command. Once the READ command is registered, the

data inputs will be ignored, and WRITEs will not be

executed. An example is shown in Figure 17. Data n + 1 is

either the last of a burst of two or the last desired of a

longer burst.

least one clock plus time, regardless of frequency.

In addition, when truncating a WRITE burst, the DQM

signal must be used to mask input data for the clock edge

prior to, and the clock edge coincident with, the

PRECHARGE command. An example is shown in Figure

18. Data n + 1 is either the last of a burst of two or the last

desired of a longer burst. Following the PRECHARGE

command, a subsequent command to the same bank

t

Data for a fixed-length WRITE burst may be followed

by, or truncated with, a PRECHARGE command to the

same bank (provided that auto precharge was not acti-

vated), and a full-page WRITE burst may be truncated

with a PRECHARGE command to the same bank. The

cannot be issued until RP is met.

In the case of a fixed-length burst being executed to

completion, a PRECHARGE command issued at the opti-

mum time (as described above) provides the same op-

eration that would result from the same fixed-length

burst with auto precharge. The disadvantage of the

PRECHARGE command is that it requires that the com-

mand and address buses be available at the appropriate

time to issue the command; the advantage of the

PRECHARGE command is that it can be used to truncate

fixed-length or full-page bursts.

t

PRECHARGE command should be issued WR after the

clock edge at which the last desired input data element is

t

registered. The auto precharge mode requires a WR of at

Figure 16

Random WRITE Cycles

T0

T1

T2

T3

CLK

COMMAND

ADDRESS

Figure 18

WRITE to PRECHARGE

WRITE

T0

T1

T2

T3

T4

T5

T6

CLK

t

WR@ CK 15ns

BANK,

COL n

BANK,

COL a

BANK,

COL x

BANK,

COL m

DQM

t

RP

D

IN

D

IN

D

IN

DIN

x

NOP

WRITE

NOP

PRECHARGE

ACTIVE

COMMAND

ADDRESS

DQ

m

n

a

BANK

(a or all)

BANK a,

COL n

BANK a,

ROW

NOTE:

Each WRITE command may be to any bank.

DQM is LOW.

t

WR

D

n

IN

DIN

n + 1

DQ

t

WR@ CK < 15ns

Figure 17

DQM

WRITE to READ

t

RP

T0

T1

T2

T3

T4

T5

NOP

WRITE

NOP

PRECHARGE

ACTIVE

COMMAND

ADDRESS

CLK

BANK

(a or all)

BANK a,

COL n

BANK a,

ROW

t

WR

WRITE

NOP

READ

NOP

COMMAND

ADDRESS

D

n

IN

DIN

n + 1

DQ

BANK,

COL n

BANK,

COL b

NOTE:

DQM could remain LOW in this example if the WRITE burst is a fixed length

of two.

DON’T CARE

DIN

D

IN

DOUT

DQ

n

n + 1

b

b + 1

NOTE:

The WRITE command may be to any bank, and the READ command may

be to any bank. DQM is LOW. CAS latency = 2 for illustration.

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

25

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

Fixed-length or full-page WRITE bursts can be trun-

cated with the BURST TERMINATE command. When

truncating a WRITE burst, the input data applied coinci-

dent with the BURST TERMINATE command will be

ignored. The last data written (provided that DQM is

LOW at that time) will be the input data applied one clock

previous to the BURST TERMINATE command. This is

shown in Figure 19, where data n is the last desired data

element of a longer burst.

PRECHARGE

The PRECHARGE command (see Figure 20) is used to

deactivate the open row in a particular bank or the open

row in all banks. The bank(s) will be available for a subse-

t

quent row access some specified time ( RP) after the

PRECHARGE command is issued. Input A10 determines

whether one or all banks are to be precharged, and in the

case where only one bank is to be precharged, inputs

BA0, BA1 select the bank. When all banks are to be

precharged, inputs BA0, BA1 are treated as “Don’t Care.”

Once a bank has been precharged, it is in the idle state

and must be activated prior to any READ or WRITE com-

mands being issued to that bank.

Figure 19

Terminating a WRITE Burst

T0

T1

T2

POWER-DOWN

Power-down occurs if CKE is registered LOW coinci-

dent with a NOP or COMMAND INHIBIT when no ac-

cesses are in progress. If power-down occurs when all

banks are idle, this mode is referred to as precharge

power-down; if power-down occurs when there is a row

active in any bank, this mode is referred to as active

power-down. Entering power-down deactivates the in-

put and output buffers, excluding CKE, for maximum

power savings while in standby. The device may not

remain in the power-down state longer than the refresh

period (64ms) since no refresh operations are performed

in this mode.

CLK

BURST

TERMINATE

WRITE

COMMAND

ADDRESS

DQ

BANK,

COL n

(ADDRESS)

(DATA)

DIN

n

The power-down state is exited by registering a NOP

or COMMAND INHIBIT and CKE HIGH at the desired

t

clock edge (meeting CKS). See Figure 21.

Figure 20

PRECHARGE Command

Figure 21

Power-Down

CLK

CKE

HIGH

( (

) )

CLK

( (

) )

> t

CKS

t

CKS

CS#

CKE

( (

) )

( (

) )

( (

) )

RAS#

COMMAND

NOP

ACTIVE

t

All banks idle

RCD

Input buffers gated off

t

RAS

CAS#

WE#

t

RC

Enter power-down mode.

Exit power-down mode.

DON’T CARE

A0-A9

A10

All Banks

Bank Selected

BANK

ADDRESS

BA0,1

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

26

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

CLOCK SUSPEND

The clock suspend mode occurs when a column ac-

cess/burst is in progress and CKE is registered LOW. In

the clock suspend mode, the internal clock is deacti-

vated, “freezing” the synchronous logic.

Clock suspend mode is exited by registering CKE

HIGH; the internal clock and related operation will re-

sume on the subsequent positive clock edge.

For each positive clock edge on which CKE is sampled

LOW, the next internal positive clock edge is suspended.

Any command or data present on the input pins at the

time of a suspended internal clock edge is ignored; any

data present on the DQ pins remains driven; and burst

counters are not incremented, as long as the clock is

suspended. (See examples in Figures 22 and 23.)

BURST READ/SINGLE WRITE

The burst read/single write mode is entered by pro-

gramming the write burst mode bit (M9) in the mode

register to a logic 1. In this mode, all WRITE commands

result in the access of a single column location (burst of

one), regardless of the programmed burst length. READ

commandsaccesscolumnsaccordingtotheprogrammed

burst length and sequence, just as in the normal mode of

operation (M9 = 0).

Figure 22

Clock Suspend During WRITE Burst

Figure 23

Clock Suspend During READ Burst

T0

T1

T2

T3

T4

T5

T0

T1

T2

T3

T4

T5

T6

CLK

CKE

CLK

CKE

INTERNAL

CLOCK

INTERNAL

CLOCK

READ

NOP

COMMAND

ADDRESS

DQ

NOP

WRITE

NOP

COMMAND

ADDRESS

BANK,

COL n

BANK,

COL n

D

OUT

D

OUT

D

n + 2

OUT

DOUT

n + 3

n

n + 1

D

n

IN

D

n + 1

IN

DIN

n + 2

D

IN

DON’T CARE

NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and

DON’T CARE

DQM is LOW.

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

27

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

CONCURRENT AUTO PRECHARGE

An access command (READ or WRITE) to another

bank while an access command with auto precharge

enabled is executing is not allowed by SDRAMs, unless

theSDRAMsupportsCONCURRENTAUTOPRECHARGE.

Micron SDRAMs support CONCURRENT AUTO

PRECHARGE. Four cases where CONCURRENT AUTO

PRECHARGE occurs are defined below.

on bank n, CAS latency later. The PRECHARGE to

bank n will begin when the READ to bank m is regis-

tered (Figure 24).

2. Interrupted by a WRITE (with or without auto

precharge): A WRITE to bank m will interrupt a READ

on bank n when registered. DQM should be used two

clocks prior to the WRITE command to prevent bus

contention. The PRECHARGE to bank n will begin

when the WRITE to bank m is registered (Figure 25).

READ with Auto Precharge

1. Interrupted by a READ (with or without auto

precharge): A READ to bank m will interrupt a READ

Figure 24

READ With Auto Precharge Interrupted by a READ

T0

T1

T2

T3

T4

T5

T6

T7

CLK

READ - AP

BANK n

READ - AP

BANK m

NOP

COMMAND

Page Active

READ with Burst of 4

Interrupt Burst, Precharge

t

Idle

BANK n

t

RP - BANK n

RP - BANK m

Internal

States

Page Active

READ with Burst of 4

Precharge

BANK m

BANK n,

COL a

BANK m,

COL d

ADDRESS

DQ

D

a

OUT

D

a + 1

OUT

D

OUT

D

d + 1

OUT

d

CAS Latency = 3 (BANK n)

CAS Latency = 3 (BANK m)

NOTE: DQM is LOW.

Figure 25

READ With Auto Precharge Interrupted by a WRITE

T0

T1

T2

T3

T4

T5

T6

T7

CLK

READ - AP

BANK n

WRITE - AP

BANK m

NOP

COMMAND

Page

Active

READ with Burst of 4

Page Active

Interrupt Burst, Precharge

t

Idle

WR - BANK m

BANK n

t

RP - BANK

n

Internal

States

WRITE with Burst of 4

Write-Back

BANK m

BANK n,

COL a

BANK m,

COL d

ADDRESS

1

DQM

D

OUT

DIN

d

D

d + 1

IN

D

d + 2

IN

DIN

d + 3

DQ

a

CAS Latency = 3 (BANK n)

NOTE: 1. DQM is HIGH at T2 to prevent OUT-a+1 from contending with DIN-d at T4.

D

DON’T CARE

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

28

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

WRITE with Auto Precharge

3. Interrupted by a READ (with or without auto

precharge): A READ to bank m will interrupt a WRITE

on bank n when registered, with the data-out appear-

ing CAS latency later. The PRECHARGE to bank n will

4. Interrupted by a WRITE (with or without auto

precharge):AWRITEtobank mwillinterruptaWRITE

on bank n when registered. The PRECHARGE to bank

t

n will begin after WR is met, where WR begins when

the WRITE to bank is registered.

t

begin after WR is met, where WR begins when the

READ to bank m is registered. The last valid WRITE to

bank n will be data-in registered one clock prior to the

READ to bank m (Figure 26).

m

The last valid data WRITE to bank n will be data

registered one clock prior to a WRITE to bank m

(Figure 27).

Figure 26

WRITE With Auto Precharge Interrupted by a READ

T0

T1

T2

T3

T4

T5

T6

T7

CLK

WRITE - AP

BANK n

READ - AP

BANK m

NOP

COMMAND

Page Active

WRITE with Burst of 4

Interrupt Burst, Write-Back

Precharge

BANK n

t

RP - BANK n

t

WR - BANK n

Internal

States

t

RP - BANK m

Page Active

READ with Burst of 4

BANK m

BANK n,

COL a

BANK m,

COL d

ADDRESS

DQ

DIN

D

a + 1

IN

D

OUT

DOUT

d + 1

a

d

CAS Latency = 3 (BANK m)

NOTE: 1. DQM is LOW.

Figure 27

WRITE With Auto Precharge Interrupted by a WRITE

T0

T1

T2

T3

T4

T5

T6

T7

CLK

WRITE - AP

BANK n

WRITE - AP

BANK m

NOP

COMMAND

Page Active

WRITE with Burst of 4

Interrupt Burst, Write-Back

Precharge

BANK n

t

RP - BANK n

t

WR - BANK n

Internal

States

t

WR - BANK m

Write-Back

Page Active

WRITE with Burst of 4

BANK m

BANK n,

COL a

BANK m,

COL d

ADDRESS

DQ

DIN

D

a + 1

IN

D

a + 2

IN

D

IN

D

d + 1

IN

D

d + 2

IN

DIN

d + 3

a

d

NOTE: 1. DQM is LOW.

DON’T CARE

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

29

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

TRUTH TABLE 2 – CKE

(Notes: 1-4)

CKE

CURRENT STATE

Power-Down

COMMAND

ACTION

n

NOTES

n-1

n

L

X

Maintain Power-Down

Maintain Self Refresh

Maintain Clock Suspend

Exit Power-Down

Self Refresh

Clock Suspend

Power-Down

L

H

L

COMMAND INHIBIT or NOP

X

5

6

7

Self Refresh

Exit Self Refresh

Clock Suspend

All Banks Idle

Reading or Writing

Exit Clock Suspend

Power-Down Entry

Self Refresh Entry

H

COMMAND INHIBIT or NOP

AUTO REFRESH

VALID

Clock Suspend Entry

H

See Truth Table 3

NOTE: 1. CKE_nis the logic state of CKE at clock edge n; CKE_n-1was the state of CKE at the previous clock edge.

2. Current state is the state of the SDRAM immediately prior to clock edge n.

3. COMMAND_nis the command registered at clock edge n, and ACTION_nis a result of COMMAND_n.

4. All states and sequences not shown are illegal or reserved.

5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1

(provided that ^tCKS is met).

6. Exiting self refresh at clock edge n will put the device in the all banks idle state once ^tXSR is met. COMMAND INHIBIT

or NOP commands should be issued on any clock edges occurring during the ^tXSR period. A minimum of two NOP

commands must be provided during ^tXSR period.

7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at

clock edge n + 1.

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

30

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

TRUTH TABLE 3 – CURRENT STATE BANK n, COMMAND TO BANK n

(Notes: 1-6; notes appear below and on next page)

CURRENT STATE CS# RAS# CAS# WE# COMMAND (ACTION)

NOTES

Any

Idle

H

L

X

H

L

X

H

L

X

H

L

COMMAND INHIBIT (NOP/Continue previous operation)

NO OPERATION (NOP/Continue previous operation)

ACTIVE (Select and activate row)

L

AUTO REFRESH

7

L

LOAD MODE REGISTER

L

H

L

PRECHARGE

11

10

8

H

L

H

L

READ (Select column and start READ burst)

WRITE (Select column and start WRITE burst)

PRECHARGE (Deactivate row in bank or banks)

READ (Select column and start new READ burst)

WRITE (Select column and start WRITE burst)

PRECHARGE (Truncate READ burst, start PRECHARGE)

BURST TERMINATE

Row Active

L

H

L

Read

(Auto

H

L

H

L

10

8

L

Precharge

Disabled)

Write

H

L

H

L

9

H

L

READ (Select column and start READ burst)

WRITE (Select column and start new WRITE burst)

PRECHARGE (Truncate WRITE burst, start PRECHARGE)

BURST TERMINATE

10

8

(Auto

L

Precharge

Disabled)

H

L

H

L

9

NOTE: 1. This table applies when CKE_n-1was HIGH and CKE_nis HIGH (see Truth Table 2) and after ^tXSR has been

met (if the previous state was self refresh).

2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown

are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and ^tRP has been met.

Row Active: A row in the bank has been activated, and ^tRCD has been met. No data bursts/accesses and

no register accesses are in progress.

Read: A READ burst has been initiated, with auto precharge disabled, and has not yet

terminated or been terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated

or been terminated.

4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP

commands, or allowable commands to the other bank should be issued on any clock edge occurring during these

states. Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to

Truth Table 4.

Precharging: Starts with registration of a PRECHARGE command and ends when ^tRP is met. Once ^tRP is

met, the bank will be in the idle state.

Row Activating: Starts with registration of an ACTIVE command and ends when ^tRCD is met. Once ^tRCD is

met, the bank will be in the row active state.

Read w/Auto

Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when ^tRP

has been met. Once ^tRP is met, the bank will be in the idle state.

Write w/Auto

Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when

^tRP has been met. Once ^tRP is met, the bank will be in the idle state.

(Continued on next page)

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

31

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

NOTE (continued):

5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands

must be applied on each positive clock edge during these states.

Refreshing: Starts with registration of an AUTO REFRESH command and ends when ^tRC is met. Once ^tRC is

met, the SDRAM will be in the all banks idle state.

Accessing Mode

Register: Starts with registration of a LOAD MODE REGISTER command and ends when ^tMRD has been

met. Once ^tMRD is met, the SDRAM will be in the all banks idle state.

Precharging All: Starts with registration of a PRECHARGE ALL command and ends when ^tRP is met. Once ^tRP is

met, all banks will be in the idle state.

6. All states and sequences not shown are illegal or reserved.

7. Not bank-specific; requires that all banks are idle.

8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.

9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.

10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and

READs or WRITEs with auto precharge disabled.

11. Does not affect the state of the bank and acts as a NOP to that bank.

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

32

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

TRUTH TABLE 4 – CURRENT STATE BANK n, COMMAND TO BANK m

(Notes: 1-6; notes appear below and on next page)

CURRENT STATE CS# RAS# CAS# WE# COMMAND (ACTION)

NOTES

Any

H

L

X

L

X

H

X

L

X

H

X

H

L

X

H

X

H

L

COMMAND INHIBIT (NOP/Continue previous operation)

NO OPERATION (NOP/Continue previous operation)

Any Command Otherwise Allowed to Bank m

ACTIVE (Select and activate row)

Idle

Row

Activating,

Active, or

Precharging

Read

H

L

READ (Select column and start READ burst)

WRITE (Select column and start WRITE burst)

PRECHARGE

7

L

H

L

H

L

ACTIVE (Select and activate row)

(Auto

H

L

READ (Select column and start new READ burst)

WRITE (Select column and start WRITE burst)

PRECHARGE

7, 10

7, 11

9

Precharge

Disabled)

Write

L

H

L

H

L

ACTIVE (Select and activate row)

(Auto

H

L

READ (Select column and start READ burst)

WRITE (Select column and start new WRITE burst)

PRECHARGE

7, 12

7, 13

9

Precharge

Disabled)

Read

L

H

L

H

L

ACTIVE (Select and activate row)

(With Auto

Precharge)

H

L

READ (Select column and start new READ burst)

WRITE (Select column and start WRITE burst)

PRECHARGE

7, 8, 14

7, 8, 15

9

L

H

L

Write

L

H

L

ACTIVE (Select and activate row)

(With Auto

Precharge)

H

L

READ (Select column and start READ burst)

WRITE (Select column and start new WRITE burst)

PRECHARGE

7, 8, 16

7, 8, 17

9

L

H

L

NOTE: 1. This table applies when CKE_n-1was HIGH and CKE_nis HIGH (see Truth Table 2) and after ^tXSR has been met (if the

previous state was self refresh).

2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the

commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given

command is allowable). Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and ^tRP has been met.

Row Active: A row in the bank has been activated, and ^tRCD has been met. No data bursts/accesses and

no register accesses are in progress.

Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated

or been terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated

or been terminated.

Read w/Auto

Precharge Enabled: Starts with registration of a READ command with auto precharge enabled, and ends when

^tRP has been met. Once ^tRP is met, the bank will be in the idle state.

Write w/Auto

Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled, and ends when

^tRP has been met. Once ^tRP is met, the bank will be in the idle state.

(Continued on next page)

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

33

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

NOTE (continued):

4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.

5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current

state only.

6. All states and sequences not shown are illegal or reserved.

7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge

enabled and READs or WRITEs with auto precharge disabled.

8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge command when its burst has been

interrupted by bank m’s burst.

9. Burst in bank n continues as initiated.

10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m

will interrupt the READ on bank n, CAS latency later (Figure 7).

11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m

will interrupt the READ on bank n when registered (Figures 9 and 10). DQM should be used one clock prior to the

WRITE command to prevent bus contention.

12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m

will interrupt the WRITE on bank n when registered (Figure 17), with the data-out appearing CAS latency later. The

last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m.

13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m

will interrupt the WRITE on bank n when registered (Figure 15). The last valid WRITE to bank n will be data-in

registered one clock prior to the READ to bank m.

14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will

interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is

registered (Figure 24).

15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will

interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to

prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 25).

16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will

interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to

bank n will begin after ^tWR is met, where ^tWR begins when the READ to bank m is registered. The last valid WRITE to

bank n will be data-in registered one clock prior to the READ to bank m (Figure 26).

17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will

interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after ^tWR is met, where ^tWR

begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior

to the WRITE to bank m (Figure 27).

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

34

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

*Stresses greater than those listed under “Absolute Maxi-

mum Ratings” may cause permanent damage to the de-

vice. This is a stress rating only, and functional operation

of the device at these or any other conditions above those

indicated in the operational sections of this specification

is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

ABSOLUTE MAXIMUM RATINGS*

Voltage on VDD/VDDQ Supply

Relative to VSS(3.3V) ............................. -1V to +4.6V

Relative to VSS(2.5V) ......................... -0.5V to +3.6V

Voltage on Inputs, NC or I/O Pins

Relative to V^SS(3.3V) ............................. -1V to +4.6V

Relative to VSS(2.5V) ......................... -0.5V to +3.6V

Operating Temperature,

T

(Industrial) ....................................... -40°C to +85°C

A

Storage Temperature (plastic) ................ -55°C to +150°C

Power Dissipation ..........................................................1W

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS - LC VERSION

(Notes: 1, 5, 6; notes appear on page 39; VDD = +3.3V 0.3V, VDDQ = +3.3V 0.3V

PARAMETER/CONDITION

Supply Voltage

SYMBOL

VDD

MIN

MAX UNITS NOTES

3

2

3.6

V

I/O Supply Voltage

VDDQ

VIH

Input High Voltage: Logic 1; All inputs

VDD + 0.3

22

Input Low Voltage: Logic 0; All inputs

VIL

VOH

VOL

II

-0.3

2.4

–

0.8

–

V

Data Output High Voltage: Logic 1; All inputs

Data Output LOW Voltage: LOGIC 0; All inputs

0.4

5

V

Input Leakage Current:

-5

µA

Any Input 0V ≤ VIN ≤ VDD (All other pins not under test = 0V)

Output Leakage Current: DQs are disabled; 0V ≤ VOUT ≤ VDDQ

IOZ

-5

5

µA

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS - V VERSION

(Notes: 1, 5, 6; notes appear on page 39; VDD = 2.5 0.2V, VDDQ = +2.5V 0.2V or +1.8V 0.15V )

PARAMETER/CONDITION

Supply Voltage

SYMBOL

MIN

2.3

MAX UNITS NOTES

VDD

2.7

V

I/O Supply Voltage

VDDQ(2.5V)

2.3

VDDQ(1.8V)

1.65

1.25

-0.3

1.95

VDD + 0.3

+0.55

–

V

Input High Voltage: Logic 1; All inputs

VIH

VIL

VOH

VOL

II

V

22

Input Low Voltage: Logic 0; All inputs

V

Data Output High Voltage: Logic 1; All inputs

Data Output Low Voltage: LOGIC 0; All inputs

Input Leakage Current:

VDDQ - 0.2

–

V

0.2

V

-2

2

µA

Any input 0V ≤ VIN ≤ VDD (All other pins not under test = 0V)

Output Leakage Current: DQs are disabled; 0V ≤ VOUT ≤ VDDQ

IOZ

-5

5

µA

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

35

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

AC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(VDD = +3.3V 0.3V or 2.5 0.2V, VDDQ = +3.3V 0.3V or +2.5V 0.2V or +1.8V 0.15V )

PARAMETER/CONDITION

SYMBOL

VIH

MIN

1.4

–

MAX UNITS NOTES

Input High Voltage: Logic 1; All inputs

Input Low Voltage: Logic 0; All inputs

–

V

VIL

0.4

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(Notes: 5, 6, 8, 9, 11; notes appear on page 39)

AC CHARACTERISTICS

PARAMETER

Access time from CLK (pos. edge)

-8

-10

SYMBOL MIN

MAX

7

8

MIN MAX UNITS NOTES

CL = 3 ^tAC (3)

7

8

ns

ms

ns

–

27

CL = 2 ^tAC (2)

CL = 1 ^tAC (1)

19

22

Address hold time

Address setup time

CLK high-level width

CLK low-level width

Clock cycle time

^tAH

1

2.5

3

1

2.5

3

^tAS

^tCH

^tCL

3

CL = 3 ^tCK (3)

8

10

12

25

1

23

CL = 2 ^tCK (2)

10

20

1

CL = 1 ^tCK (1)

CKE hold time

^tCKH

CKE setup time

^tCKS

2.5

1

2.5

1

2.5

1

2.5

1

CS#, RAS#, CAS#, WE#, DQM hold time

CS#, RAS#, CAS#, WE#, DQM setup time

Data-in hold time

Data-in setup time

Data-out high-impedance time

^tCMH

^tCMS

^tDH

^tDS

2.5

CL = 3 ^tHZ (3)

7

8

19

7

8

22

10

CL = 2 ^tHZ (2)

CL = 1 ^tHZ (1)

Data-out low-impedance time

Data-out hold time (load)

^tLZ

^tOH

^tOH_N

^tRAS

^tRC

^tRCD

^tREF

^tRFC

^tRP

1

2.5

1.8

48

80

20

2.5

1.8

50

Data-out hold time (no load)

ACTIVE to PRECHARGE command

ACTIVE to ACTIVE command period

ACTIVE to READ or WRITE delay

Refresh period (4,096 rows)

AUTO REFRESH period

PRECHARGE command period

ACTIVE bank a to ACTIVE bank b command

Transition time

28

120,000

64

120,000

64

100

20

80

20

0.5

100

20

^tRRD

^tT

1.2

0.5

1.2

7

24

WRITE recovery time

^tWR 1 CLK +

7ns

1 CLK +

5ns

15

80

15

100

ns

25

20

Exit SELF REFRESH to ACTIVE command

^tXSR

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

36

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

AC FUNCTIONAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 11; notes appear on page 39)

PARAMETER

SYMBOL

^tCCD

^tCKED

^tPED

^tDQD

^tDQM

^tDQZ

-8

1

0

2

0

5

2

1

2

3

2

1

-10 UNITS NOTES

READ/WRITE command to READ/WRITE command

CKE to clock disable or power-down entry mode

CKE to clock enable or power-down exit setup mode

DQM to input data delay

1

0

2

0

5

2

1

2

3

2

1

^tCK

^tCK 15, 21

^tCK 16, 21

^tCK

^tCK 16, 21

17

14

17

DQM to data mask during WRITEs

DQM to data high-impedance during READs

WRITE command to input data delay

Data-in to ACTIVE command

^tDWD

^tDAL

Data-in to PRECHARGE command

Last data-in to burst STOP command

Last data-in to new READ/WRITE command

Last data-in to PRECHARGE command

LOAD MODE REGISTER command to ACTIVE or REFRESH command

Data-out to high-impedance from PRECHARGE command

^tDPL

^tBDL

17

^tCDL

^tRDL

^tMRD

^tROH(3)

^tROH(2)

^tROH(1)

^tCK

26

17

CL = 3

CL = 2

CL = 1

IDD SPECIFICATIONS AND CONDITIONS (x16)

(Notes: 1, 5, 6, 11, 13; notes appear on page 39; VDD = +3.3V 0.3V or 2.5 0.2V, VDDQ = +3.3V 0.3V or +2.5V

0.2V or +1.8V 0.15V )

MAX

PARAMETER/CONDITION

SYMBOL

-8

-10 UNITS NOTES

Operating Current: Active Mode;

IDD1

130 100

mA

3, 18,

19, 32

t

Burst = 2; READ or WRITE; RC = RC (MIN)

Standby Current: Power-Down Mode; All banks idle; CKE = LOW

Standby Current: Active Mode;

CKE = HIGH; CS# = HIGH; All banks active after RCD met;

No accesses in progress

IDD2

IDD3

350 350

µA

32

35

30

95

mA

3, 12,

19, 32

t

Operating Current: Burst Mode; Page burst;

READ or WRITE; All banks active

IDD4

100

mA

3, 18,

19, 32

t

Auto Refresh Current

CKE = HIGH; CS# = HIGH

RFC = RFC (MIN)

IDD5

IDD6

210 170

mA

3, 12,

18, 19,

32, 33

RFC = 15.625µs

3

IDD7 - SELF REFRESH CURRENT OPTIONS (x16)

(Notes: Note 4 appears on page 39) (VDD = +3.3V 0.3V or 2.5 0.2V, VDDQ) = +3.3V 0.3V or +2.5V 0.2V or

+1.8V 0.15V)

Temperature Compensated Self Refresh

Parameter/Condition

Max

Temperature

-8 and -10

UNITS NOTES

Self Refresh Current:

CKE < 0.2V

85ºC

70ºC

45ºC

15ºC

800

500

350

300

µA

4

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

37

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

IDD SPECIFICATIONS AND CONDITIONS (x32)

(Notes: 1, 5, 6, 11, 13; notes appear on page 39; VDD = +3.3V 0.3V or 2.5 0.2V, VDDQ = +3.3V 0.3V or +2.5V

0.2V or +1.8V 0.15V )

MAX

PARAMETER/CONDITION

SYMBOL

-8

-10 UNITS NOTES

Operating Current: Active Mode;

Burst = 2; READ or WRITE; RC = RC (MIN)

IDD1

150 120

mA

3, 18,

19, 32

t

Standby Current: Power-Down Mode;

All banks idle; CKE = LOW

IDD2

IDD3

350 350

µA

32

Standby Current: Active Mode;

CKE = HIGH; CS# = HIGH; All banks active after RCD met;

No accesses in progress

40

35

mA

3, 12,

19, 32

t

Operating Current: Burst Mode; Page burst;

READ or WRITE; All banks active

IDD4

115 110

220 180

mA

3, 18,

19, 32

t

Auto Refresh Current

CKE = HIGH; CS# = HIGH

RFC = RFC (MIN)

RFC = 15.625µs

IDD5

IDD6

mA

3, 12,

18, 19,

32, 33

t

3

IDD7 - SELF REFRESH CURRENT OPTIONS (x32)

(Notes: Note 4 appears on page 39) (VDD = +3.3V 0.3V or 2.5 0.2V, VDDQ) = +3.3V 0.3V or +2.5V 0.2V or

+1.8V 0.15V)

Temperature Compensated Self Refresh

Parameter/Condition

Max

Temperature

-8 and -10

UNITS NOTES

Self Refresh Current:

CKE < 0.2V

85ºC

70ºC

45ºC

15ºC

1000

550

400

350

µA

4

CAPACITANCE

(Note: 2; notes appear on page 39)

PARAMETER

SYMBOL MIN

MAX UNITS NOTES

Input Capacitance: CLK

CI1

CI2

CIO

2.5

4.0

3.5

3.8

6.0

pF

29

30

31

Input Capacitance: All other input-only pins

Input/Output Capacitance: DQs

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

38

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

NOTES

t

1. All voltages referenced to VSS.

2. This parameter is sampled. V^DD, VDDQ = +3.3V;

14. Timing actually specified by CKS; clock(s) specified

as a reference only at minimum cycle rate.

t

f = 1 MHz, T = 25°C; pin under test biased at 1.4V.

15. Timing actually specified by WR plus RP; clock(s)

specified as a reference only at minimum cycle rate.

A

3. IDD is dependent on output loading and cycle rates.

Specified values are obtained with minimum cycle

time and the outputs open.

4. Enables on-chip refresh and address counters.

5. The minimum specifications are used only to

indicate cycle time at which proper operation over

t

16. Timing actually specified by WR.

17. Required clocks are specified by JEDEC functionality

and are not dependent on any timing parameter.

18. The I^DDcurrent will increase or decrease propor-

tionally according to the amount of frequency alter-

ation for the test condition.

the full temperature range (-40°C ≤ T ≤ +85°C for

IT parts) is ensured.

A

19. Address transitions average one transition every two

clocks.

6. An initial pause of 100µs is required after power-up,

followed by two AUTO REFRESH commands, before

proper device operation is ensured. (V^DDand VDDQ

must be powered up simultaneously. VSS and VSSQ

mustbeatsamepotential.)ThetwoAUTOREFRESH

command wake-ups should be repeated any time

20. CLK must be toggled a minimum of two times during

this period.

t

21. Based on CK =8ns for -8 and CK =10ns for -10.

22. V^IHovershoot: VIH (MAX) = VDDQ + 2V for a pulse width

≤ 3ns, and the pulse width cannot be greater than one

third of the cycle rate. VIL undershoot: VIL (MIN) = -2V

for a pulse width ≤ 3ns.

t

the REF refresh requirement is exceeded.

t

7. AC characteristics assume T = 1ns.

8. In addition to meeting the transition rate specifica-

tion, theclockandCKEmusttransitbetweenV^IHand

VIL (or between VIL and VIH) in a monotonic manner.

9. Outputs measured for 3.3V at1.5V or 2.5V at 1.25V

with equivalent load:

23. The clock frequency must remain constant (stable

clock is defined as a signal cycling within timing

constraints specified for the clock pin) during access

t

or precharge states (READ, WRITE, including WR,

and PRECHARGE commands). CKE may be used to

reduce the data rate.

24. Auto precharge mode only. The precharge timing

Q

t

budget ( RP) begins at 7ns for -8 after the first clock

30pF

delay, after the last WRITE is executed. May not ex-

ceed limit set for precharge mode.

25. Precharge mode only.

26. JEDEC and PC100 specify three clocks.

27. AC for -8 at CL = 3 with no load is 7ns and is guaran-

t

10. HZ defines the time at which the output achieves the

t

open circuit condition; it is not a reference to V^OHor

VOL. The last valid data element will meet OH before

going High-Z.

teed by design.

t

28. Parameter guaranteed by design.

29. PC100 specifies a maximum of 4pF.

30. PC100 specifies a maximum of 5pF.

31. PC100 specifies a maximum of 6.5pF.

11. AC timing and IDD tests have VIL and VIH, with timing

referenced to VIH/2 = crossover point. If the input

transition time is longer than t (MAX), then the

t

T

32. For -8, CL = 2 and CK = 10ns; for -10, CL = 3 and

timing is referenced at VIL (MAX) and VIH (MIN) and

no longer at the VIH/2 crossover point.

12. Other input signals are allowed to transition no more

than once every two clocks and are otherwise at valid

VIH or VIL levels.

t

CK =10ns.

33. CKE is HIGH during refresh command period

t

RFC (MIN) else CKE is LOW. The IDD6 limit is actu-

ally a nominal value and does not result in a fail

value.

13. IDD specifications are tested after the device is prop-

erly initialized.

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

39

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

INITIALIZE AND LOAD MODE REGISTER^1,2

T1

T0

T3

T5

T7

T9

T19

T29

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

CLK

t

CK

t

CKS CKH

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

CKE

COMMAND⁵

DQML, DQMU

t

CMS CMH

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

4

3

4

ACT

NOP

PRE

LMR

PRE

AR

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

t

AS AH

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

A0-A9, A11

A10

CODE

RA

BA

ALL BANKS

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

CODE

t

AS

t

AH

t

AH

t

AH

t

AS

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

BA0 = L,

BA1 = H

BA0 = L,

BA1 = L

BA0, BA1

DQ

High-Z

( (

) )

((

))

((

))

((

))

((

))

((

))

((

))

T = 100µs

t

RP

t

RFC

RP

MRD

RFC

Power-up:

DD and

CLK stable

Load Extended

Mode Register

Load Mode

Register

V

DON’T CARE

NOTE:

1. The two AUTO REFRESH commands at T9 and T19 may be applied before either LOAD MODE REGISTER (LMR) command.

2. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE command, RA = Row Address,

BA = Bank Address

3. Optional refresh command.

4. The Load Mode Register for both MR/EMR and 2 Auto Refresh commands can be in any order. However, all must occur prior to an Active command.

5. Device timing is -10 with 100 MHz clock.

TIMING PARAMETERS

-8

-10

-8

-10

SYMBOL*

MIN

1

MAX

MIN

1

MAX UNITS

SYMBOL*

MIN

1

MAX

MIN

1

MAX UNITS

t

AH

ns

CKH

ns

t

AS

2.5

3

2.5

3

CKS

2.5

1

2.5

1

t

CH

CMH

t

CL

3

CMS

2.5

2

2.5

2

t

3

t

CK (3)

8

10

12

25

MRD

RFC

RP

CK

t

CK (2)

10

20

80

20

100

20

ns

t

CK (1)

*CAS latency indicated in parentheses.

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

40

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

POWER-DOWN MODE¹

T0

T1

T2

Tn + 1

Tn + 2

( (

t

) )

CK

CL

CLK

CKE

( (

) )

t

CH

t

CKS

( (

) )

t

CKS

CKH

t

CMS CMH

PRECHARGE

( (

) )

( (

) )

COMMAND

NOP

ACTIVE

( (

) )

( (

) )

DQML, DQMU

( (

) )

( (

) )

A0-A9, A11

A10

ROW

ALL BANKS

( (

) )

( (

) )

SINGLE BANK

t

AH

AS

( (

) )

( (

) )

BA0, BA1

DQ

BANK

BANK(S)

High-Z

( (

) )

Two clock cycles

Input buffers gated off while in

power-down mode

Precharge all

active banks

All banks idle

All banks idle, enter

power-down mode

Exit power-down mode

DON’T CARE

TIMING PARAMETERS

-8

-10

MAX UNITS

-8

-10

SYMBOL*

MIN

1

MAX

MIN

1

SYMBOL*

MIN

MAX

MIN

25

1

MAX UNITS

t

AH

ns

CK (1)

20

1

ns

t

AS

2.5

3

2.5

3

CKH

t

CH

CKS

2.5

1

2.5

1

t

CL

3

CMH

t

CK (3)

8

10

12

CMS

2.5

t

CK (2)

10

*CAS latency indicated in parentheses.

NOTE: 1. Violating refresh requirements during power-down may result in a loss of data.

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

41

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

CLOCK SUSPEND MODE¹

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

t

CK

t

CL

CLK

CKE

t

CH

t

CKS CKH

t

CKS

CKH

t

CMS

CMH

COMMAND

READ

NOP

WRITE

NOP

t

CMS

CMH

DQMU, DQML

A0-A9, A11

t

AH

AS

2

COLUMN m

COLUMN e

t

AS

t

AH

A10

t

AS

t

AH

BA0, BA1

BANK

t

AC

t

AC

t

OH

t

HZ

t

DS

t

DH

D

OUT

m

D

OUT m + 1

D

OUT

e

DOUT e + 1

DQ

t

LZ

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-8

-10

-8

-10

MAX UNITS

SYMBOL*

MIN

1

MAX

MIN

MAX UNITS

SYMBOL*

MIN

MAX

MIN

t

AC (3)

7

8

7

8

ns

CKH

1

2.5

1

ns

t

AC (2)

CKS

2.5

1

t

AC (1)

19

22

CMH

t

AH

1

2.5

3

1

2.5

3

CMS

2.5

1

2.5

1

t

AS

DH

t

CH

DS

2.5

t

CL

3

HZ (3)

7

8

7

8

ns

t

CK (3)

8

10

12

HZ (2)

t

CK (2)

10

HZ (1)

19

22

t

LZ

1

CK (1)

20

25

ns

t

OH

2.5

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 2, the CAS latency = 3, and auto precharge is disabled.

2. x16: A9 and A11 = “Don’t Care”

x32: A8, A9 and A11 = “Don’t Care”

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

42

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

AUTO REFRESH MODE

T0

T1

T2

Tn + 1

CL

To + 1

( (

) )

( (

) )

t

CLK

CKE

t

( (

CK

CH

) )

( (

) )

( (

) )

t

CKS

CKH

t

CMS

CMH

( (

) )

( (

) )

AUTO

REFRESH

AUTO

REFRESH

COMMAND

PRECHARGE

NOP

ACTIVE

( (

) )

( (

) )

( (

) )

DQMU, DQML

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

A0-A9, A11

A10

ROW

ALL BANKS

( (

) )

( (

) )

( (

) )

( (

) )

SINGLE BANK

t

AH

AS

( (

) )

( (

) )

BANK(S)

BA0, BA1

DQ

BANK

( (

) )

High-Z

( (

) )

( (

) )

t

1

RFC

1

RP

RFC

Precharge all

active banks

DON’T CARE

TIMING PARAMETERS

-8

-10

-8

-10

SYMBOL*

MIN

1

MAX

MIN

1

MAX UNITS

SYMBOL*

MIN

20

1

MAX

MIN

25

MAX UNITS

t

AH

ns

CK (1)

ns

t

AS

2.5

3

2.5

3

CKH

1

t

CH

CKS

2.5

1

2.5

1

t

CL

3

CMH

t

CK (3)

8

10

12

CMS

2.5

80

20

2.5

100

20

t

CK (2)

10

RFC

t

RP

*CAS latency indicated in parentheses.

NOTE: 1. Each AUTO REFRESH command performs a refresh cycle. Back-to-back commands are not required.

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

43

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

SELF REFRESH MODE

T0

T1

T2

Tn + 1

To + 1

To + 2

( (

) )

( (

) )

t

CL

CLK

CKE

t

( (

) )

( (

) )

t

CH

CK

t

> t

CKS

RAS

( (

) )

( (

) )

( (

) )

t

CKS

CKH

t

CMS

CMH

( (

) )

( (

) )

( (

) )

AUTO

REFRESH

AUTO

REFRESH

COMMAND

PRECHARGE

NOP

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

DQMU, DQML

( (

) )

( (

) )

( (

) )

( (

) )

A0-A9, A11

A10

ALL BANKS

( (

) )

( (

) )

( (

) )

( (

) )

SINGLE BANK

t

AH

AS

( (

) )

( (

) )

( (

) )

( (

) )

BA0, BA1

DQ

BANK(S)

High-Z

( (

) )

( (

) )

t

XSR

RP

Precharge all

active banks

Enter self refresh mode

Exit self refresh mode

(Restart refresh time base)

DON’T CARE

CLK stable prior to exiting

self refresh mode

TIMING PARAMETERS

-8

-10

MAX UNITS

-8

-10

SYMBOL*

MIN

1

MAX

MIN

1

SYMBOL*

MIN

1

MAX

MIN

1

MAX UNITS

t

AH

ns

CKH

CKS

CMH

CMS

RAS

RP

ns

t

AS

2.5

3

2.5

3

2.5

1

2.5

1

t

CH

t

CL

3

2.5

48

20

80

2.5

50

t

CK (3)

8

10

12

25

120,000

ns

t

CK (2)

10

20

t

CK (1)

XSR

100

*CAS latency indicated in parentheses.

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

44

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

READ – WITHOUT AUTO PRECHARGE¹

T0

T1

T2

T3

T4

T5

T6

T7

T8

t

CK

t

CL

CLK

t

CH

t

CKS

CKH

CKE

t

CMS CMH

COMMAND

ACTIVE

NOP

READ

NOP

PRECHARGE

NOP

ACTIVE

ROW

t

CMS CMH

DQMU, DQML

A0-A9, A11

t

AH

AS

2

ROW

COLUMN m

t

AS

t

AH

ALL BANKS

ROW

A10

SINGLE BANKS

BANK(S)

DISABLE AUTO PRECHARGE

BANK

t

AS

t

AH

BA0, BA1

BANK

t

AC

t

AC

t

AC

t

AC

t

OH

t

OH

t

OH

t

OH

DOUT

m

D

OUT m+1

D

OUT m+2

DOUT m+3

DQ

t

LZ

t

HZ

t

RCD

CAS Latency

RP

t

RAS

t

RC

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-8

-10

MAX UNITS

-8

-10

SYMBOL*

MIN

MAX

MIN

SYMBOL*

MIN

MAX

MIN

1

MAX UNITS

t

AC (3)

7

8

7

8

ns

CMH

1

ns

t

AC (2)

CMS

2.5

t

AC (1)

19

22

HZ (3)

7

8

7

8

ns

t

AH

1

2.5

3

1

2.5

3

HZ (2)

t

AS

HZ (1)

19

22

t

CH

LZ

1

t

CL

3

OH

2.5

48

80

20

2.5

50

t

CK (3)

8

10

12

25

1

RAS

120,000

t

CK (2)

10

20

1

RC

100

20

t

CK (1)

RCD

t

CKH

RP

20

t

CKS

2.5

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual”

PRECHARGE.

2. x16: A9 and A11 = “Don’t Care”

x32: A8, A9,and A11 = “Don’t Care”

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

45

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

READ – WITH AUTO PRECHARGE¹

T0

T1

T2

T3

T4

T5

T6

T7

T8

t

CK

t

CL

CLK

CKE

t

CH

t

CKS

CKH

t

CMS CMH

COMMAND

DQMU, DQML

A0-A9, A11

ACTIVE

NOP

READ

t

NOP

ACTIVE

t

CMS

CMH

t

AH

AS

2

ROW

COLUMN m

t

AS

t

AH

ENABLE AUTO PRECHARGE

ROW

A10

t

AS

t

AH

BA0, BA1

BANK

t

AC

t

AC

t

AC

t

AC

t

OH

t

OH

t

OH

t

OH

DOUT

m

DOUT

m

+ 1

DOUT

m

+ 2

DOUT m + 3

DQ

t

LZ

t

HZ

t

RP

RCD

CAS Latency

t

RAS

t

RC

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-8

-10

MAX UNITS

-8

-10

SYMBOL*

MIN

MAX

MIN

SYMBOL*

MIN

1

MAX

MIN

1

MAX UNITS

t

AC (3)

7

8

7

8

ns

CMH

ns

t

AC (2)

CMS

2.5

t

AC (1)

19

22

HZ (3)

7

8

7

8

ns

t

AH

1

2.5

3

1

2.5

3

HZ (2)

t

AS

HZ (1)

19

22

t

CH

LZ

1

t

CL

3

OH

2.5

48

80

20

2.5

50

70

20

t

CK (3)

8

10

12

25

1

RAS

120,000

t

CK (2)

10

20

1

RC

t

CK (1)

RCD

t

CKH

RP

t

CKS

2.5

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.

2. x16: A9 and A11 = “Don’t Care”

x32: A8, A9,and A11 = “Don’t Care”

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

46

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

SINGLE READ – WITHOUT AUTO PRECHARGE¹

T0

T1

T2

T3

T4

T5

T6

T7

T8

t

CK

t

CL

CLK

t

CH

t

CKS

CKH

CKE

t

CMS CMH

3

COMMAND

PRECHARGE

ACTIVE

NOP

READ

NOP

ACTIVE

ROW

NOP

t

CMS CMH

DQMU, DQML

A0-A9, A11

t

AH

AS

COLUMN m²

ROW

t

AS

t

AH

ALL BANKS

ROW

A10

DISABLE AUTO PRECHARGE

BANK

SINGLE BANKS

BANK(S)

t

AS

t

AH

BA0, BA1

BANK

t

AC

t

OH

D

OUT m

DQ

t

LZ

t

HZ

t

RCD

CAS Latency

RP

t

RAS

t

RC

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-8

-10

MAX UNITS

-8

-10

SYMBOL*

MIN

MAX

MIN

SYMBOL*

MIN

1

MAX

MIN

1

MAX UNITS

t

AC (3)

7

8

7

8

ns

CMH

CMS

ns

t

AC (2)

2.5

t

AC (1)

19

22

HZ (3)

HZ (2)

HZ (1)

LZ

7

8

7

8

ns

t

AH

1

2.5

3

1

2.5

3

t

AS

19

22

t

CH

1

t

CL

3

OH

2.5

48

80

20

2.5

50

t

CK (3)

8

10

12

25

1

RAS

RC

120,000

t

CK (2)

10

20

1

100

20

t

CK (1)

RCD

RP

t

CKH

20

t

CKS

2.5

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 1, the CAS latency = 2, and the READ burst is followed by a “manual”

PRECHARGE.

2. x16: A9 and A11 = “Don’t Care”

x32: A8, A9,and A11 = “Don’t Care”

3. PRECHARGE command not allowed or ^tRAS would be violated.

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

47

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

SINGLE READ – WITH AUTO PRECHARGE¹

T0

T1

T2

T3

T4

T5

T6

T7

T8

t

CK

t

CL

CLK

CKE

t

CH

t

CKS

CKH

t

CMS CMH

3

COMMAND

DQMU, DQML

A0-A9, A11

ACTIVE

NOP

READ

t

NOP

ACTIVE

NOP

t

CMS

CMH

t

AH

AS

2

ROW

COLUMN m

t

AS

t

AH

ENABLE AUTO PRECHARGE

ROW

A10

t

AS

t

AH

BA0, BA1

BANK

t

AC

t

OH

D

OUT

m

DQ

t

CAS Latency

t

HZ

RCD

t

RP

t

RAS

t

RC

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-8

-10

MAX UNITS

-8

-10

SYMBOL*

MIN

MAX

MIN

SYMBOL*

MIN

MAX

MIN

1

MAX UNITS

t

AC (3)

7

8

7

8

ns

CMH

CMS

HZ (3)

HZ (2)

HZ (1)

LZ

1

ns

t

AC (2)

2.5

t

AC (1)

19

22

7

8

7

8

ns

t

AH

1

2.5

3

1

2.5

3

t

AS

19

22

t

CH

1

t

CL

3

OH

2.5

48

80

20

2.5

50

t

CK (3)

8

10

12

25

1

RAS

RC

120,000

t

CK (2)

10

20

1

100

20

t

CK (1)

RCD

RP

t

CKH

20

t

CKS

2.5

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 1, and the CAS latency = 2.

2. x16: A9 and A11 = “Don’t Care”

x32: A8, A9,and A11 = “Don’t Care”

3. READ command not allowed else ^tRAS would be violated.

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

48

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

ALTERNATING BANK READ ACCESSES¹

T0

T1

T2

T3

T4

T5

T6

T7

T8

t

CK

t

CL

CLK

t

CH

t

CKS

CKH

CKE

COMMAND

t

CMS

CMH

ACTIVE

NOP

READ

t

NOP

ACTIVE

NOP

READ

NOP

ACTIVE

t

CMS

CMH

DQMU, DQML

A0-A9, A11

t

AH

AS

2

ROW

COLUMN m

COLUMN b

t

AS

t

AH

ENABLE AUTO PRECHARGE

ROW

A10

t

AS

t

AH

BA0, BA1

BANK 0

BANK 3

t

BANK 3

BANK 0

t

AC

t

AC

t

AC

t

AC

t

OH

t

OH

t

OH

t

OH

t

OH

DOUT

m

DOUT m + 1

DOUT m + 2

D

OUT m + 3

DOUT b

DQ

t

LZ

t

RCD - BANK 0

t

RCD - BANK 0

CAS Latency - BANK 0

RP - BANK 0

t

RAS - BANK 0

t

RC - BANK 0

t

RCD - BANK 3

CAS Latency - BANK 3

RRD

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-8

-10

-8

-10

SYMBOL*

MIN

MAX

MIN

MAX UNITS

SYMBOL*

MIN

2.5

1

MAX

MIN

2.5

1

MAX UNITS

t

AC (3)

7

8

7

8

ns

CKS

ns

t

AC (2)

CMH

t

AC (1)

19

22

CMS

2.5

1

2.5

1

t

AH

1

2.5

3

1

2.5

3

LZ

t

AS

OH

2.5

48

80

20

2.5

50

t

CH

RAS

120,000

ns

t

CL

3

RC

100

20

t

CK (3)

8

10

12

25

1

RCD

t

CK (2)

10

20

1

RP

20

t

CK (1)

RRD

20

t

CKH

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.

2. x16: A9 and A11 = “Don’t Care”

x32: A8, A9,and A11 = “Don’t Care”

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

49

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

READ – FULL-PAGE BURST¹

T0

T1

T2

T3

T4

T5

T6

Tn + 1

Tn + 2

Tn + 3

Tn + 4

( (

) )

( (

) )

t

CL

t

CK

CLK

t

CH

t

CKS

CKH

( (

) )

CKE

( (

) )

t

CMS

CMH

( (

) )

( (

) )

COMMAND

ACTIVE

NOP

READ

t

NOP

BURST TERM

NOP

t

CMS

CMH

( (

) )

DQMU, DQML

A0-A9, A11

( (

) )

t

AS

t

AH

( (

) )

( (

) )

2

ROW

COLUMN m

t

AS

t

AH

( (

) )

( (

) )

ROW

A10

t

AS

t

AH

( (

) )

( (

) )

BA0, BA1

BANK

t

AC

( (

) )

t

AC

t

OH

t

OH

( (

) )

( (

) )

D

OUT

m

D

OUT m+1

D

OUT m+2

D

OUT m-1

D

OUT

m

DOUT m+1

DQ

t

LZ

t

HZ

512 (x16) locations within same row

t

RCD

CAS Latency

Full page completed

DON’T CARE

Full-page burst does not self-terminate.

Can use BURST TERMINATE command. ³

UNDEFINED

TIMING PARAMETERS

-8

-10

-8

-10

SYMBOL*

MIN

MAX

MIN

MAX UNITS

SYMBOL*

MIN

1

MAX

MIN

1

MAX UNITS

t

AC (3)

7

8

7

8

ns

CKH

ns

t

AC (2)

CKS

2.5

1

2.5

1

t

AC (1)

19

22

CMH

t

AH

1

2.5

3

1

2.5

3

CMS

2.5

t

AS

HZ (3)

7

8

7

8

ns

t

CH

HZ (2)

t

CL

3

HZ (1)

19

22

t

CK (3)

8

10

12

25

LZ

1

t

CK (2)

10

20

OH

2.5

20

2.5

20

t

CK (1)

ns

RCD

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the CAS latency = 2.

2. x16: A9 and A11 = “Don’t Care”

x32: A8, A9,and A11 = “Don’t Care”

3. Page left open; no ^tRP.

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

50

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

READ – DQM OPERATION¹

T0

T1

T2

T3

T4

T5

T6

T7

T8

t

CL

CK

CLK

t

CH

t

CKS

CKH

CKE

t

CMS

CMH

COMMAND

ACTIVE

NOP

READ

t

NOP

t

CMS CMH

DQMU, DQML

t

AS

t

AH

2

A0-A9, A11

A10

ROW

COLUMN m

t

AH

AS

ENABLE AUTO PRECHARGE

ROW

DISABLE AUTO PRECHARGE

BANK

t

AS

t

AH

BA0, BA1

BANK

t

AC

t

OH

AC

OH

AC

OH

D

OUT

m

D

OUT m + 2

DOUT m + 3

DQ

t

LZ

t

HZ

LZ

HZ

t

RCD

CAS Latency

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-8

-10

MAX UNITS

-8

-10

SYMBOL*

MIN

MAX

MIN

SYMBOL*

MIN

1

MAX

MIN

MAX UNITS

t

AC (3)

7

8

7

8

ns

CKH

1

ns

t

AC (2)

CKS

2.5

1

2.5

1

t

AC (1)

19

22

CMH

t

AH

1

2.5

3

1

2.5

3

CMS

2.5

t

AS

HZ (3)

7

8

7

8

ns

t

CH

HZ (2)

t

CL

3

HZ (1)

19

22

t

CK (3)

8

10

12

25

LZ

1

t

CK (2)

10

20

OH

2.5

20

2.5

20

t

CK (1)

RCD

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.

2. x16: A9 and A11 = “Don’t Care”

x32: A8, A9,and A11 = “Don’t Care”

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

51

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

WRITE – WITHOUT AUTO PRECHARGE¹

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

t

CL

CK

CLK

CKE

t

CH

t

CKS

CKH

t

CMS

CMH

COMMAND

NOP

ACTIVE

NOP

WRITE

NOP

PRECHARGE

NOP

ACTIVE

t

CMS

CMH

DQMU, DQML

A0-A9, A11

t

AH

AS

3

ROW

t

ROW

BANK

COLUMN m

AS

AH

ALL BANKS

ROW

t

A10

DISABLE AUTO PRECHARGE

BANK

SINGLE BANK

BANK

AS

AH

BA0, BA1

BANK

t

DH

DS

DH

DS

DH

DS

DH

DS

D

IN

m

D

IN m + 1

D

IN m + 2

D

IN m + 3

DQ

2

t

RCD

RP

WR

t

RAS

t

RC

DON’T CARE

TIMING PARAMETERS

-8

-10

-8

-10

SYMBOL*

MAX

1

MIN

MAX UNITS

SYMBOL*

MIN

1

MAX

MIN

1

MAX UNITS

t

AH

1

2.5

3

ns

CMH

ns

t

AS

2.5

3

CMS

2.5

1

2.5

1

t

CH

DH

t

CL

3

DS

2.5

48

80

20

15

2.5

50

100

20

15

t

CK (3)

8

10

12

25

1

RAS

120,000

ns

t

CK (2)

10

20

1

RC

t

CK (1)

RCD

t

CKH

RP

t

CKS

2.5

WR

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 4, and the WRITE burst is followed by a “manual” PRECHARGE.

2. 15ns is required between <DIN m + 3> and the PRECHARGE command, regardless of frequency.

3. x16: A9 and A11 = “Don’t Care”

x32: A8, A9,and A11 = “Don’t Care”

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

52

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

WRITE – WITH AUTO PRECHARGE¹

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

t

CL

CK

CLK

CKE

t

CH

t

CKS

CKH

t

CMS

CMH

COMMAND

DQMU, DQML

A0-A9, A11

ACTIVE

NOP

WRITE

NOP

ACTIVE

t

CMS

CMH

t

AS

AH

2

ROW

BANK

COLUMN m

t

AH

AS

ENABLE AUTO PRECHARGE

ROW

t

A10

t

AS

AH

BA0, BA1

BANK

t

DS

DH

DS

DH

DS

DH

DS

DH

D

IN

m

D

IN m + 1

D

IN m + 2

DIN m + 3

DQ

t

RP

t

RCD

WR

t

RAS

t

RC

DON’T CARE

TIMING PARAMETERS

-8

-10

-8

-10

SYMBOL*

MIN

1

MAX

MIN

MAX UNITS

SYMBOL*

MIN

2.5

MAX

MIN

2.5

MAX UNITS

t

AH

1

2.5

3

ns

CMS

ns

–

t

AS

2.5

3

DH

1

t

CH

DS

2.5

t

CL

3

RAS

48

120,000

50

120,000

t

CK (3)

8

10

12

25

1

RC

80

100

20

t

CK (2)

10

20

1

RCD

20

t

CK (1)

RP

20

t

CKH

WR

1 CLK +

7ns

1 CLK +

5ns

t

CKS

2.5

1

2.5

1

t

CMH

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 4.

2. x16: A9 and A11 = “Don’t Care”

x32: A8, A9,and A11 = “Don’t Care”

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

53

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

SINGLE WRITE – WITHOUT AUTO PRECHARGE¹

T0

T1

T2

T3

T4

T5

T6

T7

T8

t

CL

CK

CLK

CKE

t

CH

t

CKS

CKH

t

CMS

CMH

4

COMMAND

ACTIVE

NOP

WRITE

NOP

PRECHARGE

NOP

ACTIVE

NOP

t

CMS

CMH

DQMU, DQML

A0-A9, A11

t

AH

AS

3

ROW

t

COLUMN m

AS

AH

ALL BANKS

ROW

t

ROW

A10

DISABLE AUTO PRECHARGE

BANK

SINGLE BANK

BANK

AS

AH

BA0, BA1

BANK

t

DH

DS

DIN

m

DQ

t

RP

2

t

RCD

WR

t

RAS

t

RC

DON’T CARE

TIMING PARAMETERS

-8

-10

-8

-10

SYMBOL*

MIN

1

MAX

MIN

1

MAX UNITS

SYMBOL*

MIN

1

MAX

MIN

1

MAX UNITS

t

AH

ns

CMH

CMS

DH

ns

t

AS

2.5

3

2.5

3

2.5

1

2.5

1

t

CH

t

CL

3

DS

2.5

48

80

20

15

2.5

50

100

20

15

t

CK (3)

8

10

12

25

1

RAS

RC

120,000

ns

t

CK (2)

10

20

1

t

CK (1)

RCD

RP

t

CKH

t

CKS

2.5

WR

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 1, and the WRITE burst is followed by a “manual” PRECHARGE.

2. 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency.

3. x16: A9 and A11 = “Don’t Care”

x32: A8, A9,and A11 = “Don’t Care”

4. PRECHARGE command not allowed else ^tRAS would be violated.

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

54

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

SINGLE WRITE – WITH AUTO PRECHARGE¹

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

t

CL

CK

CLK

CKE

t

CH

t

CKS

CKH

t

CMS

CMH

3

NOP

COMMAND

NOP

ACTIVE

NOP

WRITE

t

NOP

t

CMS

CMH

DQMU, DQML

A0-A9, A11

t

AS

AH

2

ROW

BANK

COLUMN m

t

AH

AS

ENABLE AUTO PRECHARGE

ROW

t

A10

t

AS

AH

BA0, BA1

BANK

t

DH

DS

D

IN m

DQ

t

RP

t

RCD

WR

t

RAS

t

RC

DON’T CARE

TIMING PARAMETERS

-8

-10

-8

-10

SYMBOL*

MIN

1

MAX

MIN

MAX UNITS

SYMBOL*

MIN

2.5

MAX

MIN

2.5

MAX UNITS

t

AH

1

2.5

3

ns

CMS

ns

–

t

AS

2.5

3

DH

1

t

CH

DS

2.5

t

CL

3

RAS

48

120,000

50

120,000

t

CK (3)

8

10

12

25

1

RC

80

100

20

t

CK (2)

10

20

1

RCD

20

t

CK (1)

RP

20

t

CKH

WR

1 CLK +

7ns

1 CLK +

5ns

t

CKS

2.5

1

2.5

1

t

CMH

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 1.

2. x16: A9 and A11 = “Don’t Care”

x32: A8, A9,and A11 = “Don’t Care”

3. WRITE command not allowed else ^tRAS would be violated.

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

55

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

ALTERNATING BANK WRITE ACCESSES¹

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

t

CL

CK

CLK

t

CH

t

CKS

CKH

CKE

t

CMS

CMH

COMMAND

ACTIVE

NOP

WRITE

NOP

ACTIVE

NOP

WRITE

NOP

ACTIVE

t

CMS

CMH

DQMU, DQML

A0-A9, A11

t

AH

AS

2

ROW

COLUMN m

COLUMN b

t

AS

t

AH

ENABLE AUTO PRECHARGE

ROW

A10

t

AS

t

AH

BA0, BA1

BANK 0

BANK 1

t

BANK 1

BANK 0

t

DS

DH

DS

DH

DS

DH

DS

DH

DS

DH

DS

DH

DS

DH

DS

DH

D

IN

m

D

IN m + 1

D

IN m + 2

D

IN m + 3

D

IN

b

D

IN b + 1

D

IN b + 2

D

IN b + 3

DQ

t

RCD - BANK 0

WR - BANK 0

RP - BANK 0

RCD - BANK 0

t

RAS - BANK 0

t

RC - BANK 0

t

WR - BANK 1

t

RCD - BANK 1

RRD

DON’T CARE

TIMING PARAMETERS

-8

-10

-8

-10

SYMBOL*

MIN

1

MAX

MIN

MAX UNITS

SYMBOL*

MIN

2.5

1

MAX

MIN

2.5

1

MAX UNITS

t

AH

1

2.5

3

ns

CMS

DH

ns

t

AS

2.5

3

t

CH

DS

2.5

48

2.5

50

t

CL

3

RAS

RC

120,000

ns

–

t

CK (3)

8

10

12

25

1

80

100

20

t

CK (2)

10

20

1

RCD

RP

20

t

CK (1)

20

t

CKH

RRD

WR

20

t

CKS

2.5

1

2.5

1

1 CLK +

7ns

1 CLK +

5ns

t

CMH

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 4.

2. x16: A9 and A11 = “Don’t Care”

x32: A8, A9,and A11 = “Don’t Care”

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

56

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

WRITE – FULL-PAGE BURST

T0

T1

T2

T3

T4

T5

Tn + 1

Tn + 2

Tn + 3

( (

) )

( (

) )

t

CL

t

CK

CLK

t

CH

t

CKS

CKH

( (

) )

CKE

( (

) )

t

CMS

CMH

( (

) )

( (

) )

COMMAND

ACTIVE

NOP

WRITE

t

NOP

BURST TERM

NOP

t

CMH

CMS

( (

) )

DQMU, DQML

A0-A9, A11

( (

) )

t

AS

t

AH

( (

) )

( (

) )

1

ROW

COLUMN m

t

AS

t

AH

( (

) )

( (

) )

ROW

A10

t

AS

t

AH

( (

) )

( (

) )

BA0, BA1

BANK

t

DS

DH

DS

DH

DS

DH

DS

DH

DS

DH

( (

) )

D

IN

m

D

IN m + 1

D

IN m + 2

D

IN m + 3

DIN m - 1

DQ

( (

) )

t

RCD

Full-page burst does not

self-terminate. Can use

BURST TERMINATE

512 (x16) locations within same row

command to stop.^{2, 3}

Full page completed

DON’T CARE

TIMING PARAMETERS

-8

-10

-8

-10

SYMBOL*

MIN

1

MAX

MIN

1

MAX UNITS

SYMBOL*

MIN

1

MAX

MIN

1

MAX UNITS

t

AH

ns

CKH

ns

t

AS

2.5

3

2.5

3

CKS

2.5

1

2.5

1

t

CH

CMH

t

CL

3

CMS

2.5

1

2.5

1

t

CK (3)

8

10

12

25

DH

t

CK (2)

10

20

DS

2.5

20

2.5

20

t

CK (1)

RCD

*CAS latency indicated in parentheses.

NOTE: 1. x16: A9 and A11 = “Don’t Care”

x32: A8, A9,and A11 = “Don’t Care”

t

2. WR must be satisfied prior to PRECHARGE command.

3. Page left open; no ^tRP.

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

57

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

WRITE – DQM OPERATION¹

T0

T1

T2

T3

T4

T5

T6

T7

t

CL

CK

CLK

CKE

t

CH

t

CKS

CKH

t

CMS

CMH

COMMAND

ACTIVE

NOP

WRITE

t

NOP

t

CMS CMH

DQMU, DQML

t

AH

AS

2

A0-A9, A11

ROW

t

COLUMN m

AS

AH

ENABLE AUTO PRECHARGE

ROW

t

A10

DISABLE AUTO PRECHARGE

BANK

AS

AH

BA0, BA1

BANK

t

DS

DH

DS

DH

DS

DH

D

IN

m

D

IN m + 2

DIN m + 3

DQ

t

RCD

DON’T CARE

TIMING PARAMETERS

-8

-10

-8

-10

SYMBOL*

MIN

MAX

MIN

1

MAX UNITS

SYMBOL*

MIN

1

MAX

MIN

1

MAX UNITS

t

AH

1

2.5

3

ns

CKH

ns

t

AS

2.5

3

CKS

2.5

1

2.5

1

t

CH

CMH

t

CL

3

CMS

2.5

1

2.5

1

t

CK (3)

8

10

12

25

DH

t

CK (2)

10

20

DS

2.5

20

2.5

20

t

CK (1)

RCD

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 4.

2. x16: A9 and A11 = “Don’t Care”

x32: A8, A9,and A11 = “Don’t Care”

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

58

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

54-BALL VFBGA (8mm x 9mm)

0.70 0.075

SEATING PLANE

0.08 C

C

54X ∅0.35

SOLDER BALL DIAMETER

REFERS TO POST REFLOW

CONDITION. THE PRE-

REFLOW DIAMETER IS Ø 0.33

BALL A9

6.40

0.80

TYP

1.0 MAX

BALL A1 ID

BALL A1

BALL A1 ID

0.80

TYP

6.40

9.00 0.10

C

L

3.20 0.05

4.50 0.05

C

L

3.20 0.05

4.00 0.05

8.00 0.10

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE: PLASTIC LAMINATE

SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or

62% Sn, 36% Pb, 2%Ag

SOLDER BALL PAD: Ø .27mm

NOTE: 1. All dimensions in millimeters.

2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

59

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

90-BALL FBGA (11mm x 13mm)

.850 .075

.10

C

SEATING PLANE

C

SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb.

Or 62% Sn, 36% Pb, 2% Ag

SOLDER BALL PAD: Ø .33mm

11.00 .10

6.40

.80

SUBSTRATE: PLASTIC LAMINATE

ENCAPSULATION MATERIAL: EPOXY NOVOLAC

90X Ø 0.45

SOLDER BALL DIAMETER REFERS

TO POST REFLOW CONDITION.

THE PRE-REFLOW DIAMETER IS Ø 0.40mm

BALL A1 ID

TYP

BALL A9

BALL A1

6.50 .05

13.00 .10

C

L

11.20

.80

5.60 .05

TYP

C

L

3.20 .05

1.20 MAX

5.50 .05

(Bottom View)

NOTE: 1. All dimensions in millimeters.

2. Recommended pad size for PCB is 0.33mm 0.025mm.

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

60

ADVANCE

128Mb: x16, x32

MOBILE SDRAM

DBFCF

FBGA DEVICE MARKING

Due to the size of the package, Micron’s standard part

number is not printed on the top of each device. Instead,

an abbreviated device mark comprised of a five-digit

alphanumericcodeisused. Theabbreviateddevicemarks

are cross referenced to Micron part numbers in Table 1.

Speed Grade

B = -10

C = -8

Width ( I/Os)

D = x16

G = x32

Device Density

F

=

128Mb

Product Type

N

P

V

Z

=

2.5V SDR SDRAM, Low Power version (54-ball, 8 x 9)

3.3V SDR SDRAM, Low Power version (54-ball, 8 x 9)

2.5V SDR SDRAM, Low Power version (90-ball, 11 x 13)

3.3V SDR SDRAM, Low Power version (90-ball, 11 x 13)

Product Group

D = DRAM

Z

= DRAM ENGINEERING SAMPLE

CROSS REFERENCE FOR FBGA OR VFBGA DEVICE MARKING

ENGINEERING

SAMPLE

ZVFGC

PRODUCTION

PART NUMBER

MT48V4M32LFFC-8

MT48LC4M32LFFC-10

MT48V8M16LFFF-10

MT48LC8M16LFFF-8

ARCHITECTURE

4 Meg x 32

8 Meg x 16

FBGA/VFBGA

90-pin, 11 x 13

54-ball, 8 x 9

MARKING

DVFGC

DZFGB

ZZFGB

ZNFDB

ZPFDC

DNFDB

DPFDC

DATA SHEET DESIGNATION

Advance: This data sheet contains initial descriptions of products still under development.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron and the M logo are registered trademarks and the Micron logo is a trademark of Micron Technology, Inc.

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

61


型号：	MT48V4M32LFFC
厂家：	MICRON TECHNOLOGY
描述：	SYNCHRONOUS DRAM 同步DRAM 动态存储器
文件：	总61页 (文件大小：1390K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MT48V4M32LFFC [MICRON]

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