ARF475FL_10 [MICROSEMI]
RF POWER MOSFET N-CHANNEL PUSH - PULL PAIR; RF功率MOSFET N沟道PUSH - PULL PAIR
| 型号： | ARF475FL_10 |
| 厂家： | 
Microsemi |
| 描述： | RF POWER MOSFET N-CHANNEL PUSH - PULL PAIR |
| 文件： | 总4页 (文件大小：139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Common Source
Push-Pull Pair
ARF475FL
D
G
S
S
S
S
G
D
RF POWER MOSFET
N-CHANNEL PUSH - PULL PAIR
165V 450W 150MHz
The ARF475FL is a matched pair of RF power transistors in a common source configuration. It is designed for high
voltage push-pull or parallel operation in narrow band ISM and MRI power amplifiers up to 150 MHz.
• High Performance Push-Pull RF Package.
• Specified 150 Volt, 128 MHz Characteristics:
• High Voltage Breakdown and Large SOA
•
•
•
Output Power = 900 Watts Peak
Gain = 15dB (Class AB)
Efficiency = 50% min
for Superior Ruggedness.
• Low Thermal Resistance.
• RoHS Compliant *
*Pb Free Terminal Finish.
MAXIMUM RATINGS
Symbol Parameter
All Ratings: T = 25°C unless otherwise specified.
C
ARF475FL
500
UNIT
VDSS
VDGO
ID
Drain-Source Voltage
Drain-Gate Voltage
Volts
500
Amps
10
Continuous Drain Current @ TC = 25°C
Gate-Source Voltage
(each device)
VGS
PD
±30
Volts
Watts
910
Total Device Dissipation @ TC = 25°C
TJ,TSTG
TL
Operating and Storage Junction Temperature Range
-55 to 175
300
°C
Lead Temperature: 0.063" from Case for 10 Sec.
STATIC ELECTRICAL CHARACTERISTICS (each device)
Symbol Characteristic / Test Conditions
MIN
TYP
MAX
UNIT
BVDSS
500
Drain-Source Breakdown Voltage (VGS = 0V, ID = 250 μA)
Volts
1
VDS(ON)
2.9
4
On State Drain Voltage (ID(ON) = 5A, VGS = 10V)
100
500
±100
Zero Gate Voltage Drain Current (VDS = VDSS, VGS = 0V)
IDSS
μA
Zero Gate Voltage Drain Current (VDS = 50V, VGS = 0, TC = 125°C)
nA
IGSS
gfs
Gate-Source Leakage Current (VGS = ±30V, VDS = 0V)
Forward Transconductance (VDS = 15V, ID = 5A)
3
0.9
2
3.6
3.3
mhos
1.1
4
Forward Transconductance Match Ratio (VDS = 15V, ID = 5A)
Gate Threshold Voltage (VDS = VGS, ID = 200mA)
Gate Threshold Voltage Match (VDS = VGS, ID = 200mA)
gfs1 gfs2
/
VGS(TH)
Volts
DVGS(TH)
0.2
THERMAL CHARACTERISTICS
Symbol Characteristic
MIN
TYP
0.15
0.30
MAX
0.165
0.33
UNIT
RθJC
Junction to Case
°C/W
RθJHS
Junction to Sink (Use High Efficiency Thermal Grease and Planar Heat Sink Surface.)
CAUTION: These Devices are Sensitive to Electrostatic Discharge. Proper Handling Procedures Should Be Followed.
Microsemi Website - http://www.microsemi.com
DYNAMIC CHARACTERISTICS (per section)
Symbol Characteristic
ARF475FL
Test Conditions
MIN
TYP
780
125
7
MAX
UNIT
Ciss
830
130
9
Input Capacitance
VGS = 0V
Coss
pF
Output Capacitance
V
DS = 50V
f = 1MHz
Crss
td(on)
tr
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
5.1
4.1
12
10
8
VGS = 15V
VDD = 250V
ns
ID = ID[Cont.] @ 25°C
RG = 1.6 W
td(off)
tf
Turn-off Delay Time
Fall Time
18
7
4.0
FUNCTIONAL CHARACTERISTICS (Push-Pull Configuration)
MIN
14
TYP
16
MAX
Symbol Characteristic
Test Conditions
UNIT
dB
f = 128 MHz
GPS
Common Source Amplifier Power Gain
Drain Efficiency
Idq = 15mA
VDD = 150V
50
55
%
η
Pout = 900W
PW = 3ms
10% duty cycle
ψ
Electrical Ruggedness VSWR 5:1
No Degradation in Output Power
1
Pulse Test: Pulse width < 380 μS, Duty Cycle < 2%.
Microsemi Reserves the right to change, without notice, the specifications and information contained herein.
Per transistor section unless otherwise specified.
3000
30
25
20
15
10
12V
Ciss
1000
500
11V
10V
Coss
100
50
9V
8V
7V
Crss
10
5
0
1
.1
1
10
100 200
0
5
10
15
20
25
30
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 2, Typical Capacitance vs. Drain-to-Source Voltage
Figure 1, Typical Output Characteristics
30
25
20
15
10
1.10
1.05
1.00
VDS> ID (ON) x RDS (ON)MAX.
250μSEC. PULSE TEST
@ <0.5 % DUTY CYCLE
TJ = -55°C
TJ = +25°C
0.95
0.90
TJ = -55°C
5
0
TJ = +125°C
0
2
4
6
8
10
-50 -25
TC, CASE TEMPERATURE (°C)
Figure 4, Typical Threshold Voltage vs Temperature
0
25 50 75 100 125 150
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 3, Typical Transfer Characteristics
ARF475FL
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
D = 0.9
0.7
0.5
Note:
t
1
0.3
t
2
SINGLE PULSE
10-3
t
1
t
/
2
Duty Factor D =
Peak T = P x Z
0.1
0.02
0
+ T
C
J
DM
θJC
0.05
10-5
10-4
10-2
10-1
1.0
RECTANGULAR PULSE DURATION (SECONDS)
FIGURE 5a, MAXIMUM EFFECTIVE TRANSIENT THERMAL IMPEDANCE, JUNCTION-TO-CASE vs PULSE DURATION
200
OPERATION HERE
LIMITED BY R
(ON)
DS
100
DC Line
TJ ( C)
TC ( C)
Dissipated Power
(Watts)
10
10µs
100µs
0.0755
0.0893
1ms
10ms
100ms
0.0135F
0.161F
1
TC =+25°C
TJ =+175°C
SINGLE PULSE
ZEXT are the external thermal
impedances: Case to sink, sink to
ambient, etc. Set to zero when modeling
only the case to junction.
0.1
1
10
100
800
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 6, Typical Maximum Safe Operating Area
Figure 5b, TRANSIENT THERMAL IMPEDANCE MODEL
Table 1 - Typical Series Equivalent Large Signal Input - Output Impedance
Freq. (MHz)
Z
(Ω) gate to gate
ZOL (Ω) drain - drain
in
30
60
90
120
150
5.2 -j10
1.37 -j5.2
.53 -j2.6
.25 -j1.0
.25 +j0.2
41 -j20
26 -j25
16 -j23
10 -j20
6.7 -j17
Z
- Gate -gate shunted with 25
Ω
IDQ = 15mA each side
in
ZOL - Conjugate of optimum load for 600 Watts peak output at V = 150V
dd
25% duty cycle and PW = 5ms
ARF475FL
+
128MHz Test amplifier
Po = 900W @150V
3ms pulse 10% Duty Cycle
+
L3
C11
Vdd
-
Vg1
R3
L2
TL3
C10
C5
C6
R1
T2
TL5
C3
C4
T1
T3
J1
TL1
C2
C7
C8
L1
J2
C1
TL2
R4
C9
R2
TL4
TL6
C1 25pF poly trimmer
C2 750pF ATC 700B
DUT
Vg2
C3-4 2200pF NPO 500V chip
C5-10 10nF 500V chip
C11 1000uF 250V electroytic
L1 30nH 1.5t #18 enam .375" dia
L2 680nH 12t #24 enam .312" dia
R1-2 3.1Ω : 3 parallel 22Ω 1W 2512 SMT
R3-4 2.2kΩ 1/4W axial
T1 1:1 balun 50Ω coax on Fair-Rite 2843000102 core
T2 4:1 25Ω coax on 2843000102 Fair-Rite balun core
T3 1:1 coax balun RG-303 on 2861006802 Fair-Rite core
TL1-2 Printed line L= 0.75" w=.23"
L3 2t #20 on Fair-Rite 2643006302 bead, ~ 2uH
TL3-6 Printed line L= 0.65" w=.23"
0.23" wide stripline on FR-4 board is ~ 30Ω Z
o
Peak Output Power vs. Vdd and Duty Cycle
Notes:
900
800
700
600
500
400
300
200
100
0
1.2
The value of L1 must be adjusted as the supply voltage is
changed to maintain resonance in the output circuit. At
128MHz its value changes from approximately 40nH at
100V to 30nH at 150V.
1
Max
Duty Cycle
0.8
0.6
0.4
0.2
0
With the 50Ω drain-to-drain load, the duty cycle above
100V must be reduced to insure power dissipation is
within the limits of the device. Maximum pulse length
should be 100mS or less. See transient thermal
impedance, figure 5.
P
Watts
o
80
100
120
140
160
Drain Supply Voltage Vdd
Thermal Considerations and Package Mounting:
.050
.050
± .01
.325 +/1 .01
The rated power dissipation is only available when the package
mounting surface is at 25°C and the junction temperature is 175°C.
The thermal resistance between junctions and case mounting sur-
face is 0.16°C/W. When installed, an additional thermal impedance
of 0.15°C/W between the package base and the mounting surface
is typical. Insure that the mounting surface is smooth and flat.
Thermal joint compound must be used to reduce the effects of
small surface irregularities. Use the minimum amount necessary to
coat the surface. The heatsink should incorporate a copper heat
spreader to obtain best results.
S
D1
D2
S
.125R
4 pls
.125dia
4 pls
.570
ARF475FL
.320
The package design clamps the ceramic base to the heatsink. A
clamped joint maintains the required mounting pressure while al-
lowing for thermal expansion of both the base and the heat sink.
Four 4-40 (M3) screws provide the required mounting force. T = 6
in-lb (0.68 N-m).
1.250
S
G1
G2
S
.225
.225
HAZARDOUS MATERIAL WARNING
The white ceramic portion of the device between leads
and mounting surface is beryllium oxide, BeO. Beryllium
oxide dust is toxic when inhaled. Care must be taken dur-
ing handling and mounting to avoid damage to this area.
These devices must never be thrown away with general
industrial or domestic waste.
.200
.300
.005 .040
1.500
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