LX7165-01CSP [MICROSEMI]
Switching Regulator, Voltage-mode, 5A, 2250kHz Switching Freq-Max, PBGA20;
| 型号： | LX7165-01CSP |
| 厂家： | 
Microsemi |
| 描述： | Switching Regulator, Voltage-mode, 5A, 2250kHz Switching Freq-Max, PBGA20 开关 |
| 文件： | 总24页 (文件大小：978K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LX7165
3V to 5.5V, 5A Constant Frequency Hysteretic
Synchronous Buck Regulator with I2C
Production Datasheet
Description
Features
The LX7165 is a digitally controlled step-down regulator
IC with an integrated 40m Ω high-side P-channel
MOSFET and a 14mΩ low-side N-channel MOSFET. It
features Microsemi’s proprietary constant-frequency
hysteretic control engine for near-instantaneous
correction to line/load transients. It does not require
high-ESR output capacitors and incorporates energy-
saving “PSM” (Power Save or Pulse Skip Mode) at light
loads, to extend battery life in mobile applications.
The LX7165 has an I2C serial interface port for output
voltage margining and monitoring if required (it can
also operate in default mode). In addition it includes
robust fault monitoring functions.
♦ Constant Frequency Hysteretic Control
♦ Extremely Fast Line/Load Transient Response
♦ I2C for Output Adjustment (3.4Mbps)
♦ 1.875 MHz Switching Frequency
♦ Extremely Low-RDSON MOSFETS
♦ Input Voltage Rail 3.3V to 5V
♦ Greater than 5A Output Current
♦ I2C Selectable Power Save Mode for Light-Load
Efficiency
♦ UVLO, OVP, OCP
♦ 0°C to +85°C Ambient Temperature
♦ Available in WLCSP-20 (0.4mm pitch)
♦ RoHS Compliant
The LX7165 will operate from 3V to 5.5V, and is
available in 3 fixed output voltage options: 0.9V, 0.95V,
and 0.97V (no voltage divider is necessary). The output
voltage can also be adjusted with an external voltage
divider up to 3.3V.
Applications
•
High Performance HDD
•
Notebooks/Netbooks/Tablets/Slates
Figure 1: Typical 5V to 1.8V at 5A schematic with or without I2C implemented
Copyright © 2013
Rev. 1.1, 01/09/2013
Microsemi
Analog Mixed Signal Group
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LX7165
3V to 5.5V, 5A Constant Frequency Hysteretic
Synchronous Buck Regulator with I2C
Production Datasheet
Other Typical Application Diagrams
Figure 2: Typical 0.9V output schematic without I2C implemented
Figure 3: A typical 3.3V output schematic with or without I2C implemented
Copyright © 2013
Rev. 1.1, 01/09/2013
Microsemi
Analog Mixed Signal Group
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LX7165
3V to 5.5V, 5A Constant Frequency Hysteretic
Synchronous Buck Regulator with I2C
Production Datasheet
Pin/Ball Configuration
Part Marking:
MSC
XXXX=Device Number
YWWA
XXXX
YWWA
E.g.: 6501=LX7165-01CSP
6502=LX7165-02CSP
Year/Work Week/Lot Code
Figure 4: Pinout
Ordering Information
Ambient
Type
Set Output
Voltage
Packaging
Type
Package
Part Number
Temperature
0.9V
0.95V
0.97V
LX7165-01CSP
LX7165-02CSP
LX7165-03CSP
Bulk
LX7165-xyCSP*
LX7165-01CSP-TR
LX7165-02CSP-TR
LX7165-03CSP-TR
LX7165-xyCSP-TR*
RoHS compliant,
0°C to 85°C
WLCSP-20 (0.4mm pitch)
Pb-free
0.9V
0.95V
0.97V
Tape and Reel
* Consult factory for other I2C slave address and set output voltage options.
“x” is the 2 LSB bits of the binary I2C slave address (0 to 3);
“y” is the set output voltage (0 is 0.6V, 1 is 0.9V, 2 is 0.95V, 3 is 0.97V)
Copyright © 2013
Rev. 1.1, 01/09/2013
Microsemi
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One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996
LX7165
3V to 5.5V, 5A Constant Frequency Hysteretic
Synchronous Buck Regulator with I2C
Production Datasheet
Pin/Ball Description
Pin/Ball
Number
Pin/Ball
Designator
Description
Open Drain status output, requires external pull up resistor. This pin
will go low when VOUT is outside the defined power good range, when
the die is hotter than the thermal shutdown threshold, when PVIN is
above the over voltage threshold, or when PVIN is below the under
voltage threshold. PGOOD will go high 45ms after the last of these fault
conditions clear.
A1
PGOOD
Enable for switching regulator. Force high to enable, force low to
disable the IC.
Serial clock input for I2C. Connect directly to GND if unused.
A2
A3
A4
B1
EN
SCL
Output voltage sense. Connect directly to output rail or resistive
voltage divider output.
Serial data bus (bidirectional) for I2C. Connect directly to GND if unused.
VOUT
SDA
B2, B3,
C1 – C4
GND
AGND
Ground. Connect to ground plane.
B4
Analog Ground. Connect to ground plane.
Input of IC and buck stage. Connect to input rail VIN (between 3V and
5.5V). A minimum input capacitance of one 1µF and one 22µF of X5R or
better multilayer ceramic, should be placed very close to IC between
this node and GND.
D1, D2
E1, E2
VIN
SW
D3, D4
E3, E4
Switching Node. Drives the external L-C low pass filter.
Copyright © 2013
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LX7165
3V to 5.5V, 5A Constant Frequency Hysteretic
Synchronous Buck Regulator with I2C
Production Datasheet
Functional Block Diagram
Figure 5: Block Diagram
Copyright © 2013
Rev. 1.1, 01/09/2013
Microsemi
Analog Mixed Signal Group
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LX7165
3V to 5.5V, 5A Constant Frequency Hysteretic
Synchronous Buck Regulator with I2C
Production Datasheet
Absolute Maximum Ratings
Performance is not necessarily guaranteed over this entire range. These are maximum stress ratings only.
Exceeding these ratings, even momentarily, can cause immediate damage, or negatively impact long-term
operating reliability.
Min
-0.3
-0.3
-2
Max
7
7
7
150
Units
V
V
VIN, SW to GND
VOUT, SDA, SCL, EN, PGOOD to GND
SW to GND (Shorter than 50ns)
Maximum Junction Temperature
Lead Soldering Temperature (40s, reflow)
Storage Temperature
V
°C
°C
°C
260 (+0, -5)
150
-65
Operating Ratings
Performance is generally guaranteed over this range as further detailed below under Electrical
Characteristics.
Min
3
0
Max
5.5
85
Units
V
°C
VIN
Ambient Temperature
Output Current
Note: Corresponding Absolute Max Junction Temperature is 150°C.
5
A
Thermal Properties
Thermal Resistance
Typ
Units
θJA
38
°C/W
Note: The θJA numbers assume no forced airflow. Junction Temperature is calculated using TJ = TA + (PD x θJA). In particular, θJA is a
function of the PCB construction. The stated number above is for a four-layer board in accordance with JESD-51 (JEDEC).
Copyright © 2013
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Analog Mixed Signal Group
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LX7165
3V to 5.5V, 5A Constant Frequency Hysteretic
Synchronous Buck Regulator with I2C
Production Datasheet
Electrical Characteristics
The following specifications apply over the operating ambient temperature of ≤0°CT
A ≤ 85°C except
where otherwise noted with the following test conditions: VIN = 5V, EN = 5V, SCL = 5V, SDA = 5V, default
register settings. Typical values stated, are either by design or by production testing at 25°C ambient.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Input Voltage
IQ
Input current
Input current at
shut down
ILOAD = 0, PSM enabled
EN = GND, TA = 25°C
200
440
0.1
600
3
µA
µA
IIN
Input current I2C
shut down
2
IIN_I C
VSEL(7) = low, EN = high
VIN rising
100
120
2.8
µA
Under voltage
rising threshold
UVLO
2.6
V
V
V
UVLOHYST UVLO hysteresis
0.26
Over voltage rising
threshold
Over voltage falling
threshold
OVPR
6.25
5.75
6.75
6.2
OVPF
V
Reference Voltage
Minimum
reference voltage
Mean
reference voltage
Maximum
reference voltage
VREFMIN
VSEL(6:0) = 00h
VSEL(6:0) = 40h
VSEL(6:0) = 7Fh
0.588
0.888
0.6
0.9
0.612
0.912
V
V
V
VREFMEAN
VREFMAX
1.184 1.195 1.206
TSS
THICCUP
Output Voltage
VREF slew rate
Hiccup time
SLEW: Ctrl2(2:0) = 011
VOUT = 0.2V
3
4
1.5
5.5
1.5
mV/μs
ms
Target based on option: 01 = 0.9,
10 = 0.95, 11 = 0.97. Measured
with respect to target voltage.
VIN from 3V to 5.5V, ILOAD = 1A.
Note 1
VOUT Default VOUT
-1.5
0
%
%
Line regulation
0.1
Load regulation
VOUT input current
VOUT under
ILOAD = 0A to 5A. Note 1
-0.23
0
%/A
µA
1
VOUT below this threshold will
initiate a hiccup sequence
VOUV
77
82
85
%VREF
voltage threshold
Copyright © 2013
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LX7165
3V to 5.5V, 5A Constant Frequency Hysteretic
Synchronous Buck Regulator with I2C
Production Datasheet
Symbol
SW
Parameter
High side on
Conditions
Min
Typ
Max
Units
RDSON_H
VIN = 5V
40
mΩ
resistance
Low side on
resistance
Current limit
Thermal shut down
threshold
RDSON_L
OCP
TSH
VIN = 5V
Note 1
Note 1
Note 1
14
7.5
mΩ
A
6.5
10.0
150
20
°C
TH
Hysteresis
°C
PWM switching
frequency
SW discharge
resistance
FSW
1.5
80
1.875
2.25
MHz
RSWDISC
EN = low; Discharge: Ctrl2(4) = 1
200
1400
Ω
EN, SDA (as input), SCL
VIH
VIL
VH
III
Input high
Input low
Hysteresis
Input current
1.1
V
V
V
0.4
1
0.1
0
μA
PGOOD
PGOOD VOUT
lower threshold
PGOOD VOUT
upper threshold
Hysteresis
VPG90
VOUT rising, percentage of VREF
85
90
95
%VREF
VPG110
VPGHY
VOUT falling, percentage of VREF
Percentage of VREF
105
110
5
115
%VREF
%VREF
Ω
PGOOD pull down
resistance
PGRDSON
100
300
PGOOD leakage
current
0
1
μA
PGOOD delay
PGOOD rising edge delay
30
45
65
ms
7 Bit DAC
Differential
linearity
Note 1: Guaranteed by design.
Monotonicity assured by design
0.8
LSB
Copyright © 2013
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LX7165
3V to 5.5V, 5A Constant Frequency Hysteretic
Synchronous Buck Regulator with I2C
Production Datasheet
Application Specifics
IOUT = 2.0A, VCC = 5V, VOUT = 3.3V
IOUT = 5.0A, VCC = 5V, VOUT = 3.3V
95%
90%
Efficiency
0.5 A to 2.5 A load step slews in 660ns, CLOAD = 3 x 22μF ceramic caps,
0.47μH inductor
2.5 A to 0.5 A load step slews in 1.6μs, CLOAD = 3 x 22μF ceramic caps,
L = 0.47μH inductor
VOUT Min Transient
VOUT Max transient
27.2mV
26.8mV
0.47μH
3x22μF
Typical Load
Inductance
Typical Load
Capacitance
DCR = 6.7mΩ, IDC = 12.2A, ISAT = 16A
6.3V, X5R
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LX7165
3V to 5.5V, 5A Constant Frequency Hysteretic
Synchronous Buck Regulator with I2C
Production Datasheet
Layout Recommendations
The LX7165 EVAL Board is a 4-layer board, the thickness of the board is 63mil in total. The second layer to
top layer is 7mil, the third layer to the bottom layer is 7mil. The recommended BGA PCB layout shown below
requires no microvias or blind vias. Each signal trace can exit the LX7165 directly without any vias under the
device. Also, with the bypass capacitors C2, C3 and C8 implemented as shown it can lower the ESL. Please
see LX7165 User Guide for additional details.
Figure 6: Layout recommendation (TOP layer)
Copyright © 2013
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LX7165
3V to 5.5V, 5A Constant Frequency Hysteretic
Synchronous Buck Regulator with I2C
Production Datasheet
Figure 7: Layout recommendation (BOTTOM layer)
Figure 8: Closeup of Layout in Region of BGA (note Ground gull-wings and via Stitching to BOTTOM)
Copyright © 2013
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LX7165
3V to 5.5V, 5A Constant Frequency Hysteretic
Synchronous Buck Regulator with I2C
Production Datasheet
Typical Performance Curves
Dynamic Response
Figure 9: No load to 0.5A PWM
Figure 10: No load to 0.5A PSM
CH2: VOUT, CH3: SW, CH4: ILOAD
CH2: VOUT, CH4: ILOAD
Figure 11: 0.5A to 2.5A PWM
Figure 12: 0.5A to 2.5A PSM
CH2: VOUT, CH4: ILOAD
CH2: VOUT, CH4: ILOAD
Copyright © 2013
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LX7165
3V to 5.5V, 5A Constant Frequency Hysteretic
Synchronous Buck Regulator with I2C
Production Datasheet
Typical Performance Curves (Continued)
Dynamic Response (Continued)
Figure 13: 0.5A to 2.5A PWM Rising Edge
Figure 14: No load to 0.5A PSM Rising Edge
CH2: VOUT, CH3: SW, CH4: ILOAD
CH2: VOUT, CH3: SW, CH4: ILOAD
Figure 15: 0.5A to 2.5A PWM Falling Edge
Figure 16: No load to 0.5A PSM Falling Edge
CH2: VOUT, CH3: SW, CH4: ILOAD
CH2: VOUT, CH3: SW, CH4: ILOAD
Copyright © 2013
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LX7165
3V to 5.5V, 5A Constant Frequency Hysteretic
Synchronous Buck Regulator with I2C
Production Datasheet
Typical Performance Curves (Continued)
Efficiency
LX7165 Efficiency / VIN=5V
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
VOUT=0.96V PWM
VOUT=1.82V PWM
VOUT=3.3V PWM
VOUT=0.96V PSM
VOUT=1.82V PSM
VOUT=3.3V PSM
10
100
1000
Load Current (mA)
Figure 17: Efficiency Curves for 5V input
Copyright © 2013
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LX7165
3V to 5.5V, 5A Constant Frequency Hysteretic
Synchronous Buck Regulator with I2C
Production Datasheet
I2C Timing Specifications
Symbol
Parameter
Conditions
Cb = 100 pF
(max) (*Note2)
Cb = 400 pF
Unit
Min
Max
Min
Max
fSCHL
SCL clock frequency
Set-up time for a
repeated START condition
Hold time (repeated)
START condition
LOW period of the SCL
clock
0
3.4
0
0.4 MHz
tSU;STA
160
-
-
-
-
600
600
-
-
-
-
ns
ns
ns
ns
tHD;STA
tLOW
160
160
60
1300
600
HIGH period of the SCL
clock
tHIGH
tSU;DAT
tHD;DAT
trCL
Data set-up time
Data hold time
10
0
10
-
70
40
100
0
20*0.1Cb
-
-
ns
ns
ns
Rise time of SCL signal
Rise time of SCL signal
after a repeated START
condition and after an
acknowledge bit
Fall time of SCL signal
Rise time of SDA signal
Fall time of SDA signal
Set-up time for STOP
condition
300
trCL1
10
80
20*0.1Cb
300
ns
tfCL
trDA
tfDA
10
10
10
40
80
80
20*0.1Cb
20*0.1Cb
20*0.01Cb 300
300
300
ns
ns
ns
tSU;STO
160
-
600
-
ns
Bus free time between a
STOP and START
condition
tBUF
160
-
1300
-
ns
tVD;DAT
tVD;ACK
Data valid time
Data valid acknowledge
time
-
-
160
160
-
-
900
900
ns
ns
Capacitive load for each
bus line
Cb
SDA and SCL lines
-
100
400
pF
Note 1: All values referred to VIH(min) and VIL(max) levels of I/O stages table.
Note 2: Loads in excess of 100pF will restrict bus operation speed below 3.4MHz
Copyright © 2013
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LX7165
3V to 5.5V, 5A Constant Frequency Hysteretic
Synchronous Buck Regulator with I2C
Production Datasheet
Operation Theory
Basic Operation
Setting the Output Voltage
The output voltage is set with the reference
voltage and how the VOUT pin (A4) is connected
to the output. With a direct connection (i.e. see
Figure 2), the reference voltage equals the output
voltage. When the VOUT pin (A4) is connected to
a resistor divider (i.e. see Figure 3), this also
determines the output voltage. At startup, the
reference voltage is determined by the parts
number “y” parameter (i.e. LX7165-xyCSP). “y”
sets the output voltage (0 is 0.6V, 1 is 0.9V, 2 is
0.95V, 3 is 0.97V). After startup, the reference
voltage can be programmed with the I2C bus VSEL
register value.
The LX7165 compares VOUT voltage to an internal
reference, VREF. When VOUT is lower than VREF
,
the upper switch turns on and the lower switch
turns off. When VOUT is higher than VREF, the
upper switch turns off and the lower switch turns
on. An internal ramp helps to keep the switching
frequency constant over a wide range of output
capacitor values and parasitic components (i.e.
ESR, ESL). In addition, a frequency control loop
keeps the switching frequency constant during
continuous conduction mode.
At light loads, if enabled, the converter
automatically reduces the switching frequency
and enters discontinuous conduction to optimize
efficiency while ensuring low VOUT ripple voltage.
VREF = 0.6V + NSEL ⋅0.0046875V
(2)
Where NSEL is the decimal value of the 7 VSEL bits.
The output voltage is determined as follows:
RTOP
RBOTTOM
An integrated I2C bus interface, operating up to
3.4Mbps, adds the following use programmability
to the converter:
VOUT =VREF × 1+
(3)
RTOP is the resistor connected from VOUT pin to
output, RBOTTOM is the resistor connected from
VOUT pin to GND.
1. On the fly programming of the output voltage
in 4.7mV increments.
2. Enable / Disable the regulator.
3. Allow PSM or limit operation to only PWM
mode.
4. Set the VREF slew rate.
5. Switch node slew rate control.
Startup
If the LX7165 is enabled, when VIN rises above the
UVLO threshold, the regulator will initiate a
startup sequence. The serial port registers are
initialized to their default values and all internal
bias voltages and currents are allowed to stabilize.
VREF then ramps up from 0V to the default voltage
at the default slew rate. At the end of the ramp
time, PGOOD is allowed to go high 45ms after
VOUT has reached the PGOOD rising threshold.
During the ramp time, the LX7165 switches to
PSM to allow discontinuous operation. This
switchover is independent of the MODE bit
setting.
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LX7165
3V to 5.5V, 5A Constant Frequency Hysteretic
Synchronous Buck Regulator with I2C
Production Datasheet
Operation Theory (Continued)
Over Current Protection
Negative Voltage Transitions
The LX7165 protects against all types of short A negative voltage transition occurs when a lower
circuit conditions. Cycle by cycle over current output voltage is programmed into the VSEL
protection turns off the upper switch when the register, and initiated by asserting the GO bit. In
current exceeds the OCP threshold. When this PSM, the LX7165 will not discharge the output
occurs, the upper switch is held off for at least filter capacitor.
350ns before being allowed to turn on again.
After startup, if VOUT drops below the VOUT
under voltage threshold, a hiccup sequence will be
initiated where both output switches are shut off
for 1.5ms before initiating another soft start cycle.
This protects against a crowbar short circuit. The
VOUT under voltage detection is not active during
start up.
Positive Voltage Transitions
After the initial start up sequence, the output
Figure 19: Negative Voltage Transition
voltage can be programmed to a new value by
programming the VSEL register bits and then
asserting the GO bit. VREF will transition to the
new value at the programmed slew rate. The
PGOK monitor bit is deasserted during the VREF
ramp time, or when VOUT is outside the error
envelope.
Enabling Regulator from I2C Bus
In addition to the EN pin, the regulator can be
enabled and disabled via the I2C bus by
programming the control register. During disable,
the regulator and most of the support circuitry is
turned off. However, the I2C bus circuitry is still
active and may be programmed.
Switch Node rise rate adjustment
The LX7165 can be programmed to operate in a
lower emissions mode by slowing down the switch
node rise rate. In this mode, the switch node rise
rate will slow down 25%, reducing the switching
frequency harmonic content.
Figure 18: Positive Voltage Transition
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LX7165
3V to 5.5V, 5A Constant Frequency Hysteretic
Synchronous Buck Regulator with I2C
Production Datasheet
I2C Interface
I2C Port Functional Description
Slave Address
In the table below, the A1 and A0 are the binary
value of the address given in the ordering
•
Simple two wire, bidirectional, serial
communication port.
information shown on page 3.
•
Multiple devices on same bus speeds from
400Kbps (FS-Mode) to 3.4Mbps (HS-Mode).
SOC Master controls bus.
Device listens for the unique address that
precedes data.
7
1
6
1
5
0
4
0
3
0
2
1
0
•
•
A1 A0 R/W
Table 1: I2C Slave Address
General I2C Port Description
START and STOP Commands
The LX7165 includes an I2C compatible serial
interface, using two dedicated pins: SCL and SDA
for I2C clock and data respectively. Each line is
externally pulled up to a logic voltage when they
are not being controlled by a device on the bus.
The LX7165 interface acts as a I2C slave that is
clocked by the incoming SCL clock. The LX7165 I2C
port will support both the Fast mode (400kHz
max) and typically the High Speed mode(3.4MHz
max). The data on the SDA line must be stable
during the HIGH period of the clock signal (SCL).
The state of the SDA line can only be changed
when SCL is LOW (except for start, stop, and
restart).
When the bus is idle, both SCL and SDA must be
high except in the power up case where they may
be held high or low during the system power up
sequence.
The STX SOC (bus master) signals START and STOP
bits signify the beginning and the end of the I2C
transfer. The START condition is defined as the
SDA signal transitioning from HIGH to LOW while
the SCL line is HIGH. The STOP condition is
defined as the SDA transitioning from LOW to
HIGH while the SCL is HIGH. The STX SOC acts as
the I2C master and always generates the START
and STOP bits. The I2C bus is considered to be busy
after START condition and free after STOP
condition. During data transfer, STX SOC master
can generate repeated START conditions. The
START and the repeated START conditions are
functionally equivalent.
Register Map
The LX7165 has four 8-bit user-accessible
registers. See Control Register Bit Definition.
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LX7165
3V to 5.5V, 5A Constant Frequency Hysteretic
Synchronous Buck Regulator with I2C
Production Datasheet
I2C Interface (Continued)
The slave leaves the data line HIGH and the
master generates the STOP command. The data
line is also left high by the slave and master after a
slave has transmitted a byte of data to the master
in a read operation, but this is a not acknowledge
that indicates that the data transfer is successful.
Data Transfers
Data is transferred in 8 bit bytes by SDA with the
MSB transferred first. Each byte of data has to be
followed by an acknowledge (ACK) bit. The
acknowledged related clock pulse is generated by
the master. The acknowledge occurs when the
transmitter master releases the SDA line to a high
state during the acknowledge clock. The SDA line
must be pulled down by the receiver slave during
the 9th clock pulse to signify acknowledgment. A
receiver slave which has been addressed must
generate an acknowledgement (“ACK”) after each
byte has been received.
Data Transfer Timing for Write Commands
In order to help assure that bad data is not written
into the part, data from a write command is only
stored after a valid STOP command has been
performed.
I2C Electrical Characteristics
After the START condition, the STX SOC (I2C)
master sends a chip address. The standard I2C
address is seven bits long. Making the eighth bit a
data direction bit (R/W). For the eighth bit (LSB), a
“0” indicates a WRITE and a “1” indicates a READ.
(For clarification, communications are broken up
into 9-bit segments, one byte followed by one bit
for acknowledging.) The second byte selects the
register to which the data will be written. The
third byte contains data to write to the selected
register.
The minimum HIGH and LOW periods of the SCL
clock specified the I2C Timing Specification table
determine the maximum bit transfer rates of, 400
kbit/s for Fast-mode devices, and 3.4 Mbits/s for
HS-mode Plus. Devices must be able to follow
transfers at their own maximum bit rates, either
by being able to transmit or receive at that speed
or by applying the I2C clock synchronization
procedure, which will force the master into a wait
state and stretch the LOW period of the SCL signal.
Of course, in the latter case the bit transfer rate is
reduced.
When a receiver slave doesn’t acknowledge the
slave address, the data line must be left HIGH by
the slave. The master can then generate a STOP
command to abort the transfer. If a slave receiver
does acknowledge the slave address but,
sometime later in the transfer cannot receive any
more data bytes, the master must again abort the
transfer. This is indicated by the slave generating
the not acknowledge on the first byte to follow.
Figures 22 and Figure 23 show all timing
parameters for the HS & FS-mode timing. The
‘normal’ START condition S does not exist in HS-
mode. Timing parameters for Address bits, R/W
bit, Acknowledge bit and DATA bits are all the
same. Only the rising edge of the first SCL clock
signal after an acknowledge bit has a larger value
because the external Rp has to pull-up SCL
without the help of the internal current-source.
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LX7165
3V to 5.5V, 5A Constant Frequency Hysteretic
Synchronous Buck Regulator with I2C
Production Datasheet
I2C Interface (Continued)
The HS & FS-mode timing parameters for the bus Timing parameters are independent for capacitive
lines are specified in the I2C Timing Specification load up to 100 pF for each bus line allowing the
Table. The minimum HIGH and LOW periods and maximum possible bit rate of 3.4 Mbit/s. At a
the maximum rise and fall times of the SCL clock higher capacitive load on the bus lines, the bit rate
signal determine the highest bit rate.
decreases gradually. The timing parameters for a
capacitive bus load of 400 pF are specified in I2C
With an internally generated SCL signal with LOW Timing Specification Table, allowing a maximum
and HIGH level periods of 200ns and 100ns bit rate of 1.7 Mbit/s. For capacitive bus loads
respectively, an HS-mode master fulfills the timing between 100 pF and 400 pF, the timing
requirements for the external SCL clock pulses parameters must be interpolated linearly. Rise
(taking the rise and fall times into account) for the and fall times are in accordance with the
maximum bit rate of 3.4 Mbit/s. So a basic maximum propagation time of the transmission
frequency of 10 MHz, or a multiple of 10 MHz, can lines SDA and SCL to prevent reflections of the
be used by an HS-mode master to generate the open ends.
SCL signal. There are no limits for maximum HIGH
and LOW periods of the SCL clock, and there is no
limit for a lowest bit rate.
Figure 20: Write Protocol
Figure 21: Read Protocol
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LX7165
3V to 5.5V, 5A Constant Frequency Hysteretic
Synchronous Buck Regulator with I2C
Production Datasheet
I2C Interface (Continued)
Figure 22: Definition for FS-Mode devices on the I2C Port
Figure 23: Timing definition for HS-mode devices on the I2C Port
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LX7165
3V to 5.5V, 5A Constant Frequency Hysteretic
Synchronous Buck Regulator with I2C
Production Datasheet
I2C Interface (Continued)
Figure 24: Write Cycle Diagram
Figure 25: Read Cycle Diagram
Control Register Bit Definition
Bit
Name
Value
Description
Status, Address 00h
7:3
2
Reserved
OCP
Latched to 1 if the over current limit is reached. Write a “1” to reset
the status flag.
Latched to 1 if an over temperature event occurs. Write a “1” to reset
the status flag.
Latched to 1 if a FB_UVLO event occurs. Write a “1” to reset the
status flag.
1
0
OTP
FB_UVLO
Vsel, Address 01h, (aka dac)
1-d
0
Device enabled.
Device disabled.
7
EN
7-bit DAC value to set VREF. The default value is determined by the
part ordering code.
6:0
VSEL[6:0]
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LX7165
3V to 5.5V, 5A Constant Frequency Hysteretic
Synchronous Buck Regulator with I2C
Production Datasheet
Bit
Name
Value
Description
Ctrl1, Address 02h, (aka reg2)
7:6
5
Reserved
ctrl1
00-d
1-d
1
TBD
Disable 45ms delay on PGOOD.
45ms delay on PGOOD is enabled.
Normal high efficiency rise rate.
Reduced switch node rise rate.
4
3
2
1
0
DLY_DIS
SW_RATE
Reserved
Reserved
MODE
0-d
1-d
0
1-d
0
1-d
0
1-d
0
PWM mode only – NO PSM.
Power Saving Mode – allows discontinuous conduction.
Vendor ID, Address 03h (Read Only)
7:4
VID[3:0]
0010
Microsemi Vendor ID .
Designates the slave address version. These bits will correspond to
the two LSB bits.
3:2
A1A0
00
Designates the default output voltage version, 00=0.6V, 01=0.9V,
10=0.95V, 11=0.97V.
1:0
VOUT
XX
Ctrl2, Address 04h, (aka reg4)
7:6
Reserved
Writing to this bit starts a VOUT transition regardless of its initial
value.
1
0-d
1
5
GO
The VOUT is ramped to the default VSEL Value.
When the regulator is disabled, the output voltage is discharged
through the SW pin.
When the regulator is disabled, the output voltage Is not discharged.
Is high when output is in regulation and VREF has stabilized.
Is low during a output voltage transition or when the output is not in
regulation.
4
3
Discharge
0-d
1
PGOK
(read only)
0
000
001
010
Reserved.
Reserved.
VREF slews at 2mV/μs.
011-d
100
101
VREF slews at 4mV/μs; this is the default setting.
VREF slews at 8mV/μs.
VREF slews at 16mV/μs.
2:0
SLEW
110
111
VREF slews at 32mV/μs.
VREF slews at 64mV/μs.
Note: -d is the default value at startup.
Copyright © 2013
Rev. 1.1, 01/09/2013
Microsemi
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One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996
LX7165
3V to 5.5V, 5A Constant Frequency Hysteretic
Synchronous Buck Regulator with I2C
Production Datasheet
Package Dimensions
WLCSP 20 Ball 0.4mm Pitch
MILLIMETERS
MIN MAX
A1 0.186 0.226 0.0073 0.0089
A2 0.360 0.400 0.0142 0.0157
INCHES
D
A2
4
3 2 1
Dim
MIN
MAX
b
20X
Ball 1
A
B
C
D
E
b
D1
D
0.240 0.280 0.0094 0.0110
1.20 BSC 0.0472 BSC
1.630 0.0642
E1
E
e
0.40 BSC
0.0157 BSC
e
E1
E
1.60 BSC
0.0630 BSC
D1
2.045
0.0805
A1
Note:
1.Solder ball composition SnAgCu
Recommended Footprint
Ø0.30mm
Solder Mask Opening
Ø0.20mm
Cu Pad
1.60mm
0.40mm
1.20mm
PRODUCTION DATA – Information contained in this document is proprietary to Microsemi
and is current as of publication date. This document may not be modified in any way without
the express written consent of Microsemi. Product processing does not necessarily include
testing of all parameters. Microsemi reserves the right to change the configuration and
performance of the product and to discontinue product at any time.
Copyright © 2013
Rev. 1.1, 01/09/2013
Microsemi
Analog Mixed Signal Group
Page 24
One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996
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