PD69108F [MICROSEMI]
8 PORTS PSE POE MANAGER;
| 型号： | PD69108F |
| 厂家： | 
Microsemi |
| 描述： | 8 PORTS PSE POE MANAGER |
| 文件： | 总17页 (文件大小：898K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD69108/F
8 PORTS PSE POE MANAGER
®
TM
DATASHEET
DESCRIPTION
KEY FEATURES
Microsemi’s PD69108 Power over Ethernet (PoE) Manager
integrates power, analog and state of the art logic into a single
48 pin, plastic QFN package. The device is used in Ethernet
switches and Midspans, enabling network devices to share power
and data over the same cable.
IEEE802.3af-2003 compliant
IEEE802.3at-2009 compliant,
including two-event classification
Supports pre-standard PD detection
Supports Cisco devices detection
Single DC voltage input (44 to 57
VDC)
Input voltage out of range protection
Wide temperature range: -10°C to
+85°C
The PD69108 device is an 8 ports, mixed-signal, high-voltage PoE
driver. It enables detection of IEEE802.3at-2009 compliant Type 1
and Type 2 PDs (Powered Devices), ensuring safe power feeding
and disconnection of ports with full digital control and a minimum of
external components.
The PD69108 executes all real time functions as specified in the
IEEE802.3af-2003 (“AF”) and IEEE802.3at-2009 High Power (“AT”)
standards, including load detection and “AF” and “AT” classification.
In addition, the PD69108 features Multiple Classification Attempts
(MCA) port status monitoring, and provides system level activities
such as power management and MIB support for system
management.
PD69108F version covering -40°C to
+85°C
Over-temperature protection
Low power dissipation (0.36 Ω sense
resistor and 0.3Ω MOSFET Rdson)
Includes Reset command pin
4 x direct address configuration pins
Continuous port monitoring and
system data
Configurable load current setting
Configurable AT/AF modes
Configurable standard and legacy
detection mode
The PoE device is designed to detect and disable disconnected
ports utilizing DC disconnection methods, as specified in the IEEE
802.3af-2003 and IEEE802.3at-2009 standards.
The unit provides PD protection such as over-load, under-load,
over-voltage and short-circuiting. It supports supply voltages
ranging from 44 to 57 VDC with no need for additional power supply
sources. The chip includes built-in internal thermal protection.
Power soft start mechanism
On-chip thermal protection
Voltage monitoring/protection
Built in 3.3 VDC and 5 VDC regulators
Internal power on reset
Optionally, the PD69108 can detect legacy/pre-standard PD
devices.
The PD69108 is a low power device using an internal MOSFET and
an external 0.36 Ω sense resistor.
RoHS compliant
Emergency power management
supporting four configurable power
bank I/Os
Can be cascaded to up to 12 PoE
devices (96 ports)
IMPORTANT: For the most current data, consult MICROSEMI’s website: http://www.microsemi.com
Copyright © 2013
Rev. 1.6
Microsemi
Analog Mixed Signal Group
1
1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
PD69108/F
8 PORTS PSE POE MANAGER
®
TM
PACKAGE ORDER INFO
THERMAL DATA
TYPICAL THERMAL RESISTANCE-JUNCTION TO AMBIENT 25° C/W
TYPICAL THERMAL RESISTANCE-JUNCTION TO CASE 4° C/W
Junction Temperature Calculation:
Plastic 48 pin QFN 8 mm x 8 mm
RoHS compliant / Pb-free/MSL1
PD69108ILQ
TA (°C)
-10 to +85
-40 to +85
PD69108FILQ
TJ = TA + (PD x θJA).
Note: Available in Tape and Reel. Append the letters “TR” to
The θJA numbers are guidelines for the thermal
performance of the device/pc-board system. All of the
above assume no ambient airflow.
the part number.
POWER DISSIPATION
Rsense Power Dissipation: 0.36 Ω x Iport2
Rds_ON Power Dissipation: 0.3Ω x Iport2
• Pport_AF = 15.4 W
==> PRsense = 28.2mW
PRds_ON = 23.4mW
==> PRsense = 107 mW
PRds_ON = 88.5mW
• Pport_AT = 30 W
** Calculated for Supply input Voltage of 55V
INTERNAL 3.3V VOLTAGE REGULATOR IS USED
EXTERNAL 3.3V VOLTAGE REGULATOR IS
USED
PD69108 self power dissipation: 1.1 W
PD69108 self power dissipation: 0.5 W
PD69108 8 ports AF Application Power dissipation = 1.1 W +
[ 8 x (28.2 mW + 23.4mW) ] = 1.51W
PD69108 AF 8 ports Application Power dissipation =
0.5 W + [ 8 x (28.2mW + 23.4mW) ] = 0.91W
PD69108 8 ports AT Application Power dissipation = 1.1 W +
[ 8 x (107 mW + 88.5mW) ] = 2.66W
PD69108 8 ports AT Application Power dissipation =
0.5 W + [ 8 x (107 mW + 88.5mW) ] = 2.06W
ABSOLUTE MAXIMUM RATINGS
PACKAGE PIN OUT
Supply Input Voltage (VMAIN
Port_Neg[0..7] Pins
Port_Sense[0..7] Pins
QGND, GND Pins
All Other Pins
PD69108 Operating Ambient Temperature
Range
PD69108F Operating Ambient Temperature
Range
Maximum Operating Junction Temperature
ESD Protection at all I/O Pins
Storage Temperature Range
)
-0.3 to 74 VDC
-0.3 to 74 VDC
-0.3 to 3.6 VDC
-0.3 to 0.3 VDC
-0.3 to 3.6 VDC
-10° to +85° C
36
35
PG3
PG0
PG1
1
2
3
4
5
6
7
8
9
PG2
34
33
PORT_SENSE7
VPORT_NEG7
Microsemi LOGO
MSC
PORT_SENSE0
VPORT_NEG0
PORT_SENSE1
VPORT_NEG1
PORT_SENSE6
32
31
30
29
28
27
26
25
VPORT_NEG6
AGND
-40° to +85° C
AGND
N/C
PD69108/F
Date Code
N/C
PORT_SENSE5
PORT_SENSE2
+150° C
± 2 KV HBM
-65° to +150° C
VPORT_NEG5
PORT_SENSE4
VPORT_NEG2
10
11
PORT_SENSE3
VPORT_NEG3
VPORT_NEG4
12
Notes:
Exceeding these ratings can cause damage to the device. All voltages are with
respect to ground. Currents are marked positive when flowing into specified
terminals and marked negative when flowing out of a specified terminal.
(Top View)
RoHS / Pb-free 100% Matte Tin Finish
Copyright © 2013
Rev. 1.6
Microsemi
Analog Mixed Signal Group
2
1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
PD69108/F
8 PORTS PSE POE MANAGER
®
TM
DATASHEET
ROHS AND SOLDER REFLOW INFORMATION
RoHS 6/6
Pb-free 100% Matte Tin Finish
Package Peak Temperature for Solder Reflow
(40 seconds maximum exposure)
260°C (+0°C, -5°C)
Notes:
Exceeding these ratings can cause damage to the device.
Copyright © 2013
Rev. 1.6
Microsemi
Analog Mixed Signal Group
3
1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
PD69108/F
8 PORTS PSE POE MANAGER
®
TM
DATASHEET
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, the following specifications apply to the operating ambient temperature.
PD69108 POE
MANAGER
MIN TYP MAX
TEST CONDITIONS /
COMMENT
PARAMETER
SYMBOL
UNITS
POWER SUPPLY
Supports Full IEEE802.3
functionality
Input Voltage
VMAIN
44
55
57
20
V
Power Supply Current
@ Operating Mode
VMAIN = 55 VDC
mA
5V Output Voltage
VAUX5
4.5
5
5.5
3.63
5
VDC
VDC
mA
3.3V Output Voltage
VAUX3P3
2.97 3.3
Without external NPN
3.3V Output Current
3.3V Input Voltage
With external NPN transistor
on VAUX5
REG_EN_N pin = 3.3V
(internal reg. is disabled)
VAUX3P3_INT=5V
30
mA
VDC
VAUX3P3
3
3.3
0.6
3.6
DIGITAL I/O ((RESET_N, MISO, MOSI, SCK, CS, PG[0..3], ADD[0..3])
Input Logic High
Threshold
Input Logic Low
Threshold
VIH
VIL
2.2
V
V
V
0.8
0.8
Input Hysteresis
Voltage
0.4
Input High Current
Input Low Current
Output High Voltage
Output Low Voltage
IIH
-10
-10
2.4
10
10
uA
uA
V
IIL
VOH
VOL
For IOH = -1 mA
IOH = 1 mA
0.4
V
POE LOAD
CURRENTS
AF Limit Mode
AF_LIM
AT_LIM
400 425
775 850
450
925
mA
mA
AT Limit
RSENSE = 0.36 Ω 1%
connected at Port_Sense
pin
AT Limit Dynamic
Range
Configurable by
communication
540
1200
mA
MAIN POWER
SWITCHING FET
On Resistance
RDSON
0.3
Ω
Internal Thermal
Protection Threshold
200
°C
Copyright © 2013
Rev. 1.6
Microsemi
Analog Mixed Signal Group
4
1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
PD69108/F
8 PORTS PSE POE MANAGER
®
TM
DATASHEET
Dynamic Characteristics
The PD69108 utilizes three current level thresholds (Imin, Icut, Ilim) and three timers (Tmin, Tcut, Tlim).
.
.
.
Loads that consume Ilim current for more than Tlim are classified as being in 'short circuit state' and are shutdown.
Loads that dissipate more than Icut for longer than Tcut are classified as ‘overloads’ and are automatically shutdown.
If output power is below Imin for more than Tmin, the PD is classified as ‘no-load’ and is shutdown.
Automatic recovery from over-load condition is attempted every TOVLREC periods (typically 1 second). Output power is
limited to Ilim, which is a maximum peak current allowed at the port.
IEEE802.3 AF Mode Parameters
PARAMETER
Automatic recovery from no-
load shutdown
CONDITIONS
MIN.
TYP.
MAX.
UNIT
TUDLREC value, measured from port shutdown
point (can be modified through control port)
Typical accuracy of Tcut
1
Sec
Cutoff timers accuracy
2
ms
Inrush current
Output current operating range
IInrsh
Iport
For t = 50 ms, Cload= 180 uF max.
Continuous operation after startup
period.
Continuous operation after startup
period, at port output.
Must disconnect for T greater than
TUVL
May or may not disconnect where
T is greater than TUVL
400
10
450
350
mA
mA
W
Output power available
operating range
Off mode current
Pport
Imin1
Imin2
TPMDO
Icut
0.57
0
15.4
5
mA
mA
ms
5
7.5
10
PD power maintenance
request drop-out time limit
Over-load current detection
range
Over load time limit
Turn on rise time
Buffer period to handle transitions
300
400
Time limited to TOVL
350
50
400
75
mA
ms
TOVL
Trise
From 10% to 90% of Vport
(Specified for PD load consisting of 100 uF
capacitor in parallel to 200 Ω).
15
us
Turn off time
Time maintain power signature
Toff
TMPS
From Vport to 2.8 VDC
DC modulation time for DC
disconnect
500
ms
ms
49
Copyright © 2013
Rev. 1.6
Microsemi
Analog Mixed Signal Group
5
1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
PD69108/F
8 PORTS PSE POE MANAGER
®
TM
DATASHEET
IEEE802.3 AT Mode Parameters
PARAMETER
Automatic recovery from
no-load shutdown
CONDITIONS
TUDLREC value, measured from port shutdown
point (can be modified through control port)
MIN.
TYP.
MAX.
UNIT
1
s
Cutoff timers accuracy
Inrush current
Typical accuracy of Tcut
2
ms
IInrsh
For t = 50 ms, Cload = 180 uF
max.
400
10
450
600
36
mA
Output current operating
range
Output power available,
operating range
Off mode current
Continuous operation after startup
period
Iport
mA
W
Continuous operation after startup
period at port output
Must disconnect where T is greater
than TUVL
May or may not disconnect where
T is greater than TUVL
Buffer period to handle transitions
Pport
Imin1
Imin2
TPMDO
Icut
0.57
0
5
mA
mA
ms
5
7.5
10
PD power maintenance
request drop-out time limit
Over-load current
detection range
Over-load time limit
300
400
Time limited to TOVL
600
50
775
75
mA
ms
TOVL
Trise
Turn on rise time
From 10% to 90% of Vport
(Specified for PD load consisting of 100 uF
capacitor in parallel to 200 Ω).
15
us
Turn off time
From Vport to 2.8 VDC
Toff
500
ms
ms
Time maintain power
signature
DC modulation time for DC
disconnect
TMPS
49
Copyright © 2013
Rev. 1.6
Microsemi
Analog Mixed Signal Group
6
1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
PD69108/F
8 PORTS PSE POE MANAGER
®
TM
DATASHEET
Package Pinout
36
PG3
PG0
PG1
1
2
3
4
5
6
7
8
9
35
PG2
PORT_SENSE7
VPORT_NEG7
34
33
Microsemi LOGO
MSC
PORT_SENSE0
VPORT_NEG0
PORT_SENSE1
VPORT_NEG1
PORT_SENSE6
32
31
30
29
28
27
26
25
VPORT_NEG6
AGND
AGND
N/C
PD69108/F
Date Code
N/C
PORT_SENSE5
PORT_SENSE2
VPORT_NEG5
PORT_SENSE4
VPORT_NEG2
10
11
PORT_SENSE3
VPORT_NEG3
VPORT_NEG4
12
PD69108 for -10° to +85°C Operating Ambient Temperature Range
PD69108F for -40° to +85°C Operating Ambient Temperature Range
Detailed Pinout Description
PIN
PIN NAME
PIN TYPE
DESCRIPTION
Exposed PAD: Metal plate on the IC bottom side connected to
analog ground.
A decent ground plane (about 500 mil inch over 500 mil inch) should
be deployed around this pin whenever possible
0
Exposed PAD
Analog Gnd
1
2
PG0
PG1
Digital Input Power supply monitoring
Digital Input Power supply monitoring
Analog Input Sense resistor port input
PORT_SENSE0
3
4
5
6
(Connected to 0.36 Ω, 1% resistor to QGND with ~12 mΩ trace for
measurements accuracy).
VPORT_NEG0
PORT_SENSE1
Analog I/O
Negative port output
Analog Input Sense resistor port input
(Connected to 0.36 Ω, 1% resistor to QGND with ~12 mΩ trace for
measurements accuracy).
VPORT_NEG1
Analog I/O
Negative port output
Copyright © 2013
Rev. 1.6
Microsemi
Analog Mixed Signal Group
7
1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
PD69108/F
8 PORTS PSE POE MANAGER
®
TM
DATASHEET
DESCRIPTION
PIN
PIN NAME
PIN TYPE
7
AGND
Power
Analog ground
Not Connected
8
N/C
PORT_SENSE2
Analog Input Sense resistor port input
9
(Connected to 0.36 Ω, 1% resistor to QGND with ~12 mΩ trace for
measurements accuracy).
10
11
VPORT_NEG2
PORT_SENSE3
Analog I/O
Negative port output
Analog Input Sense resistor port input
(Connected to 0.36 Ω, 1% resistor to QGND with ~12 mΩ trace for
measurements accuracy).
12
13
14
VPORT_NEG3
N/C
N/C
Analog I/O
Analog I/O
Analog I/O
Power
Negative port output
Test pin for production use only
Keep open, not connected
VMAIN
Supplies voltage for the internal analog circuitry. A low ESR 1 uF (or
higher) bypass capacitor, connected to AGND should be placed as
close as possible to this pin through low resistance traces.
15
VAUX5
Power
Power
Regulated 5 VDC output voltage source; it needs to be connected to
a filtering capacitor of 4.7 uF or higher.
If an external NPN is used to regulate the voltage, connect this pin to
the "Emitter" (the "collector" should be connected to Vmain)
16
DRV_VAUX5
Driven outputs for 5 VDC external regulation; if internal regulation is
used, connect to pin 16.
17
If an external NPN is used to regulate the voltage, connect this pin to
the "Base".
18
19
AGND
Power
Power
Analog ground
VAUX3P3_INT
Connected to VAX3P3 (pin 20) if internal 3.3 VDC regulator is used.
Connect to VAUX5 (pin 16) if external 3.3 VDC regulator is used
VAUX3P3
Power
Regulated 3.3v output voltage source. A 4.7 μF or higher filtering
capacitor should be connected between this pin and AGND.
When an external 3.3 VDC regulator is used, connect it to this pin to
supply the chip.
20
21
22
QGND
IREF
Power
Quiet analog ground.
Analog Input Reference resistor pin. Connect a 30.1 kΩ 1% resistor to QGND.
Trimming Input for IC production.
Should be connected to VAUX3P3.
23
TRIM
Analog Input
REG_EN_N
REG_EN_N Enable/Disable the internal 3.3 VDC regulator in case an external
3.3 VDC is used to supply the chip.
24
• GND: Internal regulator enabled
• 3.3 VDC: Internal regulator disabled
25
26
27
28
VPORT_NEG4
PORT_SENSE4
Analog I/O
Analog Input Sense resistor port input
(Connected to 0.36 Ω, 1% resistor to QGND with ~12 mΩ trace for
Negative port output.
measurements accuracy).
VPORT_NEG5
PORT_SENSE5
Analog I/O
Negative port output.
Analog Input Sense resistor port input.
(Connected to 0.36 Ω, 1% resistor to QGND with ~12 mΩ trace for
measurements accuracy).
29
30
31
N/C
Not Connected
AGND
Power
Analog ground.
VPORT_NEG6
Analog I/O
Negative port output.
Copyright © 2013
Rev. 1.6
Microsemi
Analog Mixed Signal Group
8
1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
PD69108/F
8 PORTS PSE POE MANAGER
®
TM
DATASHEET
DESCRIPTION
Analog Input Sense resistor port input.
PIN
32
PIN NAME
PORT_SENSE6
PIN TYPE
(Connected to 0.36 Ω, 1% resistor to QGND with ~12 mΩ trace for
measurements accuracy).
33
VPORT_NEG7
PORT_SENSE7
Analog I/O
Negative port output.
Analog Input Sense resistor port input.
(Connected to 0.36 Ω, 1% resistor to QGND with ~12 mΩ trace for
34
measurements accuracy).
Digital Input Power supply monitoring.
Digital Input Power supply monitoring.
35
36
PG2
PG3
TST
Digital I/O
Test pin for production use only.
Keep connected to DGND.
37
RESET_N
Digital Input Reset input; active low ('0' = reset)
An external 10K pull-up resistor should be connected between this
38
pin and DVDD.
39
40
41
MOSI
Digital Input SPI bus, Master Data out/slave in
Digital Output SPI bus, Master Data in/slave out
Digital Input SPI bus, Chip Select
MISO
SPI_CS
DVDD
Power
Digital 3.3 V input. It needs to be connected to filtering capacitor of
42
1 uF.
43
44
45
46
47
48
DGND
SCK
Digital I/O
Digital GND
Digital Input SPI bus, Serial clock input
ADDR3
ADDR2
ADDR1
ADDR0
Digital Input Address bus to set SPI address
Digital Input Address bus to set SPI address
Digital Input Address bus to set SPI address
Digital Input Address bus to set SPI address
Address Pin Description (ADDR<3:0>)
ADDR3 ADDR2 ADDR1 ADDR0 SPI ADDRESS [HEX]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E – Broadcast (See note)
F
•
•
'1' = DVDD (3.3 V)
'0' = DGND (digital ground)
Note: This address is used for Broadcast. Do not set any PD69108s in the system to this address.
Copyright © 2013
Rev. 1.6
Microsemi
Analog Mixed Signal Group
9
1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
PD69108/F
8 PORTS PSE POE MANAGER
®
TM
DATASHEET
SPI Detailed Timing Information
SPI1 frame
8 SCK clock cycles
8 SCK clock cycles
8 SCK clock cycles
D3
D5
Noise Spike
D14
D7
D1
D2
D2
D6
D8
D4
D13
CS_N
SCK
D9
D10
MOSI
MISO
D12
D15
D11
Name
D1
Min Delay
Max Delay
714ns
55
Description
SPI clock period
SPI duty cycle
D2
45
SPI_CS setup to SPI clock Positive Edge (delay after
SPI_CS active signal)
D3
D4
D5
340 ns
SPI_CS hold to SPI clock Positive Edge (delay before
SPI_CS inactive Signal)
340 ns
Delay between last SCK in eSPI1 frame and first SCK at
adjacent eSPI1 frame
2 spi clock cycles
D6
D7
1 spi clock cycles
1 spi clock cycles
1 SPI clock cycles
340 ns
Between byte 0 (IC addr) and byte 1(addr)
Between byte 1 (addr) and byte 2(data).
Between byte 2 (MS data byte) and byte 3(LS data byte).
MOSI setup time
D8
D9
D10
D11
D12
D13
D14
210 ns
MOSI hold time
140ns
300ns
MISO tri-state to valid data from clock positive edge
MISO valid data to tri-state from SPI_CS positive edge
SPI_CS width (Delay eSPI1 frame to adjacent eSPI1 frame)
Filtered Glitch Width
1 SPI clock cycles
60ns
D3 + 15.5 SPI clock
cycles
D3+23.75 SPI clock
cycles
D15
MISO tri-state from SPI_CS Negative Edge to valid data
Copyright © 2013
Rev. 1.6
Microsemi
Analog Mixed Signal Group
10
1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
PD69108/F
8 PORTS PSE POE MANAGER
®
TM
DATASHEET
PACK AGE DESCRIPTION
48-Pin 8x8mm QFN
MILLIMETERS
INCHES
DIM
MIN
0.80
MAX
1.00
MIN
0.031
MAX
0.039
0.002
A
E2
L
D
b
A1
A3
K
e
L
0.00
0.05
0
0.20 REF
0.20 MIN
0.50 BSC
0.30
0.18
6.35
0.008 REF
0.008 MIN
0.02 BSC
0.50
0.30
6.60
6.60
0.012
0.007
0.250
0.250
0.02
b
0.012
0.260
0.260
D2
E
D2
E2
D
6.35
8.00 BSC
8.00 BSC
0.315 BSC
0.315 BSC
E
K
Note:
e
Dimensions do not include protrusions; these do not exceed 0.155 mm
(.006”) on any side. Lead dimension do not include solder coverage.
A
A1
A3
Copyright © 2013
Rev. 1.6
Microsemi
Analog Mixed Signal Group
11
1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
PD69108/F
8 PORTS PSE POE MANAGER
®
TM
DATASHEET
PD69108 Internal Block Diagram
The PD69108 is based on two major sections:
.
.
A Digital section which controls and monitors the logical PoE functions (state machines, timings etc.)
An Analog section which performs the Front End analog PoE functionality.
Figure 1 illustrates both functions.
ADDR[3:0]
Digital
PG[3:0]
Vmain
Analog
PORT 8 Tool Box
PORT 7 Tool Box
PORT 6 Tool Box
PORT 5 Tool Box
PORT 4 Tool Box
PORT 3 Toool Box
PORT 2 Tool Box
Voltage
Regulator
MSC
(Miscellaneous ,
Power bank,
General counter,
IC ctrl)
POR
CLK
sync
sync
Analog
Mesurment
sync
Voltage
Reg
Generator for
Line Detection
& Classification
sck
cs_n SPI
mosi
miso
Table
CRG
AIR
(Analog
Interface)
(CPU/Contro
Registers)
(
SPI Control,
Watch Dog)
Thermal
Protection
Current Limiter
Controlled
Reference
ADC
VCM
A/D
(Voltage Curren
Measurement)
Full
RTP
Main MOSFET
DGND
AGND
Sense Resistor
Figure 1: PD69108 Internal Block Diagram
Copyright © 2013
Rev. 1.6
Microsemi
Analog Mixed Signal Group
12
1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
PD69108/F
8 PORTS PSE POE MANAGER
®
TM
DATASHEET
Logic Main Control Module
Voltage Regulator
The Logic Main Control Block includes the Digital Timing
Mechanisms and State Machines synchronizing and
activating PoE functions according to MCU control
commands such as:
The voltage regulator generates 3.3 VDC and 5 VDC for
the internal circuitry. These voltages are derived from
the Vmain supply.
To use the internal voltage regulator connect:
.
.
.
.
.
.
.
Real Time Protection (RTP)
Start Up Macro (DVDT)
Load Signature Detection (RES DET)
Classification Macro (CLASS)
Voltage and Current Monitoring Registers (VMC)
ADC Interfacing
.
.
.
VAUX5 to DRV_VAUX5
VAUX3P3 to VAUX3P3_INT
REG_EN_N to AGND.
There are two options to reduce the PD69108 power
dissipation by regulating the voltage outside the chip:
Direct Digital Signals with Analog Block
.
Use an external NPN transistor to regulate the
5 VDC.
Line Detection Generator
In this setup, the configuration of the regulators pins
should be:
Upon request from the MCU to the Main Control
Module, four different voltage levels are generated by
the Line Detection Generator to ensure a robust AF / AT
Line Detection functionality.
•
•
DRV_VAUX5 is connected to the NPN BASE
VAUX5 is connected to the NPN EMITTER
(Connect the Collector to VMAIN)
Classification Generator
•
•
VAUX3P3 is connected to VAUX3P3_INT
REG_EN_N is connected to AGND
Upon request from the MCU to the Main Control
Module, the State Machine applies a regulated Class
Event and Mark Event voltage to the ports, as required
by the IEEE standard.
.
Supply the PD69108 with an external 3.3 V voltage
regulator.
In this setup, the configuration of the regulators pins
should be:
Current Limiter
This circuit continuously monitors the current of powered
ports and limits the current to a specific value, according
to pre-defined limits as set by AF/AT and Current_Set
pins. In cases where the current exceeds this specific
level, the system starts measuring the elapsed time. If
this time period is greater than a preset threshold, the
port is disconnected.
•
•
•
•
VAUX5 is connected to DRV_VAUX5
VAUX3P3_INT is connected to VAUX5
VAUX3P3 is connected to the external 3.3 V
REG_EN_N is connected to VAUX3P3
The above two options can be implemented
simultaneously.
Main MOSFET
Main power switching FET, used to control PoE current
into the load.
CLK
CLK is an internal 8 MHz clock oscillator.
ADC
A 10-Bit Analog to Digital converter, used to convert
analog signals into digital registers for the Logic Control
module.
Power on Reset (POR)
Monitors the internal 3.3 V voltage DC levels; if this
voltage drops below specific thresholds, a reset signal is
generated and the PD69108 is reset.
Copyright © 2013
Rev. 1.6
Microsemi
Analog Mixed Signal Group
13
1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
PD69108/F
8 PORTS PSE POE MANAGER
®
TM
DATASHEET
Theory of Operation
Line Detection
The PD69108 performs IEEE802.3af and IEEE802.3at
functionality as well as legacy (capacitor) and Cisco’s
PDs detection and additional protections such as short
circuit and dV/dT protection upon startup.
The Line Detection feature detects a valid AF or AT
load, as specified in the AF / AT standard. The resistor
value should go from 19 kΩ to 26.5 kΩ. Line detection
is based on four different voltage levels generated over
the PD (the load) as illustrated in Figure 2.
Power
“ON”
v
Power
“OFF”
2 Events
Classification Phase
Start-Up
(Inrush)
Detection
Phase
t
Figure 2: Typical PoE Voltage Time Diagram
During this period current is limited to 425 mA for a
typical duration of 65 mS, which allows the PD load to
charge and allow steady state power condition.
Legacy (Cap) Detection
In cases where legacy is set, the PD69108's Detection
mechanism detects and powers up legacy PDs as well
as AF/AT compliant PDs.
Over-Load Detection and Port Shut Down
This mechanism is designed to detect and power up
CISCO legacy PDs as well.
After power up, the PD69108 automatically initializes its
internal protection mechanisms utilized to monitor and
disconnect power from the load in cases where extreme
conditions such as over-current or short ports terminals
scenario occur, as specified in the IEEE802.3AF/AT
standard.
Classification
The classification process takes place immediately after
resistor detection has successfully completed. The goal
of the classification process is to detect PD class, as
specified in the IEEE802.3AF and AT standards.
Disconnect Detection
The PD69108 supports DC Disconnect Function as per
the IEEE802.3AF/AT standard.
In the AF mode, classification mechanism is based on a
single voltage level (single finger).
This mechanism continuously monitors load current and
disconnects power in cases where load current is below
7.5 mA (typical) for more than 322 mS.
In the AT mode, classification mechanism is based on
two voltage levels (dual finger) as defined in
IEEE802.3at-2009.
Over-Temperature Protection
Port Start Up
The PD69108 has internal temperature sensors that
continuously monitor the main MOSFET junction
temperature and disconnect load power in cases where
Upon a successful detection and classification process,
power is applied to the load via a controlled Start Up
mechanism.
Copyright © 2013
Rev. 1.6
Microsemi
Analog Mixed Signal Group
14
1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
PD69108/F
8 PORTS PSE POE MANAGER
®
TM
DATASHEET
junction temperature exceeds 200° C. This mechanism
protects the device from extreme events, such as high
ambient temperature or other thermo-mechanical
failures that could damage the PD69108.
VMAIN Out of Range Protection
The PD69108 automatically disconnects port power in
cases where Vmain exceeds 60 VDC. This valuable
mechanism protects the load in cases where main
power source is faulty or damaged.
TYPICAL APPLICATION
This typical application illustrates a simple Power Over Ethernet system Solution for an 8 Ethernet Ports Switch or
Hub.
“POS” and “NEG” Signals should be connected to the Switch RJ45 Jack
Vmain
Vport_Pos0
47nF
QGND
QGND
VAUX5
Vport_Neg0
DRV_VAUX5
Vport_Neg0
VAUX3P3
VAUX3P3_INT
Vport_Sense0
x8
Connected to DVDD or
DGND according to
desired address
0.36?
Addr0
Addr1
Addr2
Addr3
x8
Vport_Neg7
Vport_Sense7
QGND
Vport_Neg7
MISO
MOSI
MISO
MOSI
To
Opto
MCU
SCK
xCS
SCK
xCS
SPI Communication
Bus
Isolated SPI
Communication
Bus
PG0
To
Power
Supply
PG1
PG2
PG3
Iref
30.1K?
Figure 3: Typical Application
* For detailed application's schematics and layout recommendations, contact: sales_AMSG@microsemi.com
Copyright © 2013
Rev. 1.6
Microsemi
Analog Mixed Signal Group
15
1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
PD69108/F
8 PORTS PSE POE MANAGER
®
TM
DATASHEET
Tape and Reel – Packaging Information
REEL MECHANICAL DATA
mm.
inch
Tape size
A max.
B max.
C
16.00 ±0.3
330
0.630 ±0.012
13”
1.5
0.059
13.0 ±0.20
20.2
0.512 ±0.008
0.795
D min.
N min.
50
1.968
G
16.4+2.0/-0.0 0.645+0.079/-0.0
T max.
29
1.142
BASE QUANTITY
2000 pcs.
Copyright © 2013
Rev. 1.6
Microsemi
Analog Mixed Signal Group
16
1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
PD69108/F
8 PORTS PSE POE MANAGER
®
TM
DATASHEET
The information contained in the document (unless it is publicly available on the Web without access restrictions) is
PROPRIETARY AND CONFIDENTIAL information of Microsemi and cannot be copied, published, uploaded, posted,
transmitted, distributed or disclosed or used without the express duly signed written consent of Microsemi. If the recipient
of this document has entered into a disclosure agreement with Microsemi, then the terms of such Agreement will also
apply . This document and the information contained herein may not be modified, by any person other than authorized
personnel of Microsemi. No license under any patent, copyright, trade secret or other intellectual property right is
granted to or conferred upon you by disclosure or delivery of the information, either expressly, by implication,
inducement, estoppels or otherwise. Any license under such intellectual property rights must be approved by Microsemi
in writing signed by an officer of Microsemi.
Microsemi reserves the right to change the configuration, functionality and performance of its products at anytime without
any notice. This product has been subject to limited testing and should not be used in conjunction with life-support or
other mission-critical equipment or applications. Microsemi assumes no liability whatsoever, and Microsemi disclaims
any express or implied warranty, relating to sale and/or use of Microsemi products including liability or warranties relating
to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property
right. Any performance specifications believed to be reliable but are not verified and customer or user must conduct and
complete all performance and other testing of this product as well as any user or customers final application. User or
customer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the
customer’s and user’s responsibility to independently determine suitability of any Microsemi product and to test and verify
the same. The information contained herein is provided “AS IS, WHERE IS” and with all faults, and the entire risk
associated with such information is entirely with the User. Microsemi specifically disclaims any liability of any kind
including for consequential, incidental and punitive damages as well as lost profit. The product is subject to other terms
and conditions which can be located on the web at http://www.microsemi.com/legal/tnc.asp
Revision History
Revision Level
Date
/
Para. Affected
-
Description
0.1 / 3-Nov-09
0.2 / 10-Jan-10
0.3 / 12-Apr-10
0.4 / 12-May-10
0.4/ 27-Jul-10
0.5/10-Apr-11
0.6/1-Aug-11
1.2/Oct 2011
1.3/Jan 2012
1.4/Feb 2012
1.5/Dec 2012
1.6/March 2013
Initial Release
Power Dissipation
Update
Ordering information update
Changing catalog numbers metrology
Update/corrections
Add SPI Timing Data
Add Theta JC
Remove “Confidential” header and updating Footer address
Updating I lim according to UL and IEEE
Adding Tape & Reel Data
Adding full temperature rang P/N
© 2013 Microsemi Corp.
All rights reserved.
For support contact: sales_AMSG@microsemi.com
Visit our web site at: www.microsemi.com
Catalogue Number DS_PD69108
Copyright © 2013
Rev. 1.6
Microsemi
Analog Mixed Signal Group
17
1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
相关型号：
©2020 ICPDF网 联系我们和版权申明