UC384XA [MICROSEMI]
CURRENT MODE PWM CONTROLLER; 电流模式PWM控制器
| 型号： | UC384XA |
| 厂家： | 
Microsemi |
| 描述： | CURRENT MODE PWM CONTROLLER |
| 文件： | 总8页 (文件大小：229K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LIN DOC #: 1840
UC184xA/284xA/384xA
C U R R E N T M O D E P W M C O N T R O L L E R
P R O D U C T I O N D A T A S H E E T
T H E I N F I N I T E P O W E R O F I N N O V A T I O N
DESCRIPTION
KEY FEATURES
■ LOW START-UP CURRENT. (0.5mA max.)
■ TRIMMED OSCILLATOR DISCHARGE
The UC184xA family of control ICs
provides all the necessary features to
implement off-line fixed-frequency,
current-mode switching power supplies
with a minimum of external compo-
nents. The current mode architecture
demonstrates improved load regulation,
pulse-by-pulse current limiting and
inherent protection of the power supply
output switch. The IC includes: A
bandgap reference trimmed to ±1%
accuracy, an error amplifier, a current
sense comparator with internal clamp to
1V, a high current totem pole output
stage for fast switching of power
MOSFET's, and an externally program-
mable oscillator to set frequency and
CURRENT. (See Product Highlight)
maximum duty cycle. The under-
voltage lock-out is designed to operate
with 250µA typ. start-up current,
allowing an efficient bootstrap supply
voltage design. Available options for
this family of products, such as start-up
voltage hysteresis and duty cycle, are
summarized below in the Available
Options section. The UC184xA family
of control ICs is also available in 14-pin
SOIC package which makes the Power
Output Stage Collector and Ground pins
available.
p OPTIMIZED FOR OFF-LINE AND DC-TO-DC
CONVERTERS.
p AUTOMATIC FEED FORWARD
COMPENSATION.
p PULSE-BY-PULSE CURRENT LIMITING.
p ENHANCED LOAD RESPONSE
CHARACTERISTICS.
p UNDER-VOLTAGE LOCKOUT WITH
HYSTERESIS.
p DOUBLE PULSE SUPPRESSION.
p HIGH-CURRENT TOTEM POLE OUTPUT.
p INTERNALLY TRIMMED BANDGAP
REFERENCE.
p 500KHz OPERATION.
PRODUCT HIGHLIGHT
p LOW RO ERROR AMPLIFIER.
COMPARISON OF UC384XA VS. SG384X DISCHARGE CURRENT
APPLICATIONS
UC384xA
■ ECONOMICAL OFF-LINE FLYBACK OR
SG384x
SG384x
Min. Limit
Max. Limit
FORWARD CONVERTERS.
TA=25°C
■ DC-DC BUCK OR BOOST CONVERTERS.
■ LOW COST DC MOTOR CONTROL.
A V A
I
L
A
B
L
E
O P
T I O N S
Part #
Start-Up Hysteresis Max. Duty
Voltage
16V
Cycle
<100%
<100%
<50%
<50%
UCx842A
6V
0.8V
6V
UCx843A 8.4V
UCx844A 16V
UCx845A 8.4V
7.5
7.8
−3σ
8.3
Mean
8.8
+3σ
9.3
0.8V
Discharge Current Distribution - mA
PACKAGE ORDER INFORMATION
Plastic DIP
8-pin
Plastic SOIC
8-pin
Plastic SOIC
14-pin
Ceramic DIP
8-pin
TA (°C)
M
DM
D
Y
0 to 70
-40 to 85
-55 to 125
UC384xAM
UC284xAM
—
UC384xADM
UC284xADM
—
UC384xAD
UC284xAD
—
—
UC284xAY
UC184xAY
Note: All surface-mount packages are available in Tape & Reel. Append the letter "T" to part number. (i.e. UC3842ADMT)
F O R F U R T H E R I N F O R M AT I O N C A L L ( 7 1 4 ) 8 9 8 - 8 1 2 1
Copyright © 1995
Rev. 1.2 12/95
1
11861 WESTERN AVENUE, GARDEN GROVE, CA. 92841
P R O D U C T D A T A B O O K 1 9 9 6 / 1 9 9 7
UC184xA/284xA/384xA
C U R R E N T M O D E P W M C O N T R O L L E R
P R O D U C T I O N D A T A S H E E T
ABSOLUTE MAXIMUM RATINGS (Note 1)
PACKAGE PIN OUTS
Supply Voltage (Low Impedance Source) (VCC) ......................................................... 30V
Supply Voltage (ICC < 30mA).......................................................................... Self Limiting
Output Current............................................................................................................. ±1A
Output Energy (Capacitive Load)................................................................................. 5µJ
Analog Inputs (VFB & ISENSE) ........................................................................ -0.3V to +6.3V
Error Amp Output Sink Current ............................................................................... 10mA
Power Dissipation at TA = 25°C (M Package).............................................................. 1W
Storage Temperature Range .................................................................... -65°C to +150°C
Lead Temperature (Soldering, 10 Seconds)............................................................. 300°C
COMP
VFB
ISENSE
RT/CT
1
2
3
4
8
7
6
5
VREF
VCC
OUTPUT
GND
M & Y PACKAGE
(Top View)
1
2
3
4
8
7
6
5
COMP
VFB
ISENSE
RT/CT
VREF
VCC
OUTPUT
GND
Note 1. Exceeding these ratings could cause damage to the device. All voltages are with respect
to Ground. Currents are positive into, negative out of the specified terminal. Pin
numbers refer to DIL packages only.
DM PACKAGE
(Top View)
THERMAL DATA
M PACKAGE:
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA
DM PACKAGE:
95°C/W
165°C/W
120°C/W
130°C/W
1
2
3
4
5
6
7
14
13
12
11
10
9
COMP
N.C.
VFB
N.C.
ISENSE
N.C.
RT/CT
VREF
N.C.
VCC
VC
OUTPUT
GND
PWR GND
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA
D PACKAGE:
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA
Y PACKAGE:
8
D PACKAGE
(Top View)
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA
Junction Temperature Calculation: TJ = TA + (PD x θJA).
The θ numbers are guidelines for the thermal performance of the device/pc-board system.
All ofJtAhe above assume no ambient airflow
Copyright © 1995
Rev. 1.2 12/95
2
P R O D U C T D A T A B O O K 1 9 9 6 / 1 9 9 7
UC184xA/284xA/384xA
C U R R E N T M O D E P W M C O N T R O L L E R
P R O D U C T I O N D A T A S H E E T
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for UC384xA with 0°C ≤ TA ≤ 70°C, UC284xA with -40°C ≤ TA ≤ 85°C,
UC184xA with -55°C ≤ TA ≤ 125°C; VCC=15V; RT=10K; CT=3.3nF. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal
to the ambient temperature.)
UC184xA/284xA
Min. Typ. Max. Min. Typ. Max.
UC384xA
Parameter
Symbol
Test Conditions
Units
Reference Section
Output Voltage
VREF
TJ = 25°C, IL = 1mA
4.95 5.00 5.05 4.90 5.00 5.10
V
Line Regulation
12 ≤ VIN ≤ 25V
1 ≤ IO ≤ 20mA
6
6
20
25
6
6
20
25
mV
mV
Load Regulation
0.2 0.4
5.1 4.82
0.2 0.4 mV/°C
Temperature Stability (Note 2 & 7)
Total Output Variation
Output Noise Voltage (Note 2)
Long Term Stability (Note 2)
Output Short Circuit Current
Oscillator Section
4.9
5.18
V
Over Line, Load, and Temperature
10Hz ≤ f ≤ 10kHz, TJ = 25°C
TA = 125°C, t = 1000hrs
50
5
50
5
µV
mV
mA
VN
ISC
25
25
-30 -100 -180 -30 -100 -180
Initial Accuracy (Note 6)
Voltage Stability
TJ = 25°C
12 ≤ VCC ≤ 25V
47
52
0.2
5
57
1
47
52
0.2
5
57
1
kHz
%
Temperature Stability (Note 2)
Amplitude (Note 2)
Discharge Current
TMIN ≤ TA ≤ TMAX
%
V
mA
mA
1.7
1.7
7.8 8.3 8.8 7.8 8.3 8.8
7.5 8.8 7.6 8.8
TJ = 25°C, VPIN 4 = 2V
VPIN 4 = 2V, TMIN ≤ TA ≤ TMAX
Error Amp Section
Input Voltage
Input Bias Current
VPIN 1 = 2.5V
2.45 2.50 2.55 2.42 2.50 2.58
V
µA
dB
MHz
dB
mA
mA
V
IB
-0.3
90
1
-1
-0.3
90
1
-2
Open Loop Gain
AVOL
2 ≤ VO ≤ 4V
65
0.7
60
2
65
0.7
60
2
Unity Gain Bandwidth (Note 2)
Power Supply Rejection Ratio (Note 3)
Output Sink Current
Output Source Current
Output Voltage High Level
Output Voltage Low Level
Current Sense Section
UGBW Tj = 25°C
PSRR
IOL
IOH
12 ≤ VCC ≤ 25V
70
6
70
6
VPIN 2 = 2.7V, VPIN 1 = 1.1V
VPIN 2 = 2.3V, VPIN 1 = 5V
-0.5 -0.8
-0.5 -0.8
5
6
5
6
VOH
VOL
VPIN 2 = 2.3V, RL = 15K to ground
VPIN 2 = 2.7V, RL = 15K to VREF
0.7 1.1
0.7 1.1
V
Gain (Note 3 & 4)
AVOL
2.85
0.9
3
1
70
-2
3.15 2.85
1.1 0.9
3
1
70
-2
3.15
1.1
V/V
V
dB
µA
ns
Maximum Input Signal (Note 3)
Power Supply Rejection Ratio (Note 3)
Input Bias Current
VPIN 1 = 5V
PSRR
IB
12 ≤ VCC ≤ 25V
-10
-10
150 300
150 300
Delay to Output (Note 2)
Output Section
Tpd
VPIN 3 = 0 to 2V
Output Low Level
ISINK = 20mA
ISINK = 200mA
0.1 0.4
1.5 2.2
0.1 0.4
1.5 2.2
V
V
VOL
Output High Level
ISOURCE = 20mA
13 13.5
12 13.5
13 13.5
12 13.5
50 150
V
V
VOH
ISOURCE = 200mA
TJ = 25°C, CL = 1nF
TJ = 25°C, CL = 1nF
VCC = 5V, ISINK = 10mA
Rise Time (Note 2)
Fall Time (Note 2)
UVLO Saturation
TR
TF
VSAT
50 150
50 150
0.7 1.2
ns
ns
V
50 150
0.7 1.2
(Electrical Characteristics continue next page.)
Copyright © 1995
Rev. 1.2 12/95
3
P R O D U C T D A T A B O O K 1 9 9 6 / 1 9 9 7
UC184xA/284xA/384xA
C U R R E N T M O D E P W M C O N T R O L L E R
P R O D U C T I O N D A T A S H E E T
ELECTRICAL CHARACTERISTICS (Con't.)
UC184xA/284xA
Min. Typ. Max. Min. Typ. Max.
UC384xA
Parameter
Symbol
Test Conditions
Units
Under-Voltage Lockout Section
Start Threshold
x842A/4A
x843A/5A
x842A/4A
x843A/5A
15
7.8 8.4 9.0 7.8 8.4 9.0
10 11 8.5 10 11.5
7.0 7.6 8.2 7.0 7.6 8.2
16
17 14.5 16 17.5
V
V
V
V
Min. Operation Voltage After Turn-On
9
PWM Section
Maximum Duty Cycle
x842A/3A
x844A/5A
94
47
96 100 94
96 100
%
%
%
48
50
0
47
48
50
0
Minimum Duty Cycle
Total Standby Section
Start-Up Current
0.3 0.5
0.3 0.5
mA
mA
V
Operating Supply Current
Zener Voltage
ICC
VZ
11
35
17
11
35
17
ICC = 25mA
30
30
Notes: 2. These parameters, although guaranteed, are not 100% tested in
production.
7. "Temperature stability, sometimes referred to as average temperature
coefficient, is described by the equation:
3. Parameter measured at trip point of latch with VVFB = 0.
VREF (max.) - VREF (min.)
Temp Stability =
∆ VCOMP
TJ (max.) - T (min.)
J
4. Gain defined as: AVOL
=
; 0 ≤ VISENSE ≤ 0.8V.
∆ VISENSE
VREF (max.) & VREF (min.) are the maximum & minimum reference
voltage measured over the appropriate temperature range. Note that
the extremes in voltage do not necessarily occur at the extremes in
temperature."
5. Adjust VCC above the start threshold before setting at 15V.
6. Output frequency equals oscillator frequency for the UC1842A
and UC1843A. Output frequency is one half oscillator frequency
for the UC1844A and UC1845A.
BLOCK DIAGRAM
*
VCC
34V
UVLO
VREF
5.0V
50mA
5V
Ref
S / R
**
Hysteresis
6V (1842A/4A)
0.8V (1843A/5A)
GROUND
UVLO
16V (1842A/4A)
8.4V (1843A/5A)
Internal
Bias
2.5V
*
VC
VREF
Good Logic
RT/CT
Oscillator
***
T
OUTPUT
Error Amp
S
R
2R
R
VFB
PWM
Latch
1V
**
POWER GROUND
Current Sense
Comparator
COMP
CURRENT SENSE
- VCC and VC are internally connected for 8 pin packages.
- POWER GROUND and GROUND are internally connected for 8 pin packages.
- Toggle flip flop used only in x844A and x845A series.
*
**
***
Copyright © 1995
Rev. 1.2 12/95
4
P R O D U C T D A T A B O O K 1 9 9 6 / 1 9 9 7
UC184xA/284xA/384xA
C U R R E N T M O D E P W M C O N T R O L L E R
P R O D U C T I O N D A T A S H E E T
CHARACTERISTIC CURVES
FIGURE 1. — OSCILLATOR FREQUENCY vs. TIMING
RESISTOR
VREF
8
CT = 1nF
RT
1M
RT/CT
4
5
CT = 2.2nF
CT
100k
GROUND
CT = 4.7nF
10k
0
1.72
RT CT
For RT > 5k, f »
Note: Output drive frequency is half the oscillator frequency for
the UCx844A/5A devices.
300
1.0k
3.0k
10.0k
30.0k
100k
RT - (ohms)
FIGURE 2. — MAXIMUM DUTY CYCLE vs. TIMING RESISTOR
100.0
80.0
60.0
40.0
20.0
0
300
1.0k
3.0k
10.0k
30.0k
100k
RT - (ohms)
Copyright © 1995
Rev. 1.2 12/95
5
P R O D U C T D A T A B O O K 1 9 9 6 / 1 9 9 7
UC184xA/284xA/384xA
C U R R E N T M O D E P W M C O N T R O L L E R
P R O D U C T I O N D A T A S H E E T
TYPICAL APPLICATION CIRCUITS
FIGURE 4. — MOSFET PARASITIC OSCILLATIONS
FIGURE 3. — CURRENT SENSE SPIKE SUPPRESSION
VCC DC BUS
VCC
DC BUS
7
6
7
Q1
RS
R1
Q1
UCx84xA
UCx84xA
6
5
IPK
CHANGE
3
1.0V
RS
IPK(MAX)
=
C
5
RS
The RC low pass filter will eliminate the leading edge current spike
caused by parasitics of Power MOSFET.
A resistor (R1) in series with the MOSFET gate will reduce overshoot
& ringing caused by the MOSFET input capacitance and any
inductance in series with the gate drive. (Note: It is very important to
have a low inductance ground path to insure correct operation of the
I.C. This can be done by making the ground paths as short and as
wide as possible.)
FIGURE 5. — EXTERNAL DUTY CYCLE CLAMP AND MULTI-UNIT SYNCHRONIZATION
8
4
8
4
RA
RB
7
6
UCx84xA
555
TIMER
3
2
5
1
5
0.01
To other
UCx84xA devices
1.44
f =
f =
(RA + 2RB)C
RB
Precision duty cycle limiting as well as synchronizing several parts is
possible with the above circuitry.
RA + 2RB
Copyright © 1995
Rev. 1.2 12/95
6
P R O D U C T D A T A B O O K 1 9 9 6 / 1 9 9 7
UC184xA/284xA/384xA
C U R R E N T M O D E P W M C O N T R O L L E R
P R O D U C T I O N D A T A S H E E T
TYPICAL APPLICATION CIRCUITS (continued)
FIGURE 6. — SLOPE COMPENSATION
VCC
DC BUS
UCx84xA
7(12)
VO
5V
8(14)
RT
UVLO
S
5V
REF
R
INTERNAL
BIAS
2.5V
2N222A
VREF
GOOD LOGIC
7(11)
6(10)
RSLOPE
4(7)
OSCILLATOR
Q1
From VO
CT
C.S.
COMP
2R
Ri
2(3)
RF
1V
ERROR
AMP
R
5(8)
3(5)
PWM
LATCH
Rd
CF
R
1(1)
C
RS
5(9)
Due to inherent instability of current mode converters running above 50% duty cycle, slope compensation should be added to either
the current sense pin or the error amplifier. Figure 6 shows a typical slope compensation technique.
FIGURE 7. — OPEN LOOP LABORATORY FIXTURE
VREF
RT
VCC
A
UCx84xA
2N2222
100K
4.7K
1K
COMP
VREF
1
2
3
4
8
7
6
5
VFB
VCC
0.1µF
0.1µF
ERROR AMP
ADJUST
1K
5K
ISENSE
ADJUST
OUTPUT
4.7K
ISENSE
OUTPUT
GROUND
RTCT
GROUND
CT
High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be
connected to pin 5 in a single point ground. The transistor and 5k potentiometer are used to sample the oscillator waveform and apply an
adjustable ramp to pin 3.
Copyright © 1995
Rev. 1.2 12/95
7
P R O D U C T D A T A B O O K 1 9 9 6 / 1 9 9 7
UC184xA/284xA/384xA
C U R R E N T M O D E P W M C O N T R O L L E R
P R O D U C T I O N D A T A S H E E T
TYPICAL APPLICATION CIRCUITS (continued)
FIGURE 8. — OFF-LINE FLYBACK REGULATOR
TI
MBR735
4.7kW 1W
220µF
250V
4.7kW
2W
3600pF
400V
1N4004
1N4004
5V
2-5A
4700µF
10V
140kW
1/2W
1N4935
AC
INPUT
1N4004
1N4004
1N4935
16V
10µF
20V
20kW
UC3844A
820pF
7
0.01µF
VFB
VCC
2
2.5kW
27kW
150kW
COMP
1
OUT
6
3
3.6kW
100pF
VREF
8
4
1kW
470pF
CUR
SEN
10kW
0.85kW
RT/CT
GND
0.01µF
.0022µF
5
ISOLATION
BOUNDARY
SPECIFICATIONS
Input line voltage:
Input frequency:
Switching frequency:
Output power:
Output voltage:
Output current:
Line regulation:
Load regulation:
Efficiency @ 25 Watts,
VIN = 90VAC:
90VAC to 130VAC
50 or 60Hz
40KHz 10%
25W maximum
5V +5%
2 to 5A
0.01%/V
8%/A*
* This circuit uses a low-cost feedback scheme in which the DC
voltage developed from the primary-side control winding is
sensed by the UC3844A error amplifier. Load regulation is
therefore dependent on the coupling between secondary and
control windings, and on transformer leakage inductance.
70%
VIN = 130VAC:
65%
Output short-circuit current:
2.5Amp average
Copyright © 1995
Rev. 1.2 12/95
8
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