WV3HG264M72EEU403D4-M [MICROSEMI]
DDR DRAM Module, 128MX72, 0.6ns, CMOS, SO-DIMM-200;
| 型号： | WV3HG264M72EEU403D4-M |
| 厂家： | 
Microsemi |
| 描述： | DDR DRAM Module, 128MX72, 0.6ns, CMOS, SO-DIMM-200 动态存储器 双倍数据速率 |
| 文件： | 总10页 (文件大小：160K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WV3HG264M72EEU-D4
White Electronic Designs
ADVANCED*
1GB – 2x64Mx72 DDR2 SDRAM UNBUFFERED, w/PLL
FEATURES
DESCRIPTION
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200-pin SO-DIMM, dual in-line memory module
Fast data transfer rates: PC2-4200 and PC2-3200
CC = VCCQ = 1.8V 0.1V
The WV3HG264M72EEU is a 2x64Mx72 Double Data
Rate DDR2 SDRAM high density module. This memory
module consists of eighteen 64Mx8 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
200-pin SO-DIMM FR4 substrate.
V
1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
Multiple internal device banks for concurrent
operation
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
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Programmable CAS# latency (CL): 3 and 4
Adjustable data-output drive strength
On-die termination (ODT)
Posted CAS# latency: 0, 1, 2, 3 and 4
Serial Presence Detect (SPD) with EEPROM
64ms: 8,192 cycle refresh
Gold edge contacts
Dual Rank
RoHS compliant
Package option
• 200 Pin SO-DIMM
• PCB – 31.75mm (1.25") Max
OPERATING FREQUENCIES
PC2-3200
200MHz
3-3-3
PC2-4200
266MHz
4-4-4
Clock Speed
CL-tRCD-tRP
August 2005
Rev. 0
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-D4
White Electronic Designs
ADVANCED
PIN CONFIGURATION
PIN NAMES
Pin No. Symbol Pin No. Symbol Pin No. Symbol Pin No. Symbol
Pin Name
A0-A9, A11-A13 Address Inputs
Function
1
VREF
VSS
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
DQ18
VSS
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
A5
VCC
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
VSS
VSS
2
A10/AP
BA0, BA2
DQ0-DQ63
CB0-CB7
DQS0-DQS8
DQS0#-DQS8#
ODT0, ODT1
CK0,CK0#
CKE0, CKE1
S0#, S1#
RAS#
CAS#
WE#
VCC
VCCQ
VSS
SA0-SA2
SDA
VREF
DM0-DM8
VCCSPD
Address Input/Auto Precharge
SDRAM Bank Address
Data Input/Output
Check Bits
Data strobes
Data strobes negative
On-die termination control
Clock inputs, positive/negative
Clock enable input
Chip select input
Row Address Strobe
Column Address Strobe
Write Enable
3
4
5
6
7
8
9
DQ0
DQ4
DQ1
DQ5
VSS
DQ19
DQ28
VSS
DQ29
DQ24
VSS
DQ25
DM3
VSS
A4
A3
A2
A1
VCC
VCC
VSS
CK0
VSS
CK0#
A10/AP
VCC
BA0
A0
WE#
BA1
VCC
RAS#
CAS#
VCC
DQS5#
DM5
DQS5
VSS
VSS
VSS
DQ46
DQ42
DQ47
DQ43
VSS
DQS0#
DM0
DQS0
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
VSS
DQS3#
DQ30
DQS3
DQ31
VSS
VSS
DQ6
DQ2
DQ7
DQ3
VSS
DQ52
DQ48
DQ53
DQ49
VSS
Core Power (1.8V)
I/O Power (1.8V)
Ground
VSS
VSS
DQ26
CB4
DQ27
CB5
VSS
VSS
DQ12
DQ8
DQ13
DQ9
VSS
DM6
DQS6#
VSS
DQS6
DQ54
VSS
DQ55
DQ50
VSS
DQ51
DQ60
VSS
DQ61
DQ56
VSS
DQ57
DM7
VSS
SPD address
Serial Data Input/Output
Input/Output Reference
Data-in mask
Serial EEPROM power supply
Serial Presence Detect(SPD) Clock Input
S1#
S0#
VSS
VSS
CB0
DM8
CB1
VSS
ODT1
ODT0
VSS
DM1
DQS1#
VSS
DQS1
DQ14
VSS
DQ15
DQ10
VSS
DQ11
NC
SCL
A13(3)
DQ32
VCC
VSS
CB6
DQS8#
CB7
DQS8
VCC
DQ33
DQ36
VSS
DQ37
DQS4#
VSS
DQS4
DM4
VSS
VSS
CKE1
CB2
CKE0
CB3
VCC
VCC
A12
NC
A9
A11
VCC
A7
A8
VCC
A6
VSS
DQ20
DQ16
DQ21
DQ17
VSS
VSS
DQS7#
DQ62
DQS7
DQ63
VSS
VCCSPD
DQ58
SA0
VSS
DQ34
DQ38
DQ35
DQ39
VSS
VSS
DM2
DQS2#
VSS
DQS2
DQ22
VSS
NOTES:
SA2 does NOT connect to memory connector and is shown ONLY on Block Diagram
SA2 is tied LOW on memory module for all memory configurations
VSS
DQ40
DQ44
DQ41
DQ45
DQ59
SA1
SDA
DQ23
SCL
August 2005
Rev. 0
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-D4
White Electronic Designs
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
S1#
S0#
DQS0
DQS0#
DM0
DQS4
DQS4#
DM4
DM
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
DM
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
DM
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
DM
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS1
DQS1#
DM1
DQS5
DQS5#
DM5
DM
DM
DM
DM
DQ8
DQ9
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS2#
DM2
DQS6
DQS6#
DM6
DM
DM
DM
DM
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS3
DQS3#
DM3
DQS7
DQS7#
DM7
DM
DM
DM
DM
CS# DQS DQS#
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS8
DQS8#
DM8
Serial PD
SCL
SDA
DM#
DM
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
WP A0 A1 A2
SA0 SA1 SA2
VCCSPD
VCC/VCCQ
VREF
Serial PD
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
S0# : DDR2 SDRAMs
S1# : DDR2 SDRAMs
S0#
S1#
VSS
BA0 - RBA1 : DDR2 SDRAMs
A0 - A12 : DDR2 SDRAMs
RAS# : DDR2 SDRAMs
CAS# : DDR2 SDRAMs
WE# : DDR2 SDRAMs
CKE : DDR2 SDRAMs
CKE : DDR2 SDRAMs
ODT : DDR2 SDRAMs
ODT : DDR2 SDRAMs
BA0 - BA1
A0 - A12
RAS#
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
CAS#
WE#
CKE0
CKE1
ODT0
ODT1
120Ω
CK
CK#
CK0
CK0#
PLL
RESET#
NOTE: All resistor values are 22 ohms unless otherwise specified.
August 2005
Rev. 0
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-D4
White Electronic Designs
ADVANCED
RECOMMENDED DC OPERATING CONDITIONS (SSTL_1.8V)
Rating
Parameter
Supply Voltage
Supply Voltage for DLL
Supply Voltage for Output
Input Reference Voltage
Termination Voltage
Symbol
VCC
VCCL
VCCQ
VREF
VTT
Min.
1.7
1.7
1.7
0.49*VCCQ
VREF-0.04
Type
1.8
1.8
1.8
0.50*VCCQ
VREF
Max.
1.9
1.9
1.9
0.51*VCCQ
VREF+0.04
Units
Notes
V
V
V
V
V
4
4
1, 2
3
There is no specific device VCC supply voltage requirement for SSTL-1.8 compliance. However under all conditions VCCQ must be less than or equal to VCC
1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF isexpected to be about 0.5 x VCCQ of the transmitting
device and VREF is expected to track variations in VCCQ
2. Peak to peak AC noise on VREF may not exceed 2ꢀ VREF(DC).
3. TT of transmitting device must track VREF of receiving device.
4. AC parameters are measured with VCC, VCCQ and VCCDL tied together.
.
.
V
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
VT
VCC
IOS
Rating
-0.5 to +2.3
-0.5 to +2.3
50
Units
V
V
mA
W
Voltage on any pin relative to VSS
Supply Voltage relative to VSS
Short Circuit Output Current
Power Dissipation
PD
18 (Max)
ENVIRONMENTAL
Parameter
Symbol
TOPR
HOPR
TSTG
Rating
0 to +85
10 to 90
-55 to +100
5 to 95
Units
°C
ꢀ
°C
ꢀ
Operating Case Temperature(1)
Operating Humidity (relative)
Storage Temperature
Storage Humidity (without condensation)
TSTG
NOTE:
1. Case Temperature is the case surface temperature on the center/top side of SDRAMs. For the measurement condition, please refer to JESD51-2 standard
CAPACITANCE
TA = 25°C, f = 1MHz, VCC = VCCQ = 1.8V
Parameter
Symbol
CI1
CI2
CI3
CO
Pins
Min
20.5
11.5
2
Max
38.5
20.5
3
Unit
pF
pF
pF
pF
Note
Control Signal Input Capacitance
Control Signal Input Capacitance
Clock Input Capacitance
Data & DQSI/O Capacitance
Address, RAS#, CAS#, WE#
CS#, CKE, ODT
CK, CK#
(1)
DQ, DQS, DQS#, DM, CB
7.5
10.5
NOTE:
1. PLL component specificatiion
August 2005
Rev. 0
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-D4
White Electronic Designs
ADVANCED
DDR2 IDD SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only
0°C ≤ TCASE < +70°C; VCCQ = + 1.8V 0.1V, VCC = +1.8V 0.1V
Symbol Proposed Conditions
IDD0 Operating one bank active-precharge current;
534
403
Units
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
1,530
1,440
mA
IDD1
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD);
CKE is HIGH, CS\ is HIGH between valid commands; Address businputs are SWITCHING; Data pattern is
same as IDD4W
1,620
1,485
mA
IDD2P
IDD2Q
IDD2N
IDD3P
Precharge power-down current;
All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING
144
450
540
144
450
540
mA
mA
mA
Precharge quiet standby current;
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputsare STABLE;
Data bus inputs are FLOATING
Precharge standby current;
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
Active power-down current;
All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0mA
540
270
540
270
mA
mA
Slow PDN Exit MRS(12) = 1mA
IDD3N
Active standby current;
All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
1,260
2,430
1,170
1,890
mA
mA
IDD4W
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP
= tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data
bus inputs are SWITCHING
IDD4R
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS
=
2,250
1,890
mA
tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as IDD4W
IDD5B
IDD6
IDD7
Burst auto refresh current;
tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
2,385
99
2,250
99
mA
mA
Self refresh current;
CK and CK\ at 0V; CKE 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC
tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address
=
3,105
3,015
mA
bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the following page for
detailed timing conditions
Note: IDD specification is based on Samsung components. Other DRAM Manufacturers specification may be different.
August 2005
Rev. 0
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-D4
White Electronic Designs
ADVANCED
AC TIMING PARAMETERS
0°C ≤ TCASE < +70°C; VCCQ = + 1.8V 0.1V, VCC = +1.8V 0.1V
534
403
Parameter
Symbol
Units
min
-500
-450
0.45
0.45
min (tCL, tCH
3750
225
max
+500
+450
0.55
0.55
x
min
-600
-500
0.45
0.45
min (tCL, tCH
5000
275
max
+600
+500
0.55
0.55
x
DQ output access time from CK/CK#
DQS output access time from CK/CK#
CK high-level width
tAC
tDQSCK
tCH
ps
ps
tCK
tCK
ps
ps
ps
ps
tCK
tCK
ps
ps
ps
ps
ps
ps
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
ps
tCK
tCK
ns
ns
ns
ns
tCK
CK low-level width
tCL
CK half period
tHP
)
)
Clock cycle time, CL=x
tCK
8000
x
8000
x
DQ and DM input hold time
tDH
DQ and DM input setup time
tDS
100
x
150
x
Control & Address input pulse width for each input
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK#
DQS low-impedance time from CK/CK#
DQ low-impedance time from CK/CK#
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
tIPW
0.6
—
0.6
—
tDIPW
tHZ
0.35
—
—
0.35
—
—
tAC max
tAC max
tAC max
300
400
—
tAC max
tAC max
tAC max
350
450
—
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tQH
tAC min
2* tAC min
—
tAC min
2* tAC min
—
—
—
DQ/DQS output hold time from DQS
Write command to first DQS latching transition
DQS input high pulse width
tHP - tQHS
WL-0.25
0.35
0.35
0.2
tHP - tQHS
WL-0.25
0.35
0.35
0.2
tDQSS
tDQSH
tDQSL
tDSS
tDSH
tMRD
tWPST
tWPRE
tIH
WL+0.25
—
WL+0.25
—
DQS input low pulse width
—
—
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
—
—
0.2
—
0.2
—
2
—
2
—
0.4
0.6
0.4
0.6
Write preamble
0.35
375
—
0.35
475
—
Address and control input hold time
Address and control input setup time
Read preamble
—
—
tIS
250
—
350
—
tRPRE
tRPST
tRRD
tRRD
tFAW
tFAW
tCCD
0.9
1.1
0.9
1.1
Read postamble
0.4
0.6
0.4
0.6
Active to active command period for 1KB page size products
Active to active command period for 2KB page size products
Four Activate Window for 1KB page size products
Four Activate Window for 2KB page size products
CAS# to CAS# command delay
7.5
—
7.5
—
10
—
10
—
37.5
50
37.5
50
2
2
NOTE: AC timing parameters are based on Samsung components. Other DRAM manufacturers parameters may be different.
Continued on next page
August 2005
Rev. 0
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-D4
White Electronic Designs
ADVANCED
AC TIMING PARAMETERS (continued)
0°C ≤ TCASE < +70°C; VCCQ = + 1.8V 0.1V, VCC = +1.8V 0.1V
534
403
Parameter
Symbol
Units
min
15
max
—
min
15
max
—
Write recovery time
tWR
tDAL
tWTR
tRTP
ns
tCK
ns
Auto precharge write recovery + precharge time
Internal write to read command delay
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
tWR+tRP
7.5
—
tWR+tRP
10
—
—
—
7.5
7.5
ns
tXSNR
tXSRD
tXP
tRFC + 10
200
tRFC + 10
200
ns
tCK
tCK
tCK
tCK
Exit precharge power down to any non-read command
Exit active power down to read command
2
—
—
2
—
—
tXARD
tXARDS
2
2
Exit active power down to read command
(Slow exit, Lower power)
6 - AL
6 - AL
CKE minimum pulse width (high and low pulse width)
ODT turn-on delay
tCKE
tAOND
tAON
3
2
3
2
tCK
tCK
ns
ns
2
2
ODT turn-on
tAC(min)
tAC(min) +2
tAC(max) +1
tAC(min)
tAC(min) +2
tAC(max) +1
tAONPD
2tCK +tAC
(max) +1
2tCK +tAC
(max) +1
ODT turn-on (Power-Down mode)
ODT turn-off delay
tAOFD
tAOF
2.5
2.5
2.5
2.5
tCK
ns
tAC(min)
tAC(max)
+0.6
tAC(min)
tAC(max)
+0.6
ODT turn-off
tAOFPD
tAC(min) +2
2.5tCK
+tAC(max)
+1
tAC(min) +2
2.5tCK
+tAC(max)
+1
ns
ODT turn-off (Power-Down mode)
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
tANPD
tAXPD
tOIT
3
3
tCK
tCK
ns
ns
8
0
8
0
12
12
Minimum time clocks remains ON after CKE asynchronously
drops LOW
tDelay
tIS+tCK +tIH
tIS+tCK +tIH
NOTE: AC timing parameters are based on Samsung components. Other DRAM manufacturers parameters may be different.
August 2005
Rev. 0
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-D4
White Electronic Designs
ADVANCED
ORDERING INFORMATION FOR D4
Part Number
Speed
CAS Latency
tRCD
4
tRP
4
Height*
WV3HG264M72EEU534D4-xG
266MHz/533Mb/s
200MHz/400Mb/s
4
3
31.75mm (1.25")
31.75mm (1.25")
WV3HG264M72EEU403D4-xG
3
3
NOTES:
• RoHS product. (“G” = RoHS Compliant)
• Vendor specific part numbers are used to provide memory component source control. The place holder for this is shown as a lower case "-x"
in the part numbers above and is to be replaced with respective vendors code. Consult factory for qualified sourcing options.
(M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR D4
67.60
(2.661)
3.80
(0.150) MAX.
Full R 2x
63.60
(2.504)
4.00 0.10
(0.158 0.039)
31.75
(1.25)
20
(0.787)
6.0
0.236
1
39
41
199
11.40
4.00
(0.158) MIN.
47.40
(0.449)
2- 1.80
(0.071)
(1.866)
2.15
(0.085)
4.20 (0.165)
2.40 (0.094)
1.0 0.1
(0.04 0.0039)
1.8
(0.071)
2.45
(0.098)
0.60
0.45 0.03
(0.024)
(0.018 0.001)
1.00 0.1
(0.04 0.0039)
0.25
(0.01)
2.55 Min
(0.102 Min)
4.00 0.10
(0.158 0.039)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
Tolerances: 0.13 (0.005) unless otherwise specified
August 2005
Rev. 0
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-D4
White Electronic Designs
ADVANCED
PART NUMBERING GUIDE
WV 3 H G 264M 72 E E U xxx D4 -x G
WEDC
MEMORY
DDR 2
GOLD
DEPTH (Dual Rank)
BUS WIDTH
x8
1.8V
UNBUFFERED
SPEED (MHz)
PACKAGE 200 PIN SO-DIMM
COMPONENT VENDOR
NAME
(M = Micron)
(S = Samsung)
G = RoHS COMPLIANT
August 2005
Rev. 0
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-D4
White Electronic Designs
ADVANCED
Document Title
1GB – 2x64Mx72 DDR2 SDRAM UNBUFFERED, w/PLL
Revision History
Rev #
History
Release Date Status
Rev 0
Created
August 2005
Advanced
August 2005
Rev. 0
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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