MH16V644AWJ-6 [MITSUBISHI]
FAST PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM; 快速页模式1073741824 - BIT （ 16777216 - WORD 64 - BIT）动态RAM
| 型号： | MH16V644AWJ-6 |
| 厂家： | 
Mitsubishi Group |
| 描述： | FAST PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM |
| 文件： | 总20页 (文件大小：188K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V644AWJ -5, -6
FAST PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM
DESCRIPTION
PIN CONFIGURATION
The MH16V644AWJ is 16777216-word x 64-bit dynamic
ram module. This consist of sixteen industry standard 16M
x 4 dynamic RAMs in SOJ and one industry standard
EEPROM in TSSOP.
85pin
1pin
The mounting of SOJs and TSSOP on a card edge dual
in-line package provides any application where high
densities and large of quantities memory are required.
This is a socket-type memory module ,suitable for easy
interchange or addition of module.
94pin
95pin
10pin
11pin
FEATURES
/RAS
access access access access
time time time time
/CAS Address /OE
Cycle
Power
Type name
time dissipation
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns)
(typ.W)
MH16V644AWJ-5
MH16V644AWJ-6
50
60
13
15
25
30
13
15
90
6.24
5.20
110
Utilizes industry standard 16M x 4 RAMs in SOJ and industry
standard EEPROM in TSSOP
168-pin (84-pin dual dual in-line package)
Single +3.3V(±0.3V) supply operation
124pin
125pin
40pin
41pin
FRONT SIDE
BACK SIDE
Low stand-by power dissipation
17.28mW(Max) . . . . . . . . . . . . . . . . . . . LVCMOS input level
Low operation power dissipation
MH16V64AWJ -5 . . . . . . . . . . . . . . . . . . 7.49W(Max)
MH16V64AWJ -6 . . . . . . . . . . . . . . . . . . 6.92W(Max)
All input are directly LVTTL compatible
All output are three-state and directly LVTTL compatible
Includes(0.22uF x 16) decoupling capacitors
4096 refresh cycle every 64ms
Fast-page mode,Read-modify-write,
/CAS before /RAS refresh,Hidden refresh capabilities
Gold plating contact pads
Row Address
A0 ~ A11
Column Address A0 ~ A11
168pin
84pin
APPLICATION
Main memory unit for computers , Microcomputer memory
MITSUBISHI
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ELECTRIC
( 1 / 20 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V644AWJ -5, -6
FAST PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM
PIN CONFIGURATION
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Vss
/OE2
/RAS2
/CAS2
/CAS3
/WE2
Vcc
85
86
Vss
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Vss
DU
NC
1
DQ32
DQ33
DQ34
DQ35
Vcc
2
3
87
/CAS6
88
4
89
5
/CAS7
DU
6
90
DQ4
DQ5
DQ6
DQ7
DQ8
Vss
91
DQ36
DQ37
DQ38
DQ39
DQ40
Vss
Vcc
7
NC
92
NC
8
NC
9
93
NC
NC
94
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
NC
95
NC
Vss
NC
96
Vss
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
DQ16
DQ17
DQ18
97
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ48
DQ49
DQ50
DQ51
Vcc
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
DQ19
Vcc
DQ20
NC
DQ52
NC
DQ14
DQ15
NC
DQ46
DQ47
DU
DU
NC
NC
NC
Vss
NC
NC
Vcc
NC
NC
Vss
Vss
Vss
DQ21
DQ22
DQ23
Vss
DQ53
DQ54
DQ55
Vss
NC
NC
Vcc
/WE0
/CAS0
/CAS1
/RAS0
/OE0
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DU
/CAS4
DQ56
DQ57
DQ58
DQ59
Vcc
/CAS5
NC
DU
Vss
A1
DQ60
DQ61
DQ62
DQ63
Vss
DQ28
DQ29
DQ30
DQ31
Vss
A0
A2
A3
A4
A5
A6
A7
A8
A9
NC
NC
A10
NC
A11
NC
Vcc
DU
DU
NC
NC
SA0
NC
Vcc
SDA
SCL
Vcc
SA1
SA2
Vcc
Vcc
DU
NC: No Connect
DU: Don't Use
MITSUBISHI
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ELECTRIC
( 2 / 20 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V644AWJ -5, -6
FAST PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM
BLOCK DIAGRAM
/RAS0
/WE0
/OE0
/RAS2
/WE2
/OE2
DQ32
DQ33
DQ34
DQ35
DQ0
DQ1
DQ2
DQ3
/OE
/W
/RAS
/RAS
/RAS
/RAS
/OE
/OE
/OE
/OE
/W
/RAS
/RAS
/RAS
/RAS
M5M465400AJ
D1
/CAS4
M5M465400AJ
D9
/CAS0
DQ4
DQ5
DQ6
DQ7
DQ36
DQ37
DQ38
DQ39
/OE
/W
/W
M5M465400AJ
M5M465400AJ
D2
D10
DQ8
DQ9
DQ10
DQ11
DQ40
DQ41
DQ42
DQ43
/OE
/W
/W
M5M465400AJ
D3
M5M465400AJ
D11
/CAS1
/CAS5
DQ44
DQ45
DQ46
DQ47
DQ12
DQ13
DQ14
DQ15
/OE
/W
/W
M5M465400AJ
D4
M5M465400AJ
D12
DQ16
DQ17
DQ18
DQ19
DQ48
DQ49
DQ50
DQ51
/OE
/W
/RAS
/RAS
/OE
/OE
/W
/RAS
/RAS
M5M465400AJ
D5
M5M465400AJ
D13
/CAS2
/CAS6
DQ52
DQ53
DQ54
DQ55
DQ20
DQ21
DQ22
DQ23
/OE
/W
/W
M5M465400AJ
D6
M5M465400AJ
D14
DQ24
DQ25
DQ26
DQ27
DQ56
DQ57
DQ58
DQ59
/OE
/W
/RAS
/RAS
/OE
/OE
/W
/RAS
/RAS
M5M465400AJ
D7
M5M465400AJ
D15
/CAS3
/CAS7
DQ60
DQ61
DQ62
DQ63
DQ28
DQ29
DQ30
DQ31
/OE
/W
/W
M5M465400AJ
M5M465400AJ
D8
D16
A0 ~ A11
Vcc
D1 ~ D16
D1 ~ D16
EEPROM
SCL
SDA
A0 A1 A2
C1 ~ C16
. . .
SA0 SA1 SA2
Vss
MITSUBISHI
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ELECTRIC
( 3 / 20 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V644AWJ -5, -6
FAST PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM
Serial Presence Detect TABLE
Bytes
Function described
Defines # bytes written into serial memory at module mfgr
Total # bytes of SPD memory device
Fundamental memory type
SPD entry data
128
SPD DATA entry(Hex)
0
1
2
3
4
5
6
7
8
9
80
256 Bytes
FPM DRAM
A0-A11
08
01
# Row Addresses on this assembly
# Column Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly...
0C
A0-A11
0C
1bank
01
x64
40
... Data Width continuation
0
00
Voltage interface standard of this assembly
3.3V LVTTL
50ns
02
RAS# access time of this assembly
CAS# access time of this assembly
-5
32
-6
-5
-6
60ns
3C
10
13ns
0D
15ns
0F
11
12
DIMM Configuration type (Non-parity,Parity,ECC)
Refresh Rate/Type
non parity
N/R(15.625uS)
x4
00
00
13
DRAM width,Primary DRAM
04
14
Error Checking DRAM data width
Reserved for future offerings
N/A
00
15-31
32-61
62
open
00
Superset Memory type(may be used in future)
SPD Data Revision Code
open
00
Rev 1
01
63
Checksum for bytes 0-62
Check sum for -5
Check sum for -6
MITSUBISHI
Miyoshi,Japan
Tajima,Japan
NC,USA
Germany
28
34
64-71
72
Manufacturers JEDEC ID code per JEP-106
Manufacturing location
1CFFFFFFFFFFFFFF
01
02
03
04
73-90
Manufacturer's Part Number
MH16V644AWJ-5 4D4831365636343441574A2D352D352020202020
MH16V644AWJ-6 4D4831365636343441574A2D362D362020202020
91-92
93-94
Revision Code
Manufacturing date
PCB revision
year/week code
serial number
open
rrrr
yy/ww
ssssssss
00
95-98
Assembly Serial Number
Manufacturer Specific Data
Reserved
99-125
126-127
128-255
open
00
Open User Free-Form area not defined
open
00
MITSUBISHI
MIT-DS-0122-0.0
26/Feb./1997
ELECTRIC
( 4 / 20 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V644AWJ -5, -6
FAST PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM
FUNCTION
The MH16V644AWJ provide, in addition to normal
read, write, and read-modify-write operations,
a number of other functions, e.g., Fsat page mode,
/CAS before /RAS refresh, and delayed-write. The
input conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Inputs
Input/Output
Refresh
Operation
Remark
Column
address
Row
Input
/RAS
/CAS
/W
/OE
Output
address
Read
ACT
ACT
ACT
ACT
ACT
ACT
NAC
ACT
ACT
ACT
ACT
ACT
ACT
DNC
NAC
ACT
ACT
ACT
DNC
NAC
DNC
ACT
DNC
DNC
ACT
ACT
DNC
DNC
APD
APD
APD
APD
DNC
DNC
DNC
APD
APD
APD
APD
DNC
DNC
DNC
OPN
VLD
VLD
VLD
OPN
DNC
DNC
VLD
OPN
IVD
VLD
VLD
OPN
OPN
YES
YES
YES
YES
YES
YES
NO
Fast page
mode
identical
Write (Early write)
Write (Delayed write)
Read-modify-write
Hidden refresh
/CAS before /RAS refresh
Standby
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open
MITSUBISHI
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ELECTRIC
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MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V644AWJ -5, -6
FAST PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter
Vcc Supply voltage
Conditions
Ratings
-0.5~ 4.6
Unit
V
With respect to Vss
IO
Output current
50
16
mA
W
Pd
Power dissipation
Operating temperature
Storage temperature
Ta=25°C
Topr
Tstg
0~70
°C
°C
-40~125
(Ta=0~70°C, unless otherwise noted) (Note 1)
Limits
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Unit
Min
3.0
0
Nom Max
Vcc
Vss
VIH
Supply voltage
V
V
V
3.3
0
3.6
0
Supply voltage
High-level input voltage, all inputs
Low-level input voltage
2.0
-0.3
Vcc+0.3
0.8
VIL
V
Note 1 : All voltage values are with respect to Vss
(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted) (Note 2)
ELECTRICAL CHARACTERISTICS
Limits
Symbol
Parameter
Test conditions
Unit
Max
Min
2.4
0
Typ
VOH
High-level output voltage
Low-level output voltage
Off-state output current
Input current (except /CAS)
IOH=-2.0mA
Vcc
0.4
10
V
VOL
IOZ
IOL=2.0mA
V
Q floating 0V £VOUT£ Vcc
0V£VIN£Vcc+0.3, Other input pins=0V
0V£VIN£Vcc+0.3, Other input pins=0V
-10
-160
-20
uA
uA
uA
I I
160
20
Input current (/CAS)
I I (CAS)
Average supply
current
from Vcc operating
/RAS, /CAS cycling
tRC=tWC=min.
output open
- 5
- 6
2080
1920
mA
ICC1 (AV)
(Note 3,4,5)
/RAS=/CAS =VIH, output open
16
8
Supply current from Vcc , stand-by
Average supply current
ICC2
mA
mA
/RAS=/CAS=WE³ Vcc -0.2, output open
/RAS=VIL,/CAS cycling
tPC=min.
output open
- 5
1600
1440
from Vcc
ICC4(AV)
Hyper-Page-Mode
- 6
(Note 3,4,5)
Average supply current from
Vcc
/CAS before /RAS refresh cycling
tRC=min.
output open
- 5
- 6
2080
1920
mA
/CAS before /RAS refresh
ICC6(AV)
(Note 3,5)
mode
Note 2: Current flowing into an IC is positive, out is negative.
3: Icc1 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open.
5: Under condition of column address being changed once or less while /RAS=VIL and /CAS=VIH
(Ta = 0~70°C, Vcc = 3.3V±0.3V, Vss = 0V, unless otherwise noted)
CAPACITANCE
Symbol
CI (/CAS) Input capacitance, /CAS input
Limits
Typ
Parameter
Unit
Test conditions
Min
Max
20
pF
pF
pF
CI
Input capacitance, except /CAS input
Input/Output capacitance,DATA
Input capacitance, SPD clock
130
VI=Vss
f=1MHZ
C(DQ)
C(SCL)
C(SDA)
22
7
Vi=25mVrms
pF
pF
pF
Input/Output capacitance,SPD DATA
7
7
C(SA0~3) Input capacitance, SPD address
MITSUBISHI
MIT-DS-0122-0.0
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ELECTRIC
( 6 / 20 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V644AWJ -5, -6
FAST PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM
(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted , see notes 6,13,14)
SWITCHING CHARACTERISTICS
Limits
Symbol
Parameter
Unit
- 5
- 6
Min
Max
15
Min
Max
13
ns
ns
ns
ns
ns
ns
ns
ns
tCAC
tRAC
tAA
Access time from /CAS
(Note 7,8)
(Note 7,9)
(Note 7,10)
(Note 7,11)
(Note 7)
60
Access time from /RAS
50
30
Column address access time
Access time from /CAS precharge
Access time from /OE
25
tCPA
tOEA
tCLZ
tOEZ
tOFF
35
30
15
13
Output low impedance time /CAS low
Output disable time after /OE high
Output disable time after /CAS high
(Note 7)
5
5
13
13
15
15
(Note 12)
(Note 12)
Note 6: An initial pause of 500us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles
containing /CAS before /RAS refresh).
Note the /RAS may be cycled during the initial pause . And any 8 /RAS or /RAS /CAS cycles are required after prolonged periods
(greater than 64 ms) of /RAS inactivity before proper device operation is achieved.
7: Measured with a load circuit equivalent to 1 TTL load and 100pF,VOH=2.4V(IOH=-2mA) and VOL=0.4V(IOL=-2mA).
The reference levels for measuring of output signals are 2.0V(VOH)and 0.8V(VOL).
8: Assumes that tRCD ³ tRCD(max), tASC ³ tASC(max) and tCP ³ tCP(max).
9: Assumes that tRCD £ tRCD(max) and tRAD £ tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table,
tRAC will increase by amount that tRCD exceeds the value shown.
10: Assumes that tRAD ³ tRAD(max) and tASC £ tASC(max).
11: Assumes that tCP £ tCP(max) and tASC ³ tASC(max).
12: tOEZ (max) and tOFF(max) defines the time at which the output achieves the high impedance state (IOUT £ I ± 10uA I ) and is not reference to
VOH(min) or VOL(max).
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Fast-Page Mode Cycles)
(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted ,see notes 13,14)
Limits
-5
-6
Symbol
Parameter
Unit
Min
Max
64
Min
Max
64
tREF
tRP
Refresh cycle time
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
/RAS high pulse width
30
18
5
40
20
10
0
tRCD
tCRP
tRPC
tCPN
tRAD
tASR
tASC
tRAH
tCAH
tDZC
tDZO
tCDD
tODD
tT
Delay time, /RAS low to /CAS low
Delay time, /CAS high to /RAS low
Delay time, /RAS high to /CAS low
/CAS high pulse width
(Note15)
(Note16)
37
45
0
10
13
0
10
15
0
Column address delay time from /RAS low
Row address setup time before /RAS low
25
5
30
10
Column address setup time before /CAS low
(Note17)
0
0
Row address hold time after /RAS low
Column address hold time after /CAS low
Delay time, data to /CAS low
Delay time, data to /OE low
Delay time, /CAS high to data
Delay time, /OE high to data
Transition time
8
10
15
0
13
0
(Note18)
(Note18)
(Note19)
(Note19)
(Note20)
0
0
13
13
1
15
15
1
50
50
ns
Note 13: The timing requirements are assumed tT =5ns.
14: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.VIH(min) and VIL(max) of the switching characteristics are
2.0V and 0.8V respectively.
15: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access
time is controlled exclusively by tCAC or tAA. .
16: tRAD(max) is specified as a reference point only. If tRAD³ tRAD(max) and tASC£tASC(max), access time is controlled exclusively by tAA.
17: tASC(max) is specified as a reference point only. If tRCD³ tRCD(max) and tASC³ tASC(max), access time is controlled exclusively by tCAC.
18: Either tDZC or tDZO must be satisfied.
19: Either tCDD or tODD must be satisfied.
20: tT is measured between VIH(min) and VIL(max).
MITSUBISHI
MIT-DS-0122-0.0
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ELECTRIC
( 7 / 20 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V644AWJ -5, -6
FAST PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM
Read and Refresh Cycles
Symbol
Limits
Parameter
-5
-6
Unit
Min
90
50
15
50
15
0
Max
Min
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
110
60
15
60
15
0
tRC
Read cycle time
tRAS
tCAS
tCSH
tRSH
tRCS
tRCH
tRRH
tRAL
10000
10000
/RAS low pulse width
10000
10000
/CAS low pulse width
/CAS hold time after /RAS low
/RAS hold time after /CAS low
Read Setup time after /CAS high
Read hold time after /CAS low
Read hold time after /RAS low
Column address to /RAS hold time
0
0
(Note 21)
(Note 21)
10
25
10
30
tORH
tOCH
13
13
15
15
/RAS hold time after /OE low
/CAS hold time after /OE low
Note 21: Either tRCH or tRRH must be satisfied for
a read cycle.
Write Cycle (Early Write and Delayed Write)
Limits
Symbol
Parameter
Unit
-5
-6
Min
90
50
15
50
15
0
Max
Min
110
60
15
60
15
0
Max
tWC
Write cycle time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10000
10000
tRAS
tCAS
tCSH
tRSH
tWCS
tWCH
tCWL
tRWL
tWP
/RAS low pulse width
10000
10000
/CAS low pulse width
/CAS hold time after /RAS low
/RAS hold time after /CAS low
Write setup time before /CAS low
Write hold time after /CAS low
/CAS hold time after /W low
/RAS hold time after /W low
Write pulse width
(Note 23)
10
15
15
10
0
10
15
15
10
0
tDS
Data setup time before /CAS low or /W low
Data hold time after /CAS low or /W low
tDH
10
10
tOEH
/OE hold time after /W low
13
15
Read-Write and Read-Modify-Write Cycles
Limits
Unit
Symbol
Parameter
-5
-6
Min
130
85
50
85
50
0
Max
Min
150
95
50
95
50
0
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRWC
tRAS
tCAS
tCSH
tRSH
tRCS
tCWD
tRWD
tAWD
Read write/read modify write cycle time
/RAS low pulse width
(Note22)
10000
10000
10000
10000
/CAS low pulse width
/CAS hold time after /RAS low
/RAS hold time after /CAS low
Read setup time before /CAS low
Delay time, /CAS low to /W low
Delay time, /RAS low to /W low
Delay time, address to /W low
(Note23)
(Note23)
(Note23)
30
65
40
30
75
45
tOEH
tCWL
/OE hold time after /W low
/CAS hold time after /W low
10
15
15
15
tRWL
tWP
tDS
/RAS hold time after /W low
15
10
0
15
10
0
Write pulse width
Data setup time before /CAS low or /W low
Data hold time after /CAS low or /W low
tDH
10
10
Note 22:tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.
24:tWCS, tCWD,tRWD ,tAWD and,tCPWD are specified as reference points only. If tWCS³ tWCS(min) the cycle is an early write cycle and the DQ pins will remain
high impedance throughout the entire cycle. If tCWD³ tCWD(min), tRWD³ tRWD (min), tAWD³ tAWD(min) and tCPWD ³ tCPWD(min) (for Hyper page mode cycle only),
the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access
time and until /CAS or /OE goes back to VIH) is indeterminate.
MITSUBISHI
MIT-DS-0122-0.0
26/Feb./1997
ELECTRIC
( 8 / 20 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V644AWJ -5, -6
FAST PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM
Fast Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle,) (Note 24)
Limits
Symbol
Parameter
Unit
-6
-5
Max
Max
Min
40
Min
35
70
85
5
Fast page mode read/write cycle time
ns
ns
ns
ns
ns
ns
tPC
tPRWC
tRAS
tCP
Fast page mode read write/read modify write cycle time
75
/RAS low pulse width for read write cycle
/CAS high pulse width
100
10
102400
15
(Note25)
(Note26)
102400
10
35
/RAS hold time after /CAS precharge
Delay time, /CAS precharge to W low
30
30
tCPRH
tCPWD
35
(Note23)
Note 24: All previously specified timing requirements and switching characteristics are applicable to their respective fast page mode cycle.
25: tRAS(min) is specified as two cycles of /CAS input are performed.
26: tCP(max) is specified as a reference point only. If tCP ³ tCP(max),access time is controlled exclusively by tCAC.
/CAS before /RAS Refresh Cycle (Note 27)
Limits
Symbol
Parameter
Unit
-5
-6
Max
Max
Min
5
Min
10
ns
ns
ns
ns
tCSR
tCHR
tRSR
tRHR
/CAS setup time before /RAS low
/CAS hold time after /RAS low
Read setup time before /RAS low
Read hold time after /RAS low
10
10
10
10
10
10
Note 27: Eight or more /CAS before /RAS cycles instead of eight /RAS cycles are necessary for proper operation of /CAS before /RAS refresh
mode.
MITSUBISHI
MIT-DS-0122-0.0
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ELECTRIC
( 9 / 20 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V644AWJ -5, -6
FAST PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM
Timing Diagrams (Note 28)
Read Cycle
tRC
tRAS
tRP
VIH
VIL
RAS
tCSH
tRPC
tCRP
tASR
tCRP
tRCD
tRSH
tCAS
VIH
VIL
CAS
tRAD
tRAL
tASR
tRAH
tASC
tCAH
tCPN
tRCH
VIH
VIL
ROW
ADDRESS
COLUMN
ROW
ADDRESS
ADDRESS
Address
tRRH
tRCS
VIH
VIL
W
tDZC
tCDD
VIH
VIL
DQ
(INPUTS)
Hi-Z
tCAC
tAA
tOFF
tCLZ
VOH
VOL
DQ
(OUTPUTS)
DATA VALID
tOEZ
Hi-Z
Hi-Z
tRAC
tDZO
tODD
tOEA
tOCH
VIH
VIL
OE
tORH
Indicates the don't care input.
VIH(min)£VIN£VIH(max) or VIL(min)£VIN£VIL(max)
Note 28
Indicates the invalid output.
MITSUBISHI
MIT-DS-0122-0.0
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ELECTRIC
(10 / 20 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V644AWJ -5, -6
FAST PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM
Write Cycle (Early write)
tWC
tRAS
tRP
VIH
RAS
VIL
tCSH
tRPC
tCRP
tASR
tRCD
tRSH
tCAS
tCRP
VIH
CAS
VIL
tASR
tRAH
tCAH
tASC
VIH
ROW
ADDRESS
COLUMN
ADDRESS
ROW
ADDRESS
Address
VIL
tWCS
tWCH
VIH
W
VIL
tDH
tDS
VIH
VIL
DQ
(INPUTS)
DATA VALID
VOH
VOL
DQ
(OUTPUTS)
Hi-Z
VIH
VIL
OE
MITSUBISHI
MIT-DS-0122-0.0
26/Feb./1997
ELECTRIC
( 11 / 20 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V644AWJ -5, -6
FAST PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM
Write Cycle (Delayed write)
tWC
tRAS
tRP
VIH
RAS
VIL
tCSH
tRPC
tCRP
tASR
tRCD
tRSH
tCAS
tCRP
VIH
CAS
VIL
tRAH
tCAH
tASC
tASR
VIH
ROW
ADDRESS
COLUMN
ADDRESS
ROW
ADDRESS
Address
VIL
tCWL
tRWL
tWP
tRCS
VIH
W
VIL
tWCH
tDZC
tDS
tDH
VIH
DQ
DATA
VALID
Hi-Z
tCLZ
(INPUTS)
VIL
VOH
DQ
Hi-Z
Hi-Z
(OUTPUTS)
VOL
tOEH
tOEZ
tDZO
tODD
VIH
OE
VIL
MITSUBISHI
MIT-DS-0122-0.0
26/Feb./1997
ELECTRIC
(12 / 20 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V644AWJ -5, -6
FAST PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM
Read-Write, Read-Modify-Write Cycle
tRWC
tRAS
tRP
VIH
RAS
VIL
tCSH
tRPC
tRCD
tRSH
tCAS
tCRP
tCRP
VIH
CAS
VIL
tRAD
tASR
tRAH
tCAH
tASR
tASC
VIH
ROW
ADDRESS
COLUMN
ADDRESS
ROW
ADDRESS
Address
VIL
tAWD
tCWL
tRWL
tWP
tCWD
tRWD
tRCS
VIH
W
VIL
tDH
tDS
tDZC
VIH
VIL
DQ
(INPUTS)
DATA VALID
Hi-Z
tCAC
tAA
tCLZ
VOH
VOL
DQ
(OUTPUTS)
DATA
VALID
Hi-Z
Hi-Z
tRAC
tODD
tDZO
tOEA
tOEH
tOEZ
VIH
VIL
OE
MITSUBISHI
MIT-DS-0122-0.0
26/Feb./1997
ELECTRIC
(13 / 20 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V644AWJ -5, -6
FAST PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM
CAS before RAS Refresh Cycle
tRC
tRC
tRP
tRAS
tRAS
tRP
VIH
VIL
RAS
tCRP
tCSR
tRPC tCSR
tRPC
tRPC
tCHR
tCHR
VIH
VIL
CAS
tCPN
tASR
VIH
VIL
COLUMN
ADDRESS
ROW
ADDRESS
Address
tRCH tRSR
tRHR
tRSR
tRHR
tRCS
VIH
VIL
W
VIH
VIL
DQ
(INPUTS)
tOFF
tOEZ
VOH
VOL
DQ
(OUTPUTS)
Hi-Z
VIH
VIL
OE
MITSUBISHI
MIT-DS-0122-0.0
26/Feb./1997
ELECTRIC
(14 / 20 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V644AWJ -5, -6
FAST PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM
Hidden Refresh Cycle (Read) (Note 29)
tRC
tRC
tRAS
tRP
tRAS
tRP
VIH
VIL
RAS
CAS
tCRP
tRCD
tRSH
tCHR
VIH
VIL
tRAD
tASR
tRAH tASC
tCAH
tASR
VIH
VIL
ROW
ADDRESS
COLUMN
ADDRESS
ROW
ADDRESS
Address
tRCS
tRRH
tRAL
VIH
VIL
W
tDZC
tCDD
tOFF
VIH
VIL
DQ
(INPUTS)
Hi-Z
tCAC
tAA
tCLZ
VOH
VOL
DQ
(OUTPUTS)
Hi-Z
DATA VALID
Hi-Z
tRAC
tDZO
tOEZ
tOEA
tORH
tODD
VIL
VIH
OE
Note 29: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle.
Timing requirements and output state are the same as that of each cycle shown above.
MITSUBISHI
MIT-DS-0122-0.0
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ELECTRIC
( 15 / 20 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V644AWJ -5, -6
FAST PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM
Fast Page Mode Read Cycle
tRAS
tRP
VIH
VIL
RAS
tCSH
tPC
tRSH
tCAS
tCRP
tASR
tRCD
tCAS
tCP
tCAS
tCP
VIH
VIL
CAS
tCPRH
tASC
tRAD
tRAH
tASC
tCAH
tCAH
tCAH
tASR
tASC
ROW
ADDRESS
VIH
VIL
ROW
COLUMN-1
COLUMN-2
tRCS
COLUMN-3
Address
ADDRESS
tRAL
tRCS
tRCH
tRCS
tRRH
tRCH
tRCH
VIH
VIL
W
tDZC
tCDD
tDZC
tDZC
VIH
VIL
DQ
(INPUTS)
Hi-Z
Hi-Z
tCAC
tAA
tOFF
tOFF
tCAC
tAA
tOFF
tCAC
tAA
tCLZ
tCLZ
tCLZ
VOH
VOL
DATA
VALID-1
DATA
VALID-2
DATA
VALID-3
DQ
(OUTPUTS)
Hi-Z
tRAC
tDZO
tCPA
tCPA
tOEZ
tOEA
tOCH
tOEA
tOCH
tOEA
tOCH
tOEZ
tOEZ
VIL
VIH
OE
tODD
tDZO
tDZO
tODD
tODD
tORH
MITSUBISHI
MIT-DS-0122-0.0
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ELECTRIC
( 16 / 20 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V644AWJ -5, -6
FAST PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM
Fast Page Mode Write Cycle (Early Write)
tRAS
tRP
VIH
VIL
RAS
tCSH
tPC
tRSH
tCAS
tCRP
tASR
tRCD
tCAS
tCP
tCAS
tCP
VIH
VIL
CAS
tRAH
tCAH
tCAH
tCAH
tASC
tASC
tASC
tASR
ROW
ADDRESS
VIH
VIL
ROW
ADDRESS
COLUMN-1
COLUMN-3
COLUMN-2
Address
tWCS
tWCH
tWCS
tWCH
tWCS
tWCH
VIH
VIL
W
tDH
tDS
tDS
tDH
tDS
tDH
VIH
VIL
DATA
VALID-1
DATA
VALID-2
DATA
VALID-3
DQ
(INPUTS)
VOH
VOL
DQ
(OUTPUTS)
Hi-Z
VIH
VIL
OE
MITSUBISHI
MIT-DS-0122-0.0
26/Feb./1997
ELECTRIC
(17 / 20 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V644AWJ -5, -6
FAST PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM
Fast-Page Mode Write Cycle (Delayed Write)
tRAS
tRP
VIH
VIL
RAS
tCSH
tRSH
tPC
tCRP
tASR
tRCD
tCAS
tCP
tCAS
VIH
VIL
CAS
tRWL
tASC
tRAH
tCAH
tCAH
tCWL
tASC
tASR
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN-1
Address
COLUMN-2
tCWL
tWP
tPCS
tRCS
tWP
VIH
VIL
W
tWCH
tDS
tWCH
tDS
tDZC
tDZC
tDH
tDH
VIH
VIL
DATA
VALID-1
DATA
VALID-2
DQ
(INPUTS)
Hi-Z
Hi-Z
tCLZ
tDZO
tCLZ
VOH
VOL
DQ
(OUTPUTS)
Hi-Z
Hi-Z
Hi-Z
tOEZ
tOEZ
tOEH
tODD
tDZO
tODD
VIH
VIL
OE
MITSUBISHI
MIT-DS-0122-0.0
26/Feb./1997
ELECTRIC
( 18 / 20 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V644AWJ -5, -6
FAST PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM
Fast Page Mode Read-Write,Read-Modify-Write Cycle
tRAS
tRP
VIH
VIL
RAS
CAS
tCSH
tRWL
tCRP
tASR
tRCD
tCAS
tPRWC
tCAS
tCP
VIH
VIL
tRAD
tRAH
tASC
tCAH
tCAH
tCWL
tASC
tASR
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN-1
COLUMN-2
Address
tAWD
tCWD
tAWD
tCWD
tCWL
tWP
tRCS
tRCS
tWP
VIH
VIL
W
tRWD
tCPWD
tDZC
tDZC
tDH
tDH
tDS
tDS
DQ
(INPUTS)
VIH
VIL
DATA
VALID-1
DATA
VALID-2
Hi-Z
Hi-Z
tCAC
tCAC
tAA
tAA
tCLZ
tRAC
tCLZ
VOH
VOL
DQ
(OUTPUTS)
DATA
VALID-1
DATA
VALID-1
Hi-Z
Hi-Z
Hi-Z
tCPA
tODD
tOEZ
tODD
tDZO tOEA
tOEH
tDZO
tOEZ
tOEA
VIH
VIL
OE
MITSUBISHI
MIT-DS-0122-0.0
26/Feb./1997
ELECTRIC
( 19 / 20 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V644AWJ -5, -6
FAST PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM
Unit:mm
Package outline
133.35
8.6MAX
3.0
127.35
2-R2.0
2.0
2.0
1.27
2-ø3.0
1.27
6.35
29x1.27=36.83
9x1.27=11.43
6.35
43x1.27=54.61
8.89
42.18
24.495
MITSUBISHI
ELECTRIC
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26/Feb./1997
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/ 20 )
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