PUMA84S32000LI-85 [MOSAIC]

SRAM Module, 1MX32, 85ns, CMOS, PQCC84, PLASTIC, LCC-84;


型号：	PUMA84S32000LI-85
厂家：	MOSAIC
描述：	SRAM Module, 1MX32, 85ns, CMOS, PQCC84, PLASTIC, LCC-84 静态存储器内存集成电路
文件：	总7页 (文件大小：163K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

1M x 32 SRAM MODULE

PUMA 84S32000 - 70/85/10

11403 West Bernado Court, Suite 100, San Diego, CA 92127.

Tel No: (619) 674 2233, Fax No: (619) 674 2230

Issue 2.1 : January 1999

Description

Features

The PUMA 84S32000 is a 32Mbit CMOS Static RAM

•

Access times of 70/85/100 ns.

organised as 1M x 32 in a JEDEC 84 pin surface mount

J-leaded PLCC, available with access times of 70, 85,

and 100ns. The output width is user configurable as 8,

16 or 32 bits using eight Chip Selects (CS1~8).

The PUMA 84S32000 offers a dramatic space saving

advantage over eight standard 512Kx8 devices. The -L

version has data retention capability and can be used in

battery backup applications.

High Density Package

JEDEC 84 'J' leaded plastic Surface Mount

Package.

•

Single 5.0 V±10% Power supply.

User Configurable as 8 / 16 / 32 bit wide output.

Operating Power

(32-BIT) 2.51 W (max)

Low Power Standby (-L)

Fully Static operation.

8.25 mW (max)

•

Data Retention Capability (-L version only).

Multiple ground pins for maximum noise immunity.

Block Diagram

Pin Definition

A0 - A18

11 10

1 84 83 82 81 80 79 78 77 76 75

D14

D13

D12

GND

D11

D10

512K x 8

SRAM

512K x 8

SRAM

D0 - D7

D17

D18

D19

GND

D20

D21

D22

D23

VCC

D24

D25

D26

D27

GND

D28

D29

D30

D0 - D7

CS5

CS1

512K x 8

SRAM

512K x 8

SRAM

D8 - D15

CS6

D8 - D15

PUMA 84S32000

CS2

CS3

VCC

VIEW

FROM

ABOVE

512K x 8

SRAM

512K x 8

SRAM

D16 - D23

CS7

D16 - D23

GND

512K x 8

SRAM

512K x 8

SRAM

D24 - D31

CS8

D24 - D31

CS4

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

Pin Functions

Address Inputs

Data Input/Output

Chip Select

A0 ~ A18

D0 ~ D31

CS1 ~ 8

Package Details

Write Enable

Output Enable

No Connect

Plastic 84 J-Leaded JEDEC PLCC

Power (+5V)

Ground

V_CC

GND

ISSUE 2.1 : January 1999

PUMA 84S32000 - 70/85/10

DC OPERATING CONDITIONS

Absolute Maximum Ratings ⁽¹⁾

Voltage on any pin relative to GND

Power Dissipation

V_T

P_T

-0.3V to 7.0

4.5

Storage Temperature

T_STG-55 to +125 ^°C

Notes (1) Stresses above those listed may cause permanent damage. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may

affect device reliability.

Recommended Operating Conditions

Parameter

Symbol

min

typ

max

Units

Supply Voltage

V_CC

V_IH

V_IL

T_A

T_AI

4.5

2.2

-0.3

5.0

5.5

V_CC+0.3

0.8

Input High Voltage

Input Low Voltage

Operating Temperature

(1)

-40

( Suffix I )

Notes: (1) Pulse width: -3.0V for less than 40ns.

DC Electrical Characteristics (V_CC=5V±10%,T_A=-40°C to +85°C)

Parameter

Symbol Test Condition

min typ max Unit

Input Leakage Current

Output Leakage Current

I_LI1

I_LO

V_IN=0V to V_CC

V_I/O=0V to V_CC

-8

µA

Operating Supply Current⁽²⁾32 bit I_CC32Cycle time = min 100% duty I_I/O=0mA

CS=V_ILV_IN= V_IHor V_IL

456

244

16 bit I_CC16As above.

8 bit I_CC8

As above.

138

Standby Supply Current

(TTL) I_SB

CS⁽¹⁾=V_IH, V_IN=V_ILor V_IH

CS≥V_CC-0.2V,Other inputs = 0~V_CC

-L Version (CMOS) I_SB1

Output Voltage Low

Output Voltage High

V_OL

V_OH

I_OL= 2.1mA,V_CC=Min

I_OH= -1.0mA,V_CC=Min

0.4

2.2

Notes: (1) CS1~4 or CS5~8 inputs operate simultaneously for 32 bit mode.

Capacitance (V_CC=5V, T_A=25°C, F=1Mhz)

Parameter

Symbol

Test Condition

min

typ

max

Unit

Input Capacitance Address,OE,WE

C_IN1

C_I/O

V_IN=0V

V_I/O=0V

Output Capacitance 8-bit mode (worst case)

Note: These parameters are calculated, not measured.

PUMA 84S32000 - 70/85/10

ISSUE 2.1 : January 1999

AC Test Conditions

Output Load

I/O Pin

166^Ω

*Input pulse levels: 0.8V to 2.4V

1.76V

*Input rise and fall times: 5 ns

*Input and Output timing reference levels: 1.5V

*V_cc=5V±10%

30pF

*PUMA module is tested in 32 bit mode.

Operation Truth Table

Below is the truth table which applies to each individual SRAM on the module. When operating the

module care should be taken to prevent any two SRAM components which are connected to the same

data byte from driving the bus simultaneously. This will prevent bus contention occurring on the module.

Please refer to the block diagram on the front page of this datasheet.

Mode

CS OE

V_CCCurrent

I/O Pin Reference Cycle

Not Selected

Output Disable

Read

I_SB1,I_SB2

I_CC1

High Z

D_OUT

Power Down

I_CC1

Read Cycle

Write Cycle

Write

I_CC1

D_IN

1 = V_IH,

0 = V_IL,

X = Don't Care

Low V_CCData Retention Characteristics - L version only

Parameter

Symbol

V_DR

Test Condition

CS=V_CC-0.2V

min

typ

max

Unit

V_CCfor Data Retention

Data Retention Current

Data Retention Time

2.0

(1)

I_CCDR1

V_CC= 3.0VA, CS > V_CC-0.2V, V_IN>0V

See Retention Waveform

1.5 mA

t_CDR

t_R

Operation Recovery Time

See Retention Waveform

ISSUE 2.1 : January 1999

PUMA 84S32000 - 70/85/10

AC OPERATING CONDITIONS

Read Cycle

Parameter

Symbol

min

max

min

max

min

max Units

Read Cycle Time

t_RC

t_AA

100

Address Access Time

Chip Select Access Time

t_ACS

t_OE

Output Enable to Output Valid

Output Hold from Address Change

Output Enable to Output in Low Z

Output Disable to Output in High Z

Chip Disable to Output in High Z

Chip Enable to Output in Low Z

t_OH

t_OLZ

t_OHZ

t_CHZ

t_CLZ

Write Cycle

Parameter

Symbol

min

max

min

max

min

max Units

Write Cycle Time

t_WC

t_CW

t_AW

t_AS

100

Chip Selection to End of Write

Address Valid to End of Write

Address Setup Time

Write Pulse Width

t_WP

t_WR

t_DW

t_OW

t_DH

Write Recovery Time

Data to Write Time Overlap

Output Active from End of Write

Data Hold from Write Time

Write to Output High Z

t_WHZ

PUMA 84S32000 - 70/85/10

ISSUE 2.1 : January 1999

Read Cycle Timing Waveform^(1,2)

t _RC

Address

t_AA

t_OE

t_OLZ

t_OH

CS1~4

Don't

care.

t_ACS

t_{OHZ (3)}

t_{CLZ (4,5)}

Dout

Data Valid

t_{CHZ (3,4,5)}

AC Read Characteristics Notes

(1) WE is High for Read Cycle.

(2) All read cycle timing is referenced from the last valid address to the first transition address.

(3) t_CHZand t_OHZare defined as the time at which the outputs achieve open circuit conditions and are not

referenced to output voltage levels.

(4) At any given temperature and voltage condition, t_CHZ(max) is less than t_CLZ(min) both for a given module

and from module to module.

(5) These parameters are sampled and not 100% tested.

Write Cycle No.1 Timing Waveform^(1,4)

t_WC

Address

t_WR(7)

t_AS(6)

t_AW

t_CW

CS1~48

Don't

Care

t_OHZ(3,9)

t_OW

t_WP(2)

(8)

High-Z

Dout

Din

t_DW

Data Valid

t_DH

High-Z

ISSUE 2.1 : January 1999

PUMA 84S32000 - 70/85/10

Write Cycle No.2 Timing Waveform ^(1,5)

t_WC

Address

t_AS(6)

t_CW

t_WR(7)

CS1~4

t_AW

t_WP(2)

Dout

Din

t_OH

Don't

Care

t_WHZ(3,9)

t_OW

(4)

(8)

High-Z

t_DH

t_DW

High-Z

Data Valid

AC Write Characteristics Notes

(1) All write cycle timing is referenced from the last valid address to the first transition address.

(2) All writes occur during the overlap of CS1~8 and WE low.

(3) If OE, CS1~8, and WE are in the Read mode during this period, the I/O pins are low impedance state.

Inputs of opposite phase to the output must not be applied because bus contention can occur.

(4) Dout is the Read data of the new address.

(5) OE is continuously low.

(6) Address is valid prior to or coincident with CS1~8 and WE low, too avoid inadvertant writes.

(7) CS1~8 or WE must be high during address transitions.

(8) When CS is low : I/O pins are in the output state. Input signals of opposite phase leading to the

output should not be applied.

(9) Defined as the time at which the outputs achieve open circuit conditions and are not referenced to

output voltage levels. These parameters are sampled and not 100% tested.

Data Retention Waveform

DATA RETENTION MODE

Vcc

4.5V

2.2V

t_CDR

t_R

2.2V

V_DR

CS1~4 > Vcc -0.2V

CS1~48

PUMA 84S32000 - 70/85/10

ISSUE 2.1 : January 1999

Package Information

Dimensions in mm(inches)

Plastic 84 Pin JEDEC Surface mount PLCC

0.10 (0.004)

30.35 (1.195) sq.

30.10 (1.185) sq.

8.50

(0.335) max

1.27

(0.050) typ.

0.46

(0.018) typ.

0.90 (0.035) typ.

Ordering Information

PUMA 84S32000LI - 70

Speed

70 ns

85 ns

100 ns

Temperature Range

Power Consumption

Blank

Commercial Temperature

Industrial Temperature

Blank

Standard

Low Power

Organisation

32000

1M x 32 SRAM

configurable as 2M x 16

and 4M x 8

Memory Type

Package

Asynchronous SRAM

PUMA 84

Memory Stack 84 pin 'J'

Leaded

Note :

Although this data is believed to be accurate, the information contained herein, is not intended to and does not create

any warranty of merchantibility or fitness for a particular purpose.

Our products are subject to a constant process of development. Data may be changed at any time without notice.

Products are not authorised for use as critical components in life support devices without the express approval of a

company director.

PUMA84S32000LI-85 [MOSAIC]

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