MC141535T_技术文档

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

MC141535

LCD Segment / Common Driver

with Controller

CMOS

TAB

MC141535 is a CMOS LCD Driver which consists of 4 annunciator outputs

and 178 high voltage LCD driving signals (17 rows and 161 segments). It has

parallel interface capability for operating with general MCU. Besides the gen-

eral LCD driver features, it has on chip LCD bias voltage generator circuit so

that limited external components are required during application.

• Single Supply Operation, 2.4 V - 3.5 V

• Low Current Stand-by Mode (<500nA)

• On Chip Bias Voltage Generator

• 8 Bit Parallel Interface

• Graphic Mode Operation

• On Chip Graphic Display Data RAM

• Four Static Annunciator (Icon) Drivers

• Low Power Icon Mode Driven by Com16 in Special Driving Scheme

• 161 Segment Drivers, 17 Row Drivers

• 1:5 Bias Ratio

Gold Bump Die

ORDERING INFORMATION

MC141535T

TAB

• 1/17 Multiplex Ratio

MCC141535Z Gold Bump Die

• Master Clear RAM (Main Dot Matrix Display / Icons Display)

• Vertical and Horizontal Scrolling for Main Display

• Re-mapping of Row and Column Drivers

• Selectable LCD Driving Voltage Temperature Compensation

• 16 Level Internal Contrast Control

• External Contrast Control

• Standard TAB, Gold Bump Die

REV 5

2/98

MC141535

3–72

MOTOROLA

Block Diagram

Annun0

to

Annun3

Com0 to

Com16

BP

Seg0~Seg160

Level

Selector

HV Buffer Cell Level Shifter

Annunciator

Control

Circuit

VLL6

17 Bit

VLL2

VCC

161 Bit Latch

Latch

VR

OSC1

OSC2

Display

Timing

Generator

VF

MUX

Selection

LCD Driving

Voltage Generator

C2P

C2N

C1P

C1N

DUM2

DUM1

C+

Tripler,

Doubler,

Voltage Regulator,

Voltage Divider,

Constrast Control,

Temperature

Horizontal / Vertical

Scroll Register

GDDRAM

17 x 161Bits

Compensation

C-

AVDD

AVSS

Command Decoder

DVSS

DVDD

Command Interface

Parallel Interface

D/C

RES

CS (CLK)

R/W

D0~D7

MOTOROLA

MC141535

3–73

MC141535T PIN ASSIGNMENT

(COPPER VIEW)

MC141535

3–74

MOTOROLA

Dummy

Bump

285

254

253

SEG140

SEG139

SEG138

SEG137

SEG136

SEG135

SEG134

SEG133

SEG132

SEG131

SEG130

SEG129

SEG128

SEG127

SEG126

SEG125

SEG124

SEG123

SEG122

SEG121

SEG120

SEG119

SEG118

SEG117

SEG116

SEG115

SEG114

SEG113

SEG112

SEG111

SEG110

SEG109

SEG108

SEG107

SEG106

SEG105

SEG104

SEG103

SEG102

SEG101

SEG100

SEG99

SEG98

SEG97

SEG96

SEG95

SEG94

SEG93

SEG92

SEG91

SEG90

SEG89

SEG88

SEG87

SEG86

SEG85

SEG84

SEG83

SEG82

SEG81

SEG80

SEG79

SEG78

SEG77

SEG76

SEG75

SEG74

SEG73

SEG72

SEG71

SEG70

SEG69

SEG68

SEG67

SEG66

SEG65

SEG64

SEG63

SEG62

SEG61

SEG60

SEG59

SEG58

SEG57

SEG56

SEG55

SEG54

SEG53

SEG52

SEG51

SEG50

SEG49

SEG48

SEG47

SEG46

SEG45

SEG44

SEG43

SEG42

SEG41

SEG40

SEG39

SEG38

SEG37

SEG36

SEG35

SEG34

SEG33

SEG32

SEG31

SEG30

SEG29

SEG28

SEG27

SEG26

SEG25

SEG24

SEG23

SEG22

SEG21

SEG20

1

N/C

N/C*

DVDD

RES

D/C

R/W

CS

A

O

1

Alignment Mark

Co-ordination

X (µm)

Y(µm)

1267.3

1359

DVSS

D0

A

B

5156.

5184

D1

D2

D3

D4

D5

O

-4483.3

4388.2

5165.8

-5267.9

444

556.1

1

2

3

D6

D7

O

556.1

N/C

AVSS

VF

-1349.4

-1311.8

D

d

O , O and O are the centers of

1

2

3

the circular alignment marks which

diameter are d. D is the center of

the square dummy bump with

edges equal to 270µm

270µm

135µm

270µm

AVSS

C2P

C2N

C1P

C1N

C+

135µm

A or B

C-

VR

The “L” shape alignment mark

VLL2

VLL3

VLL4

VLL5

VLL6

OSC1

VCC

OSC2

AVDD

N/C

Y

O

2

B

X

O

101

3

133

100

132

MC141535 Die Pad Assignment

MOTOROLA

MC141535

3–75

This device contains circuitry to protect the inputs

against damage due to high static voltages or elec-

tric ﬁelds; however, it is advised that normal precau-

tions to be taken to avoid application of any voltage

higher than maximum rated voltages to this high

impedance circuit. For proper operation it is recom-

MAXIMUM RATINGS* (Voltages Referenced to V , T =25˚C)

SS

A

Symbol

AV ,DV

Parameter

Value

Unit

Supply Voltage

Input Voltage

-0.3 to +4.0

V

DD

V

-0.3 to V +10.5

SS SS

CC

mended that V and V

be constrained to the

in

out

V

-0.3 to V +0.3

V

in

SS

DD

range V < or = (V or V ) < or = V . Reliability

SS

in

out

DD

I

Current Drain Per Pin Excluding V and V

25

mA

of operation is enhanced if unused input are con-

nected to an appropriate logic voltage level (e.g.,

DD

SS

Operating Temperature

For Using Internal Oscillator

For Using External Oscillator

either V

or V ). Unused outputs must be left

SS

DD

T

-25 to +85

-30 to +85

˚C

A1

open. This device may be light sensitive. Caution

should be taken to avoid exposure of this device to

any light source during normal operation. This

device is not radiation protected.

T

A2

T

Storage Teperature Range

-65 to +150

˚C

stg

* Maximum Ratings are those values beyond which damage to the device may occur. Functional

operation should be restricted to the limits in the Electrical Characteristics tables or Pin Descrip-

tion section.

V

= AV = DV (DV = V of Digital circuit, AV = V of Analogue Circuit)

SS

DD

SS SS SS SS SS SS

= AV = DV (DV = V of Digital circuit, AV = V of Analogue Circuit)

DD

ELECTRICAL CHARACTERISTICS (Voltage Referenced to V , T =25˚C)

SS

A

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

Supply voltage (Absolute value Referenced to V

)

SS

DV

AV

Operating Range of Logic Circuit Supply DV

2.4

3.0

-

3.5

V

DD

Operating Range of Voltage Generator Circuit

Supply AV

DD

Supply Current (Measure with V ﬁxed at 3.0V)

DD

I

Access Mode Supply Current Drain from Pin AVDD Internal DC/DC Converter On, Display On, Tripler

0

-

200

70

300

100

110

30

µA

AC

and DVDD.

Enable, R/W Accessing, T =1MHz, Osc. Freq.

cyc

=38.4kHz, 1/17 Duty Cycle,1/7 Bias.

Display Mode Supply Current Drain from Pin AVDD Internal DC/DC Converter On, Display On, Nor-

I

DP1

DP2

and DVDD.

mal Display Mode, Tripler Enable, R/W Halt, Osc.

Freq.=38.4kHz.

I

Display Mode Supply Current Drain from Pin AVDD Internal DC/DC Converter On, Display On, Nor-

78

and DVDD

mal Display Mode, Tripler Enable, R/W Halt, Osc.

Freq.=38.4kHz. Horizontal Scrolling

I

Display Mode Supply Current Drain from Pin AVDD Internal DC/DC Converter On, Display On, Icon

15

ICON

and DVDD

Display Mode, Tripler Enable, R/W Halt, Osc.

Freq.=38.4kHz.

I

Stand-by Mode Supply Current Drain from Pin

AVDD and DVDD

Stand-by Mode Supply Current Drain from Pin

AVDD and DVDD.

Stand-by Mode Supply Current Drain from Pin

AVDD and DVDD.

Display Off, Oscillator Disabled, R/W Halt

0

300

2.5

5

500

5

nA

µA

SB1

SB2

SB3

Display Off, Oscillator Enable, R/W Halt, External

Oscillator and Frequency = 38.4kHz.

Display Off, Oscillator Enable, R/W Halt, Internal

Oscillator and Frequency = 38.4kHz.

7

VLCD Voltage

LCD Driving Voltage Generator Output Voltage at

Pin V

V

Display On, Internal DC/DC Converter Enabled,

Tripler Enable, Osc. Freq. = 38.4kHz, Regulator

Enabled, Divider Enabled

Display On, Internal DC/DC Converter Enabled,

Doubler Enable, Osc. Freq. = 38.4kHz, Regulator

Enabled, Divider Enabled

-

3*AV

2*AV

-

10.5

V

CC1

CC2

DD

.

CC

LCD Driving Voltage Generator Output Voltage at

Pin V

.

CC

LCD Driving Voltage input at pin V

.

Internal DC/DC Converter Disabled.

AV

DD

LCD

CC

Output Voltage

V

Output High Voltage at Pins D0-D7, Annun0-3, BP

and OSC2.

Output Low Voltage at Pins D0-D7, Annun0-3, BP

and OSC2.

I

=100µA

0.9*V

0

-

V

DD

V

OH1

out

DD

V

0.1*V

DD

OL1

out

V

∆V

LCD Driving Voltage Source at Pin VR

Delta of VR Voltage Drop

Regulator Enabled

Regulator Disabled

Regulator Enabled, I =50µA

0

-

0

-

0

-

V

-0.5

CC

-

VCC

±2.5

V

R1

R2

R3

out

Variation of V Input (V is ﬁxed)

Regulator Enabled

±1

%

R

DD

MC141535

3–76

MOTOROLA

ELECTRICAL CHARACTERISTICS (Voltage Referenced to V , T =25˚C)

SS

A

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

Input Voltage

V

Input High Voltage at Pins, RES, CS, D0-D7, R/W,

D/C, OSC1 and OSC2.

Input Low Voltage at Pins, RES, CS, D0-D7, R/W,

D/C, OSC1 and OSC2.

0.8*V

0

-

V

DD

V

IH1

DD

V

0.2*V

IL1

DD

LCD Display Voltage. (LCD Driving Voltage Output from Voltage Drivder Enabled, Regulator Enabled.

Pins VLL6, VLL5, VLL4, VLL3 and VLL2.)

V

-

V

-

V

LL6

LL5

LL4

LL3

LL2

R

0.8*V

0.6*V

0.4*V

0.2*V

R

V

External Voltage Generator, Voltage Divider Dis- 1/2V

-

V

1/2V

V

LL6

LL5

LL4

LL3

LL2

CC

able, Regulator Enabled.

1/2V

0

CC

0

Output Current

Output High Current Source from Pins D0-D7, V =VDD-0.4V

I

50

-

µA

OH

out

Annun0-3, BP and OSC2.

I

Output Low Current Drain from Pins D0-D7, V =0.4V

-50

1

OL

OZ

out

Annun0-3, BP and OSC2.

Output Tri-state Current Drain Source at pins D0-

D7 and OSC2

I

-1

I /I

Input Current at pins RES, CS, D0-D7, R/W, D/C OSC1

and OSC2.

-1

-

1

µA

kΩ

V

IL IH

Ron

On Resistance

Channel Resistance between LCD Driving Signal During Display on, 0.1V Apply between Two Ter-

Pins (SEG and COM) and Driving Voltage Input minals, V within Operating Voltage Range.

10

3.5

7.5

CC

Pins (V

to V ).

LL6

LL2

V

Memory Retention Voltage (DV

)

DD

2

-

SB

Standby Mode, Retained All Internal Conﬁguration

and RAM Data

C

Input Capacitance

5

pF

IN

OSC1, OSC2 and All Logic Pins

ELECTRICAL CHARACTERISTICS (Voltage Referenced to V , DV =2.4-3.15V, T =25˚C)

SS

DD

A

Temperature Coefﬁcient Compensation

Flat Temperature Coefﬁcient

Temperature Coefﬁcient 1*

PTC0

PTC1

PTC2

PTC3

TC1=0, TC2=0, Voltage Regulator Disabled.

TC1=0, TC2=1, Voltage Regulator Enabled.

TC1=1, TC2=0, Voltage Regulator Enabled.

TC1=1, TC2=1, Voltage Regulator Enabled.

-

0.0

-

%

-0.18

-0.22

-0.35

Temperature Coefﬁcient 2*

Temperature Coefﬁcient 3*

* The formular for the temperature coefficient is:

1

VR at 50˚C - VR at 0˚C

50˚C - 0˚C

TC(%)=

X

X100%

VR at 25˚C

MOTOROLA

MC141535

3–77

ELECTRICAL CHARACTERISTICS (Voltage Referenced to V , AV =DV =2.4 to 3.15V, T =25˚C)

SS

DD

A

Total variation of VR ∆V is affected by ther following factors :

RT

Process varition of Regulator ∆V

R

External V Variation contributed to Regulator ∆V

DD

VDD

External resistor pair Ra/Rf contributed to Regulator ∆V

res

2

where∆V_RT

=

(∆V_R)²+ (∆V_V)²+ (∆V_res

)

DD

Assume external V varition is +/-6% at 3.15V and 1% varition resistor used at application.

DD

TC Level

∆V

(%)

∆V (%)

VDD

R

res

RT

TC0

TC1

TC2

TC3

±6.0

±4.0

±2.5

±1.4

±6.652

±4.924

±3.805

±3.195

Reference

Generator

±2.5

±1.414

AC ELECTRICAL CHARACTERISTICS (T =25˚C, Voltage referenced to V , V =2.4 to 3.15V)

A

SS

DD

Symbol

Parameter

Oscillation Frequency.

Test Condition

Min

Typ

Max

Unit

Normal Display Frequency Selected

F

Oscillation Frequency of Display Timing Generator

with 60Hz Frame Frequency.

Annunciator Display Frequency (with 50% duty

cycle) from Pins Annun0-3 and BP

-

38.4

18.75

60

-

kHz

Hz

OSC1

ANN1

FRM1

LCD Driving Signal Frame Freqency.

Graphic or Icon Display Mode.

Hz

Oscillation Frequency.

Slow Display Frequency Selected

F

Annunciator Display Frequency (with 50% duty

cycle) from Pins Annun0-3 and BP With Low Dis-

play Frequency Enabled

-

9.375

30

-

Hz

ANN2

FRM2

LCD driving Signal Frame Freqency. (Graphic or

Icon Display Mode With Low Display Frequency

Enabled.)

OSC

Internal Oscillation Frequency

Internal OSC Oscillation Frequency with Different

Value of Feedback Resistor. (Internal Oscillator

See Figure 1 for the relationship

Enabled. V within Operation Range.)

DD

280k

260k

90k

70k

Oscillation

Frequency

(Hz)

50k

30k

10k

100k

500k

1.0M

1.5M

2.0M

Resistor Value between OSC1 and OSC2 (Ω)

Figure 1. Internal Oscillator Frequency Relationship with External Resistor Value

MC141535

3–78

MOTOROLA

1 2 3 4

Normal Display Mode

COMx

VLL6

VLL5

VLL4

VLL3

VLL2

VLL1

VLL6

VLL5

VLL4

VLL3

VLL2

VLL1

SEGy

Icon Display Mode

COM16

V

LL6

LL4

1/F

FRM

1/F

ANN

BP, Annun0-3

Figure 2. LCD Driving Signal Timing Diagram

MOTOROLA

MC141535

3–79

TABLE 2a. Parallel Timing Characteristics (Write Cycle) (T =-10 to 60˚C, DV =2.4 to 3.15V, V =0V)

A

DD

SS

Symbol

Parameter

Min

1000

290

0

Typ

Max

Unit

ns

t

Enable Cycle Time

Enable Pulse Width

Address Setup Time

Data Setup Time

Data Hold Time

-

cycle

t

ns

EH

t

ns

AS

DS

DH

t

290

0

ns

t

ns

t

Address Hold Time

5

ns

AH

t

cycle

CS

t

EH

R/W

t

AH

AS

D/C

t

DS

DH

D0-D7

Valid Data

Figre 3.Timing Characteristics (Write Cycle)

MC141535

3–80

MOTOROLA

TABLE 2b. Parallel Timing Characteristics (Read Cycle) (T =-10 to 60˚C, DV =2.4 to 3.15V, V =0V)

A

DD

SS

Symbol

Parameter

Min

Typ

Max

Unit

ns

t

Enable Cycle Time

Enable Pulse Width

Address Setup Time

Data Setup Time

Data Hold Time

1000

-

cycle

t

375

0

-

ns

EH

t

-

ns

AS

DD

DH

t

-

350

ns

7

-

ns

t

Address Hold Time

5

ns

AH

t

cycle

CS

t

EH

R/W

t

AH

AS

D/C

t

DS

DH

D0-D7

Valid Data

Figure 4.Timing Charecteristics (Read Cycle)

MOTOROLA

MC141535

3–81

C+ and C-

PIN DESCRIPTIONS

If internal drivider circuit is enabled, a capacitor is required to con-

nect between these two pins.

D/C (Data / Command)

This input pin tell the LCD driver the input at D0-D7 is data or com-

mand. Input High for data while input Low for command.

VR and VF

This is a feedback path for the gain control (external contrast con-

trol) of VLL1 to VLL6. For adjusting the LCD driving voltage, it

requires a feedback resistor placed between VR and VF, a gain con-

trol resistor placed between VF and AVSS, a 10 µF capacitor placed

between VR and AVSS. (Refer to the Application Circuit)

CS (CLK) (Chip Select / Input Clock)

This pin is normal Low clock input. Data on D0-D7 is latched at the

falling edge of CS.

RES (Reset)

An active Low pulse to this pin reset the internal status of the

driver (same as power on reset). The minimum pulse width is 10 µs.

COM0-COM16 (Row Drivers)

These pins provide the row driving signal to LCD panel. Com0-

Com15 are used in 16 mux display. Com16 is used to drive the non-

static icons. Output is low during display off.

D0-D7 (Data)

This bi-directional bus is used for data / command transfering.

SEG0-SEG160 (Column Drivers)

These 161 pins provide LCD column driving signal to LCD panel.

They output 0V during display off.

R/W (Read / Write)

This is an input pin. To read the display data RAM or the internal

status (Busy / Idel), pull this pin High. The R/W input Low indicates a

write operation to the display data RAM or to the internal setup regis-

ters.

BP (Annunciator Backplane)

This pin combines with Annun0-Annun3 pins to form annunciator

driving part. When the annunciator circuit is enabled, it will output

OSC1 (Oscillator Input)

square wave of F

Hz. It outputs low when oscillator is disabled.

ANNn

For internal oscillator mode, this is an input for the internal low

power RC oscillator circuit. In this mode, an external resistor of cer-

tain value should be connected between the OSC1 and OSC2 pins

for a range of internal operating frequencies (refer to Figure 1). For

external oscillator mode, OSC1 should be left open.

Annun0 - Annun3 (Annunciator Frontplanes)

These pins are four independent annunciator driving outputs. The

enabled annunciator outputs from its corresponding pin a F

square wave which is 180 degrees out of phase with BP. Disabled

annunciator output from its corresponding pin an square wave in-

phase with BP. When all annunciators are disabled, all these pins

output 0V.

Hz

ANNn

OSC2 (Oscillator Output / External Osscillator Input)

For internal oscillator mode, this is an output for the internal low

power RC oscillator circuit. For external oscillator mode, OSC2 will

be an input pin for external clock and no external resistor is needed.

AVDD and AVSS

AVDD is the positive supply to LCD bias voltage generator. AVSS

is ground.

VLL6 - VLL2

Group of voltage level pins for driving the LCD panel. They can

either be connected to external driving circuit for external bias supply

or connected internally to built-in divider circuit if internal divider is

enable. For Internal DC/DC Converter enabled, a capacitor to AV

is required on each pin.

VCC

For using the Internal DC/DC Converter, a 0.1 µF capacitor from

this pin to AVSS is required. It can also be an external bias input pin

if Internal DC/DC Converter is not used. Power is supplied to the

LCD Driving Level Selector and HV Buffer Cell with this pin. Nor-

mally, this pin is not intended to be a power supply to other compo-

nent.

SS

C1N and C1P

If Internal DC/DC Converter is enabled, a capacitor is required to

connect these two pins.

DVDD and DVSS

Power is supplied to the digital control circuit of the driver using

these two pins. DVDD is power and DVSS is ground.

C2N and C2P

If Internal DC/DC Converter and Tripler are enabled, a capacitor is

required between these two pins. Otherwise, leave these pins open.

MC141535

3–82

MOTOROLA

OPERATION OF LIQUID CRYSTAL DISPLAY DRIVER

Description of Block Diagram Module

Command Decoder and Command Interface

MPU Parallel Interface

This module determines whether the input data is interpreted as data

or command. Data is directed to this module based upon the input of

the D/C pin. If D/C high, data is written to Graphic Display Data RAM

(GDDRAM). D/C low indicates that the input at D0-D7 is interpreted as

a Command.

Reset is of same function as Power ON Reset (POR). Once RES

received the reset pulse, all internal circuitry will back to its initial status.

Refer to Command Description section for more information.

The parallel interface consists of 8 bi-directional data lines (D0-D7),

R/W, and the CS. The R/W input High indicates a read operation from

the Graphic Display Data RAM (GDDRAM). R/W input Low indicates a

write operation to Display Data RAM or Internal Command Registers

depending on the status of D/C input. The CS input serves as data

latch signal (clock). Refer to AC operation conditions and characteris-

tics section for Parallel Interface Timing Description.

Graphic Display Data RAM (GDDRAM)

The GDDRAM is a bit mapped static RAM holding the bit pattern to

be displayed. The size of the RAM is determined by number of row

times the number of column (161x17 = 2737 bits). Figure 5 is a

description of the GDDRAM address map. For mechanical flexibility, re-

mapping on both Segment and Common outputs are provided.

Column address 00H

Column address A0H

(or column address A0H)

(or column address 00H)

Com0

(Com15)

Row 0

LSB

Page 1

MSB

LSB

Page 2

MSB

Com15

(Com0)

Row 15

Row 16 LSB

Page 3

Com16

Note : The configuration in parentheses represent the remapping of Commons and Columns

Figure 5. Graphic Display Data RAM (GDDRAM) Address Map

MOTOROLA

MC141535

3–83

Display Timing Generator

Annunciator Control Circuit

This module is an on chip low power RC oscillator circuitry (Figure 6).

The oscillator frequency can be selected in the range of 15kHz to

50kHz by external resistor. One can enable the circuitry by software

command. For external clock provided, feed the clock to OSC2 and

leave OSC1 open.

The LCD waveform of the 4 annunciators and BP are generated by

this module. The 4 independent annunciators are enabled by software

command. Annunciator is also controlled by oscillator circuit. Before

turning the annunciators on, the oscillator must be on in advance.

Annunciator output waveform shown in Figure 7.

Oscillator enable

Internal Oscillator selected

enable1 enable2

Oscillation Circuit

enable

Buffer

MC141535

External component

OSC2

OSC1

Feedback for internal oscillator

For external CLK input

Figure 6. Oscillator Circuitry

DV

DD

BP

ANNUN1

ANNUN2

DV

SS

DD

DV

SS

DD

DV

SS

ANNUN1

ANNUN2

OFF

ON

OFF

Figure 7. Annunciators and BP Display Waveform

17 Bit Latch / 161 Bit Latch

LCD Driving Voltage Generator

This module generates the LCD voltage needed for display output. It

takes a single supply input and generate necessary bias voltages. It

consists of :

1. Voltage Doubler and Voltage Tripler

To generate the Vcc voltage. Either Doubler or Tripler can be

enabled.

A 178 bit long register which carrys the display signal information.

First 32 bits are Common driving signals and other 161 bits are Seg-

ment driving signals. Data will be input to the HV-buffer Cell for bump-

ing up to the required level.

Level Selector

2. Voltage Regulator

Feedback gain control for initial LCD voltage. it can also be used with

external contrast control.

Level Selector is a control of the display synchronization. Display

voltage can be separated into two sets and used with different cycles.

Synchronization is important since it selects the required LCD voltage

level to the HV Buffer Cell for output signal voltage pump.

3. Voltage Divider

Divide the LCD display voltage (V -V ) from the regulator output.

LL2 LL6

This is a low power consumption circuit which can save the most dis-

play current compare with traditional resistor ladder method.

All blocks can be individually turned off if external voltage generator

is employed.

HV Buffer Cell (Level Shifter)

HV Buffer Cell works as a level shift-er which translates the low volt-

age output signal to the required driving voltage. The output is shifted

out with an internal FRM clock which comes from the Display Timing

Generator. The voltage levels are given by the level selector which is

synchronized with the internal M signal.

Voltage Regulator

1. Self adjust temperature compensation circuitry

Provide 4 different compensation grade selections to satisfy the vari-

ous liquid crystal temperature grades. The grading can be selected

by software control.

2. Contrast Control Block

Software control of 16 voltage levels of LCD voltage.

Horizontal Shifter

This Horizontal Shifter shift the 16 rows of GDDRAM data horizon-

tally according to the value in the Horizontal Scroll register (which is

programmable through sending two commands consecutively). Such

Horizontal Shifter’s output will go to the 161 Bit Latch for display.

MC141535

3–84

MOTOROLA

LCD Panel Driving Waveform

The following is an example of how the Common and Segment driv-

ers may be connected to a LCD panel. The waveforms shown in Figure

8a, 8b and 8c illustrate the desired multiplex scheme.

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

Figure 8a. LCD Display Example “0”

MOTOROLA

MC141535

3–85

TIME SLOT

1 2 3 4

VLL6

VLL5

VLL4

VLL3

VLL2

VLL1

COM0

COM1

SEG0

SEG1

VLL6

VLL5

VLL4

VLL3

VLL2

VLL1

VLL6

VLL5

VLL4

VLL3

VLL2

VLL1

VLL6

VLL5

VLL4

VLL3

VLL2

VLL1

Figure 8b. LCD Driving Signal from MC141535

TIME SLOT

1 2 3 4

VLL6

VLL5

VLL4

VLL3

VLL2

VLL1

-VLL2

-VLL3

-VLL4

-VLL5

-VLL6

Seg0-Com0

“OFF” Pixel

VLL6

VLL5

VLL4

VLL3

VLL2

VLL1

-VLL2

-VLL3

-VLL4

-VLL5

-VLL6

Seg0-Com1

“ON” Pixel

Figure 8c. Effective LCD waveform on LCD pixel

MC141535

3–86

MOTOROLA

Command Description

Set Display On/Off (Display Mode / Stand-by Mode)

annunciators are displayed.

This Displat On command turns the LCD Common and Segment out-

puts on and has no effect to the annunciator output. This command

starts the conversion of data in GDDRAM to necessary waveforms on

the Common and Segment driving outputs. The on-chip bias generator

is also turned on by this command. (Note : "Oscillator On" command

should be sent before "Display On" is selected)

Set Vertical Scroll Value

This command maps the selected GDDRAM row (00H-0FH) to

Com0. With scroll value equals to 0, Row 0 of GDDRAM is mapped to

Com0 and Row 1 through Row 15 are mapped to Com1 through

Com15 respectively. With scroll value equal to 1, Row 1 of GDDRAM is

mapped to Com0, then Row 2 through Row 15 will be mapped to Com1

through Com14 respectively and Row 0 will be mapped to Com15.

The Display Off command turns the display off and the states of the

LCD driver are as follow during display off :

1. The Common and Segment outputs are fixed at V

2. The bias Voltage Generator is turned off.

3. The RAM and content of all registers are retained.

4. IC will accept new commands and data.

The status of the Annunciators and Oscillator are not affected by this

command. The Oscillator is not affected by this command either.

(V ).

Save / Restore Column Address

LL1

SS

With bit option = 1 in this command, the Save / Restore Column

Address command saves a copy of the Column Address of GDDRAM.

With a bit option = 0, this command restores the copy obtained from the

previous execution of saving column address. This instruction is very

useful for writing full graphics characters that are larger than 8 pixels

vertically.

Set Horizontal Scroll

This command is used in combination with “Set Horizontal Scroll

Value” to set the LCD driver to scroll the display horizontally. The next

input from D0 to D7 is the scroll value. Note that Row16 is not affected

by this command.

Set Column Mapping

This instruction selects the mapping of GDDRAM to Segment drivers

for mechanical flexibility. There are 2 mappings to select:

1. Column 0 - Column 160 of GDDRAM mapped to Seg0-Seg160

respectively;

Set Horizontal Scroll Value

2. Column 0 - Column 160 of GDDRAM mapped to Seg160-Seg0

respectively.

Detail information please refer to section “Display Output Descrip-

tion”.

When display is turned on, this command maps the selected

GDDRAM column (00H-A0H) to Seg0-Seg160. With scroll value equals

to 0, Col 0 of GDDRAM is mapped to Seg0 and Col 1 through Col 160

are mapped to Seg 1 through Seg160 respectively. With Scroll value

equals to 1, Col 1 of GDDRAM is mapped to Seg 0, then Col 2 through

Col 160 will be mapped to Seg 1 through Seg 159 respectively and Col

0 will be mapped to Seg 160. This command must issue follow com-

mand "Set Horizontal Scroll".

Set Row Mapping

This instruction selects the mapping of GDDRAM to Common Drivers

for mechanical flexibility. There are 2 selected mappings:

1. Row 0 - Row 15 of GDDRAM to Com0 - Com15 respectively;

2. Row 0 - Row 15 of GDDRAM to Com15 - Com0 respectively.

Output of Row 16 (Com16) will not be changed by this command.

See section “Display Output Description” for related information.

Set GDDRAM Column Address

This command positions the address pointer on a column location.

The address can be set to location 00H-A0H (161 columns) in combina-

tion with the command “Set MSB of GDDRAM Column Address“. The

column address will be increased automatically after a read or write

operation. Refer “Address Incement Table” and command “Set

GDDRAM Page Address” for further information.

Set Annunciator Control Signals

This command is used to control the active states of the 4 stand

alone annunciator drivers.

Set Oscillator Enable / Disable

Set MSB of GDDRAM Column Address

This command is used to either turn on or off the oscillator. For using

internal or external oscillator, this command should be executed. The

setting for this command is not affected by command “Set Display On/

Off” and “Set Annunciator Control Signals”. See command “Set Exter-

nal / Internal Oscillator” for more information

This command set the MSB of the GDDRAM Column address

pointer. Set this MSB to 0 for accessing the 00H-7FH address; while set

this MSB to 1 for accessing 80H-A0H address

Set GDDRAM Page Address

This command positions the row address to 1 of 3 possible positions

in GDDRAM. Refer to figure 5.

Set External / Internal Oscillator

This command is used to select either internal or external oscillator.

When Internal Oscillator is selected, feedback resistor between OSC1

and OSC2 is needed. For external oscillation circuit, feed clock input

signal to OSC2 and leave OSC1 open.

Master Clear GDDRAM

This command is to clear the content of page 1 and 2 of the Display

Data RAM. Issue this command followed by a dummy write command.

Set Internal DC/DC Converter On/Off

Master Clear Icons

Use this command selects the Internal DC/DC Converter to generate

This command is used to clear the data in page 3 of GDDRAM which

storing the icon line data. Before using this command, set the page

address to page 3 by the command “Set GDDRAM Page Address”. A

dummy write data operation is also needed after this “Master Clear

Icons” command to make the clear icon action effective.

the V

Vcc is provided.

from AV . Turn off the Internal DC/DC Converter if external

CC DD

Set Voltage Doubler / Tripler

Use this command to select Doubler or Tripler when the Internal DC/

DC Converter is on.

Set Display Mode

This command switch the driver to full display mode or icon display

mode. In low power icon mode, only icons (driven by COM16) and

Set Internal Regulator On/Off

Choose bit option 0 to disable the Internal Regulator. Choose bit

MOTOROLA

MC141535

3–87

option 1 to enables the Internal Regulator which consists of the internal

contrast control and temperature compensation circuits.

contrast control circuitry is in use. After power-on reset, the contrast

level is the lowest.

Set Internal Voltage Divider On/Off

Read Contrast Value

If the Internal Voltge Divider is disabled, external bias can be used

This command allows the user to read the current contrast level

value. With R/W input high (READ), D/C input low (COMMAND) and D7

D6 D5 D4 are equal to 0 0 0 1, the value of the internal contrast value

can be read on D0-D3 at the falling edge of CS.

for V

to V

If the Interna Voltagel Divider is enabled, the internal

LL6

LL2.

circuit will generated the 1:5 bias driving voltage.

Set Internal Contrast Control On/Off

This command is used to turn on or off the internal control of delta

voltage of the bias voltages. With bit option = 1, the software selection

for delta bias voltage control is enabled. With bit option = 0, internal

contrast control is disabled.

Set Temperature Coefficient

A temperature gradient selector circuit controlled by two control bits

TC1 and TC2. This command can select 4 different LCD driving voltage

temperature coefficients to match various liquid crystal temperature

grades. Those temperature coefficients are specified in Electrical Char-

acteristics Tables.

Increase / Decrease Contrast Level

If the internal contrast control is enabled, this command is used to

increase or decrease the contrast level within the 16 contrast levels.

The constrast level starts from the lowest value after POR.

Set Display Frequency

This commnad set the LCD panel display to normal frequency or

slow frequency.

Set Contrast Level

This command is to select one of the 16 contrast levels when internal

COMMAND TABLE

Bit Pattern

000000X X

Command

Comment

Set GDDRAM Page Address using X X as address bits.

Set GDDRAM Page Address

1

0

1 0

X X =00 : page 1 (POR)

1

0

X X =01 : page 2

1

0

X X =10 : page 3

1

0

0001X X X X

2 1 0

Set / Read Contrast Level

With R/W pin input low, set one of the 16 available values to the

internal contrast register, using X X X X as data bits. The con-

3

2 1 0

trast register is reset to 0000 during POR.

With R/W pin input high, and at the rising edge of CS, the value of

the internal contrast register will be latched out at D3 D2 D1 D0

pins, i.e. X X X X , at the rising edge of CS.

3

2 1 0

0010000X

0010001X

0010010X

0010011X

0010100X

0010101X

0010110X

Set Voltage Doubler / Tripler

Set Column Mapping

Set Row Mapping

X =0: Tripler enable (POR)

0

X =1: Doubler enable

0

X =0 : Col0 to Seg0 (POR)

0

X =1 : Col0 to Seg119

0

X =0 : Row0 to Com0

0

X =1: Row0 to Com15

0

Set MSB of GDDRAM Column

Address

X =0 : MSB = 0 (POR)

0

X =1 : MSB = 1

0

Set Display On/Off

X =0: display off (POR)

0

X =1: display on

0

Set Internal DC/DC Converter On/Off

Set Internal Regulator Enable

X =0: Internal DC/DC Converter off(POR)

0

X =1: Internal DC/DC Converter on

0

X =0: Internal Regulator off (POR)

0

X =1: Internal Regulator on

0

When application uses a supply with built-in temperature compen-

sation, the regulator should be disabled .

0010111X

0011000X

Set Internal Voltage Divider On/Off

Set Internal Contrast Control On/Off

X =0: Internal Voltage Divider off(POR)

0

X =1: Internal Voltage Divider on

0

When an external bias network is preferred, the voltage divider

should be disabled.

X =0: Internal Constrast Control off(POR)

0

X =1: Internal Constrast Control on

0

Internal contrast circuits can be disabled if external contrast cir-

cuits is preferred.

MC141535

3–88

MOTOROLA

COMMAND TABLE

Bit Pattern

Command

Comment

X =0 : normal display mode (POR)

0011001X

0011010X

00110110

00110111

0011100X

0011101X

Set Display Mode

0

X =1 : icon display mode

0

Save/Restore GDDRAM Column

Address

X =0 : restore address

0

X =1 : save address

0

Master Clear GDDRAM

Master Clear Icons

Set Display Frequency

Reserved.

Master clear page 1 and 2 of GDDRAM, dummy write is required

after this command.

Master Clear of GDDRAM page 3.

GDDRAM page 3 should be selected and dummy write is required

X =0: normal display frequency

0

X =1: slow display mode

0

X =0: normal operation (POR)

0

X =1: test mode

0

(Note: Make sure to set X =0 during application)

0

0100X X X X

Set Vertical Scroll Value

Use X X X X as number of lines to scroll.

3 2 1 0

3

2

1

0

Scroll value = 0 upon POR

01100A A X

Set Annunciator Control Signals

A A =00: select annunciator 1 (POR)

1

0

1 0

A A =01: select annunciator 2

1

0

A A =10: select annunciator 3

1

0

A A =11: select annunciator 4

1

0

X =0: turn selected annunciator off (POR)

0

X =1: turn selected annunciator on

0

01101000

Set Horizontal Scrolling

Set horizontal scrolling mode. The next input from D0~D7 will be

interpreted as the horizontal shift value.

011011X X

Set Temperature Coefﬁcient

X X =00: 0.00% (POR)

1 0

1

0

X X =01: -0.18%

1

0

X X =10: -0.22%

1

0

X X =11: -0.35%

1

0

0111000X

Increase / Decrease Contrast Value

X =0: Decrease by one level

0

X =1: Increase by one level

0

(Note: increment/decrement wraps round among the 16 contrast

levels. Start at the lowest level when POR.

0111001X

0111010X

0111011X

Reserved

0

X =0: normal operation (POR)

0

X =1: test mode select

0

(Note: Make sure to set X =0 during application)

0

0111100X

0111101X

Reserved

0

Set External / Internal Oscillator

X =0: External oscillator (POR)

0

X =1: Internal oscillator.

0

For internal oscillator place a resistor between OSC1 and OSC2.

For external oscillator mode, feed clock input to OSC2.

0111110X

0111111X

Reserved

0

Set Oscillator Enable / Disable

X =0: oscillator master disable (POR)

0

X =1: oscillator master enable.

0

This is the master control fro oscillator circuitry. This command

should be issued after the “External / Internal Oscillator” com-

mand.

1X X X X X X X

5 4 3 2 1 0

Set GDDRAM Column Address

Set Horizontal Scroll Value

Set GDDRAM Column Address.

6

Use X X X X X X X as address bits.

6

5 4 3 2 1 0

X X X X X X X X

6 5 4 3 2 1 0

To set the amount of Horizontal scroll

7

MOTOROLA

MC141535

3–89

Data Read / Write

To read data from the GDDRAM, input High to R/W pin and D/C pin. Data is valid at the falling edge of CS. And the GDDRAM column

address pointer will be increasd by one automatically.

To write data to the GDDRAM, input Low to R/W pin and High to D/C pin. Data is latched at the falling edge of CS. And the GDDRAM column

address pointer will be increasd by one automatically.

No auto address pointer increment will be performed for the Dummy Write Data after Master Clear GDDRAM. (Refer to the “Commands

Required for R/W Actions on RAM” Table)

Address Increment Table (Automatic)

D/C

0

R/W

Comment

Address Increment

Remarks

0

1

0

1

Write Command

Read Command

Write Data

No

0

No

*1

*2

1

Yes

1

Read Data

*3

Address Increment is done automatically data read write. The column address pointer of GDDRAM is affected.

Remarks : *1. Refer to the command “Read Contrast Vaule”.

*2. If write data is issued after Command Clear RAM, Address increse is not applied.

*3. Column Address will be wrapped round when overflow.

Commmands Required for Display Mode Setup

Display Mode

Commands Required

Normal Display Mode

Set External / Internal Oscillator

Set Oscillator Enable,

(0111101X )*

(01111111)*

0

Set Display Mode (Normal Display)

Set Display On.

(00110010)*

(00101001)*

Icon Display Mode

Annunciator Display

Set External / Internal Oscillator

Set Oscillator Enable,

Set Display Mode (Icon Display)

Set Display On.

(0111101X )*

0

(01111111)*

(00110011)*

(00101001)*

Set External / Internal Oscillator

Set Oscillator Enable,

(0111101X )*

0

(01111111)*

Set Annunciator On/Off.

(01100A A X )*

1 0 0

Standby Mode 1.

Standby Mode 2.

Set Display Off,

Set Oscillator Disable.

(00101000)*

(01111110)*

Set External Oscillator

Set Display Off,

Set Oscillator Enable.

Set Annunciator On / Off,

(01111011)*

(00101000)*

(01111111)*

(01100A A X )*

1

0 0

Standby Mode 3.

Set Internal Oscillator

Set Display Off,

Set Oscillator Enable.

Set Annunciator On / Off,

(01111010)*

(00101000)*

(01111111)*

(01100A A X )*

1

0 0

Other Related Command with Display Mode : Set Segment Mapping, Set Common Mapping, Set Vertical Scroll Value.

Commands Related to Voltage Generator :

Set Oscillator Enable / Disable, Set Internal Regulator On/Off, Set Temperature Coefficient, Set Internal Constrast Control On/Off, Increase /

Decrease Contrast Level, Set Internal Voltage Divider On/Off, Set Display On/Off, Set Reference Voltage Generator, Set Contrast Level, Set

Voltage Doubler / Tripler

MC141535

3–90

MOTOROLA

Commands Required for R/W Actions on RAM

R/W Actions on RAMs

Commands Required

Read/Write Data from/to GDDRAM.

Set GDDRAM Page Address

Set MSB of GDDRAM Column Address

Set GDDRAM Column Address

Read/Write Data

(000000X X )*

1 0

(0010011X )*

0

(1X X X X X X X )*

6

5 4 3 2 1 0

(X X X X X X X X )

7

6 5 4 3 2 1 0

Save/Restore GDDRAM Column Address.

Increase GDDRAM Address.

Save/Restore GDDRAM Column Address.

(0011010X )

0

Dummy Read Data

(X X X X X X X X )

7 6 5 4 3 2 1 0

Set GDDRAM Column Address

(1X X X X X X X )

6 5 4 3 2 1 0

Master Clear GDDRAM

Master Clear Icons

Master Clear GDDRAM

Dummy Write Data

(00110110)

(X X X X X X X X )

7

6 5 4 3 2 1 0

Set Clear Page 3 of GDDRAM

Master Clear Icons

(00000010)*

(00110111)

Dummy Write Data

(X X X X X X X X )

7 6 5 4 3 2 1 0

Horizontal Scrolling with Writing GDDRAM

Set GDDRAM Page 1

(00000000)*

(0010011X )*

Set MSB of GDDRAM Column Address

Set GDDRAM Column Address

Write Data

0

(1X X X X X X X )*

6

5 4 3 2 1 0

(X X X X X X X X )

7

6 5 4 3 2 1 0

Set GDDRAM Page 1

(00000001)*

(0010011X )*

Set MSB of GDDRAM Column Address

Set GDDRAM Column Address

Write Data

0

(1X X X X X X X )*

6

5 4 3 2 1 0

(X X X X X X X X )

7

6 5 4 3 2 1 0

Set Horizontal Scroll

Set Scroll Value

(01101000)

(00000001)

* No need to resend the command again if it is set previously.

The read / write action to the Display Data RAM does not depend on the display mode. This means the user can change the RAM content

whether the target RAM content is being displayed.

MOTOROLA

MC141535

3–91

Display Output Description by Working Example

COM0

This is an example of output pattern on the LCD panel. The follow-

ing table is a description of what is inside the CDDRAM, CGRAM and

GDDRAM. Figure 9b and 9c are the output pattern on the LCD display

with different command enabled.

(Display Mode, Page Swapping, Scrolling, Column Re-map and Row

Re-map)

COM16

SEG0

SEG160

Figure 9a

Content of GDDRAM

PAGE 1

PAGE 2

PAGE 3

5

A

5

A

5

A

5

A

-

0

3

C

3

C

-

3

C

3

C

0

1

0

1

0

1

0

-

0

1

0

1

0

1

0

Figure 9b

Column remap disable

Row re-map disable

Column remap enable

Row re-map disable

Column remap disable

Row re-map enable

Column remap disable

Row re-map disable

Scroll Value = 0Fh

Column remap disable

Row re-map disable

Horizontal scroll = 1

Column remap disable

Row re-map disable

Horizontal scroll = 160

Column remap enable

Row re-map disable

Horizontal scroll = 1

Column remap enable

Row re-map disable

Horizontal scroll = 160

Figure 9c. Examples of LCD display with different command enabled

MC141535

3–92

MOTOROLA

MC141535T TAB PACKAGE DIMENSION (1 OF 2)

98ASL00248A ISSUE A

DO NOT SCALE THIS DRAWING

COPPER SIDE

MOTOROLA

MC141535

3–93

MC141535T TAB PACKAGE DIMENSION (2 OF 2)

98ASL00248A ISSUE A

DO NOT SCALE THIS DRAWING

MC141535

3–94

MOTOROLA

Application Circuit

16/17 MUX Dispaly with Analog Circuitry enabled,Tripler enabled and 1:5 bias

DV

AV

DD

0.1µF

0.1µF 0.1µF

0.1µF 0.1µF 0.1µF 0.1µF

DVSS DVDD

AVDD AVSS

VLL2 VLL3

VLL4 VLL5 VLL6 VCC

COM0 to

COM16

RES

D/C

CS

SEG0 to

SEG160

To LCD

Panel

CMOS

MC141535

MPU/

MCU with

Parallel

Interface

Annun 0-3

and BP

R/W

D0~D7

OSC2 OSC1 C+

C- VF

VR C2P C2N C1P C1N

760kΩ

EPROM

RAM

1MΩ

0.1µF

200kΩ

0.1µF

4.7µF

0.1µF

560pF

Remark :

1. VR and VF can be left open Regulator Disable.

2. CS pin low at Standby Mode.

MOTOROLA

MC141535

3–95

Application Circuit

16/17 MUX Display with Analog Circuit disabled, External Bias

DV

AV

DD

V

CC

0.1µF

DVSS DVDD

AVDD DVSS

VLL2 VLL3

VLL4 VLL5 VLL6 VCC

COM0 to

COM16

RES

D/C

CS

SEG0 to

SEG160

To LCD

Panel

CMOS

MC141535

MPU/

MCU with

Parallel

Interface

Annun 0-3

and BP

R/W

D0~D7

OSC1 C+

C-

VF

VR

C2P C2N

C1N

OSC2

C1P

EPROM

RAM

External Clock

Remark :

1. VR and VF can be left open Regulator Disable.

2. CS pin low at Standby Mode.

MC141535

3–96

MOTOROLA

MC141535 Die Pad Co-ordinate

1

Name

N/C

x (um)

y (um)

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

Name

OSC2

AVDD

N/C

BP

x (um)

y (um)

Name

x (um)

y (um)

Name

x (um)

y (um)

-5151.88 -1390.83

-5050.13 -1390.83

-4948.38 -1390.83

-4846.63 -1390.83

-4744.88 -1390.83

-4643.13 -1390.83

-4541.38 -1390.83

2038.33 -1288.71 141 SEG28 3931.25

2140.08 -1288.71 142 SEG29 3855.03

2269.58 -1390.83 143 SEG30 3778.81

2371.33 -1390.83 144 SEG31 3702.59

2473.08 -1390.83 145 SEG32 3626.37

2574.83 -1390.83 146 SEG33 3550.15

2676.58 -1390.83 147 SEG34 3473.93

2778.33 -1390.83 148 SEG35 3397.71

2880.08 -1390.83 149 SEG36 3321.49

2981.83 -1390.83 150 SEG37 3245.27

3083.58 -1390.83 151 SEG38 3169.05

3185.33 -1390.83 152 SEG39 3092.83

3287.08 -1390.83 153 SEG40 3016.61

3388.83 -1390.83 154 SEG41 2940.39

3490.58 -1390.83 155 SEG42 2864.17

3592.33 -1390.83 156 SEG43 2787.95

3694.08 -1390.83 157 SEG44 2711.73

3795.83 -1390.83 158 SEG45 2635.51

3897.58 -1390.83 159 SEG46 2559.29

3999.33 -1390.83 160 SEG47 2483.07

4101.08 -1390.83 161 SEG48 2406.85

4202.83 -1390.83 162 SEG49 2330.63

4304.58 -1390.83 163 SEG50 2254.41

4406.33 -1390.83 164 SEG51 2178.19

4508.08 -1390.83 165 SEG52 2101.97

4609.83 -1390.83 166 SEG53 2025.75

4711.58 -1390.83 167 SEG54 1949.53

4813.33 -1390.83 168 SEG55 1873.31

4915.08 -1390.83 169 SEG56 1797.09

5016.83 -1390.83 170 SEG57 1720.87

5163.35 -1160.69 171 SEG58 1644.65

5163.35 -1084.47 172 SEG59 1568.43

5163.35 -1008.25 173 SEG60 1492.21

1275.76

211 SEG98 -1404.15 1275.76

212 SEG99 -1480.37 1275.76

213 SEG100 -1556.59 1275.76

214 SEG101 -1632.81 1275.76

215 SEG102 -1709.03 1275.76

216 SEG103 -1785.25 1275.76

217 SEG104 -1861.47 1275.76

218 SEG105 -1937.69 1275.76

219 SEG106 -2013.91 1275.76

220 SEG107 -2090.13 1275.76

221 SEG108 -2166.35 1275.76

222 SEG109 -2242.57 1275.76

223 SEG110 -2318.79 1275.76

224 SEG111 -2395.01 1275.76

225 SEG112 -2471.23 1275.76

226 SEG113 -2547.45 1275.76

227 SEG114 -2623.67 1275.76

228 SEG115 -2699.89 1275.76

229 SEG116 -2776.11 1275.76

230 SEG117 -2852.33 1275.76

231 SEG118 -2928.55 1275.76

232 SEG119 -3004.77 1275.76

233 SEG120 -3080.99 1275.76

234 SEG121 -3157.21 1275.76

235 SEG122 -3233.43 1275.76

236 SEG123 -3309.65 1275.76

237 SEG124 -3385.87 1275.76

238 SEG125 -3462.09 1275.76

239 SEG126 -3538.31 1275.76

240 SEG127 -3614.53 1275.76

241 SEG128 -3690.75 1275.76

242 SEG129 -3766.97 1275.76

243 SEG130 -3843.19 1275.76

244 SEG131 -3919.41 1275.76

245 SEG132 -3995.63 1275.76

246 SEG133 -4071.85 1275.76

247 SEG134 -4148.07 1275.76

248 SEG135 -4224.29 1275.76

249 SEG136 -4300.51 1275.76

250 SEG137 -4376.73 1275.76

251 SEG138 -4452.95 1275.76

252 SEG139 -4529.17 1275.76

253 SEG140 -4605.39 1275.76

254 SEG141 -5163.35 1242.09

255 SEG142 -5163.35 1165.87

256 SEG143 -5163.35 1089.65

257 SEG144 -5163.35 1013.43

2

3

4

5

6

7

8

DVDD -4264.62 -1307.21

9

RES

D/C

R/W

CS

DVSS

D0

D1

D2

D3

D4

-4183.22 -1307.21

-4101.82 -1307.21

-4020.42 -1307.21

-3939.02 -1307.21

-3857.62 -1307.21

-3776.22 -1307.21

-3694.82 -1307.21

-3613.42 -1307.21

-3532.02 -1307.21

-3450.62 -1307.21

-3369.22 -1307.21

-3287.82 -1307.21

-3206.42 -1307.21

-3054.72 -1390.83

-2952.97 -1390.83

-2851.22 -1390.83

-2749.47 -1390.83

-2647.72 -1390.83

-2545.97 -1390.83

-2444.22 -1390.83

-2342.47 -1390.83

-2240.72 -1390.83 100

-2138.97 -1390.83 101

-2037.22 -1390.83 102

-1935.47 -1390.83 103

-1833.72 -1390.83 104 COM16 5163.35

-1731.97 -1390.83 105 COM15 5163.35

-1630.22 -1390.83 106 COM14 5163.35

-1528.47 -1390.83 107 COM13 5163.35

-1426.72 -1390.83 108 COM12 5163.35

-1324.97 -1390.83 109 COM11 5163.35

-1223.22 -1390.83 110 COM10 5163.35

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

D5

D6

D7

N/C

AVSS

VF

ANN2

ANN3

-932.03

-855.81

-779.59

-703.37

-627.15

-550.93

-474.71

-398.49

-322.27

-206.09

-129.87

-53.65

174 SEG61 1415.99

175 SEG62 1339.77

176 SEG63 1263.55

177 SEG64 1187.33

178 SEG65 1111.11

179 SEG66 1034.89

180 SEG67

181 SEG68

182 SEG69

183 SEG70

184 SEG71

185 SEG72

186 SEG73

187 SEG74

188 SEG75

189 SEG76

190 SEG77

191 SEG78

192 SEG79

193 SEG80

194 SEG81

195 SEG82

196 SEG83

197 SEG84

198 SEG85

199 SEG86

200 SEG87

201 SEG88

202 SEG89

203 SEG90

204 SEG91

205 SEG92

958.67

882.45

806.23

730.01

653.79

577.57

501.35

425.13

348.91

272.69

196.47

120.25

44.03

-1121.47 -1390.83 111

-1019.72 -1390.83 112

-917.97 -1390.83 113

-816.22 -1390.83 114

-714.47 -1390.83 115

-612.72 -1390.83 116

-510.97 -1390.83 117

-409.22 -1390.83 118

-307.47 -1390.83 119

-205.72 -1390.83 120

COM9

COM8

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

5163.35

22.57

98.79

175.01

251.23

327.45

403.67

479.89

556.11

632.33

708.55

784.77

860.99

937.21

1013.43

1089.65

1165.87

1242.09

1275.76

258 SEG145 -5163.35

259 SEG146 -5163.35

260 SEG147 -5163.35

261 SEG148 -5163.35

262 SEG149 -5163.35

263 SEG150 -5163.35

264 SEG151 -5163.35

265 SEG152 -5163.35

266 SEG153 -5163.35

267 SEG154 -5163.35

268 SEG155 -5163.35

269 SEG156 -5163.35

270 SEG157 -5163.35

271 SEG158 -5163.35

937.21

860.99

784.77

708.55

632.33

556.11

479.89

403.67

327.45

251.23

175.01

98.79

-57.72

44.03

-1288.71 121

-1288.71 122

AVSS

C2P

C2N

C1P

C1N

C+

145.78

247.53

349.28

451.03

552.78

654.53

756.28

858.03

959.78

-1288.71 123 SEG10 5163.35

-1288.71 124 SEG11 5163.35

-1288.71 125 SEG12 5163.35

-1288.71 126 SEG13 5163.35

-1288.71 127 SEG14 5163.35

-1288.71 128 SEG15 5163.35

-1288.71 129 SEG16 5163.35

-1288.71 130 SEG17 5163.35

-1288.71 131 SEG18 5163.35

-32.19

-108.41

-184.63

-260.85

-337.07

-413.29

-489.51

-565.73

-641.95

-718.17

-794.39

-870.61

-946.83

22.57

-53.65

C-

VR

1122.58 -1288.71 132 SEG19 5163.35

1224.33 -1288.71 133 SEG20 4541.01

1326.08 -1288.71 134 SEG21 4464.79

1427.83 -1288.71 135 SEG22 4388.57

1529.58 -1288.71 136 SEG23 4312.35

1631.33 -1288.71 137 SEG24 4236.13

1733.08 -1288.71 138 SEG25 4159.91

1834.83 -1288.71 139 SEG26 4083.69

1936.58 -1288.71 140 SEG27 4007.47

272 SEG159 -5163.35 -129.87

273 SEG160 -5163.35 -206.09

274 COM16 -5163.35 -322.27

VLL2

VLL3

VLL4

VLL5

VLL6

OSC1

VCC

OSC2

275

276

277

278

279

280

281

282

283

284

285

COM0 -5163.35 -398.49

COM1 -5163.35 -474.71

COM2 -5163.35 -550.93

COM3 -5163.35 -627.15

COM4 -5163.35 -703.37

COM5 -5163.35 -779.59

COM6 -5163.35 -855.81

COM7 -5163.35 -932.03

206 SEG93 -1023.05 1275.76

207 SEG94 -1099.27 1275.76

208 SEG95 -1175.49 1275.76

209 SEG96 -1251.71 1275.76

210 SEG97 -1327.93 1275.76

Die Size : 431.5 mil x 129.53 mil

Pad No. Pad Size Unit Pad No. Pad Size

1-7

8-21

Unit

µm

62x62

50x107

62x62

µm 101-132 107x50

µm 133-253 50x107

µm 254-285 107x50

ANN1

ANN0

BP

-5163.35 -1008.25

-5163.35 -1084.47

-5163.35 -1160.69

Note : Do not connect the NC pin to external circuit

21-100

MOTOROLA

MC141535

3–97


型号：	MC141535T
厂家：	MOTOROLA
描述：	Liquid Crystal Driver, 178-Segment, CMOS, TAB-216
文件：	总26页 (文件大小：438K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC141535T [MOTOROLA]

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