MC141541P_技术文档

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SEMICONDUCTOR TECHNICAL DATA

P SUFFIX

PLASTIC DIP

CASE 648

CMOS

The MC141541 is a high performance HCMOS device designed to interface

with a microcontroller unit to allow colored symbols or characters to be

displayed on a color monitor. The on–chip PLL allows both multi–system

operation and self–generation of system timing. It also minimizes the MCU’s

burden through its built–in 273 bytes display/control RAM. By storing a full

screen of data and control information, this device has the capability to carry out

‘screen–refresh’ without MCU supervision.

Since there is no spacing between characters, special graphics–oriented

characters can be generated by combining two or more character blocks. There

are two different resolutions that users can choose. By changing the number of

dots per horizontal line to 320 (CGA) or 480 (EGA), smaller characters with

higher resolution can be easily achieved.

Special functions such as character bordering or shadowing, multi–level

windows, double height and double width, and programmable vertical length of

character can also be incorporated. Furthermore, neither massive information

update nor extremely high data transmission rate are expected for normal on–

screen display operation, and serial protocols are implemented in lieu of any

parallel formats to achieve minimum pin count.

A special feature, character RAM fonts, is implemented in this MOSD

enhanced version (EMOSD). Users can download their own fonts and display

them at any time once the chip is powered on. There are two ways for users to

build and store fonts. One is a conventional approach to have masked ROM

fonts. A newer approach is to store the fonts in the EPROM accessed by the

MCU and then download them into the EMOSD character RAM. With this new

technique, users have more flexibility in preparing their fonts and the effective

number of fonts is greatly increased.

ORDERING INFORMATION

MC141541P

Plastic DIP

PIN ASSIGNMENT

V

1

2

16

15

V

SS(A)

SS

VCO

R

RP

)

3

4

5

6

7

8

14

13

12

11

10

9

G

B

DD(A

HFLB

FBKG

HTONE/

PWMCK

SS

VFLB

SDA(MOSI)

SCL(SCK)

V

DD

•

Two Selectable Resolutions: 320 (CGA) and 480 (EGA) Dots per Line

Fully Programmable Character Array of 10 Rows by 24 Columns

273 Bytes Direct Mapping Display RAM Architecture

Internal PLL Generates a Wide–Ranged System Clock

For High–End Monitor Application, Maximum Horizontal Frequency is

110 kHz (52.8 MHz Dot Clock at 480 Mode)

Programmable Vertical Height of Character to Meet Multi–Sync

Requirement

•

Programmable Vertical and Horizontal Positioning for Display Center

120 Characters and Graphic Symbols ROM and Eight Programmable

Character RAM

•

10 x 16 Dot Matrix Character

Character–by–Character Color Selection

A Maximum of Four Selectable Colors per Row

Double Character Height and Double Character Width

Character Bordering or Shadowing

Three Fully Programmable Background Windows with Overlapping

Capability

•

Provides a Clock Output Synchronous to the Incoming H Sync for External

PWM

•

M_BUS (IIC) Interface with Address $7A

Single Positive 5 V Supply

REV 1

2/97

TN97031200

Motorola, Inc. 1997

MOTOROLA

MC141541

1

BLOCK DIAGRAM

5

8

7

8

6

SDA(MOSI)

8

54

15

WADDR

DATA

SCL(SCK)

SS

MEMORY AND DATA

MANAGEMENT

DATA RECEIVER

RFG

3

WCOLOR

AND

CONTROL

RA,CA,DA

8

26

Z

9

BUS ARBITRATION

LOGIC

MCLK

ADDRC

26

13

CCOLORS

AND SELECT

Y

ROW

BUFFER

NROW

CHS

4

CWS

10

R

VFLB

VERTICAL

CONTROL

CIRCUIT

6

CHS

VERD

CRADDR

CRS

5

8

CH

4

LP

CHARACTER ROMS/RAMS

3

2

5

10

RP

CHAR

HORD

HORIZONTAL

CONTROL

AND PLL

VCO

HFLB

SC CCLK

10–BIT SHIFT

REGISTERS

4

V

DD(A)

54

WADDR

1

V

(A)

SS

BACKGROUND

GENERATOR

W

3

13

CCOLORS

AND SELECT

COLOR ENCODER

9

15

V

DD

WCOLOR

AND CONTROL

16

V

SS

15

14

13

12

11

MC141541

2

MOTOROLA

ABSOLUTE MAXIMUM RATINGS Voltage Referenced to V

SS

This device contains circuitry to protect the

inputs against damage due to high static volt-

ages or electric fields; however, it is advised that

normal precautions be taken to avoid applica-

tions of any voltage higher than the maximum

rated voltages to this high impedance circuit.

For proper operation it is recommended that

Symbol

Characteristic

Supply Voltage

Value

Unit

V

DD

– 0.3 to + 7.0

V

in

Input Voltage

V

– 0.3 to

+ 0.3

V

SS

DD

Id

Current Drain per Pin Excluding V

and V

SS

25

mA

DD

V

and V

out

in out DD

be constrained to the range V

≤

SS

in

(V or V ) ≤ V . Unused inputs must always

be tied to an appropriate logic voltage level (e.g.,

Operating Temperature Range

Storage Temperature Range

0 to 85

– 65 to + 150

°C

Ta

eitherV

open.

or V ). Unusedoutputsmustbeleft

DD

SS

T

stg

NOTE: MaximumRatingsarethosevaluesbeyondwhichdamagetothedevicemayoccur.

Functional operation should be restricted to the limits in the Electrical Characteris-

tics tables or Pin Description section.

AC ELECTRICAL CHARACTERISTICS (V

DD

= V

= 5.0 V, V

= V

= 0 V, T = 25°C, Voltage Referenced to V

)

SS

DD(A)

SS

SS(A)

A

Symbol

Characteristic

Min

Typ

Max

Unit

Output Signal (R, G, B, FBKG and HTONE/PWMCK) C

= 30 pF, see

load

Figure 1

Rise Time

Fall Time

t

—

6

ns

r

f

F

HFLB Input Frequency

—

110

kHz

HFLB

DC CHARACTERISTICS V

= V

= 5.0 V ± 10%, V

= V

= 0 V, T = 25°C, Voltage Referenced to V

SS(A) A SS

DD

DD(A)

SS

Symbol

Characteristic

Min

– 0.8

DD

Typ

Max

Unit

V

OH

High Level Output Voltage

= – 5 mA

V

—

V

I

out

Low Level Output Voltage

= 5 mA

V

OL

—

V

+ 0.4

V

SS

I

out

Digital Input Voltage (Not Including SDA and SCL)

V

Logic Low

Logic High

—

0.3 V

—

V

IL

DD

V

IH

0.7 V

DD

Input Voltage of Pin SDA and SCL in SPI Mode

Logic Low

Logic High

V

—

0.3 V

—

V

IL

V

IH

0.7 V

Input Voltage of Pin SDA and SCL in M_BUS Mode

Logic Low

Logic High

V

—

0.3 V

—

V

IL

V

IH

0.7 V

I

High–Z Leakage Current (R, G, B and FBKG)

– 10

—

+ 10

µA

II

I

Input Current (Not Including RP, VCO, R, G, B, FBKG and

HTONE/PWMCK)

– 10

—

+ 10

+ 15

µA

I

Supply Current (No Load on Any Output)

mA

DD

90%

10%

tf

90%

10%

tr

Figure 1. Switching Characteristics

MC141541

3

MOTOROLA

er the external R, G, and B amplifiers’ gain to achieve a

transparent windowing effect. If the PWMCK_EN bit is set to

1 via M_BUS or SPI, this pin is changed to a mode–depen-

dent clock output with 50/50 duty cycle and is synchronous

with the input horizontal synchronization signal at Pin 5. The

frequency is dependent on the mode in which the EMOSD is

currently running. The exact frequencies in the different reso-

lution modes are described in Table 1.

PIN DESCRIPTIONS

V

(Pin 1)

SS(A)

This pin provides the signal ground to the PLL circuitry.

Analog ground for PLL operation is separated from digital

ground for optimal performance.

VCO (Pin 2)

Pin 2 is a control voltage input to regulate an internal oscil-

lator frequency. See the Application Diagram for the applica-

tion values used.

Table 1. PWM CLK Frequency

Resolution

320 dots/line

480 dots/line

Frequency

Duty Cycle

50/50

RP (Pin 3)

32 x H

f

An external RC network is used to bias an internal VCO to

resonate at the specific dot frequency. The maximum voltage

at Pin 3 should not exceed 3.5 V at any condition. See the

Application Diagram for the application values used.

48 x H

50/50

NOTE: H

f is the frequency of the input H sync on Pin 5.

Typically, this clock is fed into an external pulse width mod-

ulation module as its clock source. Because of the synchro-

nization between PWM clock and H sync, a better

performance on the PWM controlled functions can be

achieved.

V

(Pin 4)

DD(A)

Pin 4 is a positive 5 V supply for PLL circuitry. Analog pow-

er for PLL is separated from digital power for optimal perfor-

mance.

FBKG (Pin 12)

HFLB (Pin 5)

This pin outputs a logic high while displaying characters or

windows when the FBKGC bit in the frame control register is

0, and output a logic high only while displaying characters

when the FBKGC bit is 1. It is defaulted to high–impedance

state after power–on, or when there is no output. An external

10 kΩ resistor pulled low is recommended to avoid level tog-

gling caused by hand effect when there is no output.

This pin inputs a negative polarity horizontal synchronize

signal pulse to phase lock an internal system clock gener-

ated by the on–chip VCO circuit.

SS (Pin 6)

This input pin is part of the SPI serial interface. An active

low signal generated by the master device enables this slave

device to accept data. This pin should be pulled high to termi-

nate the SPI communication. If M_BUS is employed as the

B,G,R (Pins 13,14,15)

EMOSD color output is TTL level RGB to the host monitor.

These three signals are active high output pins that are in a

high–impedance state when EMOSD is disabled.

serial interface, this pin should be tied to either V

or V

.

DD

SS

SDA (MOSI) (Pin 7)

V

(Pin 16)

SS

Data and control messages are being transmitted to this

chip from a host MCU via one of the two serial bus systems.

With either protocol, this wire is configured as a uni–direc-

tional data line. (Detailed description of these two protocols

will be discussed in the M_BUS and SPI sections).

This is the ground pin for the digital logic of the chip.

SYSTEM DESCRIPTION

MC141541 is a full–screen memory architecture. Refresh

is performed by the built–in circuitry after a screenful of dis-

play data has been loaded through the serial bus. Only

changes to the display data need to be input afterward.

Serial data, which includes screen mapping address, dis-

play information, and control messages, are transmitted via

one of the two serial buses: M_BUS or SPI (mask option).

These two sets of buses are multiplexed onto a single set of

wires. Standard parts offer M_BUS transmission. Parts

which offer SPI transmission mode must be specially

manufactured as custom parts.

SCL (SCK) (Pin 8)

A separate synchronizing clock input from the transmitter

is required for either protocol. Data is read at the rising edge

of each clock signal.

V

(Pin 9)

DD

This is the power pin for the digital logic of the chip.

VFLB (Pin 10)

Data is received from the serial port and stored by the

memory management circuit. Line data is stored in a row

buffer for display and refreshing. During this storing and re-

trieving cycle, bus arbitration logic patrols the internal traffic

to make sure that no crashes occur between the slower seri-

al bus receiver and the fast ‘screen–refresh’ circuitry. After

the full–screen display data is received through one of the

serial communication interfaces, the link can be terminated if

a change of the display is not required.

Similar to Pin 5, this pin inputs a negative polarity vertical

synchronize signal pulse.

HTONE/PWMCK (Pin 11)

This is a multiplexed pin. When the PWMCK_EN bit is

cleared after power–on or by the MCU, this pin is HTONE

and outputs a logic high during windowing except when

graphics or characters are being displayed. It is used to low-

MC141541

4

MOTOROLA

The bottom half of the Block Diagram contains the hard-

ware functions for the entire system. It performs all the

EMOSD functions such as programmable vertical length

(from 16 lines to 63 lines), display clock generation (which is

phase locked to the incoming horizontal sync signal at Pin 5

HFLB), bordering or shadowing, and multiple windowing.

Display RAM and Control Registers

After the proper identification by the receiving device, a

data train of arbitrary length is transmitted from the master.

There are three transmission formats from (a) to (c) as stated

below. The data train in each sequence consists of row ad-

dress (R), column address (C), and display information (I), as

shown in Figure 3. In format (a), display information data

must be preceded with the corresponding row address and

column address. This format is particularly suitable for updat-

ing small amounts of data between different rows. However,

if the current information byte has the same row address as

the one before, format (b) is recommended.

COMMUNICATION PROTOCOLS

M_BUS Serial Communication

This is a two–wire serial communication link that is fully

compatible with the IIC bus system. It consists of an SDA bi-

directional data line and an SCL clock input line. Data is sent

from a transmitter (master) to a receiver (slave) via the SDA

line, and is synchronized with a transmitter clock on the SCL

line at the receiving end. The maximum data rate is limited to

100 kbps and the default chip address is $7A, but is hard-

ware changeable by mask set.

row addr

col addr

info

Figure 3. Data Packet

For a full–screen pattern change that requires a massive

information update, or during power–up, most of the row and

column addresses of either (a) or (b) formats will be consec-

utive. Therefore, a more efficient data transmission format (c)

should be applied. This sends the RAM starting row and col-

umn addresses once only, and then treats all subsequent

data as display information. The row and column addresses

will be automatically incremented internally for each display

information data from the starting location.

The data transmission formats are:

(a) R – > C – > I – > R – > C – > I – > . . . . . . . . .

(b) R – > C – > I – > C – > I – > C – > I. . . . . . .

(c) R – > C – > I – > I – > I – > . . . . . . . . . . . . .

To differentiate the row and column addresses when trans-

ferring data from master, the MSB (most significant bit) is set,

as in Figure 4: ‘1’ to represent row, and ‘0’ for column ad-

dress. Furthermore, to distinguish the column address be-

tween formats (a), (b), and (c), the sixth bit of the column

address is set to ‘1’ which represents format (c), and ‘0’ for

format (a) or (b). However, there is some limitation on using

mixed formats during a single transmission. It is permissible

to change the format from (a) to (b), or from (a) to (c), or from

(b) to (a), but not from (c) back to (a) or (b).

Operating Procedure

Figure 2 shows the M_BUS transmission format. The mas-

ter initiates a transmission routine by generating a start

condition followed by a slave address byte. Once the ad-

dress is properly identified, the slave will respond with an ac-

knowledge signal by pulling the SDA line low during the ninth

SCL clock. Each data byte that follows must be eight bits

long, plus the acknowledge bit, for a total of nine bits. Ap-

propriate row and column address information and display

data can be downloaded sequentially in one of the three

transmission formats described in the Data Transmission

Formats section. In the cases of no acknowlege or comple-

tion of data transfer, the master will generate a stop condition

to terminate the transmission routine. Note that the OSD_EN

bit must be set after all the display information has been sent,

in order to activate the EMOSD circuitry of MC141541 so that

the received information can be displayed.

DATA BYTES

CHIP ADDRESS

SDA

ACK

BIT

4

FORMAT

ADDRESS

ROW

7

1

0

6

X

0

1

5

3

2

1

0

SCL

X

D

a, b, c

a, b

c

D

COLUMN

1

2–7

8

9

D

X: don’t care

D: valid data

STOP CONDITION

START CONDITION

Figure 4. Row & Column Address Bit Patterns

Character RAM

Figure 2. M_BUS Format

The structure of eight character RAM fonts is shown in Fig-

ure 5. They occupy the font number from 0 to 7. Because of

the 10 x 16 dot matrix font, each font is broken down into two

segments in the horizontal direction and 16 lines in the verti-

cal direction. Therefore, there are five dots that need to be

defined for each specified segment–line location. This 5–bit

data forms the lower five bits of the information data byte and

the higher three bits are ignored. Because there are 16 seg-

ments (two segments per font) and 16 lines, both the seg-

ment and line addresses are four bits wide.

DATA TRANSMISSION FORMATS

In this enhanced version MOSD, both display RAM, con-

trol registers, and character RAM fonts need to be pro-

grammed after power–on. The arrangement of the display

RAM and control registers is on the row–column basis, while

the character RAM is on the segment–line basis. Although

the address basis is different, the data downloading proto-

cols are very similar and will be described in the following

sections.

MC141541

5

MOTOROLA

from (a) to (c), or from (b) to (a), but not from (c) back to (a) or

(b).

BIT

4

FORMAT

ADDRESS

7

1

0

6

1

0

1

5

3

2

1

0

a, b, c

a, b

c

SEG

X

D

X

LINE

X

X: don’t care

D: valid data

Figure 7. Segment and Line Address Bit Patterns

MEMORY MANAGEMENT

Figure 5. Segment Address Structure

Inside this chip there are three kinds of RAM: display

RAM, control registers, and character RAM. Display RAM

and control registers are addressed with row and column

(coln) number in sequence, while the character RAM is ad-

dressed with segment and line number. The transmission

format is described in the Data Transmission Formats sec-

tion. In addition to the eight RAM fonts numbered from $00 to

$07, 120 masked ROM fonts numbered from $08 to $7F are

also built in to this chip.

Basically, the transmission format is very similar to that for

display RAM or control registers. The major difference is to

replace the row and column address with segment address

and line address, respectively. After the proper identification

by the receiving device, a data train of arbitrary length is

transmitted from the master.

There are three transmission formats, from (a) to (c) as

stated below. The data train in each sequence consists of

segment adress (S), line address (L), and font information (I),

as shown in Figure 6. In format (a), each font information

data has to be preceded with the corresponding segment ad-

dress and line address. This format is particularly suitable for

updating small portions of font patterns. However, if the cur-

rent information byte has the same segment address as the

one before, format (b) is recommended.

Display RAM and Control Registers

The spaces between Row 0 and Coln 0 to Row 9 and Coln

23 are called display registers, and each contains a charac-

ter RAM/ROM number corresponding to a display location on

the monitor screen. Every data row is associated with two

control registers, located at Coln 30 and 31 of their respec-

tive rows, that control the character display format for that

row. In addition, three window control registers for each of

three windows, together with three frame control registers,

occupy the first 13 columns of Row 10.

SEG ADDRESS

LINE ADDRESS

INFORMATION

COLUMN

0

23 24... 29 30 31

0

X

D4 D3 D2 D1 D0

NOTE: X means don’t care bit and D means valid data bit.

Figure 6. Data Packet

DISPLAY REGISTERS

For a new font pattern change which requires a massive

information update, or during power–up, most of the segment

and column address on either format (a) or (b) will appear to

be redundant. A more efficient data transmission format (c)

should be applied. It sends the character RAM starting seg-

ment and line addresses only once, and then treats all sub-

sequent data as font information. The segment and line

addresses will be automatically incremented internally for

each RAM font data from the starting location.

9

0

2

3

5

6

8 9

12

10 WINDOW 1 WINDOW 2 WINDOW 3 FRAME CRTL REG

WINDOW AND FRAME CONTROL REGISTERS

Figure 8. Memory Map

The data transmission formats are:

(a) S – > L– > I – > S – > L – > I – > . . . . . . . . .

The user should handle the internal RAM address location

with care, especially those rows with double length alphanu-

meric symbols. For example, if Row n is destined to be

double height on the memory map, the data displayed on

screen Rows n and n+1 will be represented by the data con-

tained in the memory address of Row n only. The data of the

next Row n+1 on the memory map will appear on the screen

as n+2 and n+3 row space, and so on. Hence, it is not neces-

sary to load a row of blank data to compensate for the double

row. The user should minimize excessive rows of data in

(b) S – > L – > I – > L – > I – > L – > I. . . . . . .

(c) S – > L – > I – > I – > I – > . . . . . . . . . . . . .

To differentiate the segment address from row and line ad-

dresses when transferring data, Bit 7 (MSB) and Bit 6 are

set, as in Figure 7, to ‘11’ to represent segment address, or

‘00’ to represent line address in format (a) or (b), or ‘01’ to

represent line address in format (c). However, there is some

limitation on using mixed formats during a single transmis-

sion. It is permissible to change the format from (a) to (b), or

MC141541

6

MOTOROLA

FONT NUMBER: $00 – $7F

memory in order to avoid overrunning the limited amount of

row space on the screen.

For rows with double width alphanumeric symbols, only

the data contained in the even numbered columns of the

memory map are shown. Odd numbered columns are

treated in the same manner as double height rows.

0

1

2

7

8

9

A

7D 7E 7F

. . . .

. . . . . . . . . . . . . . . . . . . . . . .

Character RAM/ROM

8 CHARACTER RAM FONTS

($00 – $07)

120 CHARACTER ROM FONTS

($08 – $7F)

The RAM fonts occupy the font numbers $00 to $07, and

their patterns can be changed at any time via the SPI or

M_BUS protocol. The masked ROM fonts are fixed and lo-

cated from number $08 to $7F. See Figure 9 for details.

Figure 9. Arrangement of Character RAM/ROM Fonts

MC141541

7

MOTOROLA

Row 10 Coln 2

REGISTERS

Display Register

7

6

5

4

3

2

1

0

ROW 10

COLN 2

COL END ADDR

R

G

B

MSB

LSB

7

6

5

4

3

2

1

0

CCS0

Bits 2–0 R, G and B — These bits control the color of Win-

dow 1. Window 1 occupies Columns 0–2 of Row 10; Window

2 occupies Columns 3–5; and Window 3 occupies Columns

6–8. Window 1 has the highest priority, and Window 3 the

least. If window overlapping occurs, the higher priority win-

dow will cover the lower one, and the higher priority color will

take over on the overlap window area. If the start address is

greater than the end address, this window will not be dis-

played.

CRADDR

Bit 7 CCS0 — This bit defines a specific character color

out of the two preset colors. Color 1 is selected if this bit is

cleared, and Color 2 otherwise.

Bit 6–0 CRADDR — These seven bits address the 128

characters or symbols residing in the character ROM.

Row Control Registers

Coln 30

Window 2 Registers

Row 10 Coln 3

7

6

5

4

3

2

1

0

R1

G1

B1

R2

G2

B2

CHS

CWS

COLN 30

7

6

5

4

3

2

1

0

ROW START ADDR

ROW END ADDR

Bits 7–2 — Color 1 is determined by R1, G1, and B1; Color

2 by R2, G2, and B2.

ROW 10

COLN 3

MSB

LSB

Bit 1 CHS — This bit determines the height of a display

symbol. When it is set, the symbol is displayed in double

height.

Row 10 Coln 4

Bit 0 CWS — Bit 0 is similar to Bit 1; when this bit is set, the

character is displayed in double width.

7

6

5

4

3

2

1

0

COL START ADDR

ROW 10

COLN 4

VPOL

WEN CCS1

MSB

LSB

Coln 31

Bit 2 WEN — This bit enables the background Window 2

generation when it is set.

7

6

5

4

3

2

1

0

Bit 1 CCS1 — This additional color select bit provides the

characters residing within Window 2 with two extra color

selections, making a total of four selections for that row.

Bit 0 VPOL — This bit selects the polarity of the incoming

vertical sync signal (VFLB) on Pin 5. If it is negative polarity,

clear this bit. Otherwise, set this bit to 1 to represent the posi-

tive V sync signal. After power–on, this bit is cleared.

R3

G3

B3

R4

G4

B4

COLN 31

Bits 7–2 — Color 3 is determined by R3, G3, and B3; Color

4 by R4, G4, and B4.

Window 1 Registers

Row 10 Coln 0

Row 10 Coln 5

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

ROW START ADDR

LSB

ROW END ADDR

ROW 10

COLN 0

ROW 10

COLN 5

COL END ADDR

R

G

B

LSB

MSB

LSB

Bit 2–0 R, G and B — These bits control the color of Win-

dow 2. Window 1 occupies Columns 0–2 of Row 10; Window

2 occupies Columns 3–5; and Window 3 occupies Columns

6–8. Window 1 has the highest priority, and Window 3 the

least. If window overlapping occurs, the higher priority win-

dow will cover the lower one, and the higher priority color will

take over on the overlap window area. If the start address is

greater than the end address, this window will not be dis-

played.

Row 10 Coln 1

7

6

5

4

3

2

1

0

COL START ADDR

ROW 10

COLN 1

WEN CCS1 HPOL

MSB

LSB

Bit 2 WEN — This bit enables the background Window 1

generation when it is set.

Bit 1 CCS1 — This additional color select bit provides the

characters residing within Window 1 with two extra color

selections, making a total of four selections for that row.

Bit 0 HPOL — This bit selects the polarity of the incoming

horizontal sync signal (HFLB) on Pin 5. If it is negative polar-

ity, clear this bit. Otherwise, set this bit to 1 to represent the

positive H sync signal. After power–on, this bit is cleared.

Window 3 Registers

Row 10 Coln 6

7

6

5

4

3

2

1

0

ROW START ADDR

ROW END ADDR

ROW 10

COLN 6

MSB

LSB

LSB MSB

MC141541

8

MOTOROLA

Bit 7 TB — Reserved test bit.

Bit 6 TB — Reserved test bit.

Row 10 Coln 7

7

6

5

4

3

2

1

0

Bit 5–0 CH5–CH0 — These six bits determine the dis-

played character height. It is possible to have a proper char-

acter height by setting a value greater than or equal to 16 on

a different horizontal frequency monitor. Setting a value be-

low 16 will not have a predictable result. Figure 10 illustrates

how this chip expands the built–in character font to the de-

sired height.

COL START ADDR

ROW 10

COLN 7

WEN CCS1

PWMCK_EN

MSB

LSB

Bit 2 WEN — This bit enables the background Window 3

generation when it is set.

Bit 1 CCS1 — This additional color select bit provides the

characters residing within Window 3 with two extra color

selections, making a total of four selections for that row.

Bit 0 PWMCK_EN — When this bit is set to 1, the HTONE/

PWMCK pin will be switched to a clock output which is syn-

chronous to the H sync and used as an external PWM (pulse

width modulation) clock source. Refer to the pin description

of HTONE/PWMCK for more information. After power–on,

the default value is 0.

0

1

2

3

4

5

6

7

16 lines

22 lines

8

9

Row 10 Coln 8

10

11

12

13

14

15

7

6

5

4

3

2

1

0

ROW 10

COLN 8

COL END ADDR

R

G

B

MSB

LSB

Built–in font

(10x16 matrix)

when CH=16

Display character

when CH=22

Bit 2–0 R, G and B — These bits control the color of Win-

dow 3. Window 1 occupies Columns 0–2 of Row 10; Window

2 occupies Columns 3–5; and Window 3 occupies 6–8. Win-

dow 1 has the highest priority, and Window 3 the least. If win-

dow overlapping occurs, the higher priority window will cover

the lower one, and the higher priority color will take over on

the overlap window area. If the start address is greater than

the end address, this window will not be displayed.

25 lines

34 lines

Frame Control Registers

Display character

when CH=25

Display character

when CH=34

Frame Control Register Row 10 Coln 9

Figure 10. Variable Character Height

Frame Control Register Row 10 Coln 12

7

6

5

4

3

2

1

0

VERTD

COLN 9

LSB

MSB

6

5

4

3

2

1

0

7

Bit 7–0 VERTD — These eight bits define the vertical start-

ing position. There are a total of 256 steps, with an increment

of four horizontal lines per step for each field. The value can-

not be zero anytime, and the default value is 4.

COLN 12

OSD_EN BSEN SHADOW TB X32B

TB

FBKGC

Bit 7 OSD_EN — The OSD circuit is activated when this bit

is set.

Frame Control Register Row 10 Coln 10

Bit 6 BSEN — This bit enables the character bordering or

shadowing function when it is set.

7

6

5

4

3

2

1

0

HORD

Bit 5 SHADOW — Characters with black–edge shadowing

are selected if this bit is set; otherwise bordering prevails.

Bit 4 TB — Reserved test bit.

Bit 3 X32B — This bit determines the number of dots per

horizontal line. There are 320 dots per horizontal line if Bit

X32B is clear, which is also the default power–on state.

Otherwise, 480 dots per horizontal sync line is chosen when

Bit X32B is set to 1. Refer to Table 2 for details.

Bit 2 TB — Reserved test bit.

COLN 10

TB

MSB

LSB

Bit 7 TB — Reserved test bit.

Bit 6–0 HORD — These bits define the horizontal starting

position for character display. Seven bits give a total of 96

steps and each increment represents a five–dot shift to the

right on the monitor screen. The value cannot be zero any-

time, and the default value is 10.

Bit 1 TB — Reserved test bit.

Frame Control Register Row 10 Coln 11

Bit 0 FBKGC — Bit 0 determines the configuration of the

FBKG output pin. When it is clear, the FBKG pin outputs high

while displaying characters or windows; otherwise, the

FBKG pin outputs high only while displaying characters.

6

5

4

3

2

1

0

7

COLN 11

TB

CH5 CH4 CH3 CH2

CH1 CH0

MC141541

9

MOTOROLA

vertical delay =

VERTD x 4 + 1 H scan lines

Table 2. Resolution Setting

Register Setting (32B)

0

1

variable number of H scan lines

VFLB

Dot Number per H Sync Line

320

480

0

1

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

10

11

12

13

14

15

Bordering

Shadowing

Figure 11. Character Bordering and Shadowing

Frame Format and Timing

Figure 12 illustrates the positions of all display characters

on the screen relative to the leading edge of horizontal and

vertical flyback signals. The shaded area indicates the area

outside the “safe viewing area” for the display characters.

Notice that there are two components in the equations stated

in Figure 12 for horizontal and vertical delays: fixed delays

from the leading edge of HFLB and VFLB signals, regardless

of the values of HORD and VERTD (47 dots + phase detec-

tion pulse width) and one H scan line for horizontal and verti-

cal delays, respectively; and variable delays determined by

the values of HORD and VERTD. Refer to Frame Control

Registers Coln 9 and 10 for the definitions of VERTD and

HORD.

Phase detection pulse width is a function of the external

charge–up resistor, which is the 330 kΩ resistor in a series

with 2 kΩ to VCO pin in the Application Diagram. Dot fre-

quency is determined by the equation H freq x 320 if Bit

X32B is clear, and H freq x 480 if Bit X32B is set to 1 and Bit

X64 is 0. For example, dot frequency is 10.24 MHz if H freq is

32 kHz while Bit X32B is 0. If Bit X32B is 1 and Bit X64 is 0,

the dot frequency will be 15.36 MHz (one and a half of the

original one).

. . . . . .

When double character width is selected for a row, only the

even–numbered characters will be displayed, as shown in

Row 2. Notice that the total number of horizontal scan lines in

the display frame is variable, depending on the chosen char-

acter height of each row. Care should be taken while config-

uring each row character height so that the last horizontal

scan line in the display frame always comes out before the

leading edge of VFLB of the next frame, to avoid wrapping

display characters of the last few rows in the current frame

into the next frame. The number of display dots in a horizon-

tal scan line is always fixed at 240, regardless of row charac-

ter width and the setting of Bit X32B.

Figure 12. Display Frame Format

MC141541

10

MOTOROLA

Although there are 24 character display registers that can

be programmed for each row, not every programmed charac-

ter can be shown on the screen in 320–dot resolution. Usual-

ly only 24 characters can be shown in this resolution at most.

This is induced by the time that is required to retrace the H

scan line. At 480–dot resolution, a total of 24 characters can

be displayed on the screen if the horizontal delay register is

set properly.

FONT

Icon Combination

MC141541 contains 120–character ROM and eight RAM.

The user can create an on–screen menu based on those

characters and programmable RAM. Refer to Table 3 for icon

combinations.

Figure 13 illustrates the timing of all output signals as a

function of window and fast–blanking features. Line 3 of all

three characters is used to illustrate the timing signals. The

shaded area depicts the window area. The characters on the

left and right appear identical except for the FBKGC bit. The

middle character does not have a window as its background.

Notice that signal HTONE/PWMCK is active only in the win-

dow area. Timing of the signal FBKG depends on the config-

uration of the FBKGC bit. The configuration of the FBKGC bit

affects only the FBKG signal timing; it has no effect on the

timing of HTONE/PWMCK. Waveform ‘R, G, or B’, which is

the actual waveform at R, G, or B pin, is the logical OR of

waveform ‘character R, G, or B’ and waveform ‘window R, G,

or B’. ‘Character R, G, or B’ and ‘window R, G, or B’ are inter-

nal signals for illustration purpose only. Also notice that

HTONE/PWMCK has exactly the same waveform as ‘win-

dow R, G, or B’.

Table 3. Combination Map

ICON

ROM ADDRESS (HEX)

Volume Bar I

48, 49, 57

Volume Bar II

Size

47

4F, 50

Position

51, 52

Geometry

53, 54, 55, 56

58,59

Contrast

Brightness

Horizontal Position

Horizontal Sizing

Vertical Position

Vertical Sizing

Pin Cushion

Deguassing

Trapezoid

5A, 5B

5C, 5D

5E, 5F

60, 61

62, 63

64, 65

66, 67

3

6C, 6D, 6E, 6F

68, 69, 6A, 6B

70, 71

Parallelogram

Color Select

Video Level

Input Select

Recall

72, 73

74, 75

76,77

Save

78, 79

Left/Right Arrows

INC/DEC sign

Speaker

7A, 7B

7C, 7D

7E, 7F

ROM CONTENT

Figures 14 – 17 show the ROM content of MC141541.

Figure 13. Timing of Output Signals as a Function

of Window and FBKGC Bit Features

MC141541

11

MOTOROLA

08

09

0A

0B

20

21

22

23

0C

0D

0E

0F

24

25

26

27

10

11

12

16

1A

13

28

2C

30

29

2A

2E

32

2B

2F

33

14

15

17

2D

18

19

1B

31

1C

1D

1E

1F

34

35

36

3A

3E

37

Figure 14. ROM Address ($08 – $1F)

38

39

3B

3C

3D

3F

Figure 15. ROM Address ($20 – $3F)

MC141541

12

MOTOROLA

40

41

45

49

42

46

4A

43

60

61

65

69

62

66

6A

63

67

6B

44

47

64

48

4B

68

4C

4D

4E

4F

6C

6D

6E

6F

50

51

52

53

70

71

72

73

54

55

56

57

74

75

76

77

58

59

5A

5B

78

79

7A

7B

5C

5D

5E

5F

7C

7D

7E

7F

Figure 16. ROM Address ($40 – $5F)

Figure 17. ROM Address ($60 – $7F)

MC141541

13

MOTOROLA

DESIGN CONSIDERATIONS

•

The dc supply path for Pin 9 (V ) should be separated

DD

from other switching devices.

Distortion

The LC filter should be connected between Pin 9 and Pin

4. Refer to the values used in the Application Diagram.

Motorola’s MC141541P has a built–in PLL for multi–sys-

tem application. Pin 2 voltage is dc–based for the internal

VCO in the PLL. When the input frequency (HFLB) to Pin 5

increases, the VCO frequency will increase accordingly. This

forces the PLL to a higher locked frequency output. The fre-

quency should be equal to 320/480 x HFLB (depending on

resolution).This is the pixel dot clock.

Biasing and filter networks should be connected to Pin 2

and Pin 3. Refer to the recommended networks in the Ap-

plication Diagram.

•

Two small capacitors can be connected between Pins 2

and 3, and between Pins 3 and 4.

Display distortion is caused by noise on Pin 2. Positive

noise increases the VCO frequency above normal. The cor-

responding scan line will be shorter accordingly. In contrast,

negative noise causes the scan line to be longer. The net re-

sult will be distortion on the display, especially on the right

hand side of the display window.

Jittering

Most display jittering is caused by HFLB jittering on Pin 5.

Care must be taken if the HFLB signal comes from the fly-

back transformer. A short path and shielded cable are rec-

ommended for a clean signal. A small capacitor can be

added between Pin 5 and Pin 16 to smooth the signal. Refer

to the value used in the Application Diagram.

In order to have distortion–free display, the following rec-

ommendations should be considered:

•

Only analog part grounds (Pin 2 to Pin 4) can be con-

nectedtoPin1(V ).V andothergroundsshouldbe

SS(A) SS

connected to PCB common ground. The V

Display Dancing

and V

SS(A)

grounds should be totally separated (i.e. V

SS

is float-

Most display dancing is caused by interference of the seri-

al bus. It can be avoided by adding series resistors to the se-

rial bus.

SS(A)

ing). Refer to the Application Diagram for the ground con-

nections.

APPLICATION DIAGRAM

V

CC

ANALOG GROUND – FLOATING

100 µH

0.1 µF

100 µF

1

9

V

DD

SS(A)

V

0.1

CC

0.01

µF

10

µF

µ

F

1 k

2 k

R

2

16

240

V

100

VCO

SS

R

0.047

µ

33 pF

1 k

F

15

14

13

12

G

3

4

RP

V

330 k

B

240

G

B

DD(A)

5

6

HFLB

SS

MPS2369

FBKG

330 pF

EMOSD

100

FBKG

IIC(SPI) BUS

100

7

8

11

10

HTONE

SDA(MOSI)

SCL(SCK)

HTONE

ANALOG GROUND

DIGITAL GROUND

VFLB

DIGITAL GROUND – COMMON GROUND

MC141541

14

MOTOROLA

PACKAGE DIMENSIONS

P SUFFIX

PLASTIC DIP

CASE 648–08

NOTES:

–A–

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

16

1

9

8

B

S

INCHES

MILLIMETERS

DIM

A

B

C

D

F

MIN

MAX

0.770

0.270

0.175

0.021

0.70

MIN

18.80

6.35

3.69

0.39

1.02

MAX

19.55

6.85

4.44

0.53

1.77

F

0.740

0.250

0.145

0.015

0.040

C

L

SEATING

PLANE

–T–

G

H

J

K

L

0.100 BSC

0.050 BSC

2.54 BSC

1.27 BSC

K

M

0.008

0.015

0.130

0.305

10

0.21

0.38

3.30

7.74

10

H

J

0.110

0.295

0

2.80

7.50

0

G

D 16 PL

0.25 (0.010)

M

S

0.020

0.040

0.51

1.01

M

T

A

MC141541

15

MOTOROLA

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and

specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola

datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”

must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of

others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other

applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury

ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola

and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees

arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that

Motorola was negligent regarding the design or manufacture of the part. Motorola and

Opportunity/Affirmative Action Employer.

are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal

Mfax is a trademark of Motorola, Inc.

How to reach us:

USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;

P.O. Box 5405, Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447

JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,

3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315

Mfax : RMFAX0@email.sps.mot.com – TOUCHTONE 602–244–6609

ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,

– US & Canada ONLY 1–800–774–1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298

INTERNET: http://www.mot.com/SPS/

MC141541/D

◊

MC141541

16

MOTOROLA


型号：	MC141541P
厂家：	MOTOROLA
描述：	Enhanced Monitor On-Screen Display 增强的监视屏幕显示消费电路商用集成电路叠加集成电路光电二极管监视器
文件：	总16页 (文件大小：365K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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