MC14515BDW [MOTOROLA]
4-Bit Transparent Latch/4-to-16 Line Decoder; 4位透明锁存器/ 4至16线译码器
| 型号： | MC14515BDW |
| 厂家： | 
MOTOROLA |
| 描述： | 4-Bit Transparent Latch/4-to-16 Line Decoder |
| 文件： | 总8页 (文件大小：257K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
The MC14514B and MC14515B are two output options of a 4 to 16 line
decoder with latched inputs. The MC14514B (output active high option)
presents a logical “1” at the selected output, whereas the MC14515B (output
active low option) presents a logical “0” at the selected output. The latches
are R–S type flip–flops which hold the last input data presented prior to the
strobe transition from “1” to “0”. These high and low options of a 4–bit latch/4
to 16 line decoder are constructed with N–channel and P–channel
enhancement mode devices in a single monolithic structure. The latches are
R–S type flip–flops and data is admitted upon a signal incident at the strobe
input, decoded, and presented at the output.
L SUFFIX
CERAMIC
CASE 623
P SUFFIX
PLASTIC
CASE 709
These complementary circuits find primary use in decoding applications
where low power dissipation and/or high noise immunity is desired.
DW SUFFIX
SOIC
CASE 751E
•
•
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC
MAXIMUM RATINGS* (Voltages Referenced to V
)
SS
Symbol
Parameter
DC Supply Voltage
Value
Unit
V
T
A
= – 55° to 125°C for all packages.
V
DD
– 0.5 to + 18.0
V , V
Input or Output Voltage (DC or Transient)
0.5 to V
DD
+ 0.5
V
in out
I , I
Input or Output Current (DC or Transient),
per Pin
± 10
mA
in out
P
Power Dissipation, per Package†
Storage Temperature
500
mW
C
D
T
stg
– 65 to + 150
260
T
Lead Temperature (8–Second Soldering)
C
L
DECODE TRUTH TABLE (Strobe = 1)*
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Selected Output
Data Inputs
MC14514 = Logic “1”
MC14515 = Logic “0”
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
Inhibit
D
C
B
A
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
S0
S1
S2
S3
BLOCK DIAGRAM
11
S0
A B C D
9
S1
S2
A B C D
A B C D
10
8
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
S4
S5
S6
S7
V
V
= PIN 24
= PIN 12
DD
SS
S3
S4
S5
A B C D
A B C D
A B C D
7
6
2
3
A
B
C
D
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
S8
S9
S10
S11
DATA 1
DATA 2
5
S6
S7
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
4
TRANSPARENT
LATCH
4 TO 16
DECODER
18
17
20
19
14
13
16
15
21
22
S8
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
S12
S13
S14
S15
DATA 3
DATA 4
S9
S10
S11
S12
S13
S14
1
X
X
X
X
All Outputs = 0, MC14514
All Outputs = 1, MC14515
1
STROBE
X = Don’t Care
*Strobe = 0, Data is latched
S15
A B C D
23
INHIBIT
REV 3
1/94
Motorola, Inc. 1995
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 55 C
25 C
Typ #
125 C
V
Vdc
DD
Characteristic
Output Voltage
Symbol
Unit
Min
Max
Min
Max
Min
Max
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
V
in
= V
DD
or 0
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
V
IH
Vdc
(V = 0.5 or 4.5 Vdc)
O
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V
(V
(V
(V
= 2.5 Vdc)
= 4.6 Vdc)
= 9.5 Vdc)
= 13.5 Vdc)
Source
Sink
5.0
5.0
10
– 1.2
– 0.25
– 0.62
– 1.8
—
—
—
—
– 1.0
– 0.2
– 0.5
– 1.5
– 1.7
– 0.36
– 0.9
– 3.5
—
—
—
—
– 0.7
– 0.14
– 0.35
– 1.1
—
—
—
—
OH
OH
OH
OH
15
(V
OL
(V
OL
(V
OL
= 0.4 Vdc)
= 0.5 Vdc)
= 1.5 Vdc)
I
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
OL
Input Current
I
15
—
—
—
± 0.1
—
—
±0.00001
± 0.1
—
—
± 1.0
µAdc
in
Input Capacitance
C
—
5.0
7.5
—
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
µAdc
DD
Total Supply Current**†
I
5.0
10
15
I
I
I
= (1.35 µA/kHz) f + I
= (2.70 µA/kHz) f + I
= (4.05 µA/kHz) f + I
TL
T
T
T
DD
DD
DD
(Dynamic plus Quiescent,
Per Package)
(C = 50 pF on all outputs, all
L
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25 C.
†To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C – 50) Vfk
T
L
T
L
where: I is in µA (per package), C in pF, V = (V
DD
– V ) in volts, f in kHz is input frequency, and k = 0.002.
SS
T
L
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautionsmust be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, V and V
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V
be left open.
should be constrained to the range V
≤ (V or V ) ≤ V
.
in out
SS
in
out
DD
or V ). Unused outputs must
SS
DD
MC14514B MC14515B
386
MOTOROLA CMOS LOGIC DATA
SWITCHING CHARACTERISTICS* (C = 50 pF, T = 25 C)
L
A
All Types
Typ #
Characteristic
Symbol
V
DD
Unit
Min
Max
Output Rise Time
t
ns
TLH
t
t
t
= (3.0 ns/pF) C + 30 ns
= (1.5 ns/pF) C + 15 ns
= (1.1 ns/pF) C + 10 ns
5.0
10
15
—
—
—
180
90
65
360
180
130
TLH
TLH
TLH
L
L
L
Output Fall Time
t
ns
ns
ns
ns
THL
t
t
t
= (1.5 ns/pF) C + 25 ns
= (0.75 ns/pF) C + 12.5 ns
= (0.55 ns/pF) C + 9.5 ns
5.0
10
15
—
—
—
100
50
40
200
100
80
THL
THL
THL
L
L
L
Propagation Delay Time; Data, Strobe to S
t
t
,
PLH
PHL
t
t
t
, t
= (1.7 ns/pF) C + 465 ns
= (0.86 ns/pF) C + 192 ns
= (0.5 ns/pF) C + 125 ns
L
5.0
10
15
—
—
—
550
225
150
1100
450
300
PLH PHL
L
L
, t
PLH PHL
, t
PLH PHL
Inhibit Propagation Delay Times
t
t
,
PLH
PHL
t
t
t
, t
= (1.7 ns/pF) C + 315 ns
= (0.66 ns/pF) C + 117 ns
= (0.5 ns/pF) C + 75 ns
L
5.0
10
15
—
—
—
400
150
100
800
300
200
PLH PHL
L
L
, t
PLH PHL
, t
PLH PHL
Setup Time
Data to Strobe
t
su
5.0
10
15
250
100
75
125
50
38
—
—
—
Hold Time
Strobe to Data
t
5.0
10
15
– 20
0
10
– 100
– 40
– 30
—
—
—
ns
ns
h
Strobe Pulse Width
t
WH
5.0
10
15
350
100
75
175
50
38
—
—
—
* The formulas given are for the typical characteristics only at 25 C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
V
DD
V
DS
S0
S1
STROBE
INHIBIT
D1
For MC14515B
1. For P–channel: Inhibit = V
DD
2. For N–channel: Inhibit = V
2. and D1–D4 constitute binary
2. code for “output under test.”
S2
S3
S4
SS
For MC14514B
S5
S6
1. For P–channel: Inhibit = V
1. and D1–D4 constitute
1. binary code for “output
1. under test.”
SS
S7
S8
D2
S9
I
D
S10
S11
S12
S13
S14
S15
2. For N–channel: Inhibit = V
DD
D3
EXTERNAL
POWER SUPPLY
D4
V
SS
Figure 1. Drain Characteristics Test Circuit
MOTOROLA CMOS LOGIC DATA
MC14514B MC14515B
387
V
V
DD
0.01
CERAMIC
µF
I
D
500
µF
24
DD
20 ns
20 ns
PULSE
GENERATOR
V
D1
D2
DD
S0
90%
10%
V
in
C
C
L
V
D3
D4
STROBE
SS
INHIBIT S15
L
12
V
SS
Figure 2. Dynamic Power Dissipation Test Circuit and Waveform
V
DD
STROBE
OUTPUT S0
OUTPUT S1
S0
S1
t
t
TLH
THL
INHIBIT
D1
20 ns
C
C
L
L
V
V
DD
SS
DD
SS
90%
50%
INPUT
PROGRAMMABLE
PULSE
GENERATOR
10%
PLH
t
t
PHL
V
D2
D3
90%
50%
10%
OUTPUT
V
OUTPUT S15
S15
SS
t
TLH
t
THL
D4
V
C
L
Figure 3. Switching Time Test Circuit and Waveforms
PIN ASSIGNMENT
ST
D1
D2
S7
S6
S5
1
2
3
4
5
6
24
23
22
21
20
19
V
DD
INH
D4
D3
S10
S11
S4
S3
S1
S2
S0
7
18
17
16
15
14
13
S8
8
S9
9
S14
S15
S12
S13
10
11
12
V
SS
MC14514B MC14515B
388
MOTOROLA CMOS LOGIC DATA
MOTOROLA CMOS LOGIC DATA
MC14514B MC14515B
389
COMPLEX DATA ROUTING
Two MC14512 eight–channel data selectors are used here
times faster then the shift frequency of the input registers, the
most significant bit (MSB) from each register could be se-
lected for transfer to the data bus. Therefore, all of the most
significant bits from all of the registers can be transferred to
the data bus before the next most significant bit is presented
for transfer by the input registers.
Information from the 3–state bus is redistributed by the
MC14514B four–bit latch/decoder. Using the four–bit ad-
dress, D1 thru D4, the information on the inhibit line can be
transferred to the addressed output line to the desired output
registers, A thru P. This distribution of data bits to the output
registers can be made in many complex patterns. For exam-
ple, all of the most significant bits from the input registers can
be routed into output register A, all of the next most signifi-
cant bits into register B, etc. In this way horizontal, vertical, or
other methods of data slicing can be implemented.
with the MC14514B four–bit latch/decoder to effect a com-
plex data routing system. A total of 16 inputs from data regis-
ters are selected and transferred via a 3–state data bus to a
data distributor for rearrangement and entry into 16 output
registers. In this way sequential data can be re–routed or
intermixed according to patterns determined by data select
and distribution inputs.
Data is placed into the routing scheme via the eight inputs
on both MC14512 data selectors. One register is assigned to
each input. The signals on A0, A1, and A2 choose one of
eight inputs for transfer out to the 3–state data bus. A fourth
signal, labelled Dis, disables one of the MC14512 selectors,
assuring transfer of data from only one register.
In addition to a choice of input registers, 1 thru 16, the rate
of transfer of the sequential information can also be varied.
That is, if the MC14512 were addressed at a rate that is eight
DATA ROUTING SYSTEM
INPUT
REGISTERS
DATA
TRANSFER
3–STATE
DATA BUS
DATA
DISTRIBUTION
OUTPUT
REGISTERS
DIS
D0
D1
D2
Q
REGISTER 1
D1 D2 D3 D4
S0
D3
D4
REGISTER A
STROBE
S1
S2
D5
D6
S3
S4
REGISTER 8
D7
A0 A1 A2
S5
S6
DATA
S7
SELECT
S8
S9
S10
A0 A1 A2
S11
S12
S13
D0
Q
REGISTER 9
D1
D2
D3
D4
D5
D6
D7
INHIBIT
S14
S15
REGISTER P
REGISTER 16
DIS
MC14514B MC14515B
390
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 623–05
ISSUE M
NOTES:
1. DIMENSION L TO CENTER OF LEADS WHEN
24
1
13
12
FORMED PARALLEL.
2. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION (WHEN FORMED
PARALLEL).
B
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
J
MIN
31.24
12.70
4.06
0.41
1.27
2.54 BSC
0.20
3.18
MAX
32.77
15.49
5.59
0.51
1.52
MIN
MAX
1.290
0.610
0.220
0.020
0.060
1.230
0.500
0.160
0.016
0.050
0.100 BSC
0.008
0.125
A
SEATING
PLANE
F
C
0.30
4.06
0.012
0.160
K
L
15.24 BSC
0.600 BSC
M
N
0
0.51
15
1.27
0
15
0.050
L
0.020
N
D
J
M
G
K
P SUFFIX
PLASTIC DIP PACKAGE
CASE 709–02
ISSUE C
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
24
1
13
12
B
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
MILLIMETERS
INCHES
DIM
A
B
C
D
F
MIN
31.37
13.72
3.94
0.36
1.02
MAX
32.13
14.22
5.08
0.56
1.52
MIN
MAX
1.265
0.560
0.200
0.022
0.060
1.235
0.540
0.155
0.014
0.040
L
A
C
N
G
H
J
K
L
2.54 BSC
0.100 BSC
K
1.65
0.20
2.92
2.03
0.38
3.43
0.065
0.008
0.115
0.080
0.015
0.135
J
H
F
M
SEATING
PLANE
D
G
15.24 BSC
0.600 BSC
M
N
0
0.51
15
1.02
0
15
0.040
0.020
MOTOROLA CMOS LOGIC DATA
MC14514B MC14515B
391
OUTLINE DIMENSIONS
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751E–04
ISSUE E
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
24
13
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
–B– 12X P
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
M
0.010 (0.25)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
1
12
24X D
J
MILLIMETERS
INCHES
M
S
S
0.010 (0.25)
T
A
B
DIM
A
B
C
D
MIN
15.25
7.40
2.35
0.35
0.41
MAX
15.54
7.60
2.65
0.49
0.90
MIN
MAX
0.612
0.299
0.104
0.019
0.035
0.601
0.292
0.093
0.014
0.016
F
R X 45
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
0.23
0.13
0
0.32
0.29
8
0.009
0.005
0
0.013
0.011
8
C
K
–T–
SEATING
M
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
PLANE
22X G
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent
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MC14514B/D
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