MC14534BDW [MOTOROLA]
5 Cascaded BCD Counters; 5级联BCD计数器
| 型号： | MC14534BDW |
| 厂家： | 
MOTOROLA |
| 描述： | 5 Cascaded BCD Counters |
| 文件： | 总9页 (文件大小：228K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
L SUFFIX
CERAMIC
CASE 623
The MC14534B is composed of five BCD ripple counters that have their
respective outputs multiplexed using an internal scanner. Outputs of each
counter are selected by the scanner and appear on four (BCD) pins.
Selection is indicated by a logic high on the appropriate digit select pin. Both
BCD and digit select outputs have three–state controls providing an
“open–circuit” when these controls are high and allowing multiplexing.
Cascading may be accomplished by using the carry–out pin. The counters
and scanner can be independently reset by applying a high to the counter
master reset (MR) and the scanner reset (SR). The MC14534B was
specifically designed for application in real time or event counters where
continual updating and multiplexed displays are used.
P SUFFIX
PLASTIC
CASE 709
DW SUFFIX
SOIC
CASE 751E
•
•
•
•
•
•
Four Operating Modes (See truth table)
Input Error Detection Circuit
Clock Conditioning Circuits for Slow Transition Inputs
Counter Sequences on Positive Transition of Clock A
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC
T
A
= – 55° to 125°C for all packages.
BLOCK DIAGRAM
TO CAPACITORS
22
1
V
= PIN 24
= PIN 12
DD
23
V
CLOCK B
CLOCK A
3
SS
PULSE ERROR
DETECTOR
ERROR OUT
PULSE
SHAPER
4
2
TEST
CONTROL
MASTER
RESET
UNITS
TENS
HUNDREDS
THOUSANDS
TEN
THOUSANDS
13
CARRY
CARRY OUT
C
÷
10
C
C
÷
10
C
C
÷
10
C
C
÷
10
C
C
÷
10
C
n+4
n+4
n+4
n+4
n+4
CONTROL
Q0
Q3
Q0
Q3
Q0
Q3
Q0
Q3
Q0
Q3
5
6
MODE A
MODE B
OUTPUT
17
18
MUX
MUX
MUX
MUX
CONTROL
Q3
Q2
MUX
BCD
OUT
19
20
SCANNER
RESET
Q1
Q0
9
R
10
SCANNER
CLOCK
SCANNER
3–STATE BCD
CONTROL
21
15
3–STATE DIGIT
CONTROL
3–State Control
Out
7
8
14
16
11
DS5
DS1
DS2
DS3
DS4
NOTE:
0
1
Q or DS
High Impedance
= 3–STATE
DIGIT SELECT
OUTPUT BUFFER
REV 3
1/94
Motorola, Inc. 1995
MAXIMUM RATINGS (Voltages referenced to V
)
SS
Symbol
Parameter
DC Supply Voltage
Input or Output Voltage (DC or Transient)
Value
Unit
V
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
V
DD
– 0.5 to + 18.0
V , V
in out
– 0.5 to V
DD
+ 0.5
V
I , I
in out
Input or Output Current (DC or Transient),
per Pin
± 10
mA
operation, V and V
to the range V
SS
Unused inputs must always be tied to an
should be constrained
in
out
P
D
Power Dissipation, per Package†
Storage Temperature
500
mW
C
(V or V
)
V
DD
.
in out
T
stg
– 65 to + 150
260
appropriate logic voltage level (e.g., either V
SS
or V ). Unused outputs must be left open.
T
L
Lead Temperature (8–Second Soldering)
C
DD
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 55 C
25 C
Typ #
125 C
V
Vdc
DD
Characteristic
Output Voltage
Symbol
Unit
Min
Max
Min
Max
Min
Max
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
V
in
= V
DD
or 0
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.0
2.0
3.0
—
—
—
1.5
3.0
4.5
1.0
2.0
3.0
—
—
—
1.0
2.0
3.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
V
IH
Vdc
(V = 0.5 or 4.5 Vdc)
O
5.0
10
15
4.0
8.0
12
—
—
—
4.0
8.0
12
3.5
7.0
11
—
—
—
4.0
8.0
12
—
—
—
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V
(V
(V
(V
= 2.5 Vdc)
= 4.6 Vdc)
= 9.5 Vdc)
= 13.5 Vdc)
Source
Sink
5.0
5.0
10
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
OH
OH
OH
OH
15
(V
OL
(V
OL
(V
OL
= 0.4 Vdc)
= 0.5 Vdc)
= 1.5 Vdc)
I
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
mAdc
OL
Output Drive Current — Pins 1 and 22
I
OH
(V
(V
(V
= 2.5 Vdc)
= 9.5 Vdc)
= 13.5 Vdc)
5.0
10
15
– 0.31
– 0.31
– 0.9
– 0.25
– 0.25
– 0.75
– 0.8
– 0.4
– 1.6
– 0.17
– 0.17
– 0.51
OH
OH
OH
Source
Sink
—
—
—
—
—
—
(V
OL
(V
OL
(V
OL
= 0.4 Vdc)
= 0.5 Vdc)
= 1.5 Vdc)
I
5.0
10
15
0.024
0.06
1.3
—
—
—
0.02
0.05
0.25
0.03
0.09
1.63
—
—
—
0.014
0.035
0.175
—
—
—
mAdc
OL
Input Current
I
15
—
—
—
± 0.1
—
—
± 0.00001
± 0.1
—
—
± 1.0
µAdc
in
Input Capacitance
C
—
5.0
7.5
—
pF
in
(V = 0)
in
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
(continued)
MC14534B
2
MOTOROLA CMOS LOGIC DATA
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V ) (continued)
SS
– 55 C
25 C
Typ #
125 C
V
Vdc
DD
Characteristic
Quiescent Current
Symbol
Unit
Min
Max
Min
Max
Min
Max
I
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.010
0.020
0.030
5.0
10
20
—
—
—
150
300
600
µAdc
DD
(Per Package)
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
I
5.0
10
15
µAdc
µAdc
T
I
T
I
T
I
T
= (0.5 µA/kHz) f + I
= (1.0 µA/kHz) f + I
= (1.5 µA/kHz) f + I
DD
DD
DD
Scan Oscillator
Frequency = 1.0 kHz
(C = 50 pF on all outputs, all
L
buffers switching)
Three–State Leakage Current
I
15
—
± 0.1
—
± 0.0001
± 0.1
—
± 3.0
TL
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25 C.
†To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C – 50) Vfk
T
L
T
L
where: I is in µA (per package), C in pF, V = (V
DD
– V ) in volts, f in kHz is input frequency, and k = 0.001.
SS
T
L
MOTOROLA CMOS LOGIC DATA
MC14534B
3
SWITCHING CHARACTERISTICS* (C = 50 pF, T = 25 C, see Figure 1)
L
A
V
Vdc
DD
Characteristic
Output Rise and Fall Time
Symbol
Min
Typ #
Max
Unit
t
t
,
5.0
10
15
—
—
—
100
50
40
200
100
80
ns
TLH
THL
Propagation Delay Time,
Clock to Q
t
t
,
µs
PLH
PHL
PLH
PHL
PHL
t
t
t
, t
= (1.8 ns/pF) C + 4.0 µs
= (0.8 ns/pF) C + 1.5 µs
= (0.6 ns/pF) C + 1.0 µs
5.0
10
15
—
—
—
4.0
1.5
1.0
8.0
3.0
2.25
PLH PHL
L
L
L
, t
PLH PHL
, t
PLH PHL
Clock to Carry Out
t
µs
µs
µs
µs
µs
t
t
t
= (1.8 ns/pF) C + 3.3 µs
= (0.8 ns/pF) C + 1.1 µs
= (0.6 ns/pF) C + 0.8 µs
5.0
10
15
—
—
—
3.3
1.1
0.8
6.6
2.2
1.7
PLH
PLH
PLH
L
L
L
Master Reset to Q
t
t
t
t
t
= (1.8 ns/pF) C + 1.8 µs
= (0.8 ns/pF) C + 0.6 µs
= (0.6 ns/pF) C + 0.5 µs
5.0
10
15
—
—
—
1.8
0.6
0.5
3.6
1.2
0.9
PHL
PHL
PHL
L
L
L
Master Reset to Error Out
t
t
t
= (1.8 ns/pF) C + 0.57 µs
= (0.8 ns/pF) C + 0.19 µs
= (0.6 ns/pF) C + 0.11 µs
5.0
10
15
—
—
—
0.6
0.2
0.12
1.5
.5
0.38
PHL
PHL
PHL
L
L
L
Scanner Clock to Q
t
t
,
PLH
t
t
t
t
= (1.8 ns/pF) C + 1.8 µs
= (0.8 ns/pF) C + 0.6 µs
= (0.6 ns/pF) C + 0.5 µs
5.0
10
15
—
—
—
1.8
0.6
0.5
3.6
1.2
0.9
PLH, PHL
L
L
L
PHL
, t
PLH PHL
, t
PLH PHL
Scanner Clock to Digit Select
t
t
,
PLH
t
t
t
, t
= (1.8 ns/pF) C + 1.5 µs
= (0.8 ns/pF) C + 0.5 µs
= (0.6 ns/pF) C + 0.4 µs
5.0
10
15
—
—
—
1.5
0.5
0.4
3.0
1.0
0.75
PHL PLH
L
L
L
PLH
, t
PHL PLH
, t
PHL PLH
Propagation Delay Time
3–State Control to Q
t
5.0
10
15
—
—
—
75
45
40
150
90
80
ns
ns
PHZ
t
5.0
10
15
—
—
—
120
55
40
240
110
80
PZH
t
5.0
10
15
—
—
—
120
55
45
240
110
90
ns
PLZ
t
5.0
10
15
—
—
—
160
70
45
320
140
90
ns
PZL
Clock Pulse Frequency
f
5.0
10
15
—
—
—
1.0
3.0
5.0
0.5
1.0
1.2
MHz
ns
cl
Clock or Scanner Clock Pulse Width
Scanner Reset Pulse Width
Scanner Reset Removal Time
Master Reset Pulse Width
Master Reset Removal Time
t
5.0
10
15
1000
500
375
500
190
125
—
—
—
WH
t
w
5.0
10
15
320
130
80
160
65
40
—
—
—
ns
t
5.0
10
15
900
150
100
270
80
50
—
—
—
ns
rem
t
5.0
10
15
2000
600
450
900
300
250
—
—
—
ns
WH(R)
t
5.0
10
15
1060
350
250
550
205
140
—
—
—
ns
rem
* The formulas given are for the typical characteristics only at 25 C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
MC14534B
4
MOTOROLA CMOS LOGIC DATA
COUNTER TIMING DIAGRAM
2
3
4
5
6
10
1
2
3
4
5
6
7
8
9
10
10
10
10
10
CLOCK A
UNITS Q0
UNITS Q1
UNITS Q2
UNITS Q3
UNITS C
n+4
TENS Q0
TENS Q3
TENS C
n+4
HUNDREDS Q0
HUNDREDS Q3
HUNDREDS C
n+4
THOUSANDS Q0
THOUSANDS Q3
THOUSANDS C
n+4
TEN THOUSANDS Q0
TEN THOUSANDS Q3
CARRY OUT
MASTER RESET
MODE CONTROL TRUTH TABLE
Carry to Second Stage
Mode A
Mode B
First Stage Output
Application
0
0
1
1
0
1
1
0
Normal Count and Display At 9 to 0 transition of first stage
5–digit Counter
Inhibited
Inhibited
Input Clock
At 4 to 5 transition of first stage 4–digit counter with ÷ 10 and roundoff at front end.
At 7 to 8 transition of first stage 4–digit counter with 1/2 pence capability.
Test Mode: Clock directly into stages 1, 2, and 4.
Counts 3, 4, 5, 6, 7 = 5
Counts 8, 9, 0, 1, 2 = 0
MOTOROLA CMOS LOGIC DATA
MC14534B
5
SCANNER TIMING DIAGRAM
SCANNER
CLOCK
SCANNER
RESET
DS1
DS2
DS3
UNITS
TENS
HUNDREDS
DS4
DS5
THOUSANDS
TEN
THOUSANDS
NOTE: If Mode B = 1, the first decade is inhibited and S1 will not go high, and the cycle will be
shortened to four stages.
DS5 is selected automatically when Scanner Reset goes high.
ERROR DETECTION TIMING DIAGRAM
RESET
CLOCK A
CLOCK B
ERROR
1
ERROR
2
ERROR
OUT
GOOD PULSE
GOOD PULSE
ERROR
3
ERROR
4
NOTE: Error detector looks for inverted pulse on Clock B. Whenever a positive edge at
Clock A is not accompanied by a negative pulse at Clock B (or vice–versa) within
a time period of the one–shots an error is counted. Three errors result in Error Out
to go to a “1”. If error detection is not needed, tie Clock B high or low and leave
Pins 1 and 22 unconnected.
CLOCK SKEW RANGE
1000
500
300
100
SKEW IN THIS RANGE
NOTES:
RESULTS IN COUNTED
50
30
1. The skew is the time difference between the
low–to–high transition of C to the high–to–
low transition of C or vice–versa. Capacitors
ERROR.
MAX
A
B
SKEW IN THIS RANGE
MAY OR MAY NOT
RESULT IN COUNTED
ERROR.
C1 = C22 tied from pins 1 and 22 to V
.
10
SS
TYP
MIN
2. This graph is accurate for C1 = C22 ≥ 100 pF.
3. When the error detection circuitry in not used,
pins 1 and 22 are left open.
5.0
3.0
SKEW IN THIS RANGE
RESULTS IN NO ERROR
COUNTED.
1.0
3.0
5.0
7.0
9.0
11
(Vdc)
13
15
17
V
DD
MC14534B
6
MOTOROLA CMOS LOGIC DATA
APPLICATIONS INFORMATION
V
DD
MC14534B
MC14534B
CLOCK A
En
C
1/2
MC14518B
Q4
CLOCK A
C
*
out
CLOCK
* Carry Out is high for a single clock period when all five BCD stages go to zero.
(Carry Out also goes high when MR is applied.)
Figure 1. Cascade Operation
Q0
CLOCK
CLOCK A
BCD FOR
SELECTED
STAGE
Q1
Q2
Q3
MC14534B
SC
DS1
DS2
DS3
DS4
DS5
When the Q outputs of a given stage are required, this configuration will
lock up the selected stage within four clock cycles. The select line feedback
may be hardwired or switched.
Figure 2. Forcing a BCD Stage to the Q Outputs
PIN ASSIGNMENT
C
1
2
3
4
5
6
24
23
22
21
20
19
V
ext
MR
DD
CLOCK B
E
C
ext
out
CLOCK A
3–ST BCD
MODE A
MODE B
Q0
Q1
DS1
DS2
SR
7
18
17
16
15
14
13
Q2
8
Q3
9
DS4
SC
10
11
12
3–ST DIG
DS3
DS5
V
C
out
SS
MOTOROLA CMOS LOGIC DATA
MC14534B
7
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 623–05
ISSUE M
NOTES:
1. DIMENSION L TO CENTER OF LEADS WHEN
24
1
13
12
FORMED PARALLEL.
2. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION (WHEN FORMED
PARALLEL).
B
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
J
MIN
31.24
12.70
4.06
0.41
1.27
2.54 BSC
0.20
3.18
MAX
32.77
15.49
5.59
0.51
1.52
MIN
MAX
1.290
0.610
0.220
0.020
0.060
1.230
0.500
0.160
0.016
0.050
0.100 BSC
0.008
0.125
A
SEATING
PLANE
F
C
0.30
4.06
0.012
0.160
K
L
15.24 BSC
0.600 BSC
M
N
0
0.51
15
1.27
0
15
0.050
L
0.020
N
D
J
M
G
K
P SUFFIX
PLASTIC DIP PACKAGE
CASE 709–02
ISSUE C
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
24
1
13
12
B
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
MILLIMETERS
INCHES
DIM
A
B
C
D
F
MIN
31.37
13.72
3.94
0.36
1.02
MAX
32.13
14.22
5.08
0.56
1.52
MIN
MAX
1.265
0.560
0.200
0.022
0.060
1.235
0.540
0.155
0.014
0.040
L
A
C
N
G
H
J
K
L
2.54 BSC
0.100 BSC
K
1.65
0.20
2.92
2.03
0.38
3.43
0.065
0.008
0.115
0.080
0.015
0.135
J
H
F
M
SEATING
PLANE
D
G
15.24 BSC
0.600 BSC
M
N
0
0.51
15
1.02
0
15
0.040
0.020
MC14534B
8
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751E–04
ISSUE E
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
24
13
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
–B– 12X P
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
M
0.010 (0.25)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
1
12
24X D
J
MILLIMETERS
INCHES
M
S
S
0.010 (0.25)
T
A
B
DIM
A
B
C
D
MIN
15.25
7.40
2.35
0.35
0.41
MAX
15.54
7.60
2.65
0.49
0.90
MIN
MAX
0.612
0.299
0.104
0.019
0.035
0.601
0.292
0.093
0.014
0.016
F
R X 45
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
0.23
0.13
0
0.32
0.29
8
0.009
0.005
0
0.013
0.011
8
C
K
–T–
SEATING
M
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
PLANE
22X G
Motorolareserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representationorguaranteeregarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
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MC14534B/D
◊
相关型号：
MC14534BDWR2
4000/14000/40000 SERIES, ASYN POSITIVE EDGE TRIGGERED 20-BIT UP DECADE COUNTER, PDSO24, SOIC-24
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