MC44460 [MOTOROLA]
PICTURE-IN-PICTURE (PIP) CONTROLLER; 子母画面( PIP )控制器型号: | MC44460 |
厂家: | MOTOROLA |
描述: | PICTURE-IN-PICTURE (PIP) CONTROLLER |
文件: | 总16页 (文件大小:442K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Order this document by MC44460/D
PICTURE–IN–PICTURE
(PIP) CONTROLLER
The MC44460 Picture–in–Picture (PIP) controller is a low cost member of
a family of high performance PIP controllers and video signal processors for
television. It is NTSC compatible and contains all the analog signal
processing, control logic and memory necessary to provide for the overlay of
a small picture from a second non synchronized source onto the main picture
of a television. All control and setup of the MC44460 is via a standard two pin
SEMICONDUCTOR
TECHNICAL DATA
2
I C bus interface. The device is fabricated using BICMOS technology. It is
available in a 56–pin shrink dip (SDIP) package.
The main features of the MC44460 are:
• Two NTSC CVBS Inputs
• Switchable Main and PIP Video Signals
• Single NTSC CVBS Output Allows Simple TV Chassis Integration
• Two PIP Sizes; 1/16 and 1/9 Screen Area
• Freeze Field Feature
56
1
• Variable PIP Position in 64–X by 64–Y Steps
• PIP Border with Programmable Color
• Programmable PIP Tint and Saturation Control
• Automatic Main to PIP Contrast Balance
• Vertical Filter
B SUFFIX
PLASTIC PACKAGE
CASE 859
(SDIP)
• Integrated 64 k Bit DRAM Memory Resulting in Minimal RFI
• Minimal RFI Allows Simple Low Cost Application into TV
• I C Bus Control – No External Variable Adjustments Needed
• Operates from a Single 5.0 V Supply
• Economical 56–Pin Shrink DIP Package
ORDERING INFORMATION
Operating
2
Temperature Range
Device
Package
MC44460B
T
J
= –65° to +150°C
SDIP
Representative Block Diagram
Decoder Clamp Caps
Sync Out
28
Filter PLL
ADC Mid–Ref
51
33
40
41
42
29
Filter
Tracking
Sync In
H PLL
Low Pass
Filter
36
34
H and V
Timebase
31
32
Video 1
Video 2
Input
Switch
503 kHz Res
Band Pass
Filter
Y
Y
Y
U V
6–Bit
ADC
37
49
NTSC
Decoder
1
2
3
4
5
Decoder ACC
Main Out
V
U
V
U
Clamp
6
H
in
3
V
in
PIP
Switch
SCL
Digital
Logic
6
57.28 MHz
0
°
90°
38
39
7
Tint DAC
Sat DAC
SDA
Reset
Vert
Decoder Xtal
Decoder PLL
4X S/C
Osc + PLL
14.32 MHz
6
10
30
Vid 1/2 Sel
Multi Test
16 F
SC
PLL
6
16X S/C
Osc + PLL
44
45
NTSC
Encoder
3.0 MHz
LPF
Encoder Phase
Encoder ACC
U DAC
V DAC
Y DAC
Clamp
3.0 MHz
LPF
0°
90°
6
Memory
8.0 k x 8
DRAM
Y
U
V
4X S/C
Osc + PLL
I Ref
3.0 MHz
LPF
6
46
47
52 53 54
6
Encoder
PLL
Encoder
Xtal
Cur Ref
Encoder Clamp Caps
This device contains 500,000 active transistors.
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
Motorola, Inc. 1996
MC44460
PIN CONNECTIONS
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
H
V
N/C
in
in
2
N/C
3
SCL
SDA
Encoder V Cap
Encoder U Cap
Endoder Y Cap
ADC Mid Ref
4
5
Reset
6
I
ref
7
16 F
SC
Filter
(dig)
(dig)
Video Out V
Video Out
CC
8
V
DD
9
V
Analog Gnd
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Video 1/2 Select
Encoder Xtal
Encoder PLL
Encoder ACC
Encoder Phase
N/C
N/C
N/C
V
(mem)
(mem)
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
Analog V
CC
DD
V
Decoder V Cap
Decoder U Cap
Decoder Y Cap
Decoder PLL
Decoder Xtal
Decoder ACC
Video In 1
SS
Analog Gnd
Video In 2
Filter PLL
503 kHz Resonator
H PLL
Multi Test
Sync Out
Sync In
(Top View)
2
MOTOROLA ANALOG IC DEVICE DATA
MC44460
MAXIMUM RATINGS
Rating
Symbol
Value
–0.5 to +6.0
–0.5 to +6.0
–0.5,
Unit
V
Power Supply Voltage
Power Supply Voltage
Input Voltage Range
V
DD
CC
V
V
V
IR
V
V
DD
+ 0.5
Output Current
I
O
160
mA
Power Dissipation
Maximum Power Dissipation @ 70°C
Thermal Resistance, Junction–to–Air
P
1.3
59
W
°C/W
D
R
θJA
Junction Temperature (Storage and Operating)
T
J
–65 to +150
°C
NOTE: ESD data available upon request.
ELECTRICAL CHARACTERISTICS (V
= V = 5.0 V, T = 25°C, unless otherwise noted.)
DD A
CC
Characteristic
Symbol
Min
Typ
Max
Unit
POWER SUPPLY
Total Supply (Pins 8, 15, 43 and 50)
Total I
Supply
95
124
160
mA
VIDEO
Composite Video Input (Pin 34 or 36)
CVi
–
–
–
–
–
–
–
1.0
2.0
1.0
6.0
10
–
–
–
–
–
–
Vpp
Vpp
Vdc
dB
Composite Video Output (Pin 49, Unterminated)
Video Output DC Level (Sync Tip)
Video Gain
–
–
Video Frequency Response (Main Video to –1.0 dB)
Color Bar Accuracy
–
MHz
deg
dB
–
±4.0
Video Crosstalk (@ 75% Color Bars)
Main to PIP
PIP to Main
–
–
–
55
55
–
–
Output Impedance
–
–
–
5.0
Ω
HORIZONTAL TIMEBASE
Free Run HPLL Frequency (Pin 16)
–
–
–
–
–
–
–
–
–
–
15734
±400
±4.0
1.0
–
–
–
–
–
Hz
Hz
ns
µs
µs
HPLL Pull–In Range
HPLL Jitter
Burst Gate Timing (from Trailing Edge Hsync, Pin 24)
Burst Gate Width
4.0
VERTICAL TIMEBASE
Vertical Countdown Window
–
–
232
–
–
–
296
31
H lines
Vertical Sync Integration Time
µs
ANALOG TO DIGITAL CONVERTER
Resolution
–
–
–
–
–
–
–
–
–
–
–
–
–
±1.0
6.0
–
Bits
LSB
LSB
MHz
kHz
Integral Non–Linearity
Differential Non–Linearity
+2.0/–1.0
1.0
–
ADC – Y Frequency Response @ –5.0 dB
ADC – U, V Frequency Response @ –5.0 dB
–
200
–
Sample Clock Frequency (4/3 F
)
4.773
–
MHz
SC
3
MOTOROLA ANALOG IC DEVICE DATA
MC44460
ELECTRICAL CHARACTERISTICS (continued) (V
= V = 5.0 V, T = 25°C, unless otherwise noted.)
DD A
CC
Characteristic
Symbol
Min
Typ
Max
Unit
DIGITAL TO ANALOG CONVERTER
Resolution
–
–
–
–
–
–
–
–
6.0
–
Bits
LSB
LSB
Deg
dB
Integral Non–Linearity
±1.0
Differential Non–Linearity
–
+2.0/–1.0
–
Tint DAC Control Range (in 64 Steps)
Saturation DAC Control Range (in 64 steps)
–10
–6.0
–
–
10
6.0
NTSC DECODER
Color Kill Threshold
–
–
–
–24
2.0
–
3.0
–
–16
4.0
0.5
dB
dB
dB
Threshold Hysteresis
ACC (Chroma Amplitude Change, +3.0 dB to –12 dB)
PIP CHARACTERISTICS
–0.5
PIP Size
–
1/9 Screen Horizontal
1/9 Screen Vertical
1/16 Screen Horizontal
1/16 Screen Vertical
–
–
–
–
114
71
84
–
–
–
–
pels
lines
pels
lines
54
Border Size Horizontal
Border Size Vertical
–
–
–
–
–
–
–
–
–
–
6.0
2.0
–
–
–
–
–
pels
lines
MHz
%
Output PEL Clock (4 F
)
14.318
100
SC
Position Control Range Horizontal (% of Main Picture)
Position Control Range Vertical (% of Main Picture)
100
%
4
MOTOROLA ANALOG IC DEVICE DATA
MC44460
PIN FUNCTION DESCRIPTION
Pin
Equivalent Internal Circuit
Description
1
Horizontal Reference In (H )
in
CMOS level pulse synchronous with TV horizontal retrace signal. This
pulse may be active high or low since there is a polarity selector bit in
an internal control register. This pulse should begin 0.5 to 0.75 µs after
the beginning of the main video H sync period. Its duty cycle should be
less than 50%.
1.0 k
1
2
Vertical Reference In (V )
in
CMOS level pulse synchronous with TV vertical retrace signal. This
pulse may be active high or low since there is a polarity selector bit in
an internal control register. This pulse should begin during the main
video vertical interval and have a duration of at least .5H.
1.0 k
1.0 k
2
3
3
4
Serial Clock (SCL)
2
CMOS level I C Compatible slave only clock input. 100 kHz Maximum
2
frequency. 50% duty cycle. See Figure 1 for timing. See I C Register
Description for internal register descriptions and addresses.
Serial Data (SDA)
1.0 k
2
CMOS level I C Compatible slave only data input/output. As an output
4
2
it is open collector. See Figure 1 for timing. See I C Register
Description for internal register descriptions and addresses.
5
Reset
5.0
The active low, Power On Reset initializes all internal registers to zero
2
and resets the I C interface. Minimum active low time required for
22 k
0.22
Power On Reset reset is 100 ms.
5
6
Current Reference
The internal reference for all analog circuitry should be connected to
an external 12.1 k resistor.
6
120
120
12.1 k
7
PLL Filter
Filter for the 16X S/C PLL which is phase locked to the 4X S/C
oscillator.
7
100
1000
100
Pins 11 to 13, 16 to 27, 55 and 56 are test pins configured as outputs in a high impedance state. In an application, no connection should be made to these pins.
5
MOTOROLA ANALOG IC DEVICE DATA
MC44460
PIN FUNCTION DESCRIPTION (continued)
Pin
Equivalent Internal Circuit
Description
8
9
8
14, 43, 50 15, 35, 48
V
, V
DD SS
14, 43, 50
9
15, 35, 48
The four V
supply. The four V
V
DD
pins must be externally connected to a 5.0 V (±5%)
DD
lines must externally connect to their respective
bypass return(s) to ensure that no ground disturbances occur in
SS
operation. All supplies must be properly bypassed and isolated for the
application. Bypass capacitors of 10 µF in parallel with 0.1 µF for each
supply are recommended as a general guideline. The 0.1 µF, high
frequency bypass capacitors should be placed as close to the power
pins as practical.
V
V
DD
M V
DD
M V
SS
SS
An V
An Gnd
An Gnd
CC
Vid V
CC
10
Video 1/2 Select Output
High output level indicates that Video 1 is selected to be the main
picture video. Low output level indicates Video 2 is selected to be the
main picture video.
10
28
Sync Out
Outputs the video signal selected as the PIP to be filtered and applied
to the H and V timebase through the Sync In pin.
28
29
Sync In
PIP sync pulses are externally filtered and applied to the H and V
timebase to allow H and V synchronization.
29
30
Multi Test
2
Under control of I C bus output signals for test and adjustment are
provided through this pin.
30
10 k
31
H PLL
Connection for horizontal timebase PLL filter. See separate discussion
for filter values.
31
0.1
4.7
µF
2.2 k
Pins 11 to 13, 16 to 27, 55 and 56 are test pins configured as outputs in a high impedance state. In an application, no connection should be made to these pins.
6
MOTOROLA ANALOG IC DEVICE DATA
MC44460
PIN FUNCTION DESCRIPTION (continued)
Pin
Equivalent Internal Circuit
Description
32
503 kHz Resonator
Single pin oscillator is used as the main timebase reference. It is phase
locked to the PIP H sync pulses. This oscillator provides the reference
to the system logic, PIP decoder and vertical timebase circuitry.
32
503 kHz
1000
33
Filter PLL
The on board reference filter produces a phase shift which is
measured and applied to an internal filter PLL. This capacitor
connected to this pin stores the phase correction voltage for the PLL
which sets the 90° phase correction reference for the rest of the on
chip filters.
33
0.1
36 and 34
Video Input 1 and 2
Accepts ac coupled 1.0 Vpp composite video input usually from a
source generated inside the TV and an external video source.
Composite
Video
The series coupling capacitor also functions as the storage capacitor
for the clamp voltage for the input circuit. It is necessary to return the
input of this capacitor to ground through a dc low impedance to enable
this clamp function. R = 50 to 100 Ω is acceptable.
2.0 k
0.1
R
19 k
37
Decoder ACC
The Decoder ACC pin provides access to the internal chroma decoder
automatic gain control amplifier. The ACC capacitor filters the feedback
loop of this amplifier.
During PIP burst gate time a voltage proportional to the burst gate
magnitude is stored on the capacitor connected to this pin to
compensate for input chroma level variation and provide a constant
U and V output level to the A/D conversion stage.
37
0.22
38
Decoder Crystal
4X Sub–Carrier crystal used to synchronize the decoding of the PIP
UV information prior to A/D conversion, sub–sampling and storage in
the field memory.
The crystal frequency is 14.31818 MHz.
38
14.3 MHz
18
Pins 11 to 13, 16 to 27, 55 and 56 are test pins configured as outputs in a high impedance state. In an application, no connection should be made to these pins.
7
MOTOROLA ANALOG IC DEVICE DATA
MC44460
PIN FUNCTION DESCRIPTION (continued)
Pin
Equivalent Internal Circuit
Description
39
Decoder PLL
Connection for Decoder PLL filter. See separate discussion for filter
values.
39
2700
0.068
68 k
44
45
46
Encoder Phase
Phase difference of the main to encoded burst is sampled and applied
to the capacitor connected to this pin to shift the phase of the
re–encoded chrominance to match the main.
44
0.01
2.0 k
Encoder ACC
The Encoder ACC pin provides access to the internal chroma
reference sample and hold circuit, which stores the sampled value of
the main channel chroma burst amplitude on this external ACC
capacitor. The ACC amplifier matches the chroma amplitude of the
insert picture to that of the main picture.
45
0.01
Encoder PLL
Connection for Encoder PLL filter. See separate discussion for filter
values.
46
1000
1.0 µF
18 k
47
Encoder Crystal
4X Sub–Carrier crystal used to synchronize the encoding of the PIP
YUV from the field memory with the main video. The output from this
PLL is phase corrected to match the PIP video signal to the main video
at the PIP switch.
38
The crystal frequency is 14.31818 MHz.
14.3 MHz
18
Pins 11 to 13, 16 to 27, 55 and 56 are test pins configured as outputs in a high impedance state. In an application, no connection should be made to these pins.
8
MOTOROLA ANALOG IC DEVICE DATA
MC44460
PIN FUNCTION DESCRIPTION (continued)
Pin
Equivalent Internal Circuit
Description
49
Video Out
The selected Video 1/2 input is available at the Video Out mixed with
the PIP overlay when selected. This signal is a nominal 2.0 V
peak–to–peak signal unterminated. This connection is intended to
drive an external series 75 Ω load into a 75 Ω termination to ground to
provide a 1.0 Vpp signal at the termination.
49
4.8 k
75
Composite
Video
51
ADC Mid Reference
The mid–point of the A/D converter reference divider network is
brought out on this pin in order to add a filter capacitor to remove any
noise in the network.
51
0.1
54, 53, 52,
42, 41, 40
Encoder and Decoder YUV Caps
During the internal H rate clamping time the YUV reference levels are
set by the charge on the capacitors attached to these pins. The
nominal value of these capacitors should be 0.01 µF.
45
0.01
Pins 11 to 13, 16 to 27, 55 and 56 are test pins configured as outputs in a high impedance state. In an application, no connection should be made to these pins.
2
Figure 1. I C Data Transfer
MSB
1
MSB
2
7
8
9
1
2
7
8
9
ACK
ACK
Start
Condition
Stop
Condition
S
Slave Address
R/
A
Data
A
Data
A
P
W
Data Transferred
(n Bytes + Acknowledge)
A = Acknowledge
S = Start
P = Stop
9
MOTOROLA ANALOG IC DEVICE DATA
MC44460
2
I C REGISTER DESCRIPTIONS
Base read address = 24h
Base write address = 25h
Test Mode/Main Vertical and Horizontal Polarity Register
Sub–address = 03h
Internal Test Mode Register (ITM0–2) – D0–D2
Sets the Multi Test Pin output to provide one of several
internal signals for test and production alignment. Also
controls the test memory address counter.
Read Register
There are two active bits in the single read byte available
from the MC44460 as follows:
Write Vertical Indicator (WVI0) – D7
ITM (2:0)
000
Multi–Test I/O and Function
Input – Analog Test mode
Input – Digital Test mode
Output – Multi Sync Detect
Output – Multi PIP Switch
Output – Multi PIP H Detect
Output – Multi PIP V Detect
Output – Multi PIP Clamp
Output – Multi Main Clamp
When 0 indicates that the write operation specified by the
2
last I C command has been completed.
PIP Sync Detect Bit (PSD0) – D1
001
When 0 indicates that the PIP video H pulses are present
and the horizontal timebase oscillator is within acceptable
limits.
010
011
100
Write Registers
101
Read Start Position/Write Start Position Registers
Sub–address = 00h
110
111
Write Raster Position Start Bits (WPS0–2) – D0–D2
Establishes the horizontal beginning of the PIP and its
black level measurement gate. This beginning may be varied
by approximately 3.0 µs. The position of this pulse may be
observed through the Multi Test Pin 30 (See Test Mode
Register Sub–address 03h).
Main vertical polarity select bit (MVP0) – D6
Selects polarity of active level of vertical reference input.
0 = positive going, 1 = negative going.
Main horizontal polarity select bit (MHP0) – D7
Selects polarity of active level of horizontal reference
input. 0 = positive going, 1 = negative going.
Read Raster Position Bits (RPS0–3) – D4–D7
Establishes the clamp gate position for the black level
reference for the main picture. This position may be varied by
approximately 5.0 µs. The position of this pulse may be
observed through the Multi Test Pin 30 (See Test Mode
Register Sub–address 03h).
PIP Freeze/PIP Size/Main and PIP Video Source Register
Sub–address = 04h
PIP Freeze Bit (STIL0) – D4
When set to one, the most recently received field is
continuously displayed until the freeze bit is cleared.
Pip Switch Delay/Vertical Filter Register
Sub–address = 01h
PIP Size Bit (PSI90) – D5
Switches the PIP size between 1/16 main size (when 0)
and 1/9 main size (when 1).
PIP Switch Delay Bits (PSD0–3) – D0–D3
Delays the start of PIP on time relative to the PIP picture.
These bits are used to center the PIP border and PIP picture
in the horizontal direction.
Main Video Source Select Bit (MSEL0) – D6
Selects which video input will be applied to the PIP switch
as the main video out.
Vertical Filter Bit (VFON) – D4
PIP Video Source Select Bit (PSEL0) – D7
Selects which video input will be applied to the video
decoder to provide the PIP video.
When the filter is activated (VFON = 1) a three line
weighted average is taken to provide the data stored in the
field memory.
Border Color Register
MSEL/PSEL
Function
Sub–address = 02h
0
Video 1 Input to Main/
Video 1 Input to PIP
Border Color Bits (BC0–2) – D0–D2
These Bits control the color of the border. Note that when
using one of the saturated border colors it is possible to get
objectionable dot crawl at the edge of the border in some TVs
unless appropriate comb filtering is used in the TV circuitry.
1
Video 2 Input to Main/
Video 2 Input to PIP
PIP On/PIP Blank Register
Sub–address = 05h
BC (2:0)
000
Border Color
PIP On Bit (PON0) – D0
Black
When on (1) turns the PIP on.
001
White 70%
No Border (clear)
No Border (clear)
Blue
PIP Blanking Bit (PBL0) – D4
When on (1) sets the PIP to black. If the PIP is off, then it
will be black if it is turned on. Overrides all other settings of
the PIP control.
010
011
100
PIP X Position Register
Sub–address = 06h
101
Green
X Position Bits (XPS0–5) – D0–D5
Moves the PIP start position from the left to the right
edge of the display in 64 steps. There is protection circuitry
110
Red
111
White
10
MOTOROLA ANALOG IC DEVICE DATA
MC44460
to prevent the PIP from interfering with the main picture
sync pulses.
are matched. In addition to this, the tint of the PIP can be
varied ±10° in a total of 64 steps by changing the value of
these bits to suit viewer preference.
PIP Y Position Register
Sub–address = 07h
PIP Luma Delay Register
Sub–address = 0Ah
Y Position Bits (YPS0–5) – D0–D5
Moves the PIP start position from the top to the bottom
edge of the display in 64 steps. There is protection circuitry to
prevent the PIP from interfering with the main picture sync
pulses.
Y Delay (YDL0–2) – D0–D2
Since the Chroma passes through a bandpass filter and
the color decoder, it is delayed with respect to the Luma
signal. Therefore, to time match the Luma and Chroma these
bits are set to a single value determined to be correct in the
application.
PIP Chroma Level Register
Sub–address = 08h
Chroma (C0–5) – D0–D5
Pip Fill/Test Register
Sub–address = 0Ch
The color of the PIP can be adjusted to suit viewer
preference by setting the value stored in these bits. A total of
64 steps varies the color from no color to maximum. This
control acts in conjunction with the auto phase control.
PIP Fill Bits (PIPFILL0–1) – D0–D1
May be used to fill the PIP with one of three selectable
solid colors
PIP Tint Level Register
Sub–address = 09h
Test Register Bits (INTC0 and MACR0) – D6–D7
Tint (T0–5) – D0–D5
Used for production test only.
An auto phase control compares the main color burst to
the internally generated pseudo color burst so that the tints
2
I C REGISTER TABLE
Data Bit
Sub–
D7
D6
D5
D4
RPS0
VFON
–
D3
D2
WPS2
PSD2
BC2
ITM2
–
D1
WPS1
PSD1
BC1
ITM1
–
D0
WPS0
PSD0
BC0
ITM0
–
address
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
RPS3
RPS2
RPS1
–
–
–
–
PSD3
–
–
–
–
–
MHP0
MVP0
–
–
–
PSEL0
MSEL0
PSI90
–
STIL0
PBL0
XPS4
YPS4
C4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PON0
XPS0
YPS0
C0
XPS5
YPS5
C5
T5
XPS3
YPS3
C3
T3
–
XPS2
YPS2
C2
XPS1
YPS1
C1
T4
T2
T1
T0
–
–
YDL2
–
YDL1
–
YDL0
–
–
–
–
–
–
–
–
–
–
11
MOTOROLA ANALOG IC DEVICE DATA
MC44460
CIRCUIT DESCRIPTION
The MC44460 Picture–in–Picture (PIP) controller is
in the NTSC Decoder is calibrated with respect to burst
magnitude by applying the output of multiplier 1 to the
reference input of the ACC block. The result is U and V
outputs which are 0.6 V ± 0.5 dB for burst amplitudes varying
from –12 dB to 3.0 dB. The second multiplier serves as a
phase detector during color burst to match the 90 degree
output from the XVCO to the 180 degree color burst and feed
a correction current to the PLL filter. The phase is correct
when the two signals are 90 degrees out of phase.
composed of an analog section, logic section and an
8.0 k x 8–bit DRAM array. A block diagram showing details of
all of these sections is shown in the Representative Block
Diagram.
The analog section includes an Input Switch, Sync
Processor, Filters, PLLs, NTSC Decoder, ADC, DACs, NTSC
Encoder and Output Switch. All necessary controls are
provided by registers in the logic section. These registers are
2
set by external control through the I C Bus.
During the H drive time, the output of the multipliers is fed
to the YUV clamp, filtered to 200 KHz and input along with the
Y signal to the multiplexer.
In operation, the MC44460 overlays a single PIP on the
main video in either a 1/9th or 1/16th size. In 1/9th, the PIP is
152 samples (114 Y, 19 V, 19 U) by 70 lines and occupies
8094 bytes of the 8192 byte DRAM. The 1/16 size is 112
samples (84 Y, 14 V, 14 U) by 52 lines and occupies 4452
bytes of the DRAM. An extra line of data is stored for each
PIP size to allow for interlace disorder correction. The 6:1:1
samples are formatted by the logic section as follows in order
to efficiently utilize memory:
The YUV samples are fed through a multiplexer to a single
six bit A/D converter. The A/D is a flash type architecture and
is capable of digitizing at a 20 MHz sample rate. It is
comprised of an internal bandgap source voltage reference,
a 64 tap resistor ladder comparator array, a binary encoder
and output latches. Once the multiplexer has switched,
sufficient time is provided to allow the A/D converter to settle
before the reading is latched. The encoder code is
determined from the values of any comparators which are not
metastable.
Byte 1: Y0(5:0), V(1:0)
Byte 2: Y1(5:0), V(3:2)
Byte 3: Y2(5:0), V(5:4)
Byte 4: Y3(5:0), U(1:0)
Byte 5: Y4(5:0), U(3:2)
Byte 6: Y5(5:0), U(5:4)
The multiplexer and A/D converter receive and convert the
YUV data at a 4F /3 rate for a 1/9th size picture or F
a 1/16th size picture. The samples are taken in the following
way to simplify the control logic:
for
SC
SC
Refer to the block diagram. Both the video inputs are
applied to an input switch which is controlled by the I C bus
Y,V,Y,U,Y,V,Y,U
2
To provide a 6:1:1 format, one of three U and V samples is
saved to memory giving a luminance sample rate of 2F /3
for a 1/9th picture and F /2 for a 1/16 picture. In the vertical
interface. Either of the inputs is applied to the PIP processing
circuitry and either to the main video signal path of the output
switch. The signal applied to the PIP processor also provides
the vertical sync reference to the PIP processor.
The PIP output from the switch is applied to a 1.0 MHz
cutoff low pass GmC biquad filter to extract the luminance
signal and a similar bandpass filter to pass chroma to the
decoder section. These filters are tracked to a master GmC
cell using subcarrier as a reference. A single–ended
transconductance stage with relatively large signal handling
SC
SC
direction, one line of every 3 (1/9th picture) or 4 (1/16th
picture) are saved. In order to avoid objectionable artifacts, a
piece–wise vertical filter is used to take a weighted average
on the luminance samples. For three lines (1/9th size) the
weight is 1/4 + 1/2 + 1/4 and for four lines (1/16 size) it is
1/4 + 1/4 + 1/4 + 1/4. This filter also delays the luma samples
correcting for the longer chroma signal path through the
decoder.
ability (>2.5 Vpp @ 4.5 V V ) is used to avoid potential
CC
Finally the logic incorporates a field generator to
determine the current field in order to correct interlace
disorders arising from a single field memory.
noise problems.
Figure 2. NTSC Decoder
A separate process runs in the logic section to create the
PIP window on the main picture. Control signals are
generated and sent to the memory controller to read data
from the field memory. Data from the eight bit memory are
then de–multiplexed into a six bit YUV format, borders are
added, blanking is generated for the video clamps and sent to
the Y, U and V DACs. Since the PIP display is based on a
data clock, it is important to minimize the main display clock
skew on a line by line basis. Skew is minimized in the
MC44460 by reclocking the display timebase to the nearest
U
V
BG
H
Switching
Color
Killer
PLL
Filter
rising or falling edge of a 16F
clock. This produces a
SC
Mult 1
Mult 2
maximum line to line skew of approximately 8.0 ns which is
not perceptible to the viewer. The PIP write logic also
incorporates a field generator for use by the memory
controller for interlace disorder correction. Interlace disorder
can occur when the line order of the two fields of the PIP
image is swapped due to a mismatch with the main picture
field or due to an incomplete field being displayed from
memory. The main and PIP field generators, along with
monitoring, when the PIP read address passes the PIP write
XVCO/
Divide
In
ACC
90°
0°
The NTSC Decoder (Figure 2) consists of two multipliers,
a voltage controlled 4 X S/C crystal oscillator/divider,
Automatic Color Control (ACC) block, Color Kill circuit and
necessary switching. During Burst Gate time, the ACC block
12
MOTOROLA ANALOG IC DEVICE DATA
MC44460
2
address, allows the read address to the memory to be
modified to correct for interlace disorder.
set through the I C bus to provide a variable tint. Saturation is
controlled by varying a register which sets the reference
2
The read logic can provide various border colors: black,
75% white (light gray), 50% white (medium gray), red, green,
blue or transparent (no border). In a system without an
adaptive comb filter, borders which contain no chroma give
the best results. Also built into the read logic is a PIP fill mode
which allows the PIP window to be filled with either a solid
green, blue or red color as an aid in aligning the PIP analog
color circuitry.
Because the DAC output video will be referenced during
back porch time, the read processor zeroes the luminance
value and sets the bipolar U and V values to mid–range
during periods outside the PIP window to ensure clamping at
correct levels. Since the PIP window is positioned relative to
the main picture’s vertical and horizontal sync, a safety
feature turns off the window if the window encroaches upon
the sync period, thus preventing erroneous clamping.
The Y, U and V DACs are all three of the same design. A
binary weighted current source is used, split into two, three
bit levels. In the three most significant bits, the current
sources are cascaded to improve the matching to the three
least significant current sources. Analog transmission gates,
switched by the bi–phase outputs of the data latches, feed
the binary currents to the single ended current mirror. The
output current is subsequently clamped and filtered for
processing buy the NTSC Encoder.
voltage to the U and V DACs. This is also under I C bus
control. By oversampling the U and V DACs, it was possible
to use identical post–DAC filtering for Y, U and V, thereby
reducing the delay inequalities between Y and UV and also
simplifying the design. After filtering, the U and V signals are
clamped to an internal reference voltage during horizontal
blanking periods and fed to the U and V modulators. In the
NTSC Decoder, the Y, U and V signals were scaled to use the
entire A/D range. Gain through the NTSC Encoder is set to
properly match these amplitudes.
The phase of the re–encoded chrominance must match
that of the incoming main video signal at the input to the PIP
switch, so a separate first order PLL is placed within the loop
of the main video signal burst PLL. The first order PLL
compares the phase of the main burst with that of the
encoded burst and moves the oscillator phase so that they
match. A special phase shift circuit allowing a continuous
range of 180° was developed to do this.
The amplitude of the re–encoded chrominance signal
must also match that of the main video signal. To do this, a
synchronous amplitude comparator looks at both burst
signals and adjusts the chrominance amplitude in the
modulator section of the NTSC encoder. The Y signal from
the YDAC is compared to the main video signal at black level
during back porch time and clamped to this same black level
voltage. The PIP chrominance and luminance are then
added together and fed to the PIP output switch through a
buffered output.
The outputs of the U and V DACS are buffered and burst
flag pulses added to both signals. The U burst flag is fixed to
generate a –180° color burst at the modulator output. The V
burst flag is variable under the control of an internal register
13
MOTOROLA ANALOG IC DEVICE DATA
MC44460
Figure 3. Application Circuit
Horiz In
Vert In
I C Ser Cl
2
2
I C Ser Data
0.01
0.01
1
56
H
MC44460
N/C
N/C
in
22.8 k
2
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
V
5.0 V
in
3
SCL
Encoder V Cap
Encoder U Cap
Endoder Y Cap
ADC Mid Ref
0.01
0.22
12.1 k
100
4
SDA
Reset
0.01
0.1
5
120
120
6
I
5.0 V
ref
10 µF
7
16 F
Filter
Video Out V
CC
SC
(dig)
75
8
V
Video Out
Analog Gnd
Video Out
DD
SS
1000
100
0.01
9
V
(dig)
1.0
µ
F
18 k
5.0 V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Video 1/2 Select
Encoder Xtal
Encoder PLL
Encoder ACC
Encoder Phase
10 µF
18
X3
N/C
N/C
N/C
1000
Video 1/2
Select Out
0.01
0.01
5.0 V
2700
0.068
V
V
(mem)
(mem)
Analog V
CC
5.0 V
DD
0.01
10
µ
F
Decoder V Cap
Decoder U Cap
Decoder Y Cap
Decoder PLL
Decoder Xtal
Decoder ACC
Video In 1
10
µ
F
0.01
SS
0.01
0.01
0.01
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
68 k
18
0.22
X2
Video 1
0.1
Analog Gnd
Video In 2
Video 2
0.1
0.01
Filter PLL
503 kHz Resonator
H PLL
75
75
X1
1000
Multi Test
Sync Out
Sync In
2.2 k
0.1
4.7 µF
330
2200
4.7 µF
62 k
X1 – 503 kHz– Murata Erie CSB503F2 or equivalent
X2 – 14.31818 MHz – Fox 143–20 or equivalent
X3 – 14.31818 MHz – Fox 143–20 or equivalent
NOTE: For proper noise isolation, Power Supply Pins 8, 14, 43 and 50 should be bypassed by both high and low
frequency capacitors. As a guideline, a 10 µF in parallel with a 0.1 µF at each supply pin is recommended.
14
MOTOROLA ANALOG IC DEVICE DATA
MC44460
OUTLINE DIMENSIONS
B SUFFIX
PLASTIC PACKAGE
CASE 859–01
(SDIP)
ISSUE O
NOTES:
1. DIMENSIONS AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
-A-
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH. MAXIMUM MOLD FLASH 0.25 (0.010).
56
29
INCHES
MILLIMETERS
DIM
A
B
C
D
E
MIN
MAX
2.065
0.560
0.200
0.022
MIN
51.69
13.72
3.94
0.36
0.89 BSC
MAX
52.45
14.22
5.08
-B-
2.035
0.540
0.155
0.014
1
28
L
0.56
0.035 BSC
F
0.032
0.070 BSC
0.300 BSC
0.008
0.115
0.046
0.81
1.778 BSC
7.62 BSC
0.20
2.92
1.17
H
G
H
J
K
L
C
0.015
0.135
0.38
3.43
0.600 BSC
15
0.040
15.24 BSC
15
0.51 1.02
-T-
SEATING
PLANE
M
N
0°
°
0°
°
K
0.020
N
G
M
F
E
D 56 PL
J 56 PL
M
S
M
S
B
0.25 (0.010)
T
A
0.25 (0.010)
T
15
MOTOROLA ANALOG IC DEVICE DATA
MC44460
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