MC54HC163AJ [MOTOROLA]
Presettable Counters; 可预置计数器
| 型号： | MC54HC163AJ |
| 厂家： | 
MOTOROLA |
| 描述： | Presettable Counters |
| 文件： | 总14页 (文件大小：155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
High–Performance Silicon–Gate CMOS
The MC54/74HC161A and HCI63A are identical in pinout to the LS161
and LS163. The device inputs are compatible with standard CMOS outputs;
with pullup resistors, they are compatible with LSTTL outputs.
The HC161A and HC163A are programmable 4–bit binary counters with
asynchronous and synchronous reset, respectively.
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
16
1
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
Low Input Current: 1.0 µA
16
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
•
Chip Complexity: 192 FETs or 48 Equivalent Gates
16
1
LOGIC DIAGRAM
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
Ceramic
Plastic
SOIC
3
4
5
6
14
13
12
11
Q0
Q1
Q2
Q3
P0
P1
P2
P3
PRESET
DATA
INPUTS
BCD OR
BINARY
OUTPUT
PIN ASSIGNMENT
RIPPLE
CARRY
OUT
RESET
1
2
16
15
V
CC
2
15
CLOCK
RIPPLE
CARRY OUT
CLOCK
3
4
14
13
P0
P1
P2
P3
Q0
Q1
Q2
1
9
RESET
LOAD
5
6
12
11
Q3
7
ENABLE P
ENABLE T
COUNT
ENABLES
ENABLE T
LOAD
7
8
10
9
PIN 16 = V
CC
PIN 8 = GND
ENABLE P
GND
10
Count
Mode
FUNCTION TABLE
Device
Reset Mode
Inputs
Clock Reset* Load Enable P Enable T
Output
Q
HC161A
HC163A
Binary
Binary
Asynchronous
Synchronous
L
X
L
X
X
H
L
X
X
H
X
L
Reset
Load Preset Data
Count
H
H
H
H
H
H
H
No Count
No Count
X
* HC163A only. HC161A is an Asynchronous Reset Device
H = high level
L = low level
X = don’t care
10/95
Motorola, Inc. 1995
REV 6
MC54/74HC161A MC54/74HC163A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
CC
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
V
in
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 1.5 to V
+ 1.5
V
CC
V
out
– 0.5 to V
+ 0.5
V
CC
I
in
± 20
mA
mA
mA
mW
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
± 25
± 50
out
V
should be constrained to the
out
DC Supply Current, V
CC
and GND Pins
range GND (V or V
)
V
CC
.
CC
in out
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
750
500
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
stg
Storage Temperature
– 65 to + 150
C
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)
260
300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
Ceramic DIP: – 10 mW/ C from 100 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
6.0
V , V
in out
V
CC
V
T
A
– 55 + 125
C
t , t
r f
Input Rise and Fall Time (Figure 1)
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
Symbol
Parameter
Test Conditions
25 C
Unit
85 C
125 C
V
IH
Minimum High–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
out
CC
|I
|
20 µA
out
V
Maximum Low–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
2.0
4.5
6.0
0.50
1.35
1.80
0.50
1.35
1.80
0.50
1.35
1.80
V
V
IL
out
CC
|I
|
20 µA
out
V
|I
= V or V
IH IL
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
OH
Minimum High–Level Output
Voltage
in
out
|
20 µA
V
= V or V
|I
|I
|
|
4.0 mA
5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
V
V
in
IH
IL out
out
V
in
|I
= V or V
IH
2.0
4.5
6.0
0.10
0.10
0.10
0.10
0.10
0.10
0.10
0.10
0.10
V
OL
Maximum Low–Level Output
Voltage
IL
|
20 µA
out
V
= V or V
|I
|I
|
|
4.0 mA
5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
V
in
in
IH IL out
out
I
in
Maximum Input Leakage Current
V
V
= V
= V
or GND
6.0
6.0
± 0.1
± 1.0
± 1.0
µA
µA
CC
I
Maximum Quiescent Supply
Current (per Package)
or GND
4
40
160
CC
in
CC
I
= 0 µA
out
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
3–2
MC54/74HC161A MC54/74HC163A
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns)
L
r
f
Guaranteed Limit
V
CC
V
– 55 to
25 C
Symbol
Parameter
Fig.
Unit
85 C
125 C
f
Maximum Clock Frequency (50% Duty Cycle)*
1, 7
2.0
4.5
6.0
6
30
35
5
24
28
4
20
24
MHz
max
PLH
PHL
PHL
PLH
PHL
PLH
PHL
PHL
t
t
t
t
t
t
t
t
Maximum Propagation Delay, Clock to Q
1, 7
1, 7
2, 7
3, 7
3, 7
1, 7
1, 7
2, 7
2, 7
1, 7
2.0
4.5
6.0
120
20
16
160
23
20
200
28
22
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
2.0
4.5
6.0
145
22
18
185
25
20
320
30
23
Maximum Propagation Delay, Reset to Q (HC161A Only)
2.0
4.5
6.0
145
20
17
185
22
19
220
25
21
Maximum Propagation Delay, Enable T to Ripple Carry Out
2.0
4.5
6.0
110
16
14
150
18
15
190
20
17
2.0
4.5
6.0
135
18
15
175
20
16
210
22
20
Maximum Propagation Delay, Clock to Ripple Carry Out
2.0
4.5
6.0
120
22
18
160
27
22
200
30
25
2.0
4.5
6.0
145
22
20
185
28
24
220
35
28
Maximum Propagation Delay, Reset to Ripple Carry Out
(HC161A Only)
2.0
4.5
6.0
155
22
18
190
26
22
230
30
25
t
t
,
Maximum Output Transition Time, Any Output
Maximum Input Capacitance
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
TLH
THL
C
—
10
10
10
in
* Applies to noncascaded/nonsynchronous clocked configurations only with synchronously cascaded counters. (1) Clock to Ripple Carry Out
propagation delays. (2) Enable T or Enable P to Clock setup times and (3) Clock to Enable T or Enable P hold times determine f . However,
max
in the table above is applicable. See
if Ripple Carry out of each stage is tied to the Clock of the next stage (nonsynchronously clocked) the f
Applications information in this data sheet.
max
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
= 5.0 V
CC
C
Power Dissipation Capacitance (Per Gate)*
pF
30
PD
2
* Used to determine the no–load dynamic power consumption: P = C
D
Motorola High–Speed CMOS Data Book (DL129/D).
V
f + I
V
. For load considerations, see Chapter 2 of the
PD CC
CC CC
3–3
MOTOROLA
MC54/74HC161A MC54/74HC163A
TIMING REQUIREMENTS (C = 50 pF, Input t = t = 6.0 ns)
L
r
f
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Fig.
Unit
85 C
125 C
t
t
t
t
Minimum Setup Time,
Preset Data Inputs to Clock
5
2.0
4.5
6.0
40
15
12
60
20
18
80
30
20
ns
su
su
su
su
Minimum Setup Time,
Load to Clock
5
4
6
5
4
6
2
5
1
2
2.0
4.5
6.0
60
15
12
75
20
18
90
30
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Minimum Setup Time,
Reset to Clock (HC163A Only)
2.0
4.5
6.0
60
20
17
75
25
23
90
35
25
Minimum Setup Time,
Enable T or Enable P to Clock
2.0
4.5
6.0
80
20
17
95
25
23
110
35
25
t
t
t
Minimum Hold Time,
Clock to Load or Preset Data Inputs
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
h
h
h
Minimum Hold Time,
Clock to Reset (HC163A Only)
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
Minimum Hold Time,
Clock to Enable T or Enable P
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
t
t
Minimum Recovery Time,
Reset Inactive to Clock (HC161A Only)
2.0
4.5
6.0
80
15
12
95
20
17
110
26
23
rec
rec
Minimum Recovery Time,
Load Inactive to Clock
2.0
4.5
6.0
80
15
12
95
20
17
110
26
23
t
t
Minimum Pulse Width,
Clock
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
w
w
Minimum Pulse Width,
Reset (HC161A Only)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
t , t
r f
Maximum Input Rise and Fall Times
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
MOTOROLA
3–4
MC54/74HC161A MC54/74HC163A
FUNCTION DESCRIPTION
The HC161A/163A are programmable 4–bit synchronous
CONTROL FUNCTIONS
counters that feature parallel Load, synchronous or asynch-
ronous Reset, a Carry Output for cascading and count–
enable controls.
The HC161A and HC163A are binary counters with
asynchronous Reset and synchronous Reset, respectively.
Resetting
A low level on the Reset pin (Pin 1) resets the internal flip–
flops and sets the outputs (Q0 through Q3) to a low level.
The HC161A resets asynchronously, and the HC163A resets
with the rising edge of the Clock input (synchronous reset).
INPUTS
Loading
With the rising edge of the Clock, a low level on Load (Pin
9) loads the data from the Preset Data input pins (P0, P1, P2,
P3) into the internal flip–flops and onto the output pins, Q0
through Q3. The count function is disabled as long as Load is
low.
Clock (Pin 2)
The internal flip–flops toggle and the output count ad-
vances with the rising edge of the Clock input. In addition,
control functions, such as resetting and loading occur with
the rising edge of the Clock input.
Count Enable/Disable
These devices have two count–enable control pins: En-
able P (Pin 7) and Enable T (Pin 10). The devices count
when these two pins and the Load pin are high. The logic
equation is:
Preset Data Inputs P0, P1, P2, P3 (Pins 3, 4, 5, 6)
These are the data inputs for programmable counting.
Data on these pins may be synchronously loaded into the in-
ternal flip–flops and appear at the counter outputs. P0 (Pin 3)
is the least–significant bit and P3 (Pin 6) is the most–signifi-
cant bit.
Count Enable = Enable P • Enable T • Load
The count is either enabled or disabled by the control in-
puts according to Table 1. In general, Enable P is a count–
enable control: Enable T is both a count–enable and a
Ripple–Carry Output control.
OUTPUTS
Q0, Q1, Q2, Q3 (Pins 14, 13, 12, 11)
Table 1. Count Enable/Disable
These are the counter outputs. Q0 (Pin 14) is the least–
significant bit and Q3 (Pin 11) is the most–significant bit.
Control Inputs
Result at Outputs
Load Enable P Enable T Q0 – Q3
Ripple Carry Out
Ripple Carry Out (Pin 15)
H
L
H
H
L
H
H
H
Count
High when Q0–Q3
are maximum*
When the counter is in its maximum state 1111, this output
goes high, providing an external look–ahead carry pulse that
may be used to enable successive cascaded counters. Rip-
ple Carry Out remains high only during the maximum count
state. The logic equation for this output is:
No Count
X
No Count High when Q0–Q3
are maximum*
X
X
L
No Count
L
Ripple Carry Out = Enable T • Q0 • Q1 • Q2 • Q3
* Q0 through Q3 are maximum when Q3 Q2 Q1 Q0 = 1111.
OUTPUT STATE DIAGRAMS
0
1
2
3
4
5
6
7
8
15
14
13
12
11
10
9
Binary Counters
3–5
MOTOROLA
MC54/74HC161A MC54/74HC163A
SWITCHING WAVEFORMS
t
t
t
f
w
r
V
V
CC
CC
90%
CLOCK
50%
RESET
50%
10%
GND
GND
t
PHL
t
w
1/fmax
50%
ANY
OUTPUT
t
t
PHL
PLH
90%
50%
10%
t
rec
ANY
OUTPUT
V
CC
50%
CLOCK
t
t
THL
TLH
GND
Figure 1.
Figure 2.
t
t
f
r
V
CC
50%
RESET
CLOCK
90%
50%
10%
ENABLE T
GND
t
t
t
t
PHL
h
su
PLH
90%
50%
10%
RIPPLE
CARRY
OUT
V
CC
50%
GND
t
t
THL
TLH
Figure 3.
Figure 4. HC163A Only
VALID
INPUTS
P0, P1,
P2, P3
V
CC
50%
GND
t
t
t
su
h
VALID
50%
V
CC
ENABLE T
OR
ENABLE P
V
50%
CC
LOAD
GND
GND
t
t
t
t
su
h
rec
su
h
V
CC
V
CC
50%
CLOCK
CLOCK
50%
GND
GND
Figure 5.
Figure 6.
TEST CIRCUIT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
C *
L
* Includes all probe and jig capacitance
Figure 7.
MOTOROLA
3–6
MC54/74HC161A MC54/74HC163A
Figure 8. 4–Bit Binary Counter with Asynchronous Reset
(MC54/74HC161A)
3–7
MOTOROLA
MC54/74HC161A MC54/74HC163A
Sequence illustrated in waveforms:
1. Reset outputs to zero.
2. Preset to binary twelve.
3. Count to thirteen, fourteen, fifteen, zero, one and two.
4. Inhibit.
RESET (HC161A)
RESET (HC163A)
LOAD
(ASYNCHRONOUS)
(SYNCHRONOUS)
P0
PRESET
DATA
INPUTS
P1
P2
P3
CLOCK (HC161A)
CLOCK (HC163A)
ENABLE P
COUNT
ENABLES
ENABLE T
Q0
Q1
OUTPUTS
Q2
Q3
RIPPLE
CARRY
OUT
12
13 14 15
0
1
2
COUNT
INHIBIT
RESET
LOAD
Figure 9. Timing Diagram
MOTOROLA
3–8
MC54/74HC161A MC54/74HC163A
Figure 10. 4–Bit Binary Counter with Synchronous Reset
(MC54/74HC163A)
3–9
MOTOROLA
MC54/74HC161A MC54/74HC163A
TYPICAL APPLICATIONS CASCADING
LOAD
INPUTS
INPUTS
INPUTS
LOAD P0 P1 P2 P3
LOAD P0 P1 P2 P3
LOAD P0 P1 P2 P3
H = COUNT
L = DISABLE
ENABLE P
RIPPLE
ENABLE P
RIPPLE
ENABLE P
RIPPLE
TO
MORE
SIGNIFICANT
STAGES
H = COUNT
L = DISABLE
ENABLE T
CARRY
OUT
ENABLE T
CARRY
OUT
ENABLE T
CARRY
OUT
CLOCK
CLOCK
CLOCK
Q3
R
Q0 Q1 Q2
R
Q0 Q1 Q2 Q3
OUTPUTS
R
Q0 Q1 Q2 Q3
RESET
CLOCK
OUTPUTS
OUTPUTS
NOTE: When used in these cascaded configurations the clock f
guaranteed limits may not apply. Actual performance will depend on
max
number of stages. This limitation is due to set up times between Enable (Port) and Clock.
Figure 11. N–Bit Synchronous Counters
INPUTS
INPUTS
INPUTS
LOAD
ENABLE P
ENABLE T
LOAD P0 P1 P2 P3
LOAD P0 P1 P2 P3
LOAD P0 P1 P2 P3
ENABLE P
RIPPLE
ENABLE P
RIPPLE
ENABLE P
RIPPLE
TO
MORE
SIGNIFICANT
STAGES
ENABLE T
CARRY
OUT
ENABLE T
CARRY
OUT
ENABLE T
CARRY
OUT
CLOCK
RESET
CLOCK
CLOCK
CLOCK
R
Q0 Q1 Q2 Q3
R
Q0 Q1 Q2 Q3
R
Q0 Q1 Q2 Q3
OUTPUTS
OUTPUTS
OUTPUTS
Figure 12. Nibble Ripple Counter
MOTOROLA
3–10
MC54/74HC161A MC54/74HC163A
TYPICAL APPLICATIONS VARYING THE MODULUS
HC163A
OTHER
HC163A
OTHER
Q0
Q1
Q0
Q1
Q2
Q3
OPTIONAL BUFFER
FOR NOISE REJECTION
OPTIONAL BUFFER
FOR NOISE REJECTION
INPUTS
INPUTS
Q2
Q3
OUTPUT
OUTPUT
RESET
RESET
Figure 13. Modulo–5 Counter
Figure 14. Modulo–11 Counter
The HC163A facilitates designing counters of any modulus with minimal external logic. The output is glitch–free due to the
synchronous Reset.
3–11
MOTOROLA
MC54/74HC161A MC54/74HC163A
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
ISSUE V
–A
–
NOTES:
16
1
9
8
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
–B
–
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY.
L
C
INCHES
MILLIMETERS
DIM
A
B
C
D
E
MIN
MAX
0.785
0.295
0.200
0.020
MIN
19.05
6.10
—
0.39
1.27 BSC
MAX
19.93
7.49
5.08
0.50
0.750
0.240
—
0.015
0.050 BSC
–T
SEAT
–
ING
N
K
PLANE
F
G
J
K
L
M
N
0.055
0.100 BSC
0.008
0.125
0.065
1.40
2.54 BSC
0.21
3.18
1.65
E
M
0.015
0.170
0.38
4.31
J 16 PL
F
G
0.300 BSC
15
0.040
7.62 BSC
15
1.01
0.51
M
S
0.25 (0.010)
T
B
D 16 PL
°
°
0°
0°
M
S
0.25 (0.010)
T
A
0.020
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A
–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
16
9
B
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
1
8
INCHES
MILLIMETERS
DIM
A
B
C
D
F
G
H
J
K
L
MIN
MAX
0.770
0.270
0.175
0.021
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
F
C
L
0.740
0.250
0.145
0.015
0.040
S
0.070
1.77
SEATING
PLANE
–T
0.100 BSC
0.050 BSC
0.015
0.130
0.305
2.54 BSC
1.27 BSC
0.38
3.30
7.74
–
M
K
0.008
0.110
0.295
0.21
2.80
7.50
H
J
G
D 16 PL
M
S
0°
10°
0°
10°
M
M
0.25 (0.010)
T
A
0.020
0.040
0.51
1.01
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A
–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
9
8
–B
–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
M
0.25 (0.010)
B
1
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
J
MIN
9.80
3.80
1.35
0.35
0.40
MAX
10.00
4.00
1.75
0.49
MIN
MAX
0.393
0.157
0.068
0.019
0.049
0.386
0.150
0.054
0.014
0.016
0.050 BSC
0.008
0.004
F
K
R X 45°
C
1.25
1.27 BSC
–T
0.19
0.10
0.25
0.25
0.009
0.009
J
SEAT
–
ING
M
K
PLANE
D 16 PL
M
P
R
0
5.80
0.25
°
7
6.20
0.50
°
0
°
7°
0.244
0.019
0.229
0.010
M
S
S
0.25 (0.010)
T
B
A
MOTOROLA
3–12
MC54/74HC161A MC54/74HC163A
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