MC68HC08AZ0CFU_技术文档

Freescale Semiconductor, Inc.

MC68HC08AZ0/D

MC68HC08AZ0

Advance Information

June 21, 2000

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Freescale Semiconductor, Inc.

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Freescale Semiconductor, Inc.

List of Sections

List of Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

EBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . 67

System Integration Module (SIM). . . . . . . . . . . . . . . . . . 85

Clock Generator Module (CGM). . . . . . . . . . . . . . . . . 107

Mask Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Break Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Monitor ROM (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Computer Operating Properly Module (COP) . . . . . . 159

Low-Voltage Inhibit (LVI) . . . . . . . . . . . . . . . . . . . . . . . 165

MOTOROLA

MC68HC08AZ0

List of Sections

1

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List of Sections

External Interrupt Module (IRQ) . . . . . . . . . . . . . . . . . . 171

Serial Communications Interface Module (SCI). . . . . 179

Serial Peripheral Interface Module (SPI) . . . . . . . . . . . 217

Timer Interface Module A (TIMA). . . . . . . . . . . . . . . . . 251

Timer Interface Module B (TIMB) . . . . . . . . . . . . . . . . . 277

Programmable Interrupt Timer (PIT). . . . . . . . . . . . . . . 299

Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . 307

Keyboard Module (KB) . . . . . . . . . . . . . . . . . . . . . . . . . 319

I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

msCAN08 Controller (msCAN08). . . . . . . . . . . . . . . . . 351

Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427

Literature Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

MC68HC08AZ0

2

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MOTOROLA

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Table of Contents

List of Sections

Table of Contents

General Description

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Memory Map

RAM

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

I/O section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

EBI

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Module I/O signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Externally controlled WAIT states . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

EBI control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

EEPROM

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Future EEPROM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Central Processor

Unit (CPU)

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

MC68HC08AZ0

MOTOROLA

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3

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Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Arithmetic/logic unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

CPU during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

System Integration

Module (SIM)

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

SIM bus clock control and generation . . . . . . . . . . . . . . . . . . . . . . . . .88

Reset and system initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

SIM counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

Exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

Break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

SIM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

Clock Generator

Module (CGM)

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

CGM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

Special modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

CGM during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

Acquisition/lock time specifications . . . . . . . . . . . . . . . . . . . . . . . . . .130

Mask Options

Break Module

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

MC68HC08AZ0 options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140

Break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

MC68HC08AZ0

4

Table of Contents

MOTOROLA

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Table of Contents

Monitor ROM

(MON)

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Computer

Operating Properly

Module (COP)

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

COP Control register (COPCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

COP module during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . 164

Low-Voltage Inhibit

(LVI)

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

LVI Status Register (LVISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

LVI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

External Interrupt

Module (IRQ)

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

IRQ module during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . 176

IRQ status and control register (ISCR) . . . . . . . . . . . . . . . . . . . . . . 176

Serial

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

SCI during break module interrupts . . . . . . . . . . . . . . . . . . . . . . . . 198

I/O signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

I/O registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Communications

Interface Module

(SCI)

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Serial Peripheral

Interface Module

(SPI)

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218

Pin name conventions and I/O register addresses . . . . . . . . . . . . . .219

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220

Transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225

Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234

Queuing transmission data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235

Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238

SPI during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239

I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240

I/O registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243

Timer Interface

Module A (TIMA)

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263

TIMA during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264

I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265

I/O registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266

Timer Interface

Module B (TIMB)

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287

TIMB during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288

I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289

I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290

Programmable

Interrupt Timer

(PIT)

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300

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Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

PIT during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

I/O registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

Analog-to-Digital

Converter (ADC)

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

I/O signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

I/O registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

Keyboard Module

(KB)

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

Keyboard module during break interrupts . . . . . . . . . . . . . . . . . . . . 325

I/O Ports

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334

Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340

Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344

Port G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

Port H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

msCAN08

Controller

(msCAN08)

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353

External pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354

Message storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355

Identifier acceptance filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

Protocol violation protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

MC68HC08AZ0

MOTOROLA

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Table of Contents

Timer link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .370

Clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371

Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374

Programmer’s model of message storage . . . . . . . . . . . . . . . . . . . .375

Programmer’s model of control registers . . . . . . . . . . . . . . . . . . . . .380

Specifications

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397

Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .398

Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399

Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399

5.0 Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . .400

Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .401

ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .402

5.0 vdc ± 0.5v Serial Peripheral Interface (SPI) Timing . . . . . . . . . .403

CGM Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .406

CGM Component Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .406

CGM Acquisition/Lock Time Information . . . . . . . . . . . . . . . . . . . . .407

Timer Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .408

Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .408

EBI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .408

Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .413

Glossary

Index

Literature Updates

Literature Distribution Centers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .437

Customer Focus Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .438

Mfax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .438

Motorola SPS World Marketing World Wide Web Server . . . . . . . . .438

Microcontroller Division’s Web Site . . . . . . . . . . . . . . . . . . . . . . . . .438

MC68HC08AZ0

8

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General Description

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Power supply pins (Vdd and Vss). . . . . . . . . . . . . . . . . . . . . . . . . . 14

Oscillator pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . 14

External reset pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

External interrupt pin (IRQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Analog power supply pin (VDDA) . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Analog ground pin (VSSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Analog ground pin (AVSS/VREFL) . . . . . . . . . . . . . . . . . . . . . . . . . 15

ADC voltage reference pin (VREFH) . . . . . . . . . . . . . . . . . . . . . . . 15

Analog supply pin (VDDAREF). . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Port A input/output (I/O) pins (PTA7–PTA0). . . . . . . . . . . . . . . . . . 15

Port B I/O pins (PTB7/ATD7–PTB0/ATD0). . . . . . . . . . . . . . . . . . . 16

Port C I/O pins (PTC5–PTC0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Port D I/O pins (PTD7–PTD0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Port E I/O pins (PTE7/SPSCK–PTE0/TxD) . . . . . . . . . . . . . . . . . . 16

Port F I/O pins (PTF6–PTF0/TACH2). . . . . . . . . . . . . . . . . . . . . . . 16

Port G I/O pins (PTG2/KBD2–PTG0/KBD0) . . . . . . . . . . . . . . . . . . 16

Port H I/O pins (PTH1/KBD4–PTH0/KBD3) . . . . . . . . . . . . . . . . . . 17

CAN transmit pin (CANTx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

CAN receive pin (CANRx). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

1-gen

MC68HC08AZ0

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General Description

Introduction

The MC68HC08AZ0 is a member of the low-cost, high-performance

M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08

Family is based on the customer-specified integrated circuit (CSIC)

design strategy. All MCUs in the family use the enhanced M68HC08

central processor unit (CPU08) and are available with a variety of

modules, memory sizes and types, and package types.

As of Decenmber 1999, the MC68HC08AZ0 is not recommended for

new designs.

Features

Features of the MC68HC08AZ0 include the following:

• High-performance M68HC08 architecture

• Fully upward-compatible object code with M6805, M146805, and

M68HC05 families

• 8.4MHz internal bus frequency at 85°C

• msCAN Controller (Motorola Scalable CAN) (implementing CAN

2.0b protocol as deﬁned in BOSCH speciﬁcation Sep. 1991)

• Available in 100 QFP package

• 512 bytes of on-chip EEPROM with security feature

• 1K byte of on-chip RAM

• Serial Peripheral Interface (SPI) module

• Serial Communications Interface (SCI) module

• 16-bit timer interface module (TIMA) with four input capture/output

compare channels

• 16-bit timer interface module (TIMB) with two input capture/output

compare channels

• Periodic Interrupt Timer (PIT)

2-gen

MC68HC08AZ0

10

General Description

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General Description

Features

• Clock Generator Module (CGM)

• 8-bit, 8-channel Analog to Digital Convertor module (ADC)

• 5-bit key wakeup port

• System protection features

– Optional Computer Operating Properly (COP) reset

– Low-voltage detection with optional reset

– Illegal opcode detection with optional reset

– Illegal address detection with optional reset

• Low-power design (fully static with STOP and WAIT modes)

• Master reset pin and power-on reset

Features of the CPU08 include the following:

• Enhanced HC05 programming model

• Extensive loop control functions

• 16 addressing modes (8 more than the HC05)

• 16-Bit Index register and stack pointer

• Memory-to-memory data transfers

• Fast 8 × 8 multiply instruction

• Fast 16/8 divide instruction

• Binary-Coded Decimal (BCD) instructions

• Optimization for controller applications

• ‘C’ language support

• External Bus Interface (EBI)

• No on-chip user ROM or mask options

• Available in 100-pin TQFP (Thin Quad Flat Pack) package

Figure 1 shows the structure of the MC68HC08AZ0

3-gen

MC68HC08AZ0

11

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General Description

P T H

P T G

P T A

P T B

P T C

P T D

P T E

P T F

D D R H

D D R G

D D R A

D D R B

D D R C

D D R D

D D R E

D D R F

4-gen

MC68HC08AZ0

12

General Description

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General Description

Pin Assignments

Figure 2 shows the 100 QFP pin assignments.

PTH0/KBD3

1

2

PTC4

75

74

73

72

71

PTD3

PTD2

IRQ

RST

PTF0/TACH2

PTF1/TACH3

PTF2

3

4

A

V

/VREFL

VSS

5

DDAREF

PTD1

PTD0

WSCLK

WEB

70

69

68

6

7

8

9

PTF3

PTF4/TBCH0

67

66

65

E

VDD1

REB

CS1

EDB7 10

11

12

13

EAB0

EAB1

EAB2

CS0

64

63

62

61

60

59

58

57

MC68HC08AZ0

EAB15

EAB14

EAB3 14

EAB4

EAB13

15

EAB5 16

E

VSS3

PTB7/ATD7

E

17

18

VSS1

PTB6/ATD6

PTB5/ATD5

PTB4/ATD4

PTB3/ATD3

PTB2/ATD2

PTB1/ATD1

PTB0/ATD0

CANRx

CANTx 19

PTF5/TBCH1 20

PTF6 21

56

55

54

22

23

PTE0/TxD

PTE1/RxD

53

52

51

24

25

PTE2/TACH0

PTE3/TACH1

PTA7

Figure 2. 100 QFP pin assignments

5-gen

MC68HC08AZ0

13

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General Description

Power supply pins

(V_DDand V_SS)

V_DDand V_SSare the power supply and ground pins. The MCU operates

from a single power supply.

Fast signal transitions on MCU pins place high, short-duration current

demands on the power supply. To prevent noise problems, take special

care to provide power supply bypassing at the MCU as Figure 3. shows.

Place the C1 bypass capacitor as close to the MCU as possible. Use a

high-frequency-response ceramic capacitor for C1. C2 is an optional

bulk current bypass capacitor for use in applications that require the port

pins to source high current levels.

MCU

V_DD

V_SS

C1

0.1 µF

+

C2

V_DD

NOTE: Component values shown

represent typical applications.

Figure 3.Power supply bypassing

V_SSis also the ground for the port output buffers and the ground return

for the serial clock in the serial peripheral interface module (SPI).

NOTE: V_SSmust be grounded for proper MCU operation.

Oscillator pins

(OSC1 and OSC2)

The OSC1 and OSC2 pins are the connections for the on-chip oscillator

circuit. See Clock Generator Module (CGM) on page 107.

External reset pin

(RST)

A ‘0’ on the RST pin forces the MCU to a known start-up state. RST is

bidirectional, allowing a reset of the entire system. It is driven low when

6-gen

MC68HC08AZ0

14

General Description

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General Description

Pin Assignments

any internal reset source is asserted. See

System Integration Module (SIM) on page 85.

External interrupt

pin (IRQ)

IRQ is an asynchronous external interrupt pin. See

External Interrupt Module (IRQ) on page 171.

Analog power

V

is the power supply pin for the clock generator module (CGM).

DDA

supply pin (V

)

DDA

Analoggroundpin

(V

The V

analog ground pin is used only for the ground connections for

SSA

)

the clock generator module (CGM) section of the circuit and should be

decoupled as per the V_SSdigital ground pin. See

SSA

Clock Generator Module (CGM) on page 107.

Analoggroundpin

The A

analog ground pin is used only for the ground connections for

VSS

(A /VREFL)

the analog to digital convertor (ADC) and should be decoupled as per

the VSS digital ground pin.

VSS

ADC voltage

reference pin

(VREFH)

VREFH is the power supply for setting the reference voltage VREFH.

Connect the VREFH pin to a voltage potential<= V

1.5V.

, not less than

DDAREF

Analog supply pin

The V

analog supply pin is used only for the supply connections

DDAREF

(V

)

for the analog to digital convertor (ADC).External filter capacitor pin

(CGMXFC)

DDAREF

CGMXFC is an external filter capacitor connection for the CGM. See

Clock Generator Module (CGM) on page 107.

PortAinput/output

(I/O) pins

PTA7–PTA0 are general-purpose bidirectional I/O port pins. See I/O

Ports on page 327.

(PTA7–PTA0)

7-gen

MC68HC08AZ0

MOTOROLA

General Description

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General Description

Port B I/O pins

(PTB7/ATD7ÐPTB0/

ATD0)

Port B is an 8-bit special function port that shares all eight pins with the

analog to digital convertor (ADC). See

Analog-to-Digital Converter (ADC) on page 307 and I/O Ports on page

327.

Port C I/O pins

(PTC5ÐPTC0)

PTC5–PTC3 and PTC1–PTC0 are general-purpose bidirectional I/O

port pins. PTC2/MCLK is a special function port that shares its pin with

the system clock. See I/O Ports on page 327.

Port D I/O pins

(PTD7ÐPTD0)

Port D is an 8-bit special function port that shares two of its pins with the

timer interface modules (TIMA and TIMB). see

Timer Interface Module A (TIMA) on page 251 and

Timer Interface Module B (TIMB) on page 277. PTD6–PTD0 also

share pins with the analog to digital convertor (ADC) like port A if the

15-channel ADC is selected.

Port E I/O pins

(PTE7/SPSCKÐPTE0/

TxD)

Port E is an 8-bit special function port that shares two of its pins with the

timer interface module (TIMA), four of its pins with the Serial Peripheral

Interface Module (SPI), and two of its pins with the Serial

Communication Interface Module (SCI). See

Serial Communications Interface Module (SCI) on page 179,

Serial Peripheral Interface Module (SPI) on page 217,

Timer Interface Module A (TIMA) on page 251 and I/O Ports on page

327.

Port F I/O pins

(PTF6ÐPTF0/TACH2)

Port F is a 7-bit special function port that shares four of its pins with the

timer interface modules. SeeTimer Interface Module A (TIMA) on

page 251, Timer Interface Module B (TIMB) on page 277 and I/O

Ports on page 327.

Port G I/O pins

(PTG2/KBD2ÐPTG0

/KBD0)

PTG2/KBD2–PTG0/KBD0 are general-purpose bidirectional I/O pins

with Key Wakeup feature. See Keyboard Module (KB) on page 319

and I/O Ports on page 327.

8-gen

MC68HC08AZ0

16

General Description

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General Description

Pin Assignments

Port H I/O pins

(PTH1/KBD4ÐPTH0/

KBD3)

PTH1/KBD4–PTH0/KBD3 are general-purpose bidirectional I/O pins

with Key Wakeup feature. See Keyboard Module (KB) on page 319

and I/O Ports on page 327.

CAN transmit pin

(CANTx)

CANTx is the digital output from the msCAN module. See msCAN08

Controller (msCAN08) on page 351.

CAN receive pin

(CANRx)

CANRx is the digital input to the msCAN module. See msCAN08

Controller (msCAN08) on page 373

Power supply

The E

and E

pins are for the sole use of the I/O pins. This will help

VSS

VDD

pins(E

and E

/E

reduce the effect of the noise induced into the V power supply.

VDD3 VDD1

SS

/E

)

VSS4 VSS1

External data pins

(EDB7ÐEDB0)

EDB7–EDB0 are the bidirectional data lines for connection to external

peripherals.

External address

pIns (EAB15ÐEAB0)

EAB15–EAB0 are the address lines for connection to external

peripherals. See EBI.

Write control pin

(WEB)

WEB is the write control signal for external peripherals. See EBI.

REB is the read control signal for external peripherals. See EBI.

WSCLK is the External WAIT State control signal. See EBI.

Read control pin

(REB)

WAIT states clock

pin (WSCLK)

External

chip-select pins

(CS1,CS0)

CS1 and CS0 are the chip-select lines for connection to external

peripherals. See EBI. The external pins are summarized in Table 1 and

the clock sources are shown in Table 3.

9-gen

MC68HC08AZ0

MOTOROLA

General Description

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General Description

Table 1. External pins summary

PIN NAME

FUNCTION

DRIVER TYPE

HYSTERESIS

RESET STATE

PTA7 -PTA0

General purpose I/O

Dual State

No

Input (Hi-Z)

PTB7/ATD7 -

PTB0/ATD0

General purpose I/0

/ ADC channel

PTC5 - PTC0

PTD7

General purpose I/O

Dual State

No

Input (Hi-Z)

PTD6/TACLK

General purpose I/O

/ Timer External Input clock

PTD5

General purpose I/O/ Timer

External Input clock

Dual State

No

Input (Hi-Z)

PTD4/TBLCK-PTD0

PTE7/SPSCK

General purpose Input

No

Input (Hi-Z)

General purpose I/0

/ SPI clock

Dual State

(open drain)

Yes

PTE6/MOSI

PTE5/MISO

PTE4/SS

General purpose I/0

/ SPI data path

Dual State

(open drain)

Yes

Input (Hi-Z)

General purpose I/0

/ SPI data path

Dual State

(open drain)

General purpose I/0

/ SPI Slave Select

Dual State

PTE3/TACH1

PTE2/TACH0

PTE1/RxD

PTE0/TxD

General purpose I/0

/ Timer A channel 1

General purpose I/0

/ TimerA channel 0

General purpose I/0

/ SCI Receive Data

General purpose I/0

/ SCI Transmit Data

PTF6

General purpose I/O

Dual State

Yes

Input (Hi-Z)

PTF5/TBCH1

General purpose I/O

/Timer B channel 1

PTF4/TBCH0

General purpose I/0

/ TimerB channel 0

Dual State

Yes

Input (Hi-Z)

PTF3

PTF2

General purpose I/0

Dual State

Yes

Input (Hi-Z)

10-gen

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General Description

Pin Assignments

Table 1. External pins summary (Continued)

PIN NAME

PTF1/TACH3

FUNCTION

DRIVER TYPE

Dual State

HYSTERESIS

RESET STATE

Input (Hi-Z)

General purpose I/0

/TimerA channel 3

Yes

PTF0/TACH2

General purpose I/0

/TimerA channel 2

Dual State

Input (Hi-Z)

PTG2/KBD2 -

PTG0/KBD0

General purpose I/0 with key

wakeup feature

PTH1/KBD4-

PTH0/KBD3

General purpose I/0 with key

wakeup feature

V

Logical chip power supply

Logical chip ground

Analog power supply(CGM)

Analog ground (CGM)

ADC reference voltage

ADC gnd & reference voltage

ADC power supply

External clock in

NA

DD

V

NA

SS

V

NA

DDA

V

NA

SSA

V

NA

REFH

A

/VREFL

NA

VSS

V

NA

DDAREF

OSC1

NA

Input (Hi-Z)

Output

NA

OSC2

External clock out

NA

CGMXFC

IRQ

PLL loop ﬁlter cap

External interrupt request

Reset

NA

Input (Hi-Z)

Output

Input (Hi-Z)

Output

Hi-Z

RST

NA

CANRx

CANTx

EAB15-EAB0

EDB7-EDB0

REB

msCAN serial Input

msCAN serial output

External address bus

External data bus

NA

YES

NA

NO

NA

Output

Dual state

Output

External read enable

External write enable

WAIT state clock

WEB

WSCLK

CS1

Chip-select 1

Output

CS0

Chip-select 0

11-gen

MC68HC08AZ0

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General Description

Details of the clock connections to each of the modules on the

MC68HC08AZ0 are shown in Table 3. A short description of each clock

source is also given in Table 2.

Table 2. Signal name conventions

Signal name

CGMXCLK

CGMOUT

Bus clock

SPSCK

Description

Buffered version of OSC1 from clock generator module (CGM)

PLL-based or OSC1-based clock output from CGM module)

CGMOUT divided by two

SPI serial clock (see SPSCK (serial clock) on page 241)

External clock Input for TIMA (see TIMA clock pin (PTD6/ATD14/TACLK) on

page 265)

TACLK

TBCLK

External clock Input for TIMB (see TIMB clock Pin (PTD4/ATD12/TBLCK) on

page 289)

Table 3. Clock source summary

Module

ADC

Clock source

CGMXCLK or bus clock

CGMXCLK or CGMOUT

CGMXCLK

msCAN

COP

CPU

EEPROM

RAM

SPI

Bus clock

CGMXCLK or bus clock

Bus clock

SPSCK

SCI

CGMXCLK

TIMA

TIMB

PIT

Bus clock or PTD6/TACLK

Bus clock or PTD4/TBLCK

Bus clock

KBI

Bus clock

EBI

Bus clock

12-gen

MC68HC08AZ0

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General Description

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General Description

Ordering Information

This section contains instructions for ordering the MC68HC08AZ0.

MC Order

Numbers

Table 4. MC Order Numbers

Operating

MC Order Number

Temperature Range

MC68HC08AZ0CFU

– 40 °C to + 85°C

13-gen

MC68HC08AZ0

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General Description

14-gen

MC68HC08AZ0

22

General Description

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Memory Map

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

I/O section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Introduction

The CPU08 can address 64K bytes of memory space. The memory map

includes:

• 1024 bytes of RAM

• 512 bytes of EEPROM

• 32,272 bytes of externally addressable memory

• 48 bytes of externally addressable user memory

• 224 bytes of monitor ROM

The following definitions apply to the memory map representation of

reserved and unimplemented locations.

•

Reserved — Accessing a reserved location can have

unpredictable effects on MCU operation.

Unimplemented — Accessing an unimplemented location

causes an illegal address reset if illegal address resets are

enabled.

1-mem

MC68HC08AZ0

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Memory Map

I/O section

Addresses $0000–$004F, shown in Figure 5, contain most of the

control, status, and data registers. Additional I/O registers have the

following addresses:

• $0500 to $057F – CAN control and message buffers. See

msCAN08 Controller (msCAN08) on page 351.

• $FE00 – (SIM break status register, SBSR)

• $FE01 – (SIM reset status register, SRSR)

• $FE03 – (SIM break flag control register, SBFCR)

• $FE07 – (EPROM control register, EPMCR)

• $FE0C and $FE0D – (break address registers, BRKH and BRKL)

• $FE0E – (break status and control register, BRKSCR)

• $FE0F – (LVI status register, LVISR)

• $FE1C – (EEPROM non-volatile register, EENVR)

• $FE1D – (EEPROM control register, EECR)

• $FE1F – (EEPROM array configuration register, EEACR)

• $FFFF – (COP control register, COPCTL)

2-mem

MC68HC08AZ0

24

Memory Map

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Memory Map

I/O section

$0000

I/O REGISTERS (80 BYTES)

↓

$004F

$0050

↓

RAM (1024 BYTES)

$044F

$0450

↓

EXTERNAL (176 BYTES)

$04FF

$0500

↓

CAN CONTROL AND MESSAGE

BUFFERS(128 BYTES)

$057F

$0580

↓

EXTERNAL (640 BYTES)

EEPROM (512 BYTES)

$07FF

$0800

↓

$09FF

$0A00

↓

EXTERNAL (1536 BYTES)

EXTERNAL (28,672 BYTES)

EXTERNAL (16,384BYTES)

EXTERNAL(15,872BYTES)

$0FFF

$1000

↓

$7FFF

$8000

↓

$BFFF

$C000

↓

$FDFF

$FE00

$FE01

$FE02

SIMBREAKSTATUSREGISTER(SBSR)

SIM RESET STATUS REGISTER (SRSR)

RESERVED

SIM BREAK FLAG CONTROL REGISTER

(SBFCR)

$FE03

Figure 4 Memory map

3-mem

MC68HC08AZ0

25

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Memory Map

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Memory Map

$FE04

$FE05

$FE06

$FE07

$FE08

$FE09

$FE0A

$FE0B

$FE0C

$FE0D

RESERVED

UNIMPLEMENTED

RESERVED

UNIMPLEMENTED

BREAK ADDRESS REGISTER HIGH (BRKH)

BREAK ADDRESS REGISTER LOW (BRKL)

BREAK STATUS AND CONTROL REGISTER

(BRKSCR)

$FE0E

$FE0F

$FE10

↓

LVI STATUS REGISTER (LVISR)

EXTERNAL (12 BYTES)

$FE1B

EEPROM NON-VOLATILE REGISTER

(EENVR)

$FE1C

$FE1D

$FE1E

EEPROM CONTROL REGISTER (EECR)

RESERVED

$FE1F EEPROM ARRAY CONFIGURATION (EEACR)

$FE20

↓

MONITOR ROM (224 BYTES)

EXTERNAL (192 BYTES)

EXTERNAL (16 BYTES)

$FEFF

$FF00

↓

$FFBF

$FFC0

↓

$FFCF

$FFD0

↓

EXTERNAL VECTORS (48 BYTES)

$FFFF

Figure 4 Memory map

4-mem

MC68HC08AZ0

26

Memory Map

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Memory Map

I/O section

Addr.

Name

Bit 7

6

5

4

3

2

1

Bit 0

R:

W:

R:

W:

R:

W:

R:

W:

R:

W:

R:

W:

R:

W:

R:

W:

R:

W:

R:

W:

R:

W:

R:

W:

R:

W:

R:

W:

R:

W:

R:

W:

R:

$0000 Port A Data Register (PTA)

$0001 Port B Data Register (PTB)

PTA7

PTA6

PTA5

PTA4

PTA3

PTA2

PTA1

PTB1

PTC1

PTD1

PTA0

PTB0

PTC0

PTD0

PTB7

0

PTB6

0

PTB25

PTC5

PTD5

PTB4

PTC4

PTD4

PTB3

PTC3

PTD3

PTB2

PTC2

PTD2

$0002

Port C Data Register

$0003 Port D Data Register (PTD)

PTD7

PTD6

Data Direction Register A

$0004

DDRA7 DDRA6 DDRA5

DDRB7 DDRB6 DDRB5

DDRA4 DDRA3 DDRA2 DDRA1 DDRA0

DDRB4 DDRB3 DDRB2 DDRB1 DDRB0

DDRC4 DDRC3 DDRC2 DDRC1 DDRC0

DDRD4 DDRD3 DDRD2 DDRD1 DDRD0

(DDRA)

Data Direction RegisterB

$0005

(DDRB)

0

Data Direction Register C

MCLKE

N

$0006

DDRC5

(DDRC)

Data Direction Register D

$0007

DDRD7 DDRD6 DDRD5

(DDRD)

$0008 Port E Data Register (PTE)

$0009 Port F Data Register (PTF)

$000A Port G Data Register (PTG)

$000B Port H Data Register (PTH)

PTE7

0

PTE6

PTE5

PTE4

PTE3

PTE2

PTF2

PTE1

PTF1

PTG1

PTH1

PTE0

PTF0

PTG0

PTH0

PTF6

0

PTF5

0

PTF4

0

PTF3

0

PTG2

0

Data Direction Register E

$000C

DDRE7 DDRE6 DDRE5

DDRE4 DDRE3 DDRE2 DDRE1 DDRE0

(DDRE)

0

Data Direction Register F

$000D

DDRF6 DDRF5

DDRF4

0

DDRF3 DDRF2 DDRF1 DDRF0

(DDRF)

0

Data Direction Register G

$000E

DDRG2 DDRG1 DDRG0

(DDRG)

0

Data Direction Register

$000F

DDRH1 DDRH0

(DDRH)

SPI Control Register

SP-

MSTR

$0010

SPRIE

DMAS

0

CPOL

MODF

CPHA SPWOM

SPE

SPR1

1

SPTIE

SPR0

Bit 0

(SPCR)

W:

R: SPRF

W:

R:

W:

R:

W:

R:

W:

R:

OVRF

SPTE

0

SPI Status and Control

$0011

Register (SPSCR)

$0012 SPI Data Register (SPDR)

Bit 7

6

5

4

M

3

2

SCI Control Register 1

$0013

LOOPS ENSCI

TXINV

SCRIE

WAKE

TE

ILTY

RE

PEN

RWU

PTY

(SCC1)

SCI Control Register 2

$0014

SCTIE

R8

TCIE

ILIE

SBK

(SCC2)

SCI Control Register 3

$0015

T8

DMARE

SCRF

DMATE

IDLE

ORIE

OR

NEIE

NF

FEIE

FE

PEIE

PE

(SCC3)

W:

R: SCTE

W:

TC

SCI Status Register 1

$0016

(SCS1)

= Unimplemented

R

= Reserved

Figure 5. Control, status, and data registers (Sheet 1 of 5)

5-mem

MC68HC08AZ0

27

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Memory Map

Addr.

Name

Bit 7

0

6

0

5

0

4

0

3

0

2

0

1

BKF

Bit 0

RPF

R:

W:

R:

W:

R:

W:

R:

W:

R:

W:

R:

W:

R:

W:

R:

W:

SCI Status Register 2

(SCS2)

$0017

$0018 SCI Data Register (SCDR)

Bit 7

0

6

0

5

4

3

0

2

1

Bit 0

SCI Baud Rate Register

$0019

SCP1

SCP0

SCR2

SCR1

SCR0

(SCBR)

IRQF

KEYF

1

0

ACK1

0

ACKK

1

IRQ Status and Control

$001A

IMASK1 MODE1

IMASKK MODEK

Register (ISCR)

0

Keyboard Status/Control

$001B

(KBSCR)

PLLF

LOCK

1

0

1

0

PLL Control Register

$001C

(PCTL)

PLLIE

AUTO

MUL7

PLLON

ACQ

BCS

XLD

0

PLL Bandwidth Control

$001D

Register (PBWC)

PLL Programming Register

$001E

(PPG)

MUL6

MUL5

MUL4

VRS7

VRS6

VRS5

VRS4

R: LVISTOP ROMSEC LVIRSTD LVIPWRD SSREC COPRS STOP

COPD

R

Mask Option Register A

$001F

(MORA)

W:

R:

W:

R;

R

TOF

0

R

0

TRST

R

0

R

Timer A Status and Control

$0020

TOIE

TSTOP

PS2

PS1

PS0

Register (TASC)

Keyboard Interrupt Enable

$0021

KBIE4

12

KBIE3

11

KBIE2

10

KBIE1

9

KBIE0

Bit 8

Register (KBIER)

W:

R: Bit 15

W;

R:

W:

R:

14

6

13

5

Timer A Counter Register

$0022

High (TACNTH)

Bit 7

4

3

2

1

Bit 0

Timer A Counter Register

£0023

Low (TACNTL)

TimerA Modulo Register

$0024

Bit 15

Bit 7

14

6

13

5

12

4

11

3

10

2

9

1

Bit 8

Bit 0

High (TAMODH)

W:

R:

W:

TimerA Modulo Register

$0025

Low (TAMODL)

Timer A Channel 0 Status R: CH0F

and Control Register

$0026

CH0IE

MS0B

13

MS0A

ELS0B

ELS0A

TOV0 CH0MAX

W:

0

(TASC0)

R:

W:

R:

TimerA Channel 0 Register

High (TACH0H)

$0027

$0028

Bit 15

Bit 7

14

6

12

4

11

3

10

2

9

1

Bit 8

Bit 0

Timer A Channel 0

Register Low (TACH0L)

5

0

W:

Timer A Channel 1 Status R: CH1F

and Control Register

$0029

CH1IE

MS1A

ELS1B

ELS1A

TOV1 CH1MAX

W:

0

(TASC1)

R:

W:

R:

Timer A Channel 1

Register High (TACH1H)

$002A

$002B

Bit 15

Bit 7

14

6

13

5

12

4

11

3

10

2

9

1

Bit 8

Bit 0

Timer A Channel 1

Register Low (TACH1L)

W:

Timer A Channel 2 Status R: CH2F

and Control Register

$002C

CH2IE

MS2B

MS2A

ELS2B

ELS2A

TOV2 CH2MAX

W:

0

(TASC2)

= Unimplemented

R

= Reserved

Figure 5. Control, status, and data registers (Sheet 2 of 5)

6-mem

MC68HC08AZ0

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I/O section

Addr.

Name

Bit 7

6

5

4

3

2

1

9

Bit 0

Bit 8

R:

W:

R:

Timer A Channel 2

Register High (TACH2H)

$002D

Bit 15

14

13

12

11

10

Timer A Channel 2

Register Low (TACH2L)

$002E

$002F

Bit 7

6

5

4

3

2

1

Bit 0

W:

Timer Channel 3 Status R: CH3F

and Control Register

CH3IE

MS3B

MS3A

ELS3B

ELS3A

TOV3 CH3MAX

W:

0

(TASC3)

R:

W:

R:

W:

R:

W:

R:

W:

R:

W:

R:

W:

R:

W:

R:

W:

Timer Channel 3 Register

High (TACH3H)

$0030

$0031

$0032

$0033

$0034

$0035

$0036

$0037

$0038

$0039

$003A

Bit 15

Bit 7

14

6

13

5

12

4

11

3

10

2

9

1

Bit 8

Bit 0

Timer Channel 3 Register

Low (TACH3L)

Unimplemented

ADSCR

R: COCO

AIEN

AD6

ADCO

AD5

CH4

AD4

CH3

AD3

CH2

AD2

CH1

AD1

CH0

AD0

W:

R:

W:

R:

W:

R:

W:

R

AD7

ADR

0

ADC Input Clock Select

(ADCLKR)

ADIV2

0

ADIV1

IRV

ADIV0

NODE

ADICLK

CS0WS

EBI COntrol Register

(EBIC)

$003B

$003C

MODE WSCLK0 CSC1

CSC0

R:

W:

EBI Chip Select Register

(EBICS)

CS1WS1 CS1WS0 CS1POL CS1EN CS0WS1 CS0WS0 CS0POL CS0EN

R:

W:

R:

W:

R:

W:

R:

W:

$003D

$003E

$003F

$0040

$0041

Unimplemented

EESEC

Mask Option Register B

(MORB)

R

0

R

TOF

0

TimerB Status and Control

Register (TBSC)

TOIE

14

TSTOP

13

PS2

10

PS1

9

PS0

8

TRST

12

R: Bit 15

W:

11

TimerB Counter Register

High (TBCNTH)

= Unimplemented

R

= Reserved

Figure 5. Control, status, and data registers (Sheet 3 of 5)

7-mem

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Memory Map

Addr.

Name

Bit 7

6

5

4

3

2

1

Bit 0

0

R:

W:

R:

W:

R:

TimerB Counter Register

Low (TBCNTL)

$0042

TimerB Modulo Register

High (TBMODH)

$0043

$0044

Bit 15

Bit 7

14

6

13

5

12

4

11

3

10

2

9

1

Bit 8

Bit 0

TimerB Modulo Register

Low (TBMODL)

W:

Timer B Channel 0Status R: CH4F

and Control Register

$0045

CH4IE

MS4B

MS4A

ELS4B

ELS4A

TOV4 CH0MAX

W:

0

(TBSC0)

R:

W:

R:

Timer B Channel 0Register

High (TBCH0H)

$0046

$0047

$0048

$0049

$004A

Bit 15

Bit 7

14

6

13

5

12

4

11

3

10

9

1

8

0

Timer B Channel 0Register

Low (TBCH0L)

2

ELS5A

10

W:

R: CH5F

W:

R:

W:

R:

Timer B Channel 1Status/

Control Register (TBSC1)

CH5IE

14

MS5B

13

MS5A

12

ELS5B

11

TOV5 CH1MAX

0

Timer B Channel 1Register

High (TBCH1H)

Bit 15

9

1

8

0

Timer B Channel1Register

Low (TBCH1L)

Bit 7

6

5

4

0

3

0

2

W:

Programmable Interrupt R: POF

Timer Status & Control

$004B

PIE

PSTOP

PPS2

PPS1

PPS0

W:

0

Bit 15

7

PRST

Register (PSC)

R:

W:

R:

W

R

W

R:

W

PIT Counter Register

HIGH) (PCNTH)

$004C

$004D

$004E

$004F

14

6

13

5

12

4

11

3

10

2

9

1

9

1

8

0

8

0

PIT Counter Register Low

(PCNTL)

PIT Modulo Register High

(PMODH)

Bit 15

7

14

6

13

5

12

4

11

3

10

2

PIT Modulo Register Low

(PMODL)

R:

W:

R: POR

W:

SIM Break Status Register

(SBSR)

$FE00

$FE01

R

0

SBSW

LVI

R

0

COP

ILOP

ILAD

SIM Reset Status Register

(SRSR)

R:

SIM Break Flag Control

Register (SBFCR)

$FE03

BCFE

W:

R

R:

W:

R:

W:

$FE07

$FE0C

$FE0D

Reserved

Break Address Register

High (BRKH)

Bit 15

14

6

13

5

12

4

11

3

10

2

9

1

Bit 8

Bit 0

R:

Break Address Register

Low (BRKL)

Bit 7

W:

= Unimplemented

R

= Reserved

Figure 5. Control, status, and data registers (Sheet 4 of 5)

8-mem

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Memory Map

I/O section

Addr.

Name

Bit 7

6

5

0

4

0

3

0

2

0

1

0

Bit 0

0

R:

W:

Break Status and Control

Register (BRKSCR)

$FE0E

BRKE

BRKA

R: LVIOUT

W:

0

$FE0F LVI Status Register (LVISR)

0

R:

W:

R:

W:

$FE1C

$FE1D

$FE1E

$FE1F

EENVR

EECR

EERA

CON2

0

CON1

CON0

EEPB3 EEPB2 EEPB1 EEPB0

0

EEBCLK

EEOFF EERAS1 EERAS0 ELAT

EEPGM

R:

R

Reserved

EEACR

R

W:

R: EERA

W:

CON2

CON1

CON0

EEBP3 EEBP2 EEBP1 EEBP0

R:

W:

LOW BYTE OF RESET VECTOR

WRITING TO $FFFF CLEARS COP COUNTER

COP Control Register

(COPCTL)

$FFFF

= Unimplemented

R

= Reserved

Figure 5. Control, status, and data registers (Sheet 5 of 5)

9-mem

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Memory Map

(1)

Table 1. Vector addresses

Address

Vector

$FFD0

$FFD1

$FFD2

$FFD3

$FFD4

$FFD5

$FFD6

$FFD7

$FFD8

$FFD9

$FFDA

$FFDB

$FFDC

$FFDD

$FFDE

$FFDF

$FFE0

$FFE1

$FFE2

$FFE3

$FFE4

$FFE5

$FFE6

$FFE7

$FFE8

$FFE9

$FFEA

$FFEB

$FFEC

$FFED

$FFEE

$FFEF

$FFF0

$FFF1

$FFF2

$FFF3

$FFF4

$FFF5

$FFF6

$FFF7

$FFF8

$FFF9

$FFFA

$FFFB

$FFFC

$FFFD

$FFFE

$FFFF

ADC vector (high)

ADC vector (low)

Low

Keyboard vector (high)

Keyboard vector (low)

SCI transmit vector (high)

SCI Transmit vector (Low)

SCI Receive vector (High)

SCI Receive vector (Low)

SCI Error vector (High)

SCI Error vector (Low)

msCAN Transmit vector(High)

msCAN Transmit vector (Low)

msCAN Receive vector(High)

msCAN Receive vector (Low)

msCAN Error vector(High)

msCAN Error vector (Low)

msCAN Wakeup vector(High)

msCAN Wakeup vector (Low)

SPI Transmit vector(High)

SPI Transmit vector (Low)

SPI Receive vector(High)

SPI Receive vector (Low)

TIMB Overflow vector(High)

TIMB Overflow vector (Low)

TIMB CH1 vector(High)

TIMB CH1 vector (Low)

TIMB CH0 vector(High)

TIMB CH0 vector (Low)

TIMA Overflow vector(High)

TIMA Overflow vector (Low)

TIMA CH3 vector(High)

TIMA CH3 vector (Low)

TIMACH2 vector(High)

TIMA CH2 vector (Low)

TIMA CH1 vector(High)

TIMA CH1 vector (Low)

TIMA CH0 vector(High)

TIMA CH0 vector (Low)

PIT vector(High)

PIT vector (Low)

PLL vector(High)

PLL vector (Low)

IRQ vector (High)

IRQ vector (Low)

SWI vector(High)

SWI vector (Low)

Reset vector (High)

Reset vector (Low)

High

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Memory Map

I/O section

1. All available ROM locations not defined by the user will by

default be filled with the software interrupt (SWI, opcode 83)

instruction – see Central Processor Unit (CPU). Take this into

account when defining vector addresses. It is recommended that

ALL vector addresses are defined.

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Memory Map

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RAM

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Introduction

This section describes the 1024 bytes of RAM.

Functional description

Addresses $0050 through $044F are RAM locations. The location of the

stack RAM is programmable. The 16-bit stack pointer allows the stack to

be anywhere in the 64K byte memory space.

NOTE: For correct operation, the stack pointer must point only to RAM

locations.

Within page zero there are 176 bytes of RAM. Because the location of

the stack RAM is programmable, all page zero RAM locations can be

used for I/O control and user data or code. When the stack pointer is

moved from its reset location at $00FF, direct addressing mode

instructions can efficiently access all page zero RAM locations. Page

zero RAM, therefore, provides an ideal location for frequently accessed

global variables.

Before processing an interrupt, the CPU uses 5 bytes of the stack to

save the contents of the CPU registers.

NOTE: For M6805 compatibility, the H register is not stacked.

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RAM

During a subroutine call, the CPU uses 2 bytes of the stack to store the

return address. The stack pointer decrements during pushes and

increments during pulls.

NOTE: Care should be taken when using nested subroutines. The CPU may

overwrite data in the RAM during a subroutine or during the interrupt

stacking operation.

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EBI

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Module I/O signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Externally controlled WAIT states . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

EBI control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Introduction

This section describes the External Bus Interface Module (EBI)

specification for the HC08AZ0 MCU. This module handles the transfer

of information between the MCU and the external address space. The

external bus provides up to 16 address lines, 8 data lines, 2 chip-selects

and 3 control signals to the external devices.

Features

• Up to 64K byte of Address Space.

• Low Noise or High Performance Modes of operation.

• 2 Pre-determined Chip-Select Lines (CS1 and CS0).

• Separate Read and Write Enable Signals

• 0,1,2 or 3 WAIT States for Slow Memory Access associated with

CS1

• Up to 7 WAIT States for Slow Device Access associated with CS0.

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EBI

Figure 6 shows the structure of the EBI.

The EBI has two basic modes of operation; Low Noise or High

Performance. In Low Noise mode the Address and Data lines are only

driven out during external accesses to reduce RF emissions

In High Performance mode the EBI operates at its fastest. This mode of

operation requires the external address and data signals from the

MC68HC08AZ0 before they are stable.

The chip-select regions are controlled by software providing the user

with a choice of four combinations.The chip-selects have a control

register which allows the chip selects to be enabled, their polarity

selected and for the appropriate number of WAIT States to be defined

for CS0 and CS1.

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EBI

Features

8

5

Decode Logic

EBI Control

Registers

Chip Select Logic

Bus Timing

Interface Logic

WAIT Logic

and

Selectable Features

Data Buffer

ADDRESS BUFFER

Figure 6 EBI Block Diagram

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EBI

Module I/O signal descriptions

Below is a description of the I/O signals shown in Figure 6. The External

Bus Interface module is connected to the HC08 Bus (IBUS) with data

bus IDB[7:0], address bits IAB[15:0] and IRW, IWS for control. It is

connected to the external devices with Address Bus A[15:0], Data Bus

D[7:0], and Control Bits WEB, REB, CS1 and CS0. In addition WSCLK

is provided for cycle-by-cycle external WAIT state selection.

Internal Address Ð

IAB[15:0]

The internal address bits are an input to the EBI module.

Internal data Ð

IDB[7:0]

The internal data bits are bidirectional signals to the EBI module. They

are used to transfer data in and out of the EBI via the IBUS. The direction

of the data flow is controlled by the IRW signal. When IRW is high (read

mode), the data bus is an output of the EBI and the data in D[7:0] is

transferred to IDB[7:0] (the internal data bus). When IRW is low (write

mode), the data bus is an input to the EBI and the data in IDB[7:0] is

transferred to D[7:0] (the external data bus). An exception to this occurs

when the IRV bit is set. In that mode, when internal accesses occur, data

on IDB[7:0] is transferred out on D[7:0].

Internalread/write

Ð IRW

The internal read/write bit is an input control signal to the EBI module. It

allows the CPU (or DMA) to read and write to the external devices. With

the proper interface logic, the IRW generates the external read signal

REB and external write signal WEB.

External access

(External)

The External signal identifies those cycles that are not internal to the

part. This is used to keep the EBI outputs quiet for internal accesses in

Low Noise Mode.

EBIEN Ð EBI enable

The EBI enable signal is provided by physical Mask Option. It is used to

disable the EBI and therefore reduce power and RF emissions in

non-expanded mode.

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EBI

Module I/O signal descriptions

Internal WAIT state

Ð IWS

The internal WAIT state signal is an output from the EBI module. It is

connected to the IMREQB (in the IBUS), which suspends the CPU state

(but not the internal clocks). The IMREQB signal delay is software

controlled for CSI and either software or hardware controlled for

CS0.This signal will be disabled for internal accesses.

External address

bus Ð A[15:0]

The external address bus are the output address signals from the EBI

module. They provide addressing information to the external devices. In

Low Noise mode the values on these lines remain at the last driven state

between external accesses.

Chip-selects Ð

CS1, CS0

The chip-selects are output control signals from the EBI module. They

enable external devices at their programmed addresses.

External data bus Ð

DB[7:0]

The external data bus are three-state bidirectional data signals to the

EBI module. These signals provide the data path between the MCU and

all external devices. In Low Noise mode the values on these lines

remain at the last driven state between external accesses.

External read Ð REB

The external read is an output control signal from the EBI module. When

REB is asserted, a read cycle starts and data is transferred from an

external device to the internal data bus. This signal is asserted only for

external accesses, or when the IRV bit is set.

External write Ð

WEB

The external write is an output control signal to the EBI module. When

WEB is asserted, a write cycle starts and data is transferred to an

external device from the internal data bus. This signal is asserted only

for external accesses or when the IRV bit is set.

WAIT state clock Ð

WSCLK

The WAIT state clock is used to insert the correct number of WAIT states

into each bus cycle when the ‘external WAIT states’ operating mode is

selected for CS0.

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EBI

Functional description

The user has two optional chip-select lines to define areas within the 64K

byte address range to be occupied by external devices. The range of

each address chip-select region can be modified by software. The

software option provides the user with a choice of regions as shown in

Figure 7.

0000

CS0 (4K)

0000

CS0 (4K)

0000

CS0 (4K)

and

Internal

1000

CS0 (12K)

4000

1000

CS0 (28k)

CS0 (44K)

8000

CS1 (60K)

CS1 (48K)

FFFF

CS1 (32K)

C000

CS1 (16K)

FFFF

Figure 7 Software controlled chip-select combinations

CS1 is intended for program space as it always includes the vector

space. CS0 may be used for any purpose and is in effect equivalent to

CS1. Extending CS0 address space below $1000 allows the user to

place external devices (e.g. I/O) in unused address locations below

$1000 without the use of an external decoder (the CS0 pin would

otherwise be redundant). Internal accesses will always have priority.

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Externally controlled WAIT states

When a chip-select is enabled, it is active for all memories and I/O cycles

within its defined (external) area. Each chip-select has control bits for

enabling, polarity setting and for inserting the correct number of WAIT

states in each bus cycle. Out of reset CS0 and CS1 are configured with

the maximum number (3) of software controlled WAIT states.

All bus timing interface signals are handled by the bus timing interface

logic that generates the proper signals for reads and writes required to

interface the internal and external buses.

Externally controlled WAIT states

The EBI generates an IWS signal which can be controlled either

internally or externally for CS0. The external option allows the user to

further decode the CS0 address space into smaller address ranges for

multiple external devices, and assign a different number of WAIT states

to each address range. The number of WAIT states associated with CS1

address space is determined internally by the CS1WS 1:0 bits.

During T4 the HC08 data bus is not driven and during this clock phase

the number of WAIT states for the cycle in progress is determined. When

CS0 is asserted, the value on the External Data bus at the end of T4 is

used to determine the number of WAIT States according to Table 2 This

WAIT state value is encoded in the first 3 bits of the data bus, D2:0. This

mode of operation is selected by enabling the function in the EBI control

register and by enabling the WSCLK pin according to Table 3 The WAIT

state value on the data bus is only latched when CS0 is asserted.

Therefore, it is not required that the bus be driven during T4 when

accessing addresses outside the CS0 range (i.e. when CS1 is asserted).

The WAIT state value driven onto the External Data bus may be derived

directly from the address lines or indirectly from a decoded chip select

signal(s). In all cases, the WAIT state value must only be allowed to drive

the External Data bus during the period WSCLK is asserted by using a

tri-statable buffer (e.g. 74AC240/244, 74AC367A/368A, 74AC125). See

examples later in this section.

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EBI

External Databus Value D2 - D0

Number of WAIT States

000

001

010

011

100

101

110

111

0

1

2

3

4

5

6

7

Table 2 Data bus values corresponding to number of WAIT states

The pin WSCLK provides the T4 signal to synchronize driving the WAIT

state value onto the External Data lines. Table 3 shows the options

available for the WSCLK pin. The WSCLK can also be disabled.

When external WAIT-state decoding is enabled, the low RF emission

data bus freeze function is disabled for data bus lines D2:0. The address

bus freeze function remains unaffected.

WSCLK1

WSCLK0

WSCLK Pin Function

Disabled, tri-state

T4 + CS0, push/pull

T4, push/pull

0

1

0

1

0

1

T4, push/pull

Table 3 WSCLK pin function

CS0 used in the WSCLK pin functions is active low, irrespective of the

state of the CS0 pin polarity bit. CS0 and WSCLK are not asserted

during internal access bus cycles. The term <T4 + CS0> is therefore an

active low signal.

Examples of external WAIT state selection are shown in Figure 8,

Figure 9 and Figure 10

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Externally controlled WAIT states

1

1/2 AC367

Address bus

Program Memory

HC08AZ0

1 WAIT-state

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

$1000–

$FFFF

A0

A15

(60K space)

$1000 –

$FFFF

CS1

CS0

CS

WSCLK

Peripheral

7 WAIT-states

D7

D6

D5

D4

D3

D2

D1

D0

$0000–

$0FFF

(4K space

less internal

addresses)

CS

A0

A1

CS0 = $0000 – $0FFF

CS1 = $1000 – $FFFF, 1WS internal

Figure 8 Defining WAIT states for Ext addresses below $1000

In Figure 8, the user wants to maximize the address space allocated to

the program memory but requires to decode a slow external peripheral

with a 4byte address space. To avoid driving the data bus unnecessarily,

WSCLK is programmed to generate CS0+T4 which will only go low

during T4 whenever the address is within the CSo range as defined by

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CSC[1:0]. The peripheral will be multiply mapped within this address

space. Whenever CS0 is asserted and the CS0 WAIT state control is

configured for external control (C0WS =1), internal logic will direct the

WAIT state generator to use the data bus as the source of the number

of WAIT states to be inserted. In this case, the value $111 will be driven

onto D2:0 during T4 which will instruct the WAIT state generator to insert

7 WAIT states (equivalent to a 1uS bus cycle for an 8MHz bus clock).

The number of WAIT states for CS1 is selected internally based on the

contents of CS1WS1:0 bits and may between 0 and 3 bus cycles.

In Figure 9, the application requires different WAIT states for program

memory, RAM and peripheral bus cycles. One of the chip selects must

therefore be subdivided into two address spaces, each with a different

number of WAIT states associated with it. A simple decode of the upper

2 address lines provides an address range of $0000-$1FFF for the

peripheral and drives External Data bus line D1 high during T4 when

within that address range, thus requesting 2 WAIT states. In this

implementation, the peripheral map is duplicated with the address range

$0000 to $0FFF as well as the required $1000 to $1FFF. In order to

prevent internal accesses effecting the peripheral, CS0 is used as a

further enable to both devices within this address space. CS0 is not

asserted for internal accesses within its address space.

WSCLK is programmed to generate CS0+T4 which will go low during T4

whenever the address is within the CS0 range as defined by CSC[1:0].

The number of WAIT states for CS1 is selected internally based on the

contents of CS1WS1:0 bits and may between 0 and 3 bus cycles.

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Externally controlled WAIT states

Address bus

HC08AZ0

Program Memory

1 WAIT-state

CS0 = $1000 – $7FFF

CS1 = $8000 – $FFFF, 1WS internal

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

A0

$8000–

$FFFF

A15

(32K space)

CS1

CS0

CS

WSCLK

RAM

0 WAIT-states

D7

D6

D5

D4

D3

D2

D1

D0

$2000–

$7FFF

1/4 AC02

(24Kspace)

0

OE

CS

Peripheral

2 WAIT-state

1/2 AC367

D7

D6

D5

D4

D3

D2

D1

D0

$1000–

$1FFF

(4Kspace)

CS1

CS2

Figure 9 Simple address space decode with different WAIT states

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EBI

Address bus

Program Memory

HC08AZ0

2 WAIT-states

CS0 = $1000 – $3FFF

CS1 = $4000 – $FFFF, 2 WS internal

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

$8000–

$FFFF

A0

(32K space)

A15

$8000 –

$FFFF

CS1

CS0

CS

WSCLK

T4+CS0

A0A1A2

Peripheral

5 WAIT-states

D7

D6

D5

D4

D3

D2

D1

D0

Vdd

Vss

$5000–

$5FFF

CS3

CS2

CS1

AC138

0 1 2 3 4 5 6 7

TO OTHER

DEVICES

CS

$5000–$5FFF

Peripheral

1 WAIT-state

A12

D7

D6

D5

D4

D3

D2

D1

D0

$1000–

$1FFF

A13

A14

1/2 AC367

CS

$1000–$1FFF

Figure 10 WAIT state selection for multiple I/O peripherals

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Externally controlled WAIT states

In Figure 10, the application has several external peripheral devices

which are decoded into the CS0 address space using an external 3-to-8

decoder (e.g. 74AC138). The addition of a tri-stateable buffer (e.g.

74AC367, hex buffer) represents the hardware overhead to provide a

unique number of WAIT states for each decoded address space.

Decoder outputs provide the peripheral chip selects. In this

implementation, the same addresses used by the decoder are driven

back onto the data bus during T4. Therefore, as the address increments,

so does the number of WAIT states assigned to each address space.

WSCLK is configured to drive CS0+T4, which drives the buffer enables

during T4 when the address is within the CS0 range.

Choosing to drive different addresses onto the data bus during T4 allow

the user to provide a different mix of WAIT states throughout the

decoded CS0 address space. Alternatively, the 3-8 line decoder could

be replaced with a PAL which would provide for a more complex decode

and assignment of WAIT states. The number of WAIT states for CS1 is

selected internally based on the contents of CS1WS1:0 bits and may

between 0 and 3 bus cycles.

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EBI control registers

The following I/O registers control and monitor operation of the EBI:-

• EBI Control Register (EBIC)

• Chip-Select Control Register (EBICS)

EBI control register

Bit 7

0

6

5

4

3

2

1

0

Read:

EBIC

$003B

IRV

MODE

C0WS

WSCLK1 WSCLK0

CSC1

CSC0

Write:

Reset

:

0

= Unimplemented

Figure 11 EBI control register (EBIC)

IRVIRV — Internal read visibility bit

This function is included for easy-debug of the customer application.

1 = The REB and WEB are active during IRV, to allow creation of

an ECLK. Enabled chip selects are active as well, and all

internal bus activity is externally visible.

0 = In normal user operation IRV should be off to prevent possible

bus contention.

MODE — EBI operating mode

1 = Low Noise

0 = High Performance

C0WS — Chip select 0 WAIT state control

1 = Externally Controlled

0 = Internally Controlled.

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EBI control registers

WSCLK1:0 — WAIT state clock select

These bits control the WSCLK operating mode according to Table 4

WSCLK1

WSCLK0

WSCLK Pin Function

Disabled, Tri-State

T4 + CS0, Open Drain

T4, Push/Pull

0

1

0

1

0

1

T4, Push/Pull

Table 4 WSCLK pin function

CSC1:0 — Chip-Select Combination

These bits control the chip-select combination according to table

Table 5

CSC1

CSC0

Chip-Select 1

$1000 – $FFFF

$4000 – $FFFF

$8000 – $FFFF

$C000 – $FFFF

Chip-Select 0

$0000 – $0FFF

$0000 – $3FFF

$0000 – $7FFF

$0000 – $BFFF

0

1

0

1

0

1

Table 5 Chip-select combinations

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EBI Chip-Select

Register

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Write:

EBICS

$003C

CS1WS1 CS1WS0 CS1POL CS1EN CS0WS1 CS0WS0 CS0POL CS0EN

Reset

:

1

0

1

0

1

= Unimplemented

Figure 12 EBI control register (EBICS)

CS1WS1:0

These bits control the number of WAIT States for Chip-Select 1 during

external accesses when the WAIT states are internally controlled.

WAIT states are inserted according to Table 6

CS1WS1:0

Number of WAIT States

00

01

10

11

0

1

2

3

Table 6 WAIT states for external accesses

CS1EN — Chip-select enable

This bit controls whether the Chip-Select is active.

0 = Chip-Select disabled.

1 = Chip-Select enabled

CS1POL — Chip-select polarity

This bit controls the polarity of the Chip-Select line.

0 = Chip-Select Active LOW

1 = Chip-Select Active HIGH

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EBI

EBI control registers

CS0WS1:0

These bits control the number of WAIT States for Chip-Select 0 during

external accesses according to Table 6

CS0WS1:0

Number of WAIT States

00

01

10

11

0

1

2

3

Table 7 WAIT states for external accesses

CS0EN — Chip-select enable

This bit controls whether the Chip-Select is active.

0 = Chip-Select disabled.

1 = Chip-Select enabled

CS0POL — Chip-select polarity

This bit controls the polarity of the Chip-Select line.

0 = Chip-Select Active LOW

1 = Chip-Select Active HIGH

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EEPROM

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Future EEPROM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

EEPROM programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

EEPROM erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

EEPROM block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

EEPROM configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

MCU configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

MC68HC08AZ0 EEPROM Security . . . . . . . . . . . . . . . . . . . . . . . . 61

EEPROM control register (EECR) . . . . . . . . . . . . . . . . . . . . . . . . . 62

EEPROM non-volatile register (EENVR) and EEPROM

array configuration register (EEACR) . . . . . . . . . . . . . . . . . . . . . . . 64

Low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

WAIT mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

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EEPROM

Introduction

This section describes the electrically erasable programmable ROM

(EEPROM).

Future EEPROM Memory

Design is underway to introduce an improved EEPROM module, which

will simplify programming and erase. Current read, write and erase

algorithms are fully compatible with the new EEPROM design. The new

EEPROM module requires a constant timebase through the set up of

new timebase control registers. If more information is required for code

compatibility please contact the factory. The silicon differences will be

identified by mask set. Please read Appendix A: Future EEPROM

Registers for preliminary details.

NOTE: This new silicon will not allow multiple writes before erase. EEPROM

bytes must be erased before reprogramming.

Features

• Byte, block or bulk erasable

• Non-volatile block protection option

• Non-volatile MCU configuration bits

• On-chip charge pump for programming/erasing.

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EEPROM

Functional description

512 bytes of EEPROM can be programmed or erased without an

external voltage supply. The EEPROM has a lifetime of 10,000

write-erase cycles. EEPROM cells are protected with a non-volatile

block protection option. These options are stored in the EEPROM

non-volatile register (EENVR) and are loaded into the EEPROM array

configuration register after reset (EEACR) or after a read of EENVR.

Hardware interlocks are provided to protect stored data corruption from

accidental programming/erasing.

The EEPROM array will leave the factory in the erased state all

addresses logic ‘1’, and bit 4 of the EENVR register will be programmed

to #1 such that the full array is available and unprotected.

EEPROM

programming

The unprogrammed state is a logic ‘1’. Programming changes the state

to a logic ‘0’. Only valid EEPROM bytes in the non-protected blocks and

EENVR can be programmed.

It is recommended that all bits should be erased before being

programmed.

The following procedure describes how to program a byte of EEPROM:

1. Clear EERAS1 and EERAS0 and set EELAT in the EECR

(See Note a. and b.)

2. Write the desired data to any user EEPROM address.

3. Set the EEPGM bit. (See Note c.)

4. Wait for a time, t

, to program the byte.

EEPGM

5. Clear EEPGM bit.

6. Wait for the programming voltage time to fall (t

).

EEFPV

7. Clear EELAT bits. (See Note d.)

8. Repeat steps 1 to 7 for more EEPROM programming.

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EEPROM

NOTES:

a. EERAS1 and EERAS0 must be cleared for programming,

otherwise the part will be in erase mode

b. Setting the EELAT bit configures the address and data buses

to latch data for programming the array. Only data with a valid

EEPROM address will be latched. If another consecutive valid

EEPROM write occurs, this address and data will override the

previous address and data. Any attempts to read other

EEPROM data will result in the latched data being read. If

EELAT is set, other writes to the EECR will be allowed after a

valid EEPROM write.

c. The EEPGM bit cannot be set if the EELAT bit is cleared and

a non-EEPROM write has occurred. This is to ensure proper

programming sequence. When EEPGM is set, the on-board

charge pump generates the program voltage and applies it to

the user EEPROM array. When the EEPGM bit is cleared, the

program voltage is removed from the array and the internal

charge pump is turned off.

d. Any attempt to clear both EEPGM and EELAT bits with a

single instruction will only clear EEPGM. This is to allow time

for removal of high voltage from the EEPROM array.

e. While these operations must be performed in the order shown,

other unrelated operations may occur between the steps.

EEPROM erasing

The unprogrammed state is a logic ‘1’. Only the valid EEPROM bytes in

the non-protected blocks and EENVR can be erased.

The following procedure shows how to erase EEPROM:

1. Clear/set EERAS1 and EERAS0 to select byte/block/bulk

erase, and set EELAT in EECR (see Note f.)

2. Write any data to the desired address for byte erase, to any

address in the desired block for block erase, or to any array

address for bulk erase.

3. Set the EEPGM bit. (See Note g.)

4. Wait for a time, t

/t

before erasing the

byte block bulk

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EEPROM

Functional description

byte/block/array.

5. Clear EEPGM bit.

6. Wait for the erasing voltage time to fall (t

7. Clear EELAT bits. (See Note h.)

).

EEFPV

8. Repeat steps 1 to 7 for more EEPROM byte/block erasing.

The EEBPx bit must be cleared to erase EEPROM data in the

corresponding block. If any EEBPx is set, the corresponding block

cannot be erased and bulk erase mode does not apply.

NOTES:

f. Setting the EELAT bit configures the address and data buses

to latch data for erasing the array. Only valid EEPROM

addresses with its data will be latched. If another consecutive

valid EEPROM write occurs, this address and data will

override the previous address and data. In block erase mode,

any EEPROM address in the block may be used in step 2. All

locations within this block will be erased. In bulk erase mode,

any EEPROM address may be used to erase the whole

EEPROM. EENVR is not affected with block or bulk erase.

Any attempts to read other EEPROM data will result in the

latched data being read. If EELAT is set, other writes to the

EECR will be allowed after a valid EEPROM write.

g. The EEPGM bit cannot be set if the EELAT bit is cleared and

a non-EEPROM write has occurred. This is to ensure proper

erasing sequence. Once EEPGM is set, the type of erase

mode cannot be modified. If EEPGM is set, the on-board

charge pump generates the erase voltage and applies it to the

user EEPROM array. When the EEPGM bit is cleared, the

erase voltage is removed from the array and the internal

charge pump is turned off.

h. Any attempt to clear both EEPGM and EELAT bits with a

single instruction will only clear EEPGM. This is to allow time

for removal of high voltage from the EEPROM array.

In general, all bits should be erased before being programmed.

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EEPROM

EEPROM block

protection

The 512 bytes of EEPROM is divided into four 128 byte blocks. Each of

these blocks can be separately protected by the EEBPx bit. Any attempt

to program or erase memory locations within the protected block will not

allow the program/erase voltage to be applied to the array. Table 8

shows the address ranges within the blocks.

Table 8. EEPROM array address blocks

BLOCK NUMBER

ADDRESS RANGE

(EEBPx)

EEBP0

EEBP1

EEBP2

EEBP3

$0800–$087F

$0880–$08FF

$0900–$097F

$0980–$09FF

If the EEBPx bit is set, the corresponding address block is protected.

These bits are effective after a reset or a read to EENVR register. The

block protect configuration can be modified by erasing/programming the

corresponding bits in the EENVR register and then reading the EENVR

register.

EEPROM

configuration

The EEPROM non-volatile register (EENVR) contains configurations

concerning block protection and redundancy. EENVR is physically

located on the bottom of the EEPROM array. The contents are

non-volatile and are not modified by reset. On reset, this special register

loads the EEPROM configuration into a corresponding volatile EEPROM

array configuration register (EEACR). Thereafter, all reads to the

EENVR will result in EEACR being reloaded.

The EEPROM configuration can be changed by programming/erasing

the EENVR like a normal EEPROM byte. The new array configuration

will take effect with a system reset or a read of the EENVR.

MCU configuration

The EEPROM non-volatile register (EENVR) also contains general

purpose bits which can be used to enable/disable functions within the

MCU which, for safety reasons, need to be controlled from non-volatile

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EEPROM

Functional description

memory. On reset, this special register loads the MCU configuration into

the volatile EEPROM array configuration register (EEACR). Thereafter,

all reads to the EENVR will result in EEACR being reloaded.

The MCU configuration can be changed by programming/erasing the

EENVR like a normal EEPROM byte. Please note that it is the users

responsibility to program the EENVR register to the correct system

requirements and verify it prior to use. The new array configuration

will take effect with a system reset or a read of the EENVR.

MC68HC08AZ0

EEPROM Security

The MC68HC08AZ0 has a special security option which prevents

program/erase access to memory locations $08F0 to $08FF. This

security function is enabled by programming the CON0 bit in the EENVR

to 0.

In addition to disabling the program and erase operations on memory

locations $08F0 to $08FF the enabling of the security option has the

following effects:

• Bulk and block erase modes are disabled.

• Programming and erasing of the EENVR is disabled.

• Non secure locations ($0800–$08EF) can be erased using the

single byte erase function as normal.

• Secured locations can be read as normal.

• Writing to a secured location no longer qualifies as a “valid

EEPROM write” as detailed in EEPROM programming Note a.,

and EEPROM erasing Note f.

NOTE: Once armed, the security is permanently enabled. As a

consequence, all functions in the EENVR will remain in the state they

were in immediately before the security was enabled.

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EEPROM

EEPROM control

register (EECR)

This read/write register controls programming/erasing of the array.

7

EEBCLK

0

6

0

5

4

3

2

1

0

EEPGM

0

READ:

WRITE:

RESET:

EECR

$FE1D

EEOFF EERAS1 EERAS0 EELAT

0

= Unimplemented

Figure 1. EEPROM control register (EECR)

EEBCLK — EEPROM BUS CLOCK ENABLE

This read/write bit determines which clock will be used to drive the

internal charge pump for programming/erasing. Reset clears this bit.

1 = Bus clock drives charge pump

0 = Internal RC oscillator drives charge pump

NOTE: It is recommended that the internal RC oscillator is used to drive the

internal charge pump for applications which have a bus frequency of less

than 8MHz.

EEOFF — EEPROM power down

This read/write bit disables the EEPROM module for lower power

consumption. Any attempts to access the array will give unpredictable

results. Reset clears this bit.

1 = Disable EEPROM array

0 = Enable EEPROM array

NOTE: The EEPROM requires a recovery time t

to stabilize after clearing

EEOFF

the EEOFF bit.

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EEPROM

Functional description

EERAS1–EERAS0 — Erase bits

These read/write bits set the erase modes. Reset clears these bits.

Table 9. EEPROM program/erase mode select

EEBPx

EERAS1

EERA0

MODE

0

1

0

1

X

0

1

0

1

X

Byte Program

Byte Erase

Block Erase

Bulk Erase

No Erase/Program

X = don’t care

EELAT — EEPROM latch control

This read/write bit latches the address and data buses for

programming the EEPROM array. EELAT can not be cleared if

EEPGM is still set. Reset clears this bit.

1 = Buses configured for EEPROM programming

0 = Buses configured for normal read operation

EEPGM — EEPROM program/erase enable

This read/write bit enables the internal charge pump and applies the

programming/erasing voltage to the EEPROM array if the EELAT bit

is set and a write to a valid EEPROM location has occurred. Reset

clears the EEPGM bit.

1 = EEPROM programming/erasing power switched on

0 = EEPROM programming/erasing power switched off

NOTE: Writing ‘0’s to both the EELAT and EEPGM bits with a single instruction

will only clear EEPGM. This is to allow time for the removal of high

voltage.

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EEPROM

EEPROM non-volatile register (EENVR) and EEPROM array configuration register (EEACR)

7

6

5

4

3

2

1

0

READ:

WRITE:

RESET:

EENVR

$FE1C

EERA

PV

CON2

PV

CON1

PV

CON0

PV

EEBP3

PV

EEBP2

PV

EEBP1

PV

EEBP0

PV

PV = Programmed Value or ‘1’ in the erased state.

Figure 2. EEPROM non-volatile register (EENVR)

7

READ: EERA

WRITE:

6

5

4

3

2

1

0

CON2

CON1

CON0

EEBP3

EEBP2

EEBP1

EEBP0

EEACR

$FE1F

RESET: EENVR EENVR EENVR EENVR EENVR EENVR EENVR EENVR

= Unimplemented

Figure 3. EEPROM array control register (EEACR)

EERA — EEPROM redundant array

This bit is reserved for future use and should always be equal to 0.

CONx — MCU configuration bits

These read/write bits can be used to enable/disable functions within

the MCU. Reset loads CONx from EENVR to EEACR.

CON2 — Unused

CON1 — Unused

CON0 — EEPROM security

1 = EEPROM security disabled

0 = EEPROM security enabled

EEBP3–EEBP0 — EEPROM block protection bits.

These read/write bits prevent blocks of EEPROM array from being

programmed or erased. Reset loads EEBP[3:0] from EENVR to

EEACR.

1 = EEPROM array block is protected

0 = EEPROM array block is unprotected

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EEPROM

Functional description

Low power modes

The WAIT and STOP instructions can put the MCU in low power

consumption standby modes.

WAIT m o d e

The WAIT instruction does not affect the EEPROM. It is possible to

program the EEPROM and put the MCU in WAIT mode. However, if the

EEPROM is inactive, power can be reduced by setting the EEOFF bit

before executing the WAIT instruction.

STOP m o d e

The STOP instruction reduces the EEPROM power consumption to a

minimum. The STOP instruction should not be executed while the high

voltage is turned on (EEPGM=1).

If STOP mode is entered while program/erase is in progress, high

voltage will automatically be turned off. However, the EEPGM bit will

remain set. When STOP mode is terminated, if EEPGM is still set, the

high voltage will automatically be turned back on. Program/erase time

will need to be extended if program/erase is interrupted by entering

STOP mode.

The module requires a recovery time t

to stabilize after leaving

EESTOP

STOP mode. Attempts to access the array during the recovery time will

result in unpredictable behavior.

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Central Processor Unit (CPU)

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Index register (H:X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Stack pointer (SP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Program counter (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Condition code register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Arithmetic/logic unit (ALU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

CPU during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Instruction Set Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Introduction

This section describes the central processor unit (CPU8). The M68HC08

CPU is an enhanced and fully object-code-compatible version of the

M68HC05 CPU. The CPU08 Reference Manual (Motorola document

number CPU08RM/AD) contains a description of the CPU instruction

set, addressing modes, and architecture.

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Central Processor Unit (CPU)

Features

Features of the CPU include the following:

• Full upward, object-code compatibility with M68HC05 family

• 16-bit stack pointer with stack manipulation instructions

• 16-bit index register with X-register manipulation instructions

• 8.4MHz CPU internal bus frequency

• 64K byte program/data memory space

• 16 addressing modes

• Memory-to-memory data moves without using accumulator

• Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions

• Enhanced binary-coded decimal (BCD) data handling

• Low-power STOP and WAIT Modes

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Central Processor Unit (CPU)

CPU registers

Figure 1 shows the five CPU registers. CPU registers are not part of the

memory map.

7

0

ACCUMULATOR (A)

15

H

X

INDEX REGISTER (H:X)

STACK POINTER (SP)

PROGRAM COUNTER (PC)

7

V 1 1 H

I

N Z C CONDITION CODE REGISTER (CCR)

CARRY/BORROW FLAG

ZERO FLAG

NEGATIVE FLAG

INTERRUPT MASK

HALF-CARRY FLAG

TWO’S COMPLEMENT OVERFLOW FLAG

Figure 1. CPU registers

Accumulator (A)

The accumulator is a general-purpose 8-bit register. The CPU uses the

accumulator to hold operands and the results of arithmetic/logic

operations.

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Write:

Reset:

A

Unaffected by reset

Figure 1. Accumulator (A)

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Central Processor Unit (CPU)

Index register

(H:X)

The 16-bit index register allows indexed addressing of a 64K byte

memory space. H is the upper byte of the index register and X is the

lower byte. H:X is the concatenated 16-bit index register.

In the indexed addressing modes, the CPU uses the contents of the

index register to determine the conditional address of the operand.

Bit

0

15 14 13 12 11 10

9

0

8

0

7

6

5

4

3

2

1

Read:

Write:

Reset:

H:X

0

X

X = Indeterminate

Figure 1. Index register (H:X)

The index register can also be used as a temporary data storage

location.

Stack pointer (SP)

The stack pointer is a 16-bit register that contains the address of the next

location on the stack. During a reset, the stack pointer is preset to

$00FF. The reset stack pointer (RSP) instruction sets the least

significant byte to $FF and does not affect the most significant byte. The

stack pointer decrements as data is pushed onto the stack and

increments as data is pulled from the stack.

In the stack pointer 8-bit offset and 16-bit offset addressing modes, the

stack pointer can function as an index register to access data on the

stack. The CPU uses the contents of the stack pointer to determine the

conditional address of the operand.

Bit

0

15 14 13 12 11 10

9

8

7

6

5

1

4

1

3

1

2

1

Read:

Write:

Reset:

SP

0

1

Figure 1. Stack pointer (SP)

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Central Processor Unit (CPU)

CPU registers

NOTE: The location of the stack is arbitrary and may be relocated anywhere in

RAM. Moving the SP out of page zero ($0000 to $00FF) frees direct

address (page zero) space. For correct operation, the stack pointer must

point only to RAM locations.

Program counter

(PC)

The program counter is a 16-bit register that contains the address of the

next instruction or operand to be fetched.

Normally, the program counter automatically increments to the next

sequential memory location every time an instruction or operand is

fetched. Jump, branch, and interrupt operations load the program

counter with an address other than that of the next sequential location.

During reset, the program counter is loaded with the reset vector

address located at $FFFE and $FFFF. The vector address is the

address of the first instruction to be executed after exiting the reset state.

Bit

0

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

Read:

Write:

Reset:

PC

Loaded with vector from $FFFE and $FFFF

Figure 1. Program counter (PC)

Condition code

register (CCR)

The 8-bit condition code register contains the interrupt mask and five

flags that indicate the results of the instruction just executed. Bits 6 and

5 are set permanently to ‘1’. The following paragraphs describe the

functions of the condition code register.

Bit 7

V

6

1

5

1

4

3

I

2

1

Z

X

Bit 0

C

Read:

Write:

Reset:

CCR

H

X

N

X

1

X

X = Indeterminate

Figure 1. Condition code register (CCR)

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V — Overflow flag

The CPU sets the overflow flag when a two's complement overflow

occurs. The signed branch instructions BGT, BGE, BLE, and BLT use

the overflow flag.

1 = Overflow

0 = No overflow

H — Half-carry flag

The CPU sets the half-carry flag when a carry occurs between

accumulator bits 3 and 4 during an ADD or ADC operation. The

half-carry flag is required for binary-coded decimal (BCD) arithmetic

operations. The DAA instruction uses the states of the H and C flags

to determine the appropriate correction factor.

1 = Carry between bits 3 and 4

0 = No carry between bits 3 and 4

I — Interrupt mask

When the interrupt mask is set, all maskable CPU interrupts are

disabled. CPU interrupts are enabled when the interrupt mask is

cleared. When a CPU interrupt occurs, the interrupt mask is set

automatically after the CPU registers are saved on the stack, but

before the interrupt vector is fetched.

1 = Interrupts disabled

0 = Interrupts enabled

NOTE: To maintain M6805 compatibility, the upper byte of the index register (H)

is not stacked automatically. If the interrupt service routine modifies H,

then the user must stack and unstack H using the PSHH and PULH

instructions.

After the I bit is cleared, the highest-priority interrupt request is

serviced first.

A return from interrupt (RTI) instruction pulls the CPU registers from the

stack and restores the interrupt mask from the stack. After any reset, the

interrupt mask is set and can only be cleared by the clear interrupt mask

software instruction (CLI).

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Arithmetic/logic unit (ALU)

N — Negative flag

The CPU sets the negative flag when an arithmetic operation, logic

operation, or data manipulation produces a negative result, setting bit

7 of the result.

1 = Negative result

0 = Non-negative result

Z — Zero flag

The CPU sets the zero flag when an arithmetic operation, logic

operation, or data manipulation produces a result of $00.

1 = Zero result

0 = Non-zero result

C — Carry/borrow flag

The CPU sets the carry/borrow flag when an addition operation

produces a carry out of bit 7 of the accumulator or when a subtraction

operation requires a borrow. Some instructions - such as bit test and

branch, shift, and rotate - also clear or set the carry/borrow flag.

1 = Carry out of bit 7

0 = No carry out of bit 7

Arithmetic/logic unit (ALU)

The ALU performs the arithmetic and logic operations defined by the

instruction set.

Refer to the CPU08 Reference Manual (Motorola document number

CPU08RM/AD) for a description of the instructions and addressing

modes and more detail about CPU architecture.

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Central Processor Unit (CPU)

CPU during break interrupts

If the break module is enabled, a break interrupt causes the CPU to

execute the software interrupt instruction (SWI) at the completion of the

current CPU instruction. See Break Module on page 139. The program

counter vectors to $FFFC–$FFFD ($FEFC–$FEFD in monitor mode).

A return from interrupt instruction (RTI) in the break routine ends the

break interrupt and returns the MCU to normal operation if the break

interrupt has been deasserted.

Instruction Set Summary

Table 1 provides a summary of the M68HC08 instruction set.

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Instruction Set Summary

Table 1 Instruction Set Summary

Effect on

Source

Form

CCR

Operation

Description

V H I N Z C

ADC #opr

IMM

DIR

EXT

IX2

A9 ii

B9 dd

C9 hh ll

D9 ee ff

E9 ff

2

3

4

3

2

4

5

ADC opr

ADC opr,X

ADC ,X

Add with Carry

A ← (A) + (M) + (C)

↕ ↕ – ↕ ↕ ↕

IX1

IX

SP1

SP2

F9

ADC opr,SP

9EE9 ff

9ED9 ee ff

ADD #opr

ADD opr

IMM

DIR

EXT

IX2

AB ii

BB dd

CB hh ll

DB ee ff

EB ff

2

3

4

3

2

4

5

ADD opr

ADD opr,X

ADD ,X

ADD opr,SP

Add without Carry

A ← (A) + (M)

↕ ↕ – ↕ ↕ ↕

IX1

IX

SP1

SP2

FB

9EEB ff

9EDB ee ff

AIS #opr

AIX #opr

Add Immediate Value (Signed) to SP

Add Immediate Value (Signed) to H:X

SP ← (SP) + (16 « M)

H:X ← (H:X) + (16 « M)

–

– IMM

A7 ii

AF ii

2

AND #opr

AND opr

IMM

DIR

EXT

IX2

A4 ii

B4 dd

C4 hh ll

D4 ee ff

E4 ff

2

3

4

3

2

4

5

AND opr

AND opr,X

AND ,X

AND opr,SP

Logical AND

A ← (A) & (M)

0

–

↕ ↕ –

IX1

IX

F4

SP1

SP2

9EE4 ff

9ED4 ee ff

ASL opr

ASLA

ASLX

ASL opr,X

ASL ,X

ASL opr,SP

DIR

INH

IX1

IX

38 dd

48

4

1

4

3

5

Arithmetic Shift Left

(Same as LSL)

58

↕ –

↕ ↕ ↕

C

0

68 ff

78

b7

b0

SP1

9E68 ff

ASR opr

ASRA

ASRX

ASR opr,X

ASR opr,SP

DIR

INH

IX1

IX

37 dd

47

4

1

4

3

5

57

C

Arithmetic Shift Right

–

↕ ↕ ↕

67 ff

77

SP1

9E67 ff

BCC rel

Branch if Carry Bit Clear

PC ← (PC) + 2 + rel ? (C) = 0

–

– REL

24 rr

3

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Table 1 Instruction Set Summary (Continued)

Effect on

Source

Form

CCR

Operation

Description

V H I N Z C

DIR (b0) 11 dd

DIR (b1) 13 dd

DIR (b2) 15 dd

DIR (b3) 17 dd

DIR (b4) 19 dd

DIR (b5) 1B dd

DIR (b6) 1D dd

DIR (b7) 1F dd

4

BCLR n, opr

Clear Bit n in M

Mn ← 0

–

BCS rel

BEQ rel

Branch if Carry Bit Set (Same as BLO)

Branch if Equal

PC ← (PC) + 2 + rel ? (C) = 1

PC ← (PC) + 2 + rel ? (Z) = 1

–

– REL

25 rr

27 rr

3

Branch if Greater Than or Equal To

(Signed Operands)

BGE opr

BGT opr

PC ← (PC) + 2 + rel ? (N V) = 0

–

– REL

90 rr

92 rr

3

Branch if Greater Than (Signed

Operands)

PC ← (PC) + 2 + rel ? (Z) | (N V) = 0

3

BHCC rel

BHCS rel

BHI rel

Branch if Half Carry Bit Clear

Branch if Half Carry Bit Set

Branch if Higher

PC ← (PC) + 2 + rel ? (H) = 0

PC ← (PC) + 2 + rel ? (H) = 1

PC ← (PC) + 2 + rel ? (C) | (Z) = 0

–

– REL

28 rr

29 rr

22 rr

3

Branch if Higher or Same

(Same as BCC)

BHS rel

PC ← (PC) + 2 + rel ? (C) = 0

–

– REL

24 rr

BIH rel

BIL rel

Branch if IRQ Pin High

Branch if IRQ Pin Low

PC ← (PC) + 2 + rel ? IRQ = 1

PC ← (PC) + 2 + rel ? IRQ = 0

–

– REL

2F rr

2E rr

3

BIT #opr

BIT opr

IMM

DIR

EXT

IX2

A5 ii

B5 dd

C5 hh ll

D5 ee ff

E5 ff

2

3

4

3

2

4

5

BIT opr

BIT opr,X

BIT ,X

BIT opr,SP

Bit Test

(A) & (M)

0

–

↕ ↕ –

IX1

IX

F5

SP1

SP2

9EE5 ff

9ED5 ee ff

Branch if Less Than or Equal To

(Signed Operands)

BLE opr

PC ← (PC) + 2 + rel ? (Z) | (N V) = 1

–

– REL

93 rr

3

BLO rel

BLS rel

BLT opr

BMC rel

BMI rel

BMS rel

Branch if Lower (Same as BCS)

Branch if Lower or Same

PC ← (PC) + 2 + rel ? (C) = 1

PC ← (PC) + 2 + rel ? (C) | (Z) = 1

PC ← (PC) + 2 + rel ? (N V) =1

PC ← (PC) + 2 + rel ? (I) = 0

PC ← (PC) + 2 + rel ? (N) = 1

PC ← (PC) + 2 + rel ? (I) = 1

–

– REL

25 rr

23 rr

91 rr

2C rr

2B rr

2D rr

3

Branch if Less Than (Signed Operands)

Branch if Interrupt Mask Clear

Branch if Minus

Branch if Interrupt Mask Set

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Instruction Set Summary

Table 1 Instruction Set Summary (Continued)

Effect on

Source

Form

CCR

Operation

Description

V H I N Z C

BNE rel

Branch if Not Equal

PC ← (PC) + 2 + rel ? (Z) = 0

PC ← (PC) + 2 + rel ? (N) = 0

PC ← (PC) + 2 + rel

–

– REL

26 rr

2A rr

20 rr

3

BPL rel

BRA rel

Branch if Plus

Branch Always

DIR (b0) 01 dd rr

DIR (b1) 03 dd rr

DIR (b2) 05 dd rr

DIR (b3) 07 dd rr

DIR (b4) 09 dd rr

DIR (b5) 0B dd rr

DIR (b6) 0D dd rr

DIR (b7) 0F dd rr

5

BRCLR n,opr,rel Branch if Bit n in M Clear

PC ← (PC) + 3 + rel ? (Mn) = 0

–

↕

BRN rel

Branch Never

PC ← (PC) + 2

– REL

21 rr

3

DIR (b0) 00 dd rr

DIR (b1) 02 dd rr

DIR (b2) 04 dd rr

DIR (b3) 06 dd rr

DIR (b4) 08 dd rr

DIR (b5) 0A dd rr

DIR (b6) 0C dd rr

DIR (b7) 0E dd rr

5

BRSET n,opr,rel Branch if Bit n in M Set

PC ← (PC) + 3 + rel ? (Mn) = 1

↕

DIR (b0) 10 dd

DIR (b1) 12 dd

DIR (b2) 14 dd

DIR (b3) 16 dd

DIR (b4) 18 dd

DIR (b5) 1A dd

DIR (b6) 1C dd

DIR (b7) 1E dd

4

BSET n,opr

BSR rel

Set Bit n in M

Mn ← 1

–

PC ← (PC) + 2; push (PCL)

SP ← (SP) – 1; push (PCH)

SP ← (SP) – 1

Branch to Subroutine

–

– REL

AD rr

4

PC ← (PC) + rel

CBEQ opr,rel

PC ← (PC) + 3 + rel ? (A) – (M) = $00

PC ← (PC) + 3 + rel ? (X) – (M) = $00

PC ← (PC) + 3 + rel ? (A) – (M) = $00

PC ← (PC) + 2 + rel ? (A) – (M) = $00

PC ← (PC) + 4 + rel ? (A) – (M) = $00

DIR

31 dd rr

41 ii rr

51 ii rr

61 ff rr

71 rr

5

4

5

4

6

CBEQA #opr,rel

CBEQX #opr,rel

CBEQ opr,X+,rel

CBEQ X+,rel

IMM

Compare and Branch if Equal

–

IX1+

IX+

CBEQ opr,SP,rel

SP1

9E61 ff rr

CLC

CLI

Clear Carry Bit

C ← 0

I ← 0

–

0

–

0 INH

– INH

98

9A

1

2

Clear Interrupt Mask

CLR opr

CLRA

M ← $00

A ← $00

X ← $00

H ← $00

M ← $00

DIR

INH

3F dd

4F

3

1

3

2

4

CLRX

INH

5F

CLRH

Clear

0

–

0

1

– INH

IX1

IX

SP1

8C

CLR opr,X

CLR ,X

6F ff

7F

CLR opr,SP

9E6F ff

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Table 1 Instruction Set Summary (Continued)

Effect on

Source

Form

CCR

Operation

Description

V H I N Z C

CMP #opr

IMM

DIR

EXT

IX2

A1 ii

B1 dd

C1 hh ll

D1 ee ff

E1 ff

2

3

4

3

2

4

5

CMP opr

CMP opr,X

CMP ,X

Compare A with M

(A) – (M)

↕ –

–

↕ ↕ ↕

IX1

IX

SP1

SP2

F1

CMP opr,SP

9EE1 ff

9ED1 ee ff

COM opr

COMA

M ← (M) = $FF – (M)

A ← (A) = $FF – (M)

X ← (X) = $FF – (M)

M ← (M) = $FF – (M)

DIR

INH

IX1

IX

33 dd

43

4

1

4

3

5

COMX

53

Complement (One’s Complement)

Compare H:X with M

0

–

↕ ↕ 1

COM opr,X

COM ,X

COM opr,SP

63 ff

73

9E63 ff

SP1

CPHX #opr

CPHX opr

IMM

DIR

65 ii ii+1

75 dd

3

4

(H:X) – (M:M + 1)

↕ –

↕ ↕ ↕

CPX #opr

CPX opr

IMM

DIR

EXT

IX2

A3 ii

B3 dd

C3 hh ll

D3 ee ff

E3 ff

2

3

4

3

2

4

5

CPX opr

CPX ,X

Compare X with M

(X) – (M)

↕ –

–

↕ ↕ ↕

CPX opr,X

CPX opr,SP

IX1

IX

SP1

SP2

F3

9EE3 ff

9ED3 ee ff

DAA

Decimal Adjust A

(A)

U –

–

↕ ↕ ↕ INH

72

2

10

A ← (A) – 1 or M ← (M) – 1 or X ← (X) – 1

PC ← (PC) + 3 + rel ? (result) ≠ 0

PC ← (PC) + 2 + rel ? (result) ≠ 0

PC ← (PC) + 3 + rel ? (result) ≠ 0

PC ← (PC) + 2 + rel ? (result) ≠ 0

PC ← (PC) + 4 + rel ? (result) ≠ 0

5

3

5

4

6

DBNZ opr,rel

DBNZA rel

DBNZX rel

DBNZ opr,X,rel

DBNZ X,rel

DBNZ opr,SP,rel

DIR

INH

3B dd rr

4B rr

Decrement and Branch if Not Zero

–

– INH

IX1

5B rr

6B ff rr

7B rr

IX

SP1

9E6B ff rr

DEC opr

DECA

M ← (M) – 1

A ← (A) – 1

X ← (X) – 1

M ← (M) – 1

DIR

INH

3A dd

4A

4

1

4

3

5

DECX

5A

Decrement

Divide

↕ –

–

↕ ↕ –

DEC opr,X

DEC ,X

DEC opr,SP

IX1

IX

6A ff

7A

9E6A ff

SP1

A ← (H:A)/(X)

H ← Remainder

DIV

–

0

–

↕ ↕ INH

52

7

EOR #opr

EOR opr

EOR opr,X

EOR ,X

EOR opr,SP

IMM

DIR

EXT

IX2

IX1

IX

SP1

SP2

A8 ii

B8 dd

C8 hh ll

D8 ee ff

E8 ff

2

3

4

3

2

4

5

Exclusive OR M with A

A ← (A

M)

–

↕ ↕ –

F8

9EE8 ff

9ED8 ee ff

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Instruction Set Summary

Table 1 Instruction Set Summary (Continued)

Effect on

Source

Form

CCR

Operation

Description

V H I N Z C

INC opr

M ← (M) + 1

A ← (A) + 1

X ← (X) + 1

M ← (M) + 1

DIR

INH

IX1

IX

3C dd

4C

4

1

4

3

5

INCA

INCX

5C

Increment

Jump

↕ –

–

↕ ↕ –

INC opr,X

INC ,X

6C ff

7C

9E6C ff

INC opr,SP

SP1

JMP opr

JMP opr,X

JMP ,X

DIR

EXT

– IX2

IX1

IX

BC dd

CC hh ll

DC ee ff

EC ff

2

3

4

3

2

PC ← Jump Address

–

FC

JSR opr

JSR opr,X

JSR ,X

DIR

EXT

– IX2

IX1

BD dd

CD hh ll

DD ee ff

ED ff

4

5

6

5

4

PC ← (PC) + n (n = 1, 2, or 3)

Push (PCL); SP ← (SP) – 1

Push (PCH); SP ← (SP) – 1

PC ← Unconditional Address

Jump to Subroutine

IX

FD

LDA #opr

LDA opr

IMM

DIR

EXT

IX2

A6 ii

B6 dd

C6 hh ll

D6 ee ff

E6 ff

2

3

4

3

2

4

5

LDA opr

LDA opr,X

LDA ,X

LDA opr,SP

Load A from M

Load H:X from M

Load X from M

A ← (M)

H:X ← (M:M + 1)

X ← (M)

0

–

↕ ↕ –

IX1

IX

F6

SP1

SP2

9EE6 ff

9ED6 ee ff

LDHX #opr

LDHX opr

IMM

DIR

45 ii jj

55 dd

3

4

LDX #opr

LDX opr

LDX opr,X

LDX ,X

LDX opr,SP

IMM

DIR

EXT

IX2

IX1

IX

SP1

SP2

AE ii

BE dd

CE hh ll

DE ee ff

EE ff

FE

9EEE ff

9EDE ee ff

2

3

4

3

2

4

5

LSL opr

LSLA

DIR

INH

IX1

IX

38 dd

48

4

1

4

3

5

LSLX

Logical Shift Left

(Same as ASL)

58

C

0

↕ –

–

↕ ↕ ↕

LSL opr,X

LSL ,X

LSL opr,SP

68 ff

78

9E68 ff

b7

b0

SP1

LSR opr

LSRA

LSRX

LSR opr,X

LSR ,X

LSR opr,SP

DIR

INH

IX1

IX

34 dd

44

4

1

4

3

5

54

0

C

Logical Shift Right

0 ↕ ↕

64 ff

74

b7

b0

SP1

9E64 ff

MOV opr,opr

MOV opr,X+

MOV #opr,opr

MOV X+,opr

DD

4E dd dd

5E dd

5

4

(M)

← (M)

Source

Destination

DIX+

IMD

IX+D

Move

0

–

0

–

↕ ↕ –

6E ii dd

7E dd

H:X ← (H:X) + 1 (IX+D, DIX+)

X:A ← (X) × (A)

MUL

Unsigned multiply

–

0 INH

42

5

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Table 1 Instruction Set Summary (Continued)

Effect on

Source

Form

CCR

Operation

Description

V H I N Z C

NEG opr

DIR

INH

IX1

IX

30 dd

40

4

1

4

3

5

M ← –(M) = $00 – (M)

A ← –(A) = $00 – (A)

X ← –(X) = $00 – (X)

M ← –(M) = $00 – (M)

NEGA

NEGX

50

Negate (Two’s Complement)

↕ –

–

↕ ↕ ↕

NEG opr,X

NEG ,X

60 ff

70

9E60 ff

NEG opr,SP

SP1

NOP

NSA

No Operation

Nibble Swap A

None

–

– INH

9D

62

1

3

A ← (A[3:0]:A[7:4])

ORA #opr

ORA opr

IMM

DIR

EXT

IX2

AA ii

BA dd

CA hh ll

DA ee ff

EA ff

2

3

4

3

2

4

5

ORA opr

ORA opr,X

ORA ,X

ORA opr,SP

Inclusive OR A and M

A ← (A) | (M)

0

–

↕ ↕ –

IX1

IX

FA

SP1

SP2

9EEA ff

9EDA ee ff

PSHA

PSHH

PSHX

PULA

PULH

PULX

Push A onto Stack

Push H onto Stack

Push X onto Stack

Pull A from Stack

Pull H from Stack

Pull X from Stack

Push (A); SP ← (SP) – 1

Push (H); SP ← (SP) – 1

Push (X); SP ← (SP) – 1

SP ← (SP + 1); Pull (A)

SP ← (SP + 1); Pull (H)

SP ← (SP + 1); Pull (X)

–

– INH

87

8B

89

86

8A

88

2

ROL opr

ROLA

DIR

INH

39 dd

49

4

1

4

3

5

ROLX

59

C

Rotate Left through Carry

Rotate Right through Carry

↕ –

–

↕ ↕ ↕

ROL opr,X

ROL ,X

ROL opr,SP

IX1

IX

69 ff

79

9E69 ff

b7

b0

SP1

ROR opr

RORA

RORX

ROR opr,X

ROR ,X

ROR opr,SP

DIR

INH

IX1

IX

36 dd

46

4

1

4

3

5

56

C

–

↕ ↕ ↕

66 ff

76

b7

b0

SP1

9E66 ff

RSP

RTI

Reset Stack Pointer

Return from Interrupt

SP ← $FF

–

– INH

9C

80

1

SP ← (SP) + 1; Pull (CCR)

SP ← (SP) + 1; Pull (A)

SP ← (SP) + 1; Pull (X)

SP ← (SP) + 1; Pull (PCH)

SP ← (SP) + 1; Pull (PCL)

↕ ↕ ↕ ↕ ↕ ↕ INH

7

SP ← SP + 1; Pull (PCH)

SP ← SP + 1; Pull (PCL)

RTS

Return from Subroutine

–

– INH

81

4

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Instruction Set Summary

Table 1 Instruction Set Summary (Continued)

Effect on

Source

Form

CCR

Operation

Description

V H I N Z C

SBC #opr

IMM

DIR

EXT

IX2

A2 ii

B2 dd

C2 hh ll

D2 ee ff

E2 ff

2

3

4

3

2

4

5

SBC opr

SBC opr,X

SBC ,X

Subtract with Carry

A ← (A) – (M) – (C)

↕ –

–

↕ ↕ ↕

IX1

IX

SP1

SP2

F2

SBC opr,SP

9EE2 ff

9ED2 ee ff

SEC

SEI

Set Carry Bit

C ← 1

I ← 1

–

1

–

1 INH

– INH

99

9B

1

2

Set Interrupt Mask

STA opr

DIR

EXT

IX2

B7 dd

C7 hh ll

D7 ee ff

E7 ff

3

4

3

2

4

5

STA opr

STA opr,X

STA ,X

STA opr,SP

Store A in M

M ← (A)

0

–

↕ ↕ – IX1

IX

SP1

SP2

F7

9EE7 ff

9ED7 ee ff

STHX opr

STOP

Store H:X in M

(M:M + 1) ← (H:X)

0

–

0

↕ ↕ – DIR

35 dd

8E

4

1

Enable IRQ Pin; Stop Oscillator

I ← 0; Stop Oscillator

–

– INH

STX opr

DIR

EXT

IX2

BF dd

CF hh ll

DF ee ff

EF ff

3

4

3

2

4

5

STX opr

STX opr,X

STX ,X

STX opr,SP

Store X in M

M ← (X)

0

–

↕ ↕ – IX1

IX

SP1

SP2

FF

9EEF ff

9EDF ee ff

SUB #opr

SUB opr

SUB opr,X

SUB ,X

SUB opr,SP

IMM

DIR

EXT

A0 ii

B0 dd

C0 hh ll

D0 ee ff

E0 ff

2

3

4

3

2

4

5

IX2

↕ ↕ ↕

IX1

Subtract

A ← (A) – (M)

↕ –

IX

SP1

SP2

F0

9EE0 ff

9ED0 ee ff

PC ← (PC) + 1; Push (PCL)

SP ← (SP) – 1; Push (PCH)

SP ← (SP) – 1; Push (X)

SP ← (SP) – 1; Push (A)

SWI

Software Interrupt

–

1

–

– INH

83

9

SP ← (SP) – 1; Push (CCR)

SP ← (SP) – 1; I ← 1

PCH ← Interrupt Vector High Byte

PCL ← Interrupt Vector Low Byte

TAP

TAX

TPA

Transfer A to CCR

Transfer A to X

CCR ← (A)

X ← (A)

↕ ↕ ↕ ↕ ↕ ↕ INH

84

97

85

2

1

–

– INH

Transfer CCR to A

A ← (CCR)

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Table 1 Instruction Set Summary (Continued)

Effect on

Source

Form

CCR

Operation

Description

V H I N Z C

TST opr

DIR

INH

IX1

IX

3D dd

4D

3

1

3

2

4

TSTA

TSTX

5D

Test for Negative or Zero

(A) – $00 or (X) – $00 or (M) – $00

0

–

↕ ↕ –

TST opr,X

TST ,X

6D ff

7D

9E6D ff

TST opr,SP

SP1

TSX

Transfer SP to H:X

Transfer X to A

H:X ← (SP) + 1

A ← (X)

–

– INH

95

9F

94

2

1

2

TXA

TXS

Transfer H:X to SP

(SP) ← (H:X) – 1

Any bit

A Accumulatorn

C Carry/borrow bitopr

CCRCondition code registerPC

Operand (one or two bytes)

Program counter

ddDirect address of operandPCH

Program counter high byte

Program counter low byte

Relative addressing mode

Relative program counter offset byte

Stack pointer, 8-bit offset addressing mode

Stack pointer 16-bit offset addressing mode

Stack pointer

dd rrDirect address of operand and relative offset of branch instructionPCL

DDDirect to direct addressing modeREL

DIRDirect addressing moderel

DIX+Direct to indexed with post increment addressing moderr

ee ffHigh and low bytes of offset in indexed, 16-bit offset addressingSP1

EXTExtended addressing modeSP2

ff Offset byte in indexed, 8-bit offset addressingSP

H Half-carry bitU

Undeﬁned

H Index register high byteV

Overﬂow bit

hh llHigh and low bytes of operand address in extended addressingX

I Interrupt maskZ

Index register low byte

Zero bit

ii Immediate operand byte&

Logical AND

IMDImmediate source to direct destination addressing mode|

IMMImmediate addressing mode

INHInherent addressing mode( )

Logical OR

Logical EXCLUSIVE OR

Contents of

IXIndexed, no offset addressing mode–( )

IX+Indexed, no offset, post increment addressing mode#

IX+DIndexed with post increment to direct addressing mode«

IX1Indexed, 8-bit offset addressing mode←

IX1+Indexed, 8-bit offset, post increment addressing mode?

IX2Indexed, 16-bit offset addressing mode:

MMemory location↕

Negation (two’s complement)

Immediate value

Sign extend

Loaded with

If

Concatenated with

Set or cleared

N Negative bit—

Not affected

Opcode Map

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Opcode Map

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System Integration Module (SIM)

SIM

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

SIM bus clock control and generation. . . . . . . . . . . . . . . . . . . . . . . . . 88

Bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Clock start-up from POR or LVI reset . . . . . . . . . . . . . . . . . . . . . . . 89

Clocks in STOP and WAIT mode . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Reset and system initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

External pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Active resets from internal sources. . . . . . . . . . . . . . . . . . . . . . . . . 91

Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Computer operating properly (COP) reset . . . . . . . . . . . . . . . . . 93

Illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Low-voltage inhibit (LVI) reset . . . . . . . . . . . . . . . . . . . . . . . . . . 94

SIM counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

SIM counter during power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . 95

SIM counter during STOP mode recovery . . . . . . . . . . . . . . . . . . . 95

SIM counter and reset states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Exception control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

SWI instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Status flag protection in break mode . . . . . . . . . . . . . . . . . . . . . . 100

Low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

WAIT mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

SIM registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

SIM break status register (SBSR). . . . . . . . . . . . . . . . . . . . . . . . . 104

SIM reset status register (SRSR) . . . . . . . . . . . . . . . . . . . . . . . . . 105

SIM break flag control register (SBFCR) . . . . . . . . . . . . . . . . . . . 106

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System Integration Module (SIM)

Introduction

This section describes the system integration module, which supports up

to 24 external and/or internal interrupts. Together with the CPU, the SIM

controls all MCU activities. A block diagram of the SIM is shown in

Figure 1. Table 1 is a summary of the SIM I/O registers. The SIM is a

system state controller that coordinates CPU and exception timing. The

SIM is responsible for:

• Bus clock generation and control for CPU and peripherals

– STOP/WAIT/reset/break entry and recovery

– Internal clock control

• Master reset control, including power-on reset (POR) and COP

timeout

• Interrupt control:

– Acknowledge timing

– Arbitration control timing

– Vector address generation

• CPU enable/disable timing

• Modular architecture expandable to 128 interrupt sources

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System Integration Module (SIM)

Introduction

MODULE STOP

MODULE WAIT

CPU STOP (FROM CPU)

CPU WAIT (FROM CPU)

STOP/WAIT

CONTROL

SIMOSCEN (TO CGM)

SIM

COUNTER

COP CLOCK

CGMXCLK (FROM CGM)

CGMOUT (FROM CGM)

÷ 2

CLOCK

CONTROL

CLOCK GENERATORS

INTERNAL CLOCKS

LVI (FROM LVI MODULE)

RESET

PIN LOGIC

POR CONTROL

RESET PIN CONTROL

MASTER

RESET

CONTROL

ILLEGAL OPCODE (FROM CPU)

ILLEGAL ADDRESS (FROM ADDRESS

MAP DECODERS)

SIM RESET STATUS REGISTER

COP (FROM COP MODULE)

RESET

INTERRUPT SOURCES

CPU INTERFACE

INTERRUPT CONTROL

AND PRIORITY DECODE

Figure 1. SIM block diagram

Table 1. SIM I/O register summary

Register Name

SIM Break Status Register (SBSR)

Bit 7

6

R

5

4

3

2

R

0

1

SBSW

LVI

Bit 0 Addr.

R

0

$FE00

$FE01

$FE03

SIM Reset Status Register (SRSR) POR

0

COP ILOP ILAD

SIM Break Flag Control Register (SBFCR) BCFE

R

0

= Reserved for factory test

Table 2 shows the internal signal names used in this section.

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System Integration Module (SIM)

Table 2. Signal naming conventions

Signal Name

CGMXCLK

CGMVCLK

Description

Buffered version of OSC1 from clock generator module (CGM)

PLL output

PLL-based or OSC1-based clock output from CGM module

(Bus clock = CGMOUT divided by two)

CGMOUT

IAB

IDB

Internal address bus

Internal data bus

PORRST

IRST

Signal from the power-on reset module to the SIM

Internal reset signal

R/W

Read/write signal

SIM bus clock control and generation

The bus clock generator provides system clock signals for the CPU and

peripherals on the MCU. The system clocks are generated from an

incoming clock, CGMOUT, as shown in Figure 2. This clock can come

from either an external oscillator or from the on-chip PLL. See

Clock Generator Module (CGM) on page 107.

CGMXCLK

OSC1

SIM COUNTER

CLOCK

SELECT

CIRCUIT

A

B

CGMOUT

BUS CLOCK

GENERATORS

÷ 2

CGMVCLK

PLL

S*

*When S = 1,

CGMOUT = B

BCS

SIM

PTC3

MONITOR MODE

USER MODE

CGM

Figure 2. CGM clock signals

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System Integration Module (SIM)

SIM bus clock control and generation

Bus timing

In user mode, the internal bus frequency is either the crystal oscillator

output (CGMXCLK) divided by four or the PLL output (CGMVCLK)

divided by four. See Clock Generator Module (CGM) on page 107.

Clock start-up

from POR or LVI

reset

When the power-on reset module or the low-voltage inhibit module

generates a reset, the clocks to the CPU and peripherals are inactive

and held in an inactive phase until after the 4096 CGMXCLK cycle POR

timeout has been completed. The RST pin is driven low by the SIM

during this entire period. The IBUS clocks start upon completion of the

timeout.

Clocks in STOP

and WAIT mode

Upon exit from STOP mode (by an interrupt, break, or reset), the SIM

allows CGMXCLK to clock the SIM counter. The CPU and peripheral

clocks do not become active until after the STOP delay timeout. This

timeout is selectable as 4096 or 32 CGMXCLK cycles. See STOP mode

on page 102.

In WAIT mode, the CPU clocks are inactive. The SIM also produces two

sets of clocks for other modules. Refer to the WAIT mode subsection of

each module to see if the module is active or inactive in WAIT mode.

Some modules can be programmed to be active in WAIT mode.

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System Integration Module (SIM)

Reset and system initialization

The MCU has the following reset sources:

• Power-on reset module (POR)

• External reset pin (RST)

• Computer operating properly module (COP)

• Low-voltage inhibit module (LVI)

• Illegal opcode

• Illegal address

All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in

monitor mode) and assert the internal reset signal (IRST). IRST causes

all registers to be returned to their default values and all modules to be

returned to their reset states.

An internal reset clears the SIM counter, see SIM counter on page 95,

but an external reset does not. Each of the resets sets a corresponding

bit in the SIM reset status register (SRSR). See SIM registers on page

104.

External pin reset

Pulling the asynchronous RST pin low halts all processing. The PIN bit

of the SIM reset status register (SRSR) is set as long as RST is held low

for a minimum of 67 CGMXCLK cycles, assuming that neither the POR

nor the LVI was the source of the reset. See Table 3 for details. Figure

3 shows the relative timing.

Table 3. PIN bit set timing

Reset type

Number of cycles required to set PIN

4163 (4096 + 64 + 3)

POR/LVI

All others

67 (64 + 3)

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Reset and system initialization

CGMOUT

RST

VECT H

IAB

PC

VECT L

Figure 3. External reset timing

Active resets from

internal sources

All internal reset sources actively pull the RST pin low for 32 CGMXCLK

cycles to allow for resetting of external peripherals. The internal reset

signal IRST continues to be asserted for an additional 32 cycles. See

Figure 4. An internal reset can be caused by an illegal address, illegal

opcode, COP timeout, LVI, or POR. See Figure 5. Note that for LVI or

POR resets, the SIM cycles through 4096 CGMXCLK cycles, during

which the SIM forces the RST pin low. The internal reset signal then

follows the sequence from the falling edge of RST as shown in Figure 4.

IRST

RST

RSTPULLED LOW BY MCU

32 CYCLES

CGMXCLK

IAB

VECTOR HIGH

Figure 4. Internal reset timing

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The COP reset is asynchronous to the bus clock.

ILLEGAL ADDRESS RST

ILLEGAL OPCODE RST

INTERNAL RESET

COPRST

LVI

POR

Figure 5. Sources of internal reset

The active reset feature allows the part to issue a reset to peripherals

and other chips within a system built around the MCU.

Po we r-o n re se t

When power is first applied to the MCU, the power-on reset module

(POR) generates a pulse to indicate that power-on has occurred. The

external reset pin (RST) is held low while the SIM counter counts out

4096 CGMXCLK cycles. 64 CGMXCLK cycles later, the CPU and

memories are released from reset to allow the reset vector sequence to

occur.

At power-on, the following events occur:

• A POR pulse is generated

• The internal reset signal is asserted

• The SIM enables CGMOUT

• Internal clocks to the CPU and modules are held inactive for 4096

CGMXCLK cycles to allow the oscillator to stabilize

• The RST pin is driven low during the oscillator stabilization time

• The POR bit of the SIM reset status register (SRSR) is set and all

other bits in the register are cleared

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Reset and system initialization

OSC1

PORRST

4096

CYCLES

32

CYCLES

32

CYCLES

CGMXCLK

CGMOUT

RST

IAB

$FFFE

$FFFF

Figure 6. POR recovery

Co m p ute r

An input to the SIM is reserved for the COP reset signal. The overflow of

the COP counter causes an internal reset and sets the COP bit in the

SIM reset status register (SRSR). The SIM actively pulls down the RST

pin for all internal reset sources.

o p e ra ting

p ro p e rly (COP)

re se t

To prevent a COP module timeout, a value (any value) should be written

to location $FFFF. Writing to location $FFFF clears the COP counter and

bits 12 through 4 of the SIM counter. The SIM counter output, which

13

4

occurs at least every 2 – 2 CGMXCLK cycles, drives the COP

counter. The COP should be serviced as soon as possible out of reset

to guarantee the maximum amount of time before the first timeout.

The COP module is disabled if the RST pin or the IRQ pin is held at

V

_DD+ V_HIwhile the MCU is in monitor mode. The COP module can be

disabled only through combinational logic conditioned with the high

voltage signal on the RST or the IRQ pin. This prevents the COP from

becoming disabled as a result of external noise. During a break state,

V_DD+ V_HIon the RST pin disables the COP module.

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Ille g a l o p c o d e

re se t

The SIM decodes signals from the CPU to detect illegal instructions. An

illegal instruction sets the ILOP bit in the SIM reset status register

(SRSR) and causes a reset.

If the STOP enable bit, STOP, in the mask option register is logic ‘0’, the

SIM treats the STOP instruction as an illegal opcode and causes an

illegal opcode reset. The SIM actively pulls down the RST pin for all

internal reset sources.

Ille g a l a d d re ss

re se t

An opcode fetch from an unmapped address generates an illegal

address reset. The SIM verifies that the CPU is fetching an opcode prior

to asserting the ILAD bit in the SIM reset status register SRSR) and

resetting the MCU. A data fetch from an unmapped address does not

generate a reset. The SIM actively pulls down the RST pin for all internal

reset sources.

NOTE: Extra care should be exercised if off-chip code is eventually ported

into another HC08 with a smaller on-chip ROM since some legal

addresses could become illegal addresses on a smaller ROM. It is

the user’s responsibility to check their code for illegal addresses.

Lo w-vo lta g e

The low-voltage inhibit module (LVI) asserts its output to the SIM when

inhib it (LVI) re se t

the V_DDvoltage falls to the LVI_TRIPFvoltage. The LVI bit in the SIM reset

status register (SRSR) is set, and the external reset pin (RST) is held low

while the SIM counter counts out 4096 CGMXCLK cycles. 64 CGMXCLK

cycles later, the CPU is released from reset to allow the reset vector

sequence to occur. The SIM actively pulls down the RST pin for all

internal reset sources.

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SIM counter

The SIM counter is used by the power-on reset module (POR) and in

STOP mode recovery to allow the oscillator time to stabilize before

enabling the internal bus (IBUS) clocks. The SIM counter also serves as

a prescaler for the computer operating properly (COP) module. The SIM

counter overflow supplies the clock for the COP module. The SIM

counter is 13 bits long and is clocked by the falling edge of CGMXCLK.

SIMcounterduring

power-on reset

The power-on reset (POR) module detects power applied to the MCU.

At power-on, the POR circuit asserts the signal PORRST. Once the SIM

is initialized, it enables the clock generation module (CGM) to drive the

bus clock state machine.

SIMcounterduring

STOP mode

recovery

The SIM counter is also used for STOP mode recovery. The STOP

instruction clears the SIM counter. After an interrupt, break, or reset, the

SIM senses the state of the short STOP recovery bit, SSREC, in the

mask option register. If the SSREC bit is a logic ‘1’, then the STOP

recovery is reduced from the normal delay of 4096 CGMXCLK cycles

down to 32 CGMXCLK cycles. This is ideal for applications using canned

oscillators that do not require long start-up times from STOP mode.

External crystal applications should use the full STOP recovery time,

that is, with SSREC cleared.

SIM counter and

reset states

External reset has no effect on the SIM counter. (See STOP mode on

page 102. for details). The SIM counter is free-running after all reset

states, see Active resets from internal sources on page 91 for counter

control and internal reset recovery sequences.

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Exception control

Normal, sequential program execution can be changed in three different

ways:

• Interrupts

– Maskable hardware CPU interrupts

– Non-maskable software interrupt instruction (SWI)

• Reset

• Break interrupts

Interrupts

At the beginning of an interrupt, the CPU saves the CPU register

contents onto the stack and sets the interrupt mask (I-bit) to prevent

additional interrupts. At the end of an interrupt, the RTI instruction

recovers the CPU register contents from the stack so that normal

processing can resume. Figure 7 shows interrupt entry timing, and

Figure 9 shows interrupt recovery timing.

MODULE

INTERRUPT

I-bit

IAB

IDB

VECT L

STARTADDRESS

DUMMY

SP

SP – 1

SP – 2

SP – 3

SP – 4

VECT H

PC–1[7:0]

V DATA H V DATA L

PC–1[15:8]

DUMMY

X

A

CCR

OPCODE

R/W

Figure 7. Interrupt entry

Interrupts are latched, and arbitration is performed in the SIM at the start

of interrupt processing. The arbitration result is a constant that the CPU

uses to determine which vector to fetch. Once an interrupt is latched by

the SIM, no other interrupt may take precedence, regardless of priority,

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Exception control

until the latched interrupt is serviced (or the I-bit is cleared). See Figure

8.

FROM RESET

BREAK

YES

INTERRUPT?

I BIT SET?

NO

YES

I-BIT SET?

NO

IRQ

INTERRUPT?

YES

NO

STACK CPU REGISTERS.

SET I-BIT.

LOAD PC WITH INTERRUPT VECTOR.

(As many interrupts as exist on chip)

FETCH NEXT

INSTRUCTION.

YES

SWI

INSTRUCTION?

NO

YES

UNSTACK CPU REGISTERS.

EXECUTE INSTRUCTION.

RTI

INSTRUCTION?

NO

Figure 8. Interrupt processing

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MODULE

INTERRUPT

I-BIT

IAB

IDB

R/W

SP – 2

SP – 4

SP – 3

SP – 1

SP

PC

PC + 1

CCR

A

X

PC–1[7:0] PC–1[15:8] OPCODE OPERAND

Figure 9. Interrupt recovery

Ha rd wa re

inte rrup ts

Processing of a hardware interrupt begins after completion of the current

instruction. When the instruction is complete, the SIM checks all pending

hardware interrupts. If interrupts are not masked (I-bit clear in the

condition code register), and if the corresponding interrupt enable bit is

set, the SIM proceeds with interrupt processing; otherwise, the next

instruction is fetched and executed.

If more than one interrupt is pending at the end of an instruction

execution, the highest priority interrupt is serviced first. Figure 9

demonstrates what happens when two interrupts are pending. If an

interrupt is pending upon exit from the original interrupt service routine,

the pending interrupt is serviced before the LDA instruction is executed.

The LDA opcode is prefetched by both the INT1 and INT2 RTI

instructions. However, in the case of the INT1 RTI prefetch, this is a

redundant operation.

NOTE: To maintain compatibility with the M6805 Family, the H register is not

pushed on the stack during interrupt entry. If the interrupt service routine

modifies the H register or uses the indexed addressing mode, software

should save the H register and then restore it prior to exiting the routine.

SWI instruc tio n

The SWI instruction is a non-maskable instruction that causes an

interrupt regardless of the state of the interrupt mask (I-bit) in the

condition code register.

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Break interrupts

CLI

LDA #$FF

BACKGROUND ROUTINE

INT1

PSHH

INT1 INTERRUPT SERVICE ROUTINE

PULH

RTI

INT2

PSHH

INT2 INTERRUPT SERVICE ROUTINE

PULH

RTI

Figure 10. Interrupt recognition example

NOTE: A software interrupt pushes PC onto the stack. A software interrupt does

not push PC – 1, as a hardware interrupt does.

Reset

All reset sources always have equal and highest priority and cannot be

arbitrated.

Break interrupts

The break module can stop normal program flow at a

software-programmable break point by asserting its break interrupt

output. See Break Module on page 139. The SIM puts the CPU into the

break state by forcing it to the SWI vector location. Refer to the break

interrupt subsection of each module to see how each module is affected

by the break state.

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Status flag

protection in

break mode

The SIM controls whether status flags contained in other modules can

be cleared during break mode. The user can select whether flags are

protected from being cleared by properly initializing the break clear flag

enable bit (BCFE) in the SIM break flag control register (SBFCR).

Protecting flags in break mode ensures that set flags will not be cleared

while in break mode. This protection allows registers to be freely read

and written during break mode without losing status flag information.

Setting the BCFE bit enables the clearing mechanisms. Once cleared in

break mode, a flag remains cleared even when break mode is exited.

Status flags with a two-step clearing mechanism — for example, a read

of one register followed by the read or write of another — are protected,

even when the first step is accomplished prior to entering break mode.

Upon leaving break mode, execution of the second step will clear the

flag as normal.

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System Integration Module (SIM)

Low-power modes

Executing the STOP/WAIT instruction puts the MCU in a

low-power-consumption mode for standby situations. The SIM holds the

CPU in a non-clocked state. The operation of each of these modes is

described below. Both STOP and WAIT clear the interrupt mask (I) in the

condition code register, allowing interrupts to occur.

WAIT mode

In WAIT mode, the CPU clocks are inactive while the peripheral clocks

continue to run. Figure 11 shows the timing for WAIT mode entry.

A module that is active during WAIT mode can wake up the CPU with an

interrupt if the interrupt is enabled. Stacking for the interrupt begins one

cycle after the WAIT instruction during which the interrupt occurred. In

WAIT mode, the CPU clocks are inactive. Refer to the WAIT mode

subsection of each module to see if the module is active or inactive in

WAIT mode. Some modules can be programmed to be active in WAIT

mode.

WAIT mode can also be exited by a reset or break. A break interrupt

during WAIT mode sets the SIM break STOP/WAIT bit, SBSW, in the

SIM break status register (SBSR). If the COP disable bit, COPD, in the

mask option register is ‘0’, then the computer operating properly (COP)

module is enabled and remains active in WAIT mode.

IAB

IDB

R/W

WAIT ADDR

WAIT ADDR + 1

SAME

PREVIOUS DATA

SAME

NEXT OPCODE

NOTE: Previous data can be operand data or the WAIT opcode, depending on the

last instruction.

Figure 11. WAIT mode entry timing

Figure 11 and Figure 13 show the timing for WAIT recovery.

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IAB

$6E0B

$A6

$6E0C

$00FF

$00FE

$00FD

$00FC

IDB $A6

$A6

$01

$0B

$6E

EXITSTOPWAIT

NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt

Figure 12. WAIT recovery from interrupt or break

32

Cycles

32

Cycles

IAB

$6E0B

$A6

RST VCT L

RST VCT H

IDB $A6

RST

$A6

CGMXCLK

Figure 13. WAIT recovery from internal reset

STOP mode

In STOP mode, the SIM counter is reset and the system clocks are

disabled. An interrupt request from a module can cause an exit from

STOP mode. Stacking for interrupts begins after the selected STOP

recovery time has elapsed. Reset or break also causes an exit from

STOP mode.

The SIM disables the clock generator module outputs (CGMOUT and

CGMXCLK) in STOP mode, stopping the CPU and peripherals. STOP

recovery time is selectable using the SSREC bit in the mask option

register (MOR). If SSREC is set, STOP recovery is reduced from the

normal delay of 4096 CGMXCLK cycles down to 32. This is ideal for

applications using canned oscillators that do not require long start-up

times from STOP mode.

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System Integration Module (SIM)

Low-power modes

NOTE: External crystal applications should use the full STOP recovery time by

clearing the SSREC bit.

A break interrupt during STOP mode sets the SIM break STOP/WAIT bit

(SBSW) in the SIM break status register (SBSR).

The SIM counter is held in reset from the execution of the STOP

instruction until the beginning of STOP recovery. It is then used to time

the recovery period. Figure 14 shows STOP mode entry timing.

CPUSTOP

IAB

IDB

R/W

STOP ADDR

STOP ADDR + 1

SAME

PREVIOUS DATA

NEXT OPCODE

SAME

NOTE: Previous data can be operand data or the STOP opcode, depending on the last

instruction.

Figure 14. STOP mode entry timing

STOP RECOVERY PERIOD

CGMXCLK

INT/BREAK

IAB

STOP + 2 STOP + 2

SP

SP – 1

SP – 2

SP – 3

STOP +1

Figure 15. STOP mode recovery from interrupt or break

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System Integration Module (SIM)

SIM registers

The SIM has three memory mapped registers. Table 4 shows the

mapping of these registers.

Table 4. SIM Registers

Address

$FE00

$FE01

$FE03

Register

SBSR

Access mode

User

SRSR

User

SBFCR

User

SIM break status

register (SBSR)

The SIM break status register contains a flag to indicate that a break

caused an exit from STOP or WAIT mode.

Bit 7

R

6

5

4

3

2

1

Bit 0

R

Read:

Write:

Reset:

SBSW

SBSR

$FE00

R

(1)

Note

0

R

= Reserved for factory test

1. Writing a logic ‘0’ clears SBSW.

Figure 16. SIM break status register (SBSR)

SBSW — SIM Break STOP/WAIT

This status bit is useful in applications requiring a return to STOP or

WAIT mode after exiting from a break interrupt. SBSW can be cleared

by writing a logic ‘0’ to it. Reset clears SBSW.

1 = STOP or WAIT mode was exited by break interrupt

0 = STOP or WAIT mode was not exited by break interrupt

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SIM registers

SBSW can be read within the break state SWI routine. The user can

modify the return address on the stack by subtracting one from it. The

following code is an example of this.

; This code works if the H register has been pushed onto the stack in the break

; service routine software. This code should be executed at the end of the

; break service routine software.

HIBYTE EQU

LOBYTE EQU

5

6

;

If not SBSW, do RTI

BRCLR SBSW,SBSR, RETURN ; See if STOP or WAIT mode was exited by

; break.

TST

BNE

DEC

LOBYTE,SP

DOLO

; If RETURNLO is not ‘0’,

; then just decrement low byte.

; Else deal with high byte, too.

; Point to STOP/WAIT opcode.

; Restore H register.

HIBYTE,SP

LOBYTE,SP

DOLO

RETURN PULH

RTI

SIM reset status

register (SRSR)

This register contains six flags that show the source of the last reset. The

SIM reset status register can be cleared by reading it. A power-on reset

sets the POR bit and clears all other bits in the register.

Bit 7

6

5

4

3

2

1

Bit 0

0

Read:

Write:

POR:

POR

COP

ILOP

ILAD

0

LVI

SRSR

$FE01

1

0

= Unimplemented

Figure 17. SIM reset status register (SRSR)

POR — Power-on reset bit

1 = Last reset caused by POR circuit

0 = Read of SRSR

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PIN — External reset bit

1 = Last reset caused by external reset pin (RST)

0 = POR or read of SRSR

COP — Computer operating properly reset bit

1 = Last reset caused by COP counter

0 = POR or read of SRSR

ILOP — Illegal opcode reset bit

1 = Last reset caused by an illegal opcode

0 = POR or read of SRSR

ILAD — Illegal address reset bit (opcode fetches only)

1 = Last reset caused by an opcode fetch from an illegal address

0 = POR or read of SRSR

LVI — Low-voltage inhibit reset bit

1 = Last reset was caused by the LVI circuit

0 = POR or read of SRSR

SIM break flag

control register

(SBFCR)

The SIM break control register contains a bit that enables software to

clear status bits while the MCU is in a break state.

Bit 7

6

5

4

3

2

1

Bit 0

R

Read:

Write:

Reset:

SBFCR

$FE03

BCFE

R

0

= Reserved for factory test

R

Figure 18. SIM break flag control register (SBFCR)

BCFE — break clear flag enable bit

This read/write bit enables software to clear status bits by accessing

status registers while the MCU is in a break state. To clear status bits

during the break state, the BCFE bit must be set.

1 = Status bits clearable during break

0 = Status bits not clearable during break

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Clock Generator Module (CGM)

CGM

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Crystal oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Phase-locked loop (PLL) circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 111

PLL circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Acquisition and tracking modes . . . . . . . . . . . . . . . . . . . . . . . . 113

Manual and automatic PLL bandwidth modes . . . . . . . . . . . . . 113

Programming the PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Special programming exceptions . . . . . . . . . . . . . . . . . . . . . . . 116

Base clock selector circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

CGM external connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Crystal amplifier input pin (OSC1) . . . . . . . . . . . . . . . . . . . . . . . . 118

Crystal amplifier output pin (OSC2) . . . . . . . . . . . . . . . . . . . . . . . 118

External filter capacitor pin (CGMXFC). . . . . . . . . . . . . . . . . . . . . 118

PLL analog power pin (VDDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Oscillator enable signal (SIMOSCEN) . . . . . . . . . . . . . . . . . . . . . 119

Crystal output frequency signal (CGMXCLK) . . . . . . . . . . . . . . . . 119

CGM base clock output (CGMOUT) . . . . . . . . . . . . . . . . . . . . . . . 119

CGM CPU interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

CGM registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

PLL control register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

PLL Bandwidth control register (PBWC). . . . . . . . . . . . . . . . . . . . 123

PLL Programming register (PPG). . . . . . . . . . . . . . . . . . . . . . . . . 125

Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Special modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

WAIT mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

CGM during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Acquisition/lock time specifications. . . . . . . . . . . . . . . . . . . . . . . . . . 130

Acquisition/lock time definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 130

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Parametric influences on reaction time. . . . . . . . . . . . . . . . . . . . .131

Choosing a filter capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

Reaction time calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

Introduction

This section describes the clock generator module (CGM). The CGM

generates the crystal clock signal, CGMXCLK, which operates at the

frequency of the crystal. The CGM also generates the base clock signal,

CGMOUT, from which the system integration module (SIM) derives the

system clocks. CGMOUT is based on either the crystal clock divided by

two or the phase-locked loop (PLL) clock, CGMVCLK, divided by two.

The PLL is a frequency generator designed for use with 1MHz to 8MHz

crystals or ceramic resonators. The PLL can generate an 8MHz bus

frequency from an 8 MHz or a 4 MHz crystal.

Features

Features of the CGM include the following:

• Phase-locked loop with output frequency in integer multiples of the

crystal reference

• Programmable hardware voltage-controlled oscillator (VCO) for

low-jitter operation

• Automatic bandwidth control mode for low-jitter operation

• Automatic frequency lock detector

• CPU interrupt on entry or exit from locked condition

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Clock Generator Module (CGM)

Functional description

The CGM consists of three major submodules:

• Crystal oscillator circuit which generates the constant crystal

frequency clock, CGMXCLK.

• Phase-locked loop (PLL) which generates the programmable

VCO frequency clock CGMVCLK.

• Base clock selector circuit; this software-controlled circuit selects

either CGMXCLK divided by two or the VCO clock CGMVCLK

divided by two, as the base clock CGMOUT. The SIM derives the

system clocks from CGMOUT.

Figure 1 shows the structure of the CGM.

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CRYSTAL OSCILLATOR

OSC2

CGMXCLK

A

TO SIM, SCI, msCAN

CLOCK

SELECT

CIRCUIT

OSC1

CGMOUT

÷2

TO SIM

B

S*

*When S = 1, CGMOUT = B

SIMOSCEN

CGMRDV

CGMRCLK

BCS

USER MODE

PTC3

V_DDA

CGMXFC

V_SS

VRS[7:4]

MONITOR MODE

VOLTAGE

CONTROLLED

OSCILLATOR

PHASE

DETECTOR

LOOP

FILTER

PLL ANALOG

CGMINT

LOCK

DETECTOR

BANDWIDTH

CONTROL

INTERRUPT

CONTROL

LOCK

AUTO

ACQ

PLLIE

PLLF

MUL[7:4]

CGMVDV

CGMVCLK

FREQUENCY

DIVIDER

Figure 1. CGM block diagram

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Functional description

Register Name

Bit 7

6

5

4

3

2

1

Bit 0

1

PLLF

1

PLL Control Register (PCTL)

PLLIE

PLLON BCS

LOCK

0

PLL Bandwidth Control Register (PBWC)

PLL Programming Register (PPG)

AUTO

ACQ

XLD

MUL7 MUL6 MUL5 MUL4 VRS7 VRS6 VRS5 VRS4

= Unimplemented

Figure 2. CGM I/O register summary

Crystal oscillator

circuit

The crystal oscillator circuit consists of an inverting amplifier and an

external crystal. The OSC1 pin is the input to the amplifier and the OSC2

pin is the output. The SIMOSCEN signal from the system integration

module (SIM) enables the crystal oscillator circuit.

The CGMXCLK signal is the output of the crystal oscillator circuit and

runs at a rate equal to the crystal frequency. CGMXCLK is then buffered

to produce CGMRCLK, the PLL reference clock.

CGMXCLK can be used by other modules which require precise timing

for operation. The duty cycle of CGMXCLK is not guaranteed to be 50%

and depends on external factors, including the crystal and related

external components.

An externally generated clock can also feed the OSC1 pin of the crystal

oscillator circuit. For this configuration, the external clock should be

connected to the OSC1 pin and the OSC2 pin allowed to float.

Phase-locked

loop (PLL) circuit

The PLL is a frequency generator that can operate in either acquisition

mode or tracking mode, depending on the accuracy of the output

frequency. The PLL can change between acquisition and tracking

modes either automatically or manually.

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Clock Generator Module (CGM)

PLL c irc uits

The PLL consists of the following circuits:

• Voltage-controlled oscillator (VCO)

• Modulo VCO frequency divider

• Phase detector

• Loop filter

• Lock detector

The operating range of the VCO is programmable for a wide range of

frequencies and for maximum immunity to external noise, including

supply and CGMXFC noise. The VCO frequency is bound to a range

from roughly one-half to twice the center-of-range frequency, f_VRS

.

Modulating the voltage on the CGMXFC pin changes the frequency

within this range. By design, f_VRSis equal to the nominal center-of-range

frequency, f_NOM, (4.9152MHz) times a linear factor L, or (L)f_NOM

.

CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK.

CGMRCLK runs at a frequency f_RCLK, and is fed to the PLL through a

buffer. The buffer output is the final reference clock, CGMRDV, running

at a frequency f_RDV= f_RCLK

.

The VCO’s output clock, CGMVCLK, running at a frequency f_VCLK, is fed

back through a programmable modulo divider. The modulo divider

reduces the VCO clock by a factor N. The divider’s output is the VCO

feedback clock, CGMVDV, running at a frequency f_VDV= f_VCLK/N. (See

Programming the PLL on page 115 for more information).

The phase detector then compares the VCO feedback clock, CGMVDV,

with the final reference clock, CGMRDV. A correction pulse is generated

based on the phase difference between the two signals. The loop filter

then slightly alters the DC voltage on the external capacitor connected

to CGMXFC based on the width and direction of the correction pulse.

The filter can make fast or slow corrections depending on its mode,

described in Acquisition and tracking modes on page 113. The value of

the external capacitor and the reference frequency determines the

speed of the corrections and the stability of the PLL.

The lock detector compares the frequencies of the VCO feedback clock,

CGMVDV, and the final reference clock, CGMRDV. Therefore, the

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Functional description

speed of the lock detector is directly proportional to the final reference

frequency f_RDV. The circuit determines the mode of the PLL and the lock

condition based on this comparison.

Ac q uisitio n a nd

tra c king m o d e s

The PLL filter is manually or automatically configurable into one of two

operating modes:

• Acquisition mode — in acquisition mode, the filter can make large

frequency corrections to the VCO. This mode is used at PLL

start-up or when the PLL has suffered a severe noise hit and the

resulting VCO frequency is much different from the desired

frequency. When in acquisition mode, the ACQ bit is clear in the

PLL bandwidth control register. See PLL Bandwidth control

register (PBWC) on page 123

• Tracking mode — in tracking mode, the filter makes only small

corrections to the frequency of the VCO. PLL jitter is much lower

in tracking mode, but the response to noise is also slower. The

PLL enters tracking mode when the VCO frequency is nearly

correct, such as when the PLL is selected as the base clock

source. See Base clock selector circuit on page 116 The PLL is

automatically in tracking mode when not in acquisition mode or

when the ACQ bit is set.

Ma nua l a nd

a uto m a tic PLL

b a nd wid th m o d e s

The PLL can change the bandwidth or operational mode of the loop filter

manually or automatically.

In automatic bandwidth control mode (AUTO = 1), the lock detector

automatically switches between acquisition and tracking modes.

Automatic bandwidth control mode is used also to determine when the

VCO clock, CGMVCLK, is safe to use as the source for the base clock,

CGMOUT. See PLL Bandwidth control register (PBWC) on page 123 If

PLL interrupts are enabled, the software can wait for a PLL interrupt

request and then check the LOCK bit. If interrupts are disabled, software

can poll the LOCK bit continuously (during PLL start-up, usually) or at

periodic intervals. In either case, when the LOCK bit is set, the VCO

clock is safe to use as the source for the base clock. See Base clock

selector circuit. If the VCO is selected as the source for the base clock

and the LOCK bit is clear, the PLL has suffered a severe noise hit and

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the software must take appropriate action, depending on the application.

(See Interrupts on page 127 for information and precautions on using

interrupts). The following conditions apply when the PLL is in automatic

bandwidth control mode:

• The ACQ bit (see PLL Bandwidth control register (PBWC) on page

123) is a read-only indicator of the mode of the filter, see

Acquisition and tracking modes on page 113.

• The ACQ bit is set when the VCO frequency is within a certain

tolerance ∆_TRKand is cleared when the VCO frequency is out with

a certain tolerance ∆_UNT. (See Acquisition/lock time specifications

on page 130).

• The LOCK bit is a read-only indicator of the locked state of the

PLL.

• The LOCK bit is set when the VCO frequency is within a certain

tolerance ∆_LOCKand is cleared when the VCO frequency is

outgrowth a certain tolerance ∆_UNL. (See Acquisition/lock time

specifications on page 130).

• CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s

lock condition changes, toggling the LOCK bit. (See PLL control

register (PCTL) on page 121).

The PLL also may operate in manual mode (AUTO = 0). Manual mode

is used by systems that do not require an indicator of the lock condition

for proper operation. Such systems typically operate well below f_BUSMAX

and require fast start-up. The following conditions apply when in manual

mode:

• ACQ is a writable control bit that controls the mode of the filter.

Before turning on the PLL in manual mode, the ACQ bit must be

clear.

• Before entering tracking mode (ACQ = 1), software must wait a

given time, t_ACQ(see Acquisition/lock time specifications on page

130), after turning on the PLL by setting PLLON in the PLL control

register (PCTL).

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Functional description

• Software must wait a given time, t_AL, after entering tracking mode

before selecting the PLL as the clock source to CGMOUT (BCS =

1).

• The LOCK bit is disabled.

• CPU interrupts from the CGM are disabled.

Pro g ra m m ing the

PLL

The following procedure shows how to program the PLL.

NOTE: The round function in the following equations means that the real

number should be rounded to the nearest integer number.

1. Choose the desired bus frequency, f_BUSDES

.

2. Calculate the desired VCO frequency (four times the

desired bus frequency).

f

= 4 × f

BUDES

VCLKDES

3. Choose a practical PLL reference frequency, f_RCLK

4. Select a VCO frequency multiplier, N.

.

f

VCLKDES

--------------------------

N = round

f

RCLK

5. Calculate and verify the adequacy of the VCO and bus

frequencies f_VCLKand f_BUS

.

f

= N × f

RCLK

VCLK

f

= (f

) ⁄ 4

VCLK

BUS

6. Select a VCO linear range multiplier, L.

f

VCLK

----------------

L = round

f

NOM

where f_NOM= 4.9152MHz

7. Calculate and verify the adequacy of the VCO programmed

center-of-range frequency f_VRS

.

f_VRS= (L)f_NOM

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8. Verify the choice of N and L by comparing f_VCLKto f_VRSand

f_VCLKDES. For proper operation, f_VCLKmust be within the

application’s tolerance of f_VCLKDES, and f_VRSmust be as close

as possible to f_VCLK

.

NOTE: Exceeding the recommended maximum bus frequency or VCO

frequency can cause the MCU to “crash”.

9. Program the PLL registers accordingly:

a. In the upper 4 bits of the PLL programming register

(PPG), program the binary equivalent of N.

b. In the lower 4 bits of the PLL programming register

(PPG), program the binary equivalent of L.

Sp e c ia l

The programming method described in Programming the PLL on page

p ro g ra m m ing

e xc e p tio ns

115, does not account for two possible exceptions — a value of zero for

N or L is meaningless when used in the equations given. To account for

these exceptions:

• A zero value for N is interpreted exactly the same as a value of

one.

• A zero value for L disables the PLL and prevents its selection as

the source for the base clock. (See Base clock selector circuit on

page 116).

Base clock

selector circuit

This circuit is used to select either the crystal clock, CGMXCLK, or the

VCO clock, CGMVCLK, as the source of the base clock, CGMOUT. The

two input clocks go through a transition control circuit that waits up to

three CGMXCLK cycles and three CGMVCLK cycles to change from

one clock source to the other. During this time, CGMOUT is held in

stasis. The output of the transition control circuit is then divided by two

to correct the duty cycle. Therefore, the bus clock frequency, which is

one-half of the base clock frequency, is one-fourth the frequency of the

selected clock (CGMXCLK or CGMVCLK).

The BCS bit in the PLL control register (PCTL) selects which clock drives

CGMOUT. The VCO clock cannot be selected as the base clock source

if the PLL is not turned on. The PLL cannot be turned off if the VCO clock

is selected. The PLL cannot be turned on or off simultaneously with the

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Functional description

selection or deselection of the VCO clock. The VCO clock also cannot

be selected as the base clock source if the factor L is programmed to a

zero. This value would set up a condition inconsistent with the operation

of the PLL, so that the PLL would be disabled and the crystal clock would

be forced as the source of the base clock.

CGM external

connections

In its typical configuration, the CGM requires seven external

components. Five of these are for the crystal oscillator and two are for

the PLL.

The crystal oscillator is normally connected in a Pierce oscillator

configuration, as shown in Figure 3. This figure shows only the logical

representation of the internal components and may not represent actual

circuitry. The oscillator configuration uses five components:

• Crystal, X

1

• Fixed capacitor, C

1

• Tuning capacitor, C (can also be a fixed capacitor)

2

• Feedback resistor, R_B

• Series resistor, R_S(optional)

The series resistor (R_S) is included in the diagram to follow strict Pierce

oscillator guidelines and may not be required for all ranges of operation,

especially with high frequency crystals. Refer to the crystal

manufacturer’s data for more information.

Figure 3 also shows the external components for the PLL:

• Bypass capacitor, C_BYP

• Filter capacitor, C_F

Care should be taken with routing in order to minimize signal cross talk

and noise. See Acquisition/lock time specifications on page 130 for

routing information and more information on the filter capacitor’s value

and its effects on PLL performance.

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Clock Generator Module (CGM)

SIMOSCEN

CGMXCLK

OSC1

V

CGMXFC

C_F

V

DDA

SSA

V_DD

*

R_S

C_BYP

R

B

X

1

C

2

1

*R_Scan be zero (shorted) when used with higher-frequency crystals. Refer to manufacturer’s data.

Figure 3. CGM external connections

I/O Signals

The following paragraphs describe the CGM I/O signals.

The OSC1 pin is an input to the crystal oscillator amplifier.

Crystal amplifier

input pin (OSC1)

Crystal amplifier

The OSC2 pin is the output of the crystal oscillator inverting amplifier.

output pin (OSC2)

External filter

capacitor pin

(CGMXFC)

The CGMXFC pin is required by the loop filter to filter out phase

corrections. A small external capacitor is connected to this pin.

NOTE: To prevent noise problems, C_Fshould be placed as close to the

CGMXFC pin as possible, with minimum routing distances and no

routing of other signals across the C_Fconnection.

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I/O Signals

PLL analog power

pin (V

V

is a power pin used by the analog portions of the PLL. The pin

DDA

)

should be connected to the same voltage potential as the V_DDpin.

DDA

NOTE: Route V

carefully for maximum noise immunity and place bypass

DDA

capacitors as close as possible to the package.

Oscillator enable

signal (SIMOSCEN)

The SIMOSCEN signal comes from the system integration module (SIM)

and enables the oscillator and PLL.

Crystal output

frequency signal

(CGMXCLK)

CGMXCLK is the crystal oscillator output signal. It runs at the full speed

of the crystal (f_XCLK) and is generated directly from the crystal oscillator

circuit. Figure 1 shows only the logical relation of CGMXCLK to OSC1

and OSC2 and may not represent the actual circuitry. The duty cycle of

CGMXCLK is unknown and may depend on the crystal and other

external factors. Also, the frequency and amplitude of CGMXCLK can be

unstable at start-up.

CGM base clock

output (CGMOUT)

CGMOUT is the clock output of the CGM. This signal goes to the SIM,

which generates the MCU clocks. CGMOUT is a 50% duty cycle clock

running at twice the bus frequency. CGMOUT is software programmable

to be either the oscillator output (CGMXCLK) divided by two or the VCO

clock (CGMVCLK) divided by two.

CGM CPU interrupt

(CGMINT)

CGMINT is the interrupt signal generated by the PLL lock detector.

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CGM registers

The following registers control and monitor operation of the CGM:

• PLL control register (PCTL). (See PLL control register (PCTL) on

page 121).

• PLL bandwidth control register (PBWC). (See PLL Bandwidth

control register (PBWC) on page 123).

• PLL programming register (PPG). (See PLL Programming register

(PPG) on page 125).

Figure 4 is a summary of the CGM registers.

Bit 7

6

5

4

3

2

1

Bit 0

1

Read:

Write:

Read:

Write:

Read:

Write:

PLLF

1

PCTL

$001C

PLLIE

PLLON

BCS

LOCK

MUL6

0

PBWC

$001D

AUTO

MUL7

ACQ

XLD

PPG

$001E

MUL5

MUL4

VRS7

VRS6

VRS5

VRS4

= Unimplemented

NOTES:

1. When AUTO = 0, PLLIE is forced to logic zero and is read-only.

2. When AUTO = 0, PLLF and LOCK read as logic zero.

3. When AUTO = 1, ACQ is read-only.

4. When PLLON = 0 or VRS[7:4] = $0, BCS is forced to logic zero and is read-only.

5. When PLLON = 1, the PLL programming register is read-only.

6. When BCS = 1, PLLON is forced set and is read-only.

Figure 4. CGM I/O Register Summary

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CGM registers

PLL control register

(PCTL)

The PLL control register contains the interrupt enable and flag bits, the

on/off switch, and the base clock selector bit.

Bit 7

PLLIE

0

6

5

PLLON

1

4

BCS

0

3

2

1

Bit 0

1

Read:

Write:

Reset:

PLLF

1

PCTL

$001C

0

1

= Unimplemented

Figure 5. PLL control register (PCTL)

PLLIE — PLL interrupt enable bit

This read/write bit enables the PLL to generate an interrupt request

when the LOCK bit toggles, setting the PLL flag, PLLF. When the

AUTO bit in the PLL bandwidth control register (PBWC) is clear,

PLLIE cannot be written and reads as ‘0’. Reset clears the PLLIE bit.

1 = PLL interrupts enabled

0 = PLL interrupts disabled

PLLF — PLL interrupt flag bit

This read-only bit is set whenever the LOCK bit toggles. PLLF

generates an interrupt request if the PLLIE bit is set also. PLLF

always reads as ‘0’ when the AUTO bit in the PLL bandwidth control

register (PBWC) is clear. The PLLF bit should be cleared by reading

the PLL control register. Reset clears the PLLF bit.

1 = Change in lock condition

0 = No change in lock condition

NOTE: The PLLF bit should not be inadvertently cleared. Any read or

read-modify-write operation on the PLL control register clears the PLLF

bit.

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PLLON — PLL on bit

This read/write bit activates the PLL and enables the VCO clock,

CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the

base clock, CGMOUT (BCS = 1). See Base clock selector circuit on

page 116 Reset sets this bit so that the loop can stabilize as the MCU

is powering up.

1 = PLL on

0 = PLL off

BCS — Base clock select bit

This read/write bit selects either the crystal oscillator output,

CGMXCLK, or the VCO clock, CGMVCLK, as the source of the CGM

output, CGMOUT. CGMOUT frequency is one-half the frequency of

the selected clock. BCS cannot be set while the PLLON bit is clear.

After toggling BCS, it may take up to three CGMXCLK and three

CGMVCLK cycles to complete the transition from one source clock to

the other. During the transition, CGMOUT is held in stasis. See Base

clock selector circuit on page 116 Reset and the STOP instruction

clear the BCS bit.

1 = CGMOUT driven by CGMVCLK/2

0 = CGMOUT driven by CGMXCLK/2

NOTE: PLLON and BCS have built-in protection that prevents the base clock

selector circuit from selecting the VCO clock as the source of the base

clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS

is set, and BCS cannot be set when PLLON is clear. If the PLL is off

(PLLON = 0), selecting CGMVCLK requires two writes to the PLL control

register. See Base clock selector circuit on page 116

PCTL[3:0] — Unimplemented bits

These bits provide no function and always read as ‘1’.

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CGM registers

PLL Bandwidth

control register

(PBWC)

The PLL bandwidth control register does the following:

• Selects automatic or manual (software-controlled) bandwidth

control mode

• Indicates when the PLL is locked

• In automatic bandwidth control mode, indicates when the PLL is in

acquisition or tracking mode

• In manual operation, forces the PLL into acquisition or tracking

mode

Bit 7

AUTO

0

6

5

ACQ

0

4

XLD

0

3

2

1

Bit 0

0

Read:

Write:

Reset:

LOCK

0

PBWC

$001D

0

= Unimplemented

Figure 7. PLL bandwidth control register (PBWC)

AUTO — Automatic bandwidth control bit

This read/write bit selects automatic or manual bandwidth control.

When initializing the PLL for manual operation (AUTO = 0), the ACQ

bit should be cleared before turning the PLL on. Reset clears the

AUTO bit.

1 = Automatic bandwidth control

0 = Manual bandwidth control

LOCK — Lock indicator bit

When the AUTO bit is set, LOCK is a read-only bit that becomes set

when the VCO clock CGMVCLK, is locked (running at the

programmed frequency). When the AUTO bit is clear, LOCK reads as

‘0’ and has no meaning. Reset clears the LOCK bit.

1 = VCO frequency correct or locked

0 = VCO frequency incorrect or unlocked

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ACQ — Acquisition mode bit

When the AUTO bit is set, ACQ is a read-only bit that indicates

whether the PLL is in acquisition mode or tracking mode. When the

AUTO bit is clear, ACQ is a read/write bit that controls whether the

PLL is in acquisition or tracking mode.

In automatic bandwidth control mode (AUTO = 1), the last-written

value from manual operation is stored in a temporary location and is

recovered when manual operation resumes. Reset clears this bit,

enabling acquisition mode.

1 = Tracking mode

0 = Acquisition mode

XLD — Crystal loss detect bit

When the VCO output, CGMVCLK, is driving CGMOUT, this

read/write bit indicates whether the crystal reference frequency

is active or not. To check the status of the crystal reference, the

following procedure should be followed:

1. Write a ‘1’ to XLD.

2. Wait 4 × N cycles. (N is the VCO frequency multiplier.)

3. Read XLD.

1 = Crystal reference is not active

0 = Crystal reference is active

The crystal loss detect function works only when the BCS bit is set,

selecting CGMVCLK to drive CGMOUT. When BCS is clear, XLD

always reads as ‘0’.

PBWC[3:0] — Reserved for test

These bits enable test functions not available in user mode. To ensure

software portability from development systems to user applications,

software should write zeros to PBWC[3:0] whenever writing to PBWC.

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CGM registers

PLL Programming

register (PPG)

The PLL programming register contains the programming information

for the modulo feedback divider and the programming information for the

hardware configuration of the VCO.

Bit 7

MUL7

0

6

MUL6

1

5

MUL5

1

4

MUL4

0

3

VRS7

0

2

VRS6

1

VRS5

1

Bit 0

VRS4

0

Read:

Write:

Reset:

PPG

$001E

Figure 8. PLL Programming register (PPG)

MUL[7:4] — Multiplier select bits

These read/write bits control the modulo feedback divider that selects

the VCO frequency multiplier, N. (See PLL circuits on page 112 and

Programming the PLL on page 115). A value of $0 in the multiplier

select bits configures the modulo feedback divider the same as a

value of $1. Reset initializes these bits to $6 to give a default multiply

value of 6.

Table 7. VCO frequency multiplier (N) selection

MUL7:MUL6:MUL5:MUL4

VCO Frequency Multiplier (N)

0000

0001

0010

0011

1

2

3

1101

1110

1111

13

14

15

NOTE: The multiplier select bits have built-in protection that prevents them from

being written when the PLL is on (PLLON = 1).

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VRS[7:4] — VCO range select bits

These read/write bits control the hardware center-of-range linear

multiplier L, which controls the hardware center-of-range frequency

f

_VRS. (See PLL circuits on page 112, Programming the PLL on page

115, and PLL control register (PCTL) on page 121).

1 = VRS[7:4] cannot be written when the PLLON bit in the PLL

control register (PCTL) is set. (See Special programming

exceptions on page 116). A value of $0 in the VCO range

select bits disables the PLL and clears the BCS bit in the

PCTL. (See Base clock selector circuit on page 116 and

Special programming exceptions on page 116 for more

information). Reset initializes the bits to $6 to give a default

range multiply value of 6.

NOTE: The VCO range select bits have built-in protection that prevents them

from being written when the PLL is on (PLLON = 1) and prevents

selection of the VCO clock as the source of the base clock (BCS = 1) if

the VCO range select bits are all clear.

The VCO range select bits must be programmed correctly. Incorrect

programming may result in failure of the PLL to achieve lock.

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Interrupts

When the AUTO bit is set in the PLL bandwidth control register (PBWC),

the PLL can generate a CPU interrupt request every time the LOCK bit

changes state. The PLLIE bit in the PLL control register (PCTL) enables

CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL,

becomes set whether interrupts are enabled or not. When the AUTO bit

is clear, CPU interrupts from the PLL are disabled and PLLF reads as ‘0’.

Software should read the LOCK bit after a PLL interrupt request to see

if the request was due to an entry into lock or an exit from lock. When the

PLL enters lock, the VCO clock CGMVCLK, divided by two can be

selected as the CGMOUT source by setting BCS in the PCTL. When the

PLL exits lock, the VCO clock frequency is corrupt, and appropriate

precautions should be taken. If the application is not

frequency-sensitive, interrupts should be disabled to prevent PLL

interrupt service routines from impeding software performance or from

exceeding stack limitations.

NOTE: Software can select CGMVCLK/2 as the CGMOUT source even if the

PLL is not locked (LOCK = 0). Therefore, software should make sure the

PLL is locked before setting the BCS bit.

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Special modes

The WAIT and STOP instructions put the MCU in

low-power-consumption standby modes.

WAIT mode

The WAIT instruction does not affect the CGM. Before entering WAIT

mode, software can disengage and turn off the PLL by clearing the BCS

and PLLON bits in the PLL control register (PCTL). Less power-sensitive

applications can disengage the PLL without turning it off. Applications

that require the PLL to wake the MCU from WAIT mode also can

deselect the PLL output without turning off the PLL.

STOP mode

When the STOP instruction executes, the SIM drives the SIMOSCEN

signal low, disabling the CGM and holding low all CGM outputs

(CGMXCLK, CGMOUT, and CGMINT).

If the STOP instruction is executed with the VCO clock, CGMVCLK,

divided by two driving CGMOUT, the PLL automatically clears the BCS

bit in the PLL control register (PCTL), thereby selecting the crystal clock,

CGMXCLK, divided by two as the source of CGMOUT. When the MCU

recovers from STOP, the crystal clock divided by two drives CGMOUT

and BCS remains clear.

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CGM during break interrupts

The system integration module (SIM) controls whether status bits in

other modules can be cleared during the break state. The BCFE bit in

the SIM break flag control register (SBFCR) enables software to clear

status bits during the break state. See System Integration Module (SIM)

on page 85.

To allow software to clear status bits during a break interrupt, a ‘1’ should

be written to the BCFE bit. If a status bit is cleared during the break state,

it remains cleared when the MCU exits the break state.

To protect the PLLF bit during the break state, write a ‘0’ to the BCFE bit.

With BCFE at ‘0’ (its default state), software can read and write the PLL

control register during the break state without affecting the PLLF bit.

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Acquisition/lock time specifications

The acquisition and lock times of the PLL are, in many applications, the

most critical PLL design parameters. Proper design and use of the PLL

ensures the highest stability and lowest acquisition/lock times.

Acquisition/lock

time definitions

Typical control systems refer to the acquisition time or lock time as the

reaction time of the system, within specified tolerances, to a step input.

In a PLL, the step input occurs when the PLL is turned on or when it

suffers a noise hit. The tolerance is usually specified as a percentage of

the step input or when the output settles to the desired value plus or

minus a percentage of the frequency change. Therefore, the reaction

time is constant in this definition, regardless of the size of the step input.

For example, consider a system with a 5% acquisition time tolerance. If

a command instructs the system to change from 0Hz to 1MHz, the

acquisition time is the time taken for the frequency to reach 1MHz ±

50kHz. 50kHz = 5% of the 1MHz step input. If the system is operating at

1MHz and suffers a –100kHz noise hit, the acquisition time is the time

taken to return from 900kHz to 1MHz ± 5kHz. 5kHz = 5% of the 100kHz

step input.

Other systems refer to acquisition and lock times as the time the system

takes to reduce the error between the actual output and the desired

output to within specified tolerances. Therefore, the acquisition or lock

time varies according to the original error in the output. Minor errors may

not even be registered. Typical PLL applications prefer to use this

definition because the system requires the output frequency to be within

a certain tolerance of the desired frequency regardless of the size of the

initial error.

The discrepancy in these definitions makes it difficult to specify an

acquisition or lock time for a typical PLL. Therefore, the definitions for

acquisition and lock times for this module are as follows:

• Acquisition time, t_ACQ, is the time the PLL takes to reduce the error

between the actual output frequency and the desired output

frequency to less than the tracking mode entry tolerance ∆_TRK

.

Acquisition time is based on an initial frequency error, (f_DES

–

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Acquisition/lock time specifications

f_ORIG)/f_DES, of not more than ±100%. In automatic bandwidth

control mode (see Manual and automatic PLL bandwidth modes

on page 113), acquisition time expires when the ACQ bit becomes

set in the PLL bandwidth control register (PBWC).

• Lock time, t_LOCK, is the time the PLL takes to reduce the error

between the actual output frequency and the desired output

frequency to less than the lock mode entry tolerance ∆_LOCK. Lock

time is based on an initial frequency error, (f_DES– f_ORIG)/f_DES, of not

more than ±100%. In automatic bandwidth control mode, lock time

expires when the LOCK bit becomes set in the PLL bandwidth

control register (PBWC). See Manual and automatic PLL

bandwidth modes on page 113.

Obviously, the acquisition and lock times can vary according to how

large the frequency error is and may be shorter or longer in many cases.

Parametric

influences on

reaction time

Acquisition and lock times are designed to be as short as possible while

still providing the highest possible stability. These reaction times are not

constant, however. Many factors directly and indirectly affect the

acquisition time.

The most critical parameter which affects the reaction times of the PLL

is the reference frequency, f_RDV. This frequency is the input to the phase

detector and controls how often the PLL makes corrections. For stability,

the corrections must be small compared to the desired frequency, so

several corrections are required to reduce the frequency error.

Therefore, the slower the reference the longer it takes to make these

corrections. This parameter is also under user control via the choice of

crystal frequency f_XCLK

.

Another critical parameter is the external filter capacitor. The PLL

modifies the voltage on the VCO by adding or subtracting charge from

this capacitor. Therefore, the rate at which the voltage changes for a

given frequency error (thus change in charge) is proportional to the

capacitor size. The size of the capacitor also is related to the stability of

the PLL. If the capacitor is too small, the PLL cannot make small enough

adjustments to the voltage and the system cannot lock. If the capacitor

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is too large, the PLL may not be able to adjust the voltage in a

reasonable time. See Choosing a filter capacitor on page 132.

Also important is the operating voltage potential applied to V_DDA. The

power supply potential alters the characteristics of the PLL. A fixed value

is best. Variable supplies, such as batteries, are acceptable if they vary

within a known range at very slow speeds. Noise on the power supply is

not acceptable, because it causes small frequency errors which

continually change the acquisition time of the PLL.

Temperature and processing also can affect acquisition time because

the electrical characteristics of the PLL change. The part operates as

specified as long as these influences stay within the specified limits.

External factors, however, can cause drastic changes in the operation of

the PLL. These factors include noise injected into the PLL through the

filter capacitor, filter capacitor leakage, stray impedances on the circuit

board, and even humidity or circuit board contamination.

Choosing a filter

capacitor

As described in Parametric influences on reaction time on page 131, the

external filter capacitor C_Fis critical to the stability and reaction time of

the PLL. The PLL is also dependent on reference frequency and supply

voltage. The value of the capacitor must, therefore, be chosen with

supply potential and reference frequency in mind. For proper operation,

the external filter capacitor must be chosen according to the following

equation:

V

DDA

---------------

C = C

F

FACT

f

RDV

For the value of V_DDA, the voltage potential at which the MCU is operating

should be used. If the power supply is variable, choose a value near the

middle of the range of possible supply values.

This equation does not always yield a commonly available capacitor

size, so round to the nearest available size. If the value is between two

different sizes, choose the higher value for better stability. Choosing the

lower size may seem attractive for acquisition time improvement, but the

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Acquisition/lock time specifications

PLL may become unstable. Also, always choose a capacitor with a tight

tolerance (±20% or better) and low dissipation.

Reaction time

calculation

The actual acquisition and lock times can be calculated using the

equations below. These equations yield nominal values under the

following conditions:

• Correct selection of filter capacitor, C_F, (see Choosing a filter

capacitor on page 132)

• Room temperature operation

• Negligible external leakage on CGMXFC

• Negligible noise

The K factor in the equations is derived from internal PLL parameters.

K

_ACQis the K factor when the PLL is configured in acquisition mode, and

_TRKis the K factor when the PLL is configured in tracking mode. See

Acquisition and tracking modes on page 113.

V

8

DDA

--------------- ---------------

t

=

ACQ

f

K

RDV

ACQ

V

4

DDA

--------------- --------------

t

=

AL

f

K

RDV

RTK

t

= t

+ t

ACQ AL

LOCK

Note the inverse proportionality between the lock time and the reference

frequency.

In automatic bandwidth control mode the acquisition and lock times are

quantized into units based on the reference frequency. <blue>See

Manual and automatic PLL bandwidth modes. A certain number of clock

cycles, n_ACQ, is required to ascertain whether the PLL is within the

tracking mode entry tolerance ∆_TRK, before exiting acquisition mode.

Also, a certain number of clock cycles, n_TRK, is required to ascertain

whether the PLL is within the lock mode entry tolerance ∆_LOCK

.

Therefore, the acquisition time t_ACQ, is an integer multiple of n_ACQ/f_RDV

,

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Clock Generator Module (CGM)

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Clock Generator Module (CGM)

and the acquisition to lock time t_AL, is an integer multiple of n_TRK/f_RDV

.

Also, since the average frequency over the entire measurement period

must be within the specified tolerance, the total time usually is longer

than t_LOCKas calculated above.

In manual mode, it is usually necessary to wait considerably longer than

t_LOCKbefore selecting the PLL clock (see Base clock selector circuit on

page 116), because the factors described in Parametric influences on

reaction time on page 131 may slow the lock time considerably.

Table 8. CGM component speciﬁcations

Characteristic

Symbol Min

Typ.

Max

–

Notes

Crystal load capacitance

Crystal ﬁxed capacitance

C

–

Consult crystal mfg. data

L

C

2 * C

–

f

L

Crystal tuning

capacitance

C

–

Consult crystal mfg. data

2

B

S

L

Feedback bias resistor

Series resistor

R

–

0

–

22MΩ

330kΩ

1M

Ω

Not required

Filter capacitor

C

* (V / f )

DDA XCLK

–

F

FACT

Filter capacitor multiply

factor

C

0.0154 F/sV

F/sV

FACT

C

must provide low

BYP

AC impedance from f =

/100 to 100 *f ,

XCLK

Bypass capacitor

C

–

0.1 µF

–

f

BYP

XCLK

so series resistance

must be considered

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Clock Generator Module (CGM)

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Mask Options

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Introduction

This section describes the mask options and the two mask option

registers. The mask options are hardwired connections specified by

Motorola. The options control the enable or disable of the following

functions:

• Resets caused by the LVI module

• Power to the LVI module

• Stop mode recovery time (32 CGMXCLK cycles or 4096

CGMXCLK cycles)

1

• ROM security

• STOP instruction

• Computer operating properly (COP) module enable

• EEPROM security

1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or

copying the ROM data difficult for unauthorized users.

There is no user-defined ROM on the MC68HC08AZ0.

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Mask Options

MC68HC08AZ0 options

On the MC68HC08AZ0 the mask options are fixed as the following:

• LVI is enabled in STOP

• ROM security is disabled

• LVI reset is enabled

• Stop mode recovery is long

• COP timeout is long

• Stop mode is enabled

• Watchdog is enabled

• EEPROM security function is enabled

Functional description

Bit 7

6

5

4

3

2

1

Bit 0

COPD

R

Read:

Write:

Reset:

LVISTOP ROMSEC LVIRSTD LVIPWRD SSREC COPRS STOP

MORA

$001F

R

Unaffected by reset

Figure 9. Mask option register A (MORA)

LVISTOP — LVI Stop Mode Enable Bit

LVISTOP enables the LVI module in stop mode. See

Low-Voltage Inhibit (LVI) on page 165.

1 = LVI enabled during stop mode

0 = LVI disabled during stop mode

The LVI is enabled in stop mode on the on the MC68HC08AZ0.

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Mask Options

Functional description

SEC — ROM security bit

SEC enables the ROM security feature. Setting the SEC bit prevents

access to the ROM contents.

1 = ROM security enabled

0 = ROM security disabled

The ROM security feature is disabled on the MC68HC08AZ0.

LVIRSTD — LVI reset disable bit

LVIRSTD disables the reset signal from the LVI module. See

Low-Voltage Inhibit (LVI) on page 165.

1 = LVI module resets disabled

0 = LVI module resets enabled

The reset signal from the LVI module is enabled on the MC68HC08AZ0

.

LVIPWRD — LVI power disable bit

LVIPWRD disables the LVI module. See Low-Voltage Inhibit (LVI) on

page 165.

1 = LVI module power disabled

0 = LVI module power enabled

The LVI module power is enabled on the MC68HC08AZ0.

SSREC — Short stop recovery bit

SSREC enables the CPU to exit stop mode with a delay of 32

CGMXCLK cycles instead of a 4096 CGMXCLK cycle delay.

1 = STOP mode recovery after 32 CGMXCLK cycles

0 = STOP mode recovery after 4096 CGMXCLK cycles

If using an external crystal oscillator, the SSREC bit should not be set.

STOP mode recovery is after 4096 CGMXCLK cycles on the

MC68HC08AZ0.

COPRS — COP rate select

COPRS is similar to COPL (please note that the logic is reversed) as

it determines the timeout period for the COP.

18

4

1 = COP timeout period is 2 — 2 CGMXCLK cycles.

13

4

0 = COP timeout period is 2 — 2 CGMXCLK cycles.

18

4

The COP mode timeout period is 2 — 2 CGMXCLK cycles on the

MC68HC08AZ0.

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Mask Options

STOP — STOP enable bit

STOP enables the STOP instruction.

1 = STOP instruction enabled

0 = STOP instruction treated as illegal opcode

The STOP instruction is enabled on the MC68HC08AZ0.

COPD — COP disable bit

COPD disables the COP module. See

Computer Operating Properly Module (COP) on page 159.

1 = COP module disabled

0 = COP module enabled

The COP module is enabled on the MC68HC08AZ0.

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Write:

Reset:

EESEC

MORB

$003F

Unaffected by reset

= Unimplemented

Figure 10. Mask option register B (MORB)

EESEC — EEPROM security enable bit.

EESEC enables the EEPROM security function. Setting EESEC

prevents program/erase access to locations $8F0 – $8FF of the

EEPROM array and to the EEACR/EENVR configuration registers.

See MC68HC08AZ0 EEPROM Security on page 61

1 = EEPROM security function enabled

0 = EEPROM security function disabled

The EEPROM security function on the MC68HC08AZ0 is enabled.

Extra care should be exercised when selecting mask option

registers since other HC08 family parts may have different options.

If in doubt, check with your local field applications representative.

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Break Module

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Flag protection during break interrupts . . . . . . . . . . . . . . . . . . . . . 141

CPU during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

TIM and PIT during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 142

COP during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Break status and control register (BRKSCR) . . . . . . . . . . . . . . . . 143

Break address registers (BRKH and BRKL) . . . . . . . . . . . . . . . . . 144

Low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Introduction

This section describes the break module. The break module can

generate a break interrupt which stops normal program flow at a defined

address in order to begin execution of a background program.

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Break Module

Features

Features of the break module include the following:

• Accessible I/O registers during the break interrupt

• CPU- and DMA-generated break Interrupts

• Software-generated break interrupts

• COP disabling during break interrupts

Functional description

When the internal address bus matches the value written in the break

address registers, the break module issues a breakpoint signal (BKPT)

to the SIM. The SIM then causes the CPU to load the instruction register

with a software interrupt instruction (SWI) after completion of the current

CPU instruction. The program counter vectors to $FFFC and $FFFD

($FEFC and $FEFD in monitor mode).

The following events can cause a break interrupt to occur:

• A CPU-generated address (the address in the program counter)

matches the contents of the break address registers.

• A DMA-generated address matches the contents of the break

address registers during a DMA transfer.

• Software writes a ‘1’ to the BRKA bit in the break status and

control register (BRKSCR).

When a CPU- or DMA-generated address matches the contents of the

break address registers, the break interrupt begins after the CPU

completes its current instruction. A return from interrupt instruction (RTI)

in the break routine ends the break interrupt and returns the MCU to

normal operation. Figure 11 shows the structure of the break module.

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Functional description

IAB[15:8]

BREAK ADDRESS REGISTER HIGH

8-BIT COMPARATOR

IAB[15:0]

CONTROL

BKPT

(TO SIM)

8-BIT COMPARATOR

BREAK ADDRESS REGISTER LOW

IAB[7:0]

Figure 11. Break module block diagram

Table 1. Break I/O register summary

Register Name

Bit 7

6

14

6

5

13

5

4

12

4

3

11

3

2

10

2

1

9

1

Bit 0 Addr.

Bit 8 $FE0C

Bit 0 $FE0D

$FE0E

Break Address Register High (BRKH) Bit 15

Break Address Register Low (BRKL) Bit 7

Break Status/Control Register (BRKSCR) BRKE BRKA

= Unimplemented

Flag protection

during break

interrupts

The system integration module (SIM) controls whether or not module

status bits can be cleared during the break state. The BCFE bit in the

SIM break flag control register (SBFCR) enables software to clear status

bits during the break state. See SIM break flag control register (SBFCR)

on page 106, and the Break Interrupts subsection for each module.

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Break Module

CPU during break

interrupts

The CPU starts a break interrupt by:

• Loading the instruction register with the SWI instruction

• Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD

in monitor mode)

The break interrupt begins after completion of the CPU instruction in

progress. If the break address register match occurs on the last cycle of

a CPU instruction, the break interrupt begins immediately.

DMA during break

interrupts

During a break interrupt, the DMA is inactive.

If a DMA-generated address matches the contents of the break address

registers, a break interrupt begins at the end of the current CPU

instruction.

If a break interrupt is asserted during the current address cycle and the

DMA is active, the DMA releases the internal address and data buses at

the next address boundary to preserve the current MCU state. During

the break interrupt, the DMA continues to arbitrate DMA channel

priorities. After the break interrupt, the DMA becomes active again and

resumes transferring data according to its highest priority service

request.

TIM and PIT during

break interrupts

A break interrupt stops the timer counter.

COP during break

interrupts

The COP is disabled during a break interrupt when V_HIis present on the

RST pin.

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Break Module

Break module registers

Three registers control and monitor operation of the break module:

• Break status and control register (BRKSCR)

• Break address register high (BRKH)

• Break address register low (BRKL)

Break status and

control register

(BRKSCR)

The break status and control register contains break module enable and

status bits.

Bit 7

BRKE

0

6

BRKA

0

5

4

3

2

1

Bit 0

0

Read:

Write:

Reset:

0

BRKSCR

$FE0E

0

= Unimplemented

Figure 12. Break status and control register (BRKSCR)

BRKE — Break enable bit

This read/write bit enables breaks on break address register matches.

BRKE is cleared by writing a ‘0’ to bit 7. Reset clears the BRKE bit.

1 = Breaks enabled on 16-bit address match

0 = Breaks disabled on 16-bit address match

BRKA — Break active bit

This read/write status and control bit is set when a break address

match occurs. Writing a ‘1’ to BRKA generates a break interrupt.

BRKA is cleared by writing a ‘0’ to it before exiting the break routine.

Reset clears the BRKA bit.

1 = Break address match

0 = No break address match

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Break address

registers (BRKH

and BRKL)

The break address registers contain the high and low bytes of the

desired breakpoint address. Reset clears the break address registers.

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Write:

Reset:

BRKH

$FE0C

Bit 15

14

13

12

11

10

9

Bit 8

0

6

0

5

0

4

0

3

0

2

0

1

0

Bit 7

Bit 0

Read:

Write:

Reset:

BRKL

$FE0D

Bit 7

0

6

0

5

0

4

0

3

0

2

0

1

0

Bit 0

0

Figure 13. Break address registers (BRKH and BRKL)

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Low-power modes

The WAIT and STOP instructions put the MCU in

low-power-consumption standby modes.

Wait Mode

If enabled, the break module is active in wait mode. The SIM break

stop/wait bit (SBSW) in the SIM break status register indicates whether

wait was exited by a break interrupt. If so, the user can modify the return

address on the stack by subtracting one from it. (See

System Integration Module (SIM) on page 85).

Stop Mode

The break module is inactive in stop mode. The STOP instruction does

not affect break module register states. A break interrupt will cause an

exit from stop mode and sets the SBSW bit in the SIM break status

register.

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Monitor ROM (MON)

Monitor ROM

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Echoing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Introduction

This section describes the monitor ROM (MON08). The monitor ROM

allows complete testing of the MCU through a single-wire interface with

a host computer.

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Monitor ROM (MON)

Features

Features of the monitor ROM include the following:

• Normal user-mode pin functionality

• One pin dedicated to serial communication between monitor ROM

and host computer

• Standard mark/space non-return-to-zero (NRZ) communication

with host computer

• Up to 28.8K baud communication with host computer

• Execution of code in RAM

• EEPROM programming

Functional description

The monitor ROM receives and executes commands from a host

computer. Figure 1 shows a sample circuit used to enter monitor mode

and communicate with a host computer via a standard RS-232 interface.

In monitor mode, the MCU can execute host-computer code in RAM

while all MCU pins except PTA0 retain normal operating mode functions.

All communication between the host computer and the MCU is through

the PTA0 pin. A level-shifting and multiplexing interface is required

between PTA0 and the host computer. PTA0 is used in a wired-OR

configuration and requires a pull-up resistor.

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Monitor ROM (MON)

Functional description

V_DD

68HC08

10 kΩ

RST

0.1 µF

V_HI

10 Ω

IRQ

V_DDA

CGMXFC

0.1 µF

1

20

MC145407

+

10 µF

OSC1

OSC2

3

4

18

17

20 pF

10 MΩ

X1

4.9152 MHz

20 pF

V

2

19

SSA

V_SS

DB-25

2

5

6

16

15

3

7

V_DD

0.1 µF

V_DD

14

V_DD

1

2

6

4

MC68HC125

10 kΩ

3

5

PTA0

PTC3

V_DD

10 kΩ

7

10 kΩ

A

PTC0

PTC1

(See

NOTE.)

B

NOTE: Position A — Bus clock = CGMXCLK ÷ 4 or CGMVCLK ÷ 4

Position B — Bus clock = CGMXCLK ÷ 2

Figure 1. Monitor mode circuit

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Monitor ROM (MON)

Entering monitor

mode

Table 1 shows the pin conditions for entering monitor mode.

Table 1. Mode selection

Bus

Frequency

Mode

CGMOUT

CGMXCLK

CGMVCLK

CGMOUT

--------------------------

2

V_HI

1

0

1

0

Monitor

----------------------------- or -----------------------------

2

CGMOUT

--------------------------

2

CGMXCLK

Enter monitor mode by either

• Executing a software interrupt instruction (SWI) or

• Applying a ‘0’ and then a ‘1’ to the RST pin.

Once out of reset, the MCU waits for the host to send eight security bytes

(see Security on page 157). After the security bytes, the MCU sends a

break signal (10 consecutive ‘0’s) to the host computer, indicating that it

is ready to receive a command.

Monitor mode uses alternate vectors for reset, SWI, and break interrupt.

The alternate vectors are in the $FE page instead of the $FF page and

allow code execution from the internal monitor firmware instead of user

code. The COP module is disabled in monitor mode as long as V_{HI (}see

5.0 Volt DC Electrical Characteristics on page 400), is applied to either

the IRQ pin or the RST pin. See System Integration Module (SIM) on

page 85 for more information on modes of operation.

NOTE: Holding the PTC3 pin low when entering monitor mode causes a bypass

of a divide-by-two stage at the oscillator. The CGMOUT frequency is

equal to the CGMXCLK frequency, and the OSC1 input directly

generates internal bus clocks. In this case, the OSC1 signal must have

a 50% duty cycle at maximum bus frequency.

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Monitor ROM (MON)

Functional description

Table 2 is a summary of the differences between user mode and monitor

mode.

Table 2. Mode differences

Functions

Reset

Vector

High

Reset

Vector

Low

Break

Vector

High

Break

Vector

Low

SWI

Vector

High

SWI

Vector

Low

Modes

COP

User

Enabled

$FFFE

$FEFE

$FFFF

$FEFF

$FFFC

$FEFC

$FFFD

$FEFD

$FFFC

$FEFC

$FFFD

$FEFD

(1)

Monitor

Disabled

1. If the high voltage (V_HI) is removed from the IRQ/V_PPpin or the RST pin, the SIM asserts its COP enable

output. The COP is a mask option enabled or disabled by the COPD bit in the mask option register. See

5.0 Volt DC Electrical Characteristics on page 400.

Data format

Communication with the monitor ROM is in standard non-return-to-zero

(NRZ) mark/space data format. (See Figure 2 and Figure 3).

BIT

START

BIT

STOP

BIT

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

Figure 2. Monitor data format

BIT

START

STOP

$A5

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT

STOP

BIT

START

BIT

BREAK

BIT 0

BIT 1

BIT 7

Figure 3. Sample monitor waveforms

The data transmit and receive rate can be anywhere from 4800 baud to

28.8K baud. Transmit and receive baud rates must be identical.

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Monitor ROM (MON)

Echoing

The monitor ROM immediately echoes each received byte back to the

PTA0 pin for error checking, as shown in Figure 4.

SENT TO

MONITOR

ADDR. LOW

READ

ADDR. HIGH ADDR. HIGH

DATA

ADDR. LOW

ECHO

RESULT

Figure 4. Read transaction

Any result of a command appears after the echo of the last byte of the

command.

Break signal

A break signal is a start bit followed by nine low bits. This is shown in

Figure 4. When the monitor receives a break signal, it drives the PTA0

pin high for the duration of two bits before echoing the break signal.

MISSING STOP BIT

TWO-STOP-BIT DELAY BEFORE ZERO ECHO

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

Figure 5. Break transaction

Co m m a nd s

The monitor ROM uses the following commands:

• READ (read memory)

• WRITE (write memory)

• IREAD (indexed read)

• IWRITE (indexed write)

• READSP (read stack pointer)

• RUN (run user program)

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Functional description

Table 3. READ (read memory) command

Description

Operand

Read byte from memory

Speciﬁes 2-byte address in high byte:low byte order

Returns contents of speciﬁed address

$4A

Data returned

Opcode

Command sequence

SENT TO

MONITOR

READ

ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW

DATA

ECHO

RESULT

Table 4. WRITE (write memory) command

Description

Write byte to memory

Operand

Speciﬁes 2-byte address in high byte:low byte order; low byte followed by data byte

Data returned

Opcode

None

$49

Command sequence

SENT TO

MONITOR

WRITE

ECHO

WRITE

ADDR. HIGH

ADDR. LOW ADDR. LOW

DATA

ADDR. HIGH

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Monitor ROM (MON)

Table 5. IREAD (indexed read) command

Description

Operand

Read next 2 bytes in memory from last address accessed

Speciﬁes 2-byte address in high byte:low byte order

Returns contents of next two addresses

$1A

Data returned

Opcode

Command sequence

SENT TO

MONITOR

IREAD

DATA

RESULT

ECHO

Table 6. IWRITE (indexed write) command

Description

Operand

Write to last address accessed + 1

Speciﬁes single data byte

Data returned

Opcode

None

$19

Command sequence

SENT TO

MONITOR

IWRITE

DATA

ECHO

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Monitor ROM (MON)

Functional description

A sequence of IREAD or IWRITE commands can sequentially access a

block of memory over the full 64K byte memory map.

Table 7. READSP (read stack pointer) command

Description

Operand

Reads stack pointer

None

Data returned

Opcode

Returns stack pointer in high byte:low byte order

$0C

Command sequence

SENT TO

MONITOR

READSP

SP HIGH

SP LOW

RESULT

ECHO

Table 8. RUN (run user program) command

Description

Operand

Executes RTI instruction

None

$28

Data returned

Opcode

Command sequence

SENT TO

MONITOR

RUN

ECHO

Baud rate

With a 4.9152MHz crystal and the PTC3 pin at ‘1’ during reset, data is

transferred between the monitor and host at 4800 baud. If the PTC3 pin

is at ‘0’ during reset, the monitor baud rate is 9600. When the CGM

output, CGMOUT, is driven by the PLL, the baud rate is determined by

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Monitor ROM (MON)

the MUL[7:4] bits in the PLL programming register (PPG). Refer to

Clock Generator Module (CGM) on page 107.

Table 9. Monitor Baud Rate Selection

VCO Frequency Multiplier (N)

Monitor

Baud Rate

1

2

3

4

5

6

4.9152 MHz

4.194 MHz

4800

4096

9600

8192

14,400

12,288

19,200

16,384

24,000

20,480

28,800

24,576

Later revisions feature a monitor mode which is optimised to operate

with either a 4.1952MHz crystal clock source (or multiples of

4.1952MHz) or a 4MHz crystal (or multiples of 4MHz). This supports

designs which use the MSCAN module, which is generally clocked from

a 4MHz, 8MHz or 16MHz crystal. The table below outlines the available

baud rates for a range of crystals and how they can match to a PC baud

rate.

Table 10

Baud rate

Closest PC baud PC

Error %

Clock freq

32kHz

PTC3=0

PTC3=1

28.98

PTC3=0

57.6

PTC3=1

28.8

PTC3=0 PTC3=1

57.97

1811.59

3623.19

7246.37

7597.83

8904.35

14492.72

0.64

1.08

0.49

0.64

0.63

0.64

1.08

0.50

0.64

1MHz

905.80

1800

900

2MHz

1811.59

3623.19

3798.91

4452.17

7246.37

3600

1800

3600

3840

4430

7200

14400

4MHz

7200

4.194MHz

4.9152MHz

8MHz

7680

8861

14400

28800

16MHz

28985.51 14492.75

Care should be taken when setting the baud rate since incorrect

baud rate setting can result in communications failure.

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Monitor ROM (MON)

Functional description

Security

A security feature discourages unauthorized reading of ROM locations

while in monitor mode. The host can bypass the security feature at

monitor mode entry by sending eight security bytes that match the byte

locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain

user-defined data.

NOTE: Do not leave locations $FFF6–$FFFD blank. For security reasons, enter

data at locations $FFF6–$FFFD even if they are not used for vectors.

During monitor mode entry, the MCU waits after the power-on reset for

the host to send the eight security bytes on pin PA0.

If the received bytes match those at locations $FFF6–$FFFD, the host

bypasses the security feature and can read all ROM locations and

execute code from ROM. Security remains bypassed until a power-on

reset occurs. After the host bypasses security, any reset other than a

power-on reset requires the host to send another eight bytes. If the reset

was not a power-on reset, security remains bypassed regardless of the

data that the host sends.

If the received bytes do not match the data at locations $FFF6–$FFFD,

the host fails to bypass the security feature. The MCU remains in monitor

mode, but reading ROM locations returns undefined data, and trying to

execute code from ROM causes an illegal address reset. After the host

fails to bypass security, any reset other than a power-on reset causes an

endless loop of illegal address resets.

After receiving the eight security bytes from the host, the MCU transmits

a break character signalling that it is ready to receive a command.

NOTE: The MCU does not transmit a break character until after the host sends

the eight security bytes.

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Monitor ROM (MON)

V

DD

4096 + 32 CGMXCLK CYCLES

24 CGMXCLK CYCLES

RST

PA7

256 CGMXCLK CYCLES (ONE BIT TIME)

FROM HOST

FROM MCU

PA0

1

4

1

4

2

1

NOTE: 1 = Echo delay (2 bit times)

2 = Data return delay (2 bit times)

4 = Wait 1 bit time before sending next byte.

Figure 6. Monitor mode entry timing

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Computer Operating Properly Module (COP)

COP

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

CGMXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

STOP instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

COPCTL write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Internal reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Reset vector fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

COPD (COP disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

COP Control register (COPCTL). . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

WAIT mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

COP module during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . 164

Introduction

This section describes the computer operating properly (COP) module,

a free-running counter that generates a reset if allowed to overflow. The

COP module helps software recover from runaway code. COP resets

can be prevented by periodically clearing the COP counter.

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Computer Operating Properly Module (COP)

Functional description

Figure 1 shows the structure of the COP module.

RESET

12-BIT COP PRESCALER

CGMXCLK

RESET STATUS REGISTER

STOP INSTRUCTION

INTERNAL RESET SOURCES

RESET VECTOR FETCH

(1)

COPCTL WRITE

COPMODULE

COPEN (FROM SIM)

COPD (FROM MOR)

6-BIT COP COUNTER

RESET

CLEAR

COP COUNTER

COPCTL WRITE

NOTE:1. See Active resets from internal sources on page 91.

Figure 1. COP block diagram

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Computer Operating Properly Module (COP)

Functional description

Table 1. COP I/O register summary

Register Name

Bit 7

6

5

4

3

2

1

Bit 0 Addr.

COP Control Register (COPCTL)

$FFFF

The COP counter is a free-running 6-bit counter preceded by a12-bit

prescaler. If not cleared by software, the COP counter overflows and

13

4

18

4

generates an asynchronous reset after 2 – 2 , or 2 – 2 CGMXCLK

cycles, depending on the state of the COP rate select bit, COPRS in

MORA. When COPRS = 1, a 4.9152 MHz crystal, gives a COP timeout

period of 53.3ms. Writing any value to location $FFFF before overflow

occurs prevents a COP reset by clearing the COP counter and stages 5

through 12 of the prescaler.

NOTE: In Expanded mode location $FFFF will be external to the MCU.

Therefore during the COP clearing operation, the peripheral located at

$FFFF will also be written to.

A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the

COP bit in the SIM reset status register (SRSR). See SIM reset status

register (SRSR) on page 105.The COP should be cleared immediately

before entering or after exiting STOP mode to assure a full COP timeout

period. A CPU interrupt routine or a DMA service routine can be used to

clear the COP.

NOTE: COP clearing instructions should be placed in the main program and not

in an interrupt subroutine. Such an interrupt subroutine could keep the

COP from generating a reset even while the main program is not working

properly.

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I/O Signals

The following paragraphs describe the signals shown in Figure 1.

CGMXCLK

CGMXCLK is the crystal oscillator output signal. The CGMXCLK

frequency is equal to the crystal frequency.

STOP instruction

COPCTL write

The STOP instruction clears the COP prescaler.

Writing any value to the COP control register (COPCTL) (see COP

Control register (COPCTL) on page 163), clears the COP counter and

clears bits 12 – 4 of the SIM counter. Reading the COP control register

returns the reset vector.

Power-on reset

The power-on reset (POR) circuit in the SIM clears the SIM counter 4096

CGMXCLK cycles after power-up.

Internal reset

An internal reset clears the COP prescaler and the COP counter.

Reset vector fetch

A reset vector fetch occurs when the vector address appears on the data

bus. A reset vector fetch clears the COP prescaler.

COPD (COP

disable)

The COPD signal reflects the state of the COP disable bit (COPD) in the

mask option register (MORA). See Mask Options on page 135

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Computer Operating Properly Module (COP)

COP Control register (COPCTL)

The COP control register is located at address $FFFF and overlaps the

reset vector. Writing any value to $FFFF clears the COP counter and

starts a new timeout period. Reading location $FFFF returns the low

byte of the reset vector.

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Write:

Reset:

Low byte of reset vector

Clear COP counter

Unaffected by reset

COPCTL

$FFFF

Figure 2. COP control register (COPCTL)

Interrupts

The COP does not generate CPU interrupt requests or DMA service

requests.

Monitor mode

The COP is disabled in monitor mode when V_HIis present on the IRQ pin

or on the RST pin.

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Low-power modes

The WAIT and STOP instructions put the MCU in

low-power-consumption standby modes.

WAIT mode

STOP mode

The COP continues to operate during WAIT mode. To prevent a COP

reset during WAIT mode, the COP counter should be cleared

periodically in a CPU interrupt routine or a DMA service routine.

STOP mode turns off the CGMXCLK input to the COP and clears the

COP prescaler. The COP should be serviced immediately before

entering or after exiting STOP mode to ensure a full COP timeout period

after entering or exiting STOP mode.

The STOP bit in the mask option register (MOR) enables the STOP

instruction. To prevent inadvertently turning off the COP with a STOP

instruction, the STOP instruction should be disabled by programming the

STOP bit to ‘0’.

COP module during break interrupts

The COP is disabled during a break interrupt when V_HIis present on the

RST pin.

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Low-Voltage Inhibit (LVI)

LVI

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Polled LVI operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Forced reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

False reset protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

LVI Status Register (LVISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

LVI interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

WAIT mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Introduction

This section describes the low-voltage inhibit module, which monitors

the voltage on the V_DDpin and can force a reset when the V_DDvoltage

falls to the LVI trip voltage.

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Low-Voltage Inhibit (LVI)

Features

Features of the LVI module include the following:

• Programmable LVI reset

• Programmable power consumption

• Digital filtering of VDD pin level

NOTE: If a low voltage interrupt (LVI) occurs during programming of EEPROM

memory, then adequate programming time may not have been allowed

to ensure the integrity and retention of the data. It is the responsibility of

the user to ensure that in the event of an LVI any addresses being

programmed receive specification programming conditions.

Functional description

Figure 1 shows the structure of the LVI module. The LVI is enabled out

of reset. The LVI module contains a bandgap reference circuit and

comparator. The LVI power bit, LVIPWRD, enables the LVI to monitor

V

_DDvoltage. The LVI reset bit, LVIRSTD, enables the LVI module to

generate a reset when V_DDfalls below a voltage, LVI_TRIPF, and remains

at or below that level for 9 or more consecutive CPU cycles.

Note that short V spikes may not trip the LVI. It is the user’s

DD

responsibility to ensure a clean V signal within the specified

DD

operating voltage range if normal microcontroller operation is to be

guaranteed.

LVIPWRD and LVIRSTD are mask options. See Mask Options on page

135. Once an LVI reset occurs, the MCU remains in reset until V_DDrises

above a voltage, LVI_TRIPR. V_DDmust be above LVI_TRIPRfor only one CPU

cycle to bring the MCU out of reset. The output of the comparator

controls the state of the LVIOUT flag in the LVI status register (LVISR).

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Low-Voltage Inhibit (LVI)

Functional description

An LVI reset also drives the RST pin low to provide low-voltage

protection to external peripheral devices.

V

DD

LVIPWRD

(FROM MOR)

CPU CLOCK

LVIRSTD

V_DD> LVI_TRIP= 0

V_DD< LVI_TRIP= 1

LVI RESET

LOW V

DD

V

DD

DETECTOR

DIGITAL FILTER

ANLGTRIP

LVIOUT

Figure 1. LVI module block diagram

Table 1. LVI I/O register summary

Register Name

Bit 7

6

5

4

3

2

1

Bit 0 Addr.

$FE0F

LVI Status Register (LVISR) LVIOUT

= Unimplemented

Polled LVI

operation

In applications that can operate at V_DDlevels below the LVI_TRIPFlevel,

software can monitor V_DDby polling the LVIOUT bit. In the mask option

register, the LVIPWRD and LVIRSTD bits must be at ‘0’ to enable the

LVI module and to enable the LVI resets. Also, the LVIPRWD bit must

be at ‘0’ to enable the LVI module, and the LVIRSTD bit must be at ‘1’ to

disable LVI resets.

Forced reset

operation

In applications that require V_DDto remain above the LVI_TRIPFlevel,

enabling LVI resets allows the LVI module to reset the MCU when V_DD

falls to the LVI_TRIPFlevel and remains at or below that level for 9 or more

consecutive CPU cycles. In the mask option register, the LVIPWRD and

LVIRSTD bits must be at ‘0’ to enable the LVI module and to enable LVI

resets.

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Low-Voltage Inhibit (LVI)

False reset

protection

The V_DDpin level is digitally filtered to reduce false resets due to power

supply noise. In order for the LVI module to reset the MCU,V_DDmust

remain at or below the LVI_TRIPFlevel for 9 or more consecutive CPU

cycles. V_DDmust be above LVI_TRIPRfor only one CPU cycle to bring the

MCU out of reset.

LVI Status Register (LVISR)

The LVI status register flags V_DDvoltages below the LVI_TRIPFlevel.

Bit 7

6

5

4

3

2

1

Bit 0

0

Read:

Write:

Reset:

LVIOUT

0

LVISR

$FE0F

0

= Unimplemented

Figure 2. LVI Status Register (LVISR)

LVIOUT — LVI Output Bit

This read-only flag becomes set when V_DDfalls below the LVI_TRIPF

voltage for 32-40 CGMXCLK cycles. (See Table 2). Reset clears the

LVIOUT bit.

Table 2. LVIOUT bit indication

V_DD

for number of CGMXCLK

cycles:

LVIOUT

at level:

V_DD> LVI_TRIPR

ANY

0

V

_DD< LVI_TRIPF

< 32 CGMXCLK cycles

between 32 & 40 CGMXCLK

cycles

0 or 1

> 40 CGMXCLK cycles

ANY

1

LVI_TRIPF< V_DD< LVI_TRIPR

Previous Value

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Low-Voltage Inhibit (LVI)

LVI interrupts

Low-power modes

WAIT mode

The LVI module does not generate interrupt requests.

The WAIT instruction puts the MCU in low-power-consumption standby

mode.

When the LVIPWRD mask option is programmed to ‘0’, the LVI module

is active after a WAIT instruction.

When the LVIRSTD mask option is programmed to ‘0’, the LVI module

can generate a reset and bring the MCU out of WAIT mode.

Stop Mode

With LVISTOP=1 and LVIPWRD=0 in the MORA register, the LVI

module will be active after a STOP instruction. Because CPU clocks are

disabled during stop mode, the LVI trip must bypass the digital filter to

generate a reset and bring the MCU out of stop.

With the LVIPWRD bit in the MORA register at a logic 0 and the

LVISTOP bit at a logic 0, the LVI module will be inactive after a STOP

instruction.

Note that the LVI feature is intended to provide the safe shutdown

of the microcontroller and thus protection of related circuitry prior

to any application V voltage collapsing completely to an unsafe

DD

level. Is is not intended that users operate the microcontroller at

lower than the specified operating voltage, V

.

DD

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External Interrupt Module (IRQ)

IRQ

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

IRQ pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

IRQ module during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 176

IRQ status and control register (ISCR) . . . . . . . . . . . . . . . . . . . . . . . 176

The IRQ module provides the nonmaskable interrupt input.

Features of the IRQ module include the following:

Introduction

Features

• Dedicated external interrupt pins (IRQ)

• IRQ interrupt control bit

• Hysteresis buffer

• Programmable edge-only or edge and level interrupt sensitivity

• Automatic interrupt acknowledge

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External Interrupt Module (IRQ)

Functional description

A ‘0’ applied to any of the external interrupt pins can latch a CPU

interrupt request. Figure 3 shows the structure of the IRQ module.

Interrupt signals on the IRQ pin are latched into the IRQ latch. An

interrupt latch remains set until one of the following occurs:

• Vector fetch — a vector fetch automatically generates an interrupt

acknowledge signal which clears the latch that caused the vector

fetch.

• Software clear — software can clear an interrupt latch by writing

to the appropriate acknowledge bit in the interrupt status and

control register (ISCR). Writing a ‘1’ to the ACK1 bit clears the IRQ

latch.

• Reset — a reset automatically clears the interrupt latch.

ACK1

TO CPU FOR

BIL/BIH

INSTRUCTIONS

VECTOR

FETCH

DECODER

V_DD

IRQF

CLR

D

Q

SYNCHRO-

NIZER

IRQ

INTERRUPT

REQUEST

CK

IRQ

LATCH

IMASK1

MODE1

TO MODE

SELECT

LOGIC

HIGH

VOLTAGE

DETECT

Figure 3. IRQ module block diagram

All of the external interrupt pins are falling-edge-triggered and are

software-configurable to be both falling-edge and low-level-triggered.

The MODE1 bit in the ISCR controls the triggering sensitivity of the IRQ

pin.

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External Interrupt Module (IRQ)

Functional description

When an interrupt pin is edge-triggered only, the interrupt latch remains

set until a vector fetch, software clear, or reset occurs.

When an interrupt pin is both falling-edge and low-level-triggered, the

interrupt latch remains set until both of the following occur:

• Vector fetch or software clear

• Return of the interrupt pin to ‘1’

The vector fetch or software clear may occur before or after the interrupt

pin returns to ‘1’. As long as the pin is low, the interrupt request remains

pending. A reset will clear the latch and the MODEx1control bit, thereby

clearing the interrupt even if the pin stays low.

Table 1. IRQ I/O register summary

Register Name

Bit 7

6

5

4

3

2

1

Bit 0 Addr.

IRQ Status/Control Register (ISCR)

IRQF ACK1 IMASK1 MODE1 $001A

When set, the IMASK1 bit in the ISCR masks all external interrupt

requests. A latched interrupt request is not presented to the interrupt

priority logic unless the corresponding IMASK bit is clear.

NOTE: The interrupt mask (I) in the condition code register (CCR) masks all

interrupt requests, including external interrupt requests. See Figure 4

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External Interrupt Module (IRQ)

.

FROM RESET

YES

I BIT SET?

NO

YES

INTERRUPT?

NO

STACK CPU REGISTERS.

SET I BIT.

LOAD PC WITH INTERRUPT VECTOR.

FETCH NEXT

INSTRUCTION.

YES

SWI

INSTRUCTION?

NO

RTI

UNSTACK CPU REGISTERS.

EXECUTE INSTRUCTION.

INSTRUCTION?

NO

Figure 4. IRQ interrupt flowchart

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External Interrupt Module (IRQ)

Functional description

IRQ pin

A ‘0’ on the IRQ pin can latch an interrupt request into the IRQ latch. A

vector fetch, software clear, or reset clears the IRQ latch.

If the MODE1 bit is set, the IRQ pin is both falling-edge-sensitive and

low-level-sensitive. With MODE1 set, both of the following actions must

occur to clear the IRQ latch:

• Vector fetch or software clear — a vector fetch generates an

interrupt acknowledge signal to clear the latch. Software may

generate the interrupt acknowledge signal by writing a ‘1’ to the

ACK1 bit in the interrupt status and control register (ISCR). The

ACK1 bit is useful in applications that poll the IRQ pin and require

software to clear the IRQ latch. Writing to the ACK1 bit can also

prevent spurious interrupts due to noise. Setting ACK1 does not

affect subsequent transitions on the IRQ pin. A falling edge that

occurs after writing to the ACK1 bit latches another interrupt

request. If the IRQ mask bit, IMASK1, is clear, the CPU loads the

program counter with the vector address at locations $FFFA and

$FFFB.

• Return of the IRQ pin to ‘1’ — as long as the IRQ pin is at ‘0’, the

IRQ latch remains set.

The vector fetch or software clear and the return of the IRQ pin to ‘1’ may

occur in any order. The interrupt request remains pending as long as the

IRQ pin is at ‘0’. A reset will clear the latch and the MODEx control bit,

thereby clearing the interrupt even if the pin stays low.

If the MODE1 bit is clear, the IRQ pin is falling-edge-sensitive only. With

MODE1 clear, a vector fetch or software clear immediately clears the

IRQ latch.

The IRQF bit in the ISCR register can be used to check for pending

interrupts. The IRQF bit is not affected by the IMASK1 bit, which makes

it useful in applications where polling is preferred.

The BIH or BIL instruction is used to read the logic level on the IRQ pin.

NOTE: When using the level-sensitive interrupt trigger, false interrupts can be

avoided by masking interrupt requests in the interrupt routine.

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External Interrupt Module (IRQ)

IRQ module during break interrupts

The system integration module (SIM) controls whether the IRQ interrupt

latch can be cleared during the break state. The BCFE bit in the SIM

break flag control register (SBFCR) enables software to clear the latches

during the break state. See SIM break flag control register (SBFCR) on

page 106.

To allow software to clear the IRQ latch during a break interrupt, a ‘1’ is

written to the BCFE bit. If a latch is cleared during the break state, it

remains cleared when the MCU exits the break state.

To protect the latches during the break state, a ‘0’ is written to the BCFE

bit. With BCFE at ‘0’ (its default state), writing to the ACK1 bit in the IRQ

status and control register during the break state has no effect on the

IRQ latch.

IRQ status and control register (ISCR)

The IRQ status and control register (ISCR) controls and monitors

operation of the IRQ module. The ISCR performs the following functions:

• Indicates the state of the IRQ interrupt flag

• Clears the IRQ interrupt latch

• Masks IRQ interrupt requests

• Controls triggering sensitivity of the IRQ interrupt pin

Bit 7

6

5

4

0

3

2

1

Bit 0

Read:

Write:

Reset:

IRQF

0

ACK1

0

ISCR

$001A

IMASK1 MODE1

0

= Unimplemented

Figure 5. IRQ status and control register (ISCR)

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External Interrupt Module (IRQ)

IRQ status and control register (ISCR)

IRQF — IRQ flag

This read-only status bit is high when the IRQ interrupt is pending.

1 = Interrupt pending

0 = Interrupt not pending

ACK1 — IRQ interrupt request acknowledge bit

Writing a ‘1’ to this write-only bit clears the IRQ latch. ACK1 always

reads as ‘0’. Reset clears ACK1.

IMASK1 — IRQ Interrupt mask bit

Writing a ‘1’ to this read/write bit disables IRQ interrupt requests.

Reset clears IMASK1.

1 = IRQ interrupt requests disabled

0 = IRQ interrupt requests enabled

MODE1 — IRQ edge/level select bit

This read/write bit controls the triggering sensitivity of the IRQ/V_PPpin.

Reset clears MODE1.

1 = Interrupt requests on falling edges and low levels

0 = Interrupt requests on falling edges only

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Serial Communications Interface Module (SCI)

SCI

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

SCI during break module interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 198

I/O signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

PTE0/TxD (transmit data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

PTE1/RxD (receive data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

I/O registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

SCI control register 1 (SCC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

SCI Control Register 2 (SCC2). . . . . . . . . . . . . . . . . . . . . . . . . . . 202

SCI control register 3 (SCC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

SCI status register 1 (SCS1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

SCI status register 2 (SCS2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

SCI data register (SCDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

SCI baud rate register (SCBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Introduction

This section describes the serial communications interface module,

which allows high-speed asynchronous communications with peripheral

devices and other MCUs.

NOTE: DMA associated functions are only valid if the MCU has a DMA module.

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Serial Communications Interface Module (SCI)

Features

Features of the SCI module include the following:

• Full duplex operation

• Standard mark/space non-return-to-zero (NRZ) format

• 32 programmable baud rates

• Programmable 8-bit or 9-bit character length

• Separately enabled transmitter and receiver

• Separate receiver and transmitter CPU interrupt requests

• Separate receiver and transmitter DMA service requests

• Programmable transmitter output polarity

• Two receiver wake-up methods:

– Idle line wake-up

– Address mark wake-up

• Interrupt-driven operation with eight interrupt flags:

– Transmitter empty

– Transmission complete

– Receiver full

– Idle receiver input

– Receiver overrun

– Noise error

– Framing error

– Parity error

• Receiver framing error detection

• Hardware parity checking

• 1/16 bit-time noise detection

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Serial Communications Interface Module (SCI)

Functional description

Figure 1 shows the structure of the SCI module. The SCI allows

full-duplex, asynchronous, NRZ serial communication between the MCU

and remote devices, including other MCUs. The transmitter and receiver

of the SCI operate independently, although they use the same baud rate

generator. During normal operation, the CPU monitors the status of the

SCI, writes the data to be transmitted, and processes received data.

During DMA transfers, the DMA fetches data from memory for the SCI

to transmit and/or the DMA stores received data in memory.

Table 1. SCI I/O register summary

Register Name

Bit 7

6

5

4

3

2

1

Bit 0 Addr.

WAKE ILTY PEN PTY $0013

TE RE RWU SBK $0014

T8 DMARE DMATE ORIE NEIE FEIE PEIE $0015

SCI Control Register 1 (SCC1)LOOPS ENSCI TXINV

M

SCI Control Register 2 (SCC2) SCTIE TCIE SCRIE ILIE

SCI Control Register 3 (SCC3) R8

SCI Status Register 1 (SCS1) SCTE

SCI Status Register 2 (SCS2)

TC

SCRF IDLE

OR

NF

FE

PE $0016

RPF $0017

$0018

BKF

SCI Data Register (SCDR)

SCI Baud Rate Register (SCBR)

SCP1 SCP0

SCR2 SCR1 SCR0 $0019

= Unimplemented

R

= Reserved

Data format

The SCI uses the standard non-return-to-zero mark/space data format

illustrated in Figure 6.

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Serial Communications Interface Module (SCI)

8-BIT DATA FORMAT

(BIT M IN SCC1 CLEAR)

POSSIBLE

PARITY

BIT

START

BIT

STOP

BIT

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

9-BIT DATA FORMAT

(BIT M IN SCC1 SET)

POSSIBLE

PARITY

BIT

START

BIT

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8 STOP

BIT

Figure 6. SCI data formats

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Serial Communications Interface Module (SCI)

Functional description

INTERNAL BUS

SCI DATA

REGISTER

SCI DATA

REGISTER

RECEIVE

SHIFT REGISTER

TRANSMIT

SHIFT REGISTER

PTE1/Rx

PTE2/Tx

TXINV

SCTIE

R8

T8

TCIE

SCRIE

ILIE

DMARE

DMATE

TE

SCTE

TC

RE

RWU

SBK

SCRF

IDLE

OR

NF

FE

PE

ORIE

NEIE

FEIE

PEIE

LOOPS

ENSCI

LOOPS

RECEIVE

CONTROL

FLAG

CONTROL

TRANSMIT

CONTROL

WAKE-UP

CONTROL

M

BKF

RPF

ENSCI

WAKE

ILTY

PEN

PTY

PRE-

BAUD RATE

∏ 4

BUS CLOCK

SCALER GENERATOR

DATA SELECTION

CONTROL

∏ 16

Figure 1. SCI module block diagram

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Serial Communications Interface Module (SCI)

Transmitter

Figure 2 shows the structure of the SCI transmitter.

INTERNAL BUS

PRE-

SCALER DIVIDER

BAUD

÷ 16

÷ 4

SCI DATA REGISTER

SCP1

SCP0

SCR1

SCR2

SCR0

11-BIT

TRANSMIT

SHIFT REGISTER

H

8

7

6

5

4

3

2

1

0

L

PTE2/TxD

TXINV

M

PEN

PTY

PARITY

GENERATION

T8

DMATW

TRANSMITTER

CONTROL LOGIC

DMATE

SCTIE

SCTE

SBK

DMATE

SCTE

LOOPS

ENSCI

TE

SCTIE

TC

TCIE

Figure 2. SCI transmitter

Character length

The transmitter can accommodate either 8-bit or 9-bit data. The state

of the M bit in SCI control register 1 (SCC1) determines character

length. When transmitting 9-bit data, bit T8 in SCI control register 3

(SCC3) is the ninth bit (bit 8).

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Serial Communications Interface Module (SCI)

Functional description

Character transmission

During an SCI transmission, the transmit shift register shifts a

character out to the PTE0/TxD pin. The SCI data register (SCDR) is

the write-only buffer between the internal data bus and the transmit

shift register. To initiate an SCI transmission:

1. Enable the SCI by writing a ‘1’ to the enable SCI bit

(ENSCI) in SCI control register 1 (SCC1).

2. Enable the transmitter by writing a ‘1’ to the transmitter

enable bit (TE) in SCI control register 2 (SCC2).

3. Clear the SCI transmitter empty bit by first reading SCI

status register 1 (SCS1) and then writing to the SCDR.

4. Repeat step 3 for each subsequent transmission.

At the start of a transmission, transmitter control logic automatically

loads the transmit shift register with a preamble of ‘1’s. After the

preamble shifts out, control logic transfers the SCDR data into the

transmit shift register. A ‘0’ start bit automatically goes into the least

significant bit position of the transmit shift register. A ‘1’ STOP bit goes

into the most significant bit position.

The SCI transmitter empty bit, SCTE, in SCS1 becomes set when the

SCDR transfers a byte to the transmit shift register. The SCTE bit

indicates that the SCDR can accept new data from the internal data

bus. If the SCI transmit interrupt enable bit, SCTIE, in SCC2 is also

set, the SCTE bit generates a transmitter CPU interrupt request or a

transmitter DMA service request.

The SCTE bit generates a transmitter DMA service request if the DMA

transfer enable bit, DMATE, in SCI control register 3 (SCC3) is set.

Setting the DMATE bit enables the SCTE bit to generate transmitter

DMA service requests and disables transmitter CPU interrupt

requests.

When the transmit shift register is not transmitting a character, the

PTE0/TxD pin goes to the idle condition, ‘1’. If at any time software

clears the ENSCI bit in SCI control register 1 (SCC1), the transmitter

and receiver relinquish control of the port E pins.

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Table 2. SCI transmitter I/O register summary

Register Name

Bit 7

6

5

4

3

2

1

Bit 0 Addr.

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TE RE RWU SBK $0014

T8 DMAREDMATE ORIE NEIE FEIE PEIE $0015

SCI Control Register 1 (SCC1)LOOPS ENSCI TXINV

M

SCI Control Register 2 (SCC2) SCTIE TCIE SCRIE ILIE

SCI Control Register 3 (SCC3) R8

SCI Status Register 1 (SCS1) SCTE

SCI Data Register (SCDR)

TC

SCRF IDLE

OR

NF

FE

PE $0016

$0018

SCI Baud Rate Register (SCBR)

SCP1 SCP0

SCR2 SCR1 SCR0 $0019

= Unimplemented

R

= Reserved

Break characters

Writing a ‘1’ to the send break bit, SBK, in SCC2 loads the transmit shift

register with a break character. A break character contains all ‘0’s and

has no start, STOP, or parity bit. Break character length depends on the

M bit in SCC1. As long as SBK is at ‘1’, transmitter logic continuously

loads break characters into the transmit shift register. After software

clears the SBK bit, the shift register finishes transmitting the last break

character and then transmits at least one ‘1’. The automatic ‘1’ at the end

of a break character guarantees the recognition of the start bit of the next

character.

The SCI recognizes a break character when a start bit is followed by

8 or 9 ‘0’ data bits and a ‘0’ where the STOP bit should be. Receiving

a break character has the following effects on SCI registers:

• Sets the framing error bit (FE) in SCS1

• Sets the SCI receiver full bit (SCRF) in SCS1

• Clears the SCI data register (SCDR)

• Clears the R8 bit in SCC3

• Sets the break flag bit (BKF) in SCS2

• May set the overrun (OR), noise flag (NF), parity error (PE), or

reception in progress flag (RPF) bits

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Serial Communications Interface Module (SCI)

Functional description

Idle characters

An idle character contains all ‘1’s and has no start, stop, or parity bit.

Idle character length depends on the M bit in SCC1. The preamble is

a synchronizing idle character that begins every transmission.

If the TE bit is cleared during a transmission, the PTE2/TxD pin

becomes idle after completion of the transmission in progress.

Clearing and then setting the TE bit during a transmission queues an

idle character to be sent after the character currently being

transmitted.

NOTE: When queueing an idle character, return the TE bit to ‘1’ before the stop

bit of the current character shifts out to the PTE0/TxD pin. Setting TE

after the stop bit appears on PTE0/TxD causes data previously written

to the SCDR to be lost.

A good time to toggle the TE bit is when the SCTE bit becomes set and

just before writing the next byte to the SCDR.

Inversion of transmitted output

The transmit inversion bit (TXINV) in SCI control register 1 (SCC1)

reverses the polarity of transmitted data. All transmitted values,

including idle, break, start, and stop bits, are inverted when TXINV is

at ‘1’. See SCI control register 1 (SCC1) on page 199.

Transmitter interrupts

The following conditions can generate CPU interrupt requests from

the SCI transmitter:

• SCI transmitter empty (SCTE) — The SCTE bit in SCS1 indicates

that the SCDR has transferred a character to the transmit shift

register. SCTE can generate a transmitter CPU interrupt request

or a transmitter DMA service request. Setting the SCI transmit

interrupt enable bit, SCTIE, in SCC2 enables the SCTE bit to

generate transmitter CPU interrupt requests. Setting both the

SCTIE bit and the DMA transfer enable bit, DMATE, in SCC3

enables the SCTE bit to generate transmitter DMA service

requests.

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Serial Communications Interface Module (SCI)

• Transmission complete (TC) — The TC bit in SCS1 indicates that

the transmit shift register and the SCDR are empty and that no

break or idle character has been generated. The transmission

complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to

generate transmitter CPU interrupt requests.

Receiver

Figure 3 shows the structure of the SCI receiver

Character length

The receiver can accommodate either 8-bit or 9-bit data. The state of

the M bit in SCI control register 1 (SCC1) determines character

length. When receiving 9-bit data, bit R8 in SCI control register 2

(SCC2) is the ninth bit (bit 8). When receiving 8-bit data, bit R8 is a

copy of the eighth bit (bit 7).

Character reception

During an SCI reception, the receive shift register shifts characters in

from the PTE1/RxD pin. The SCI data register (SCDR) is the

read-only buffer between the internal data bus and the receive shift

register.

After a complete character shifts into the receive shift register, the

data portion of the character transfers to the SCDR. The SCI receiver

full bit, SCRF, in SCI status register 1 (SCS1) becomes set, indicating

that the received byte can be read. If the SCI receive interrupt enable

bit, SCRIE, in SCC2 is also set, the SCRF bit generates a receiver

CPU interrupt request or a receiver DMA service request.

The SCRF bit generates a receiver DMA service request if the DMA

receive enable bit, DMARE, in SCI control register 3 (SCC3) is set.

Setting the DMARE bit enables the SCRF bit to generate receiver

DMA service requests and disables receiver CPU interrupt requests.

Data sampling

The receiver samples the PTE1/RxD pin at the RT clock rate. The RT

clock is an internal signal with a frequency 16 times the baud rate. To

adjust for baud rate mismatch, the RT clock is resynchronized at the

following times (see Figure 4):

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Serial Communications Interface Module (SCI)

Functional description

.

INTERNAL BUS

SCR1

SCR2

SCR0

SCP1

SCP0

SCI DATA REGISTER

11-BIT

PRE-

SCALER

BAUD

DIVIDER

÷ 4

÷ 16

RECEIVE SHIFT REGISTER

CGMXCLK

DATA

RECOVERY

H

8

7

6

5

4

3

2

1

0

L

PTE1/RxD

ALL ZEROS

BKF

RPF

M

RWU

SCRF

IDLE

WAKE

ILTY

WAKE-UP

LOGIC

PEN

PTY

R8

PARITY

CHECKING

IDLE

ILIE

DMARE

SCRF

SCRIE

DMARE

SCRIE

SCRF

SCRIE

DMARE

OR

ORIE

NF

NEIE

FE

FEIE

PE

PEIE

Figure 3. SCI receiver block diagram

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Table 3. SCI receiver I/O register summary

Register name

Bit 7

6

5

4

3

2

1

Bit 0 Addr.

WAKE ILTY PEN PTY $0013

TE RE RWU SBK $0014

T8 DMAREDMATE ORIE NEIE FEIE PEIE $0015

SCI control register 1 (SCC1)LOOPS ENSCI TXINV

M

SCI control register 2 (SCC2) SCTIE TCIE SCRIE ILIE

SCI control register 3 (SCC3) R8

SCI status register 1 (SCS1) SCTE

SCI status register 2 (SCS2)

SCI data register (SCDR)

TC

SCRF IDLE

OR

NF

FE

PE $0016

RPF $0017

$0018

BKF

SCI baud rate register (SCBR)

SCP1 SCP0

SCR2 SCR1 SCR0 $0019

= Unimplemented

R

= Reserved

• After every start bit

• After the receiver detects a data bit change from ‘1’ to ‘0’ (after the

majority of data bit samples at RT8, RT9, and RT10 returns a valid

‘1’ and the majority of the next RT8, RT9, and RT10 samples

returns a valid ‘0’).

START BIT

LSB

PTE1/RxD

SAMPLES

START BIT

QUALIFICATION

START BIT

DATA

VERIFICATION SAMPLING

RT

CLOCK

RT CLOCK

STATE

RT CLOCK

RESET

Figure 4. Receiver data sampling

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Functional description

To locate the start bit, data recovery logic does an asynchronous

search for a ‘0’ preceded by three ‘1’s. When the falling edge of a

possible start bit occurs, the RT clock begins to count to 16.

To verify the start bit and to detect noise, data recovery logic takes

samples at RT3, RT5, and RT7. Table 4 summarizes the results of

the start bit verification samples.

Table 4. Start bit veriﬁcation

RT3, RT5, and RT7 samples Start bit verification

Noise flag

000

001

010

011

100

101

110

111

Yes

No

0

1

0

1

0

Yes

No

If start bit verification is not successful, the RT clock is reset and a

new search for a start bit begins.

To determine the value of a data bit and to detect noise, recovery logic

takes samples at RT8, RT9, and RT10. Table 5 summarizes the

results of the data bit samples.

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Table 5. Data bit recovery

RT8, RT9, and RT10 Samples Data bit determination Noise flag

000

001

010

011

100

101

110

111

0

1

0

1

0

1

0

NOTE: The RT8, RT9, and RT10 samples do not affect start bit verification. If

any or all of the RT8, RT9, and RT10 start bit samples are ‘1’s following

a successful start bit verification, the noise flag (NF) is set and the

receiver assumes that the bit is a start bit.

To verify a stop bit and to detect noise, recovery logic takes samples

at RT8, RT9, and RT10. Table 6 summarizes the results of the stop

bit samples.

Table 6. Stop bit recovery

RT8, RT9, and RT10 samples

Framing error flag

noise flag

000

001

010

011

100

101

110

111

1

0

1

0

1

0

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Functional description

Framing errors

If the data recovery logic does not detect a ‘1’ where the stop bit

should be in an incoming character, it sets the framing error bit, FE,

in SCS1. The FE flag is set at the same time that the SCRF bit is set.

A break character that has no stop bit also sets the FE bit.

Receiver wake-up

So that the MCU can ignore transmissions intended only for other

receivers in multiple-receiver systems, the receiver can be put into a

standby state. Setting the receiver wake-up bit, RWU, in SCC2 puts

the receiver into a standby state during which receiver interrupts are

disabled.

Depending on the state of the WAKE bit in SCC1, either of two

conditions on the PTE1/RxD pin can bring the receiver out of the

standby state:

• Address mark — An address mark is a ‘1’ in the most significant

bit position of a received character. When the WAKE bit is set, an

address mark wakes the receiver from the standby state by

clearing the RWU bit. The address mark also sets the SCI receiver

full bit, SCRF. Software can then compare the character

containing the address mark to the user-defined address of the

receiver. If they are the same, the receiver remains awake and

processes the characters that follow. If they are not the same,

software can set the RWU bit and put the receiver back into the

standby state.

• Idle input line condition — When the WAKE bit is clear, an idle

character on the PTE1/RxD pin wakes the receiver from the

standby state by clearing the RWU bit. The idle character that

wakes the receiver does not set the receiver idle bit, IDLE, or the

SCI receiver full bit, SCRF. The idle line type bit, ILTY, determines

whether the receiver begins counting ‘1’s as idle character bits

after the start bit or after the stop bit.

NOTE: Clearing the WAKE bit after the PTE1/RxD pin has been idle may cause

the receiver to wake up immediately.

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Receiver interrupts

The following sources can generate CPU interrupt requests from the

SCI receiver:

• SCI receiver full (SCRF) — The SCRF bit in SCS1 indicates that

the receive shift register has transferred a character to the SCDR.

SCRF can generate a receiver CPU interrupt request or a receiver

DMA service request.. Setting the SCI receive interrupt enable bit,

SCRIE, in SCC2 enables the SCRF bit to generate receiver CPU

interrupts. Setting both the SCRIE bit and the DMA receive enable

bit, DMARE, in SCC3 enables receiver DMA service requests and

disables receiver CPU interrupt requests.

• Idle input (IDLE) — The IDLE bit in SCS1 indicates that 10 or 11

consecutive ‘1’s shifted in from the PTE1/RxD pin. The idle line

interrupt enable bit, ILIE, in SCC2 enables the IDLE bit to generate

CPU interrupt requests.

NOTE: When receiver DMA service requests are enabled (DMARE = 1), then

receiver CPU interrupt requests are disabled, and the state of the ILIE

bit has no effect.

Error interrupts

The following receiver error flags in SCS1 can generate CPU interrupt

requests:

• Receiver overrun (OR) — The OR bit indicates that the receive

shift register shifted in a new character before the previous

character was read from the SCDR. The previous character

remains in the SCDR, and the new character is lost. The overrun

interrupt enable bit, ORIE, in SCC3 enables OR to generate SCI

error CPU interrupt requests.

• Noise flag (NF) — The NF bit is set when the SCI detects noise on

incoming data or break characters, including start, data, and stop

bits. The noise error interrupt enable bit, NEIE, in SCC3 enables

NF to generate SCI error CPU interrupt requests.

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Serial Communications Interface Module (SCI)

Functional description

• Framing error (FE) — The FE bit in SCS1 is set when a ‘0’ occurs

where the receiver expects a stop bit. The framing error interrupt

enable bit, FEIE, in SCC3 enables FE to generate SCI error CPU

interrupt requests.

• Parity error (PE) — The PE bit in SCS1 is set when the SCI

detects a parity error in incoming data. The parity error interrupt

enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU

interrupt requests.

Error flags during DMA service requests

When the DMA is servicing the SCI receiver, it clears the SCRF bit

when it reads the SCI data register. The DMA does not clear the other

status bits (BKF or RPF), nor does it clear error bits (OR, NF, FE, and

PE). If the error bits are enabled to generate interrupt requests, the

interrupt requests may accumulate during DMA servicing. To clear

error bits while the DMA is servicing the receiver, enable SCI error

CPU interrupts and clear the bits in an interrupt routine. Note the

following latency considerations:

1. If interrupt latency is short enough for an error bit to be serviced

before the next SCRF, then it can be determined which byte

caused the error. If interrupt latency is long enough for a new

SCRF to occur before servicing an error bit, then:

a. It cannot be determined whether the error bit being serviced is

due to the byte in the SCI data register or to a previous byte.

Multiple errors can accumulate that correspond to different

bytes. In a message-based system, you may have to repeat

the entire message

b. When the DMA is enabled to service the SCI receiver, merely

reading the SCI data register clears the SCRF bit. The second

step in clearing an error bit, reading the SCI data register,

could inadvertently clear a new, unserviced SCRF that

occurred during the error-servicing routine. Then the DMA

would ignore the byte that set the new SCRF, and the new

byte would be lost.

To prevent clearing of an unserviced SCRF bit, clear the

SCRIE bit at the beginning of the error-servicing interrupt

routine and set it at the end. Clearing SCRIE disables DMA

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service so that both a read of SCS1 and a read of SCDR are

required to clear the SCRF bit. Setting SCRIE enables DMA

service so that the DMA can recognize a service request that

occurred during the error-servicing interrupt routine.

c. In the CPU interrupt routine to service error bits, do not use

BRSET or BRCLR instructions. BRSET and BRCLR read the

SCS1 register, which is the first step in clearing the register.

Then the DMA could read the SCI data register, the second

step in clearing it, thereby clearing all error bits. The next read

of the data register would miss any error bits that were set.

2. DMA latency should be short enough so that an SCRF is serviced

before the next SCRF occurs. If DMA latency is long enough for a

new SCRF to occur before servicing an error bit, then:

a. Overruns occur. Set the ORIE bit to enable SCI error CPU

interrupt requests and service the overrun in an interrupt

routine. In a message-based system, disable the DMA in the

interrupt routine and manually recover. Otherwise, the byte

that was lost in the overrun could prevent the DMA from

reaching its byte count. If the DMA reaches it byte count in the

following message, two messages may be corrupted.

b. If the CPU does not service an overrun interrupt request, the

DMA can eventually clear the SCRF bit by reading the SCI

data register. The OR bit remains set. Each time a new byte

sets the SCRF bit, new data transfers from the shift register to

the SCI data register (provided that another overrun does not

occur), even though the OR bit is set. The DMA removed the

overrun condition by reading the data register, but the OR bit

has not been cleared.

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Low-power modes

The WAIT and STOP instructions put the MCU in

low-power-consumption standby modes.

Wait mode

The SCI module remains active after the execution of a WAIT

instruction. In wait mode the SCI module registers are not accessible by

the CPU. Any enabled CPU interrupt request from the SCI module can

bring the MCU out of wait mode.

If SCI module functions are not required during wait mode, reduce power

consumption by disabling the module before executing the WAIT

instruction.

The DMA can service the SCI without exiting WAIT mode.

STOP mode

The SCI module is inactive after the execution of a STOP instruction.

The STOP instruction does not affect SCI register states. SCI module

operation resumes after an external interrupt.

Because the internal clock is inactive during stop mode, entering stop

mode during an SCI transmission or reception results in invalid data.

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SCI during break module interrupts

The system integration module (SIM) controls whether status bits in

other modules can be cleared during interrupts generated by the break

module. The BCFE bit in the SIM break flag control register (SBFCR)

enables software to clear status bits during the break state. See SIM

break flag control register (SBFCR) on page 106.

To allow software to clear status bits during a break interrupt, write a ‘1’

to the BCFE bit. If a status bit is cleared during the break state, it remains

cleared when the MCU exits the break state.

To protect status bits during the break state, write a ‘0’ to the BCFE bit.

With BCFE at 0 0 0 (its default state), software can read and write I/O

registers during the break state without affecting status bits. Some status

bits have a two-step read/write clearing procedure. If software does the

first step on such a bit before the break, the bit cannot change during the

break state as long as BCFE is at ‘0’. After the break, doing the second

step clears the status bit.

I/O signals

Port E shares two of its pins with the SCI module. The two SCI I/O pins are:

• PTE0/TxD — Transmit data

• PTE1/RxD — Receive data

PTE0/TxD (transmit

data)

The PTE0/TxD pin is the serial data output from the SCI transmitter. The

SCI shares the PTE0/TxD pin with port E. When the SCI is enabled, the

PTE0/TxD pin is an output regardless of the state of the DDRE0 bit in

data direction register E (DDRE).

PTE1/RxD (receive

data)

The PTE1/RxD pin is the serial data input to the SCI receiver. The SCI

shares the PTE1/RxD pin with port E. When the SCI is enabled, the

PTE1/RxD pin is an input regardless of the state of the DDRE1 bit in data

direction register E (DDRE).

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I/O registers

The following I/O registers control and monitor SCI operation:

• SCI control register 1 (SCC1)

• SCI control register 2 (SCC2)

• SCI control register 3 (SCC3)

• SCI status register 1 (SCS1)

• SCI status register 2 (SCS2)

• SCI data register (SCDR)

• SCI baud rate register (SCBR)

SCIcontrolregister

1 (SCC1)

SCI control register 1 does the following:

• Enables loop mode operation

• Enables the SCI

• Controls output polarity

• Controls character length

• Controls SCI wake-up method

• Controls idle character detection

• Enables parity function

• Controls parity type

Bit 7

6

5

TXINV

0

4

M

0

3

WAKE

0

2

ILTY

0

1

PEN

0

Bit 0

PTY

0

Read:

Write:

Reset:

SCC1

$0013

LOOPS ENSCI

0

Figure 5. SCI control register 1 (SCC1)

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LOOPS — Loop mode select bit

This read/write bit enables loop mode operation. In loop mode the

PTE1/RxD pin is disconnected from the SCI, and the transmitter

output goes into the receiver input. Both the transmitter and the

receiver must be enabled to use loop mode. Reset clears the LOOPS

bit.

1 = Loop mode enabled

0 = Normal operation enabled

ENSCI — Enable SCI bit

This read/write bit enables the SCI and the SCI baud rate generator.

Clearing ENSCI sets the SCTE and TC bits in SCI status register 1

and disables transmitter interrupts. Reset clears the ENSCI bit.

1 = SCI enabled

0 = SCI disabled

TXINV — Transmit inversion bit

This read/write bit reverses the polarity of transmitted data. Reset

clears the TXINV bit.

1 = Transmitter output inverted

0 = Transmitter output not inverted

NOTE: Setting the TXINV bit inverts all transmitted values, including idle, break,

start, and stop bits.

M — Mode (character length) bit

This read/write bit determines whether SCI characters are 8 or 9 bits

long (see Table 7). The ninth bit can serve as an extra stop bit, as a

receiver wake-up signal, or as a parity bit. Reset clears the M bit.

1 = 9-bit SCI characters

0 = 8-bit SCI characters

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I/O registers

WAKE — wake-up condition bit

This read/write bit determines which condition wakes up the SCI: a ‘1’

(address mark) in the most significant bit position of a received

character or an idle condition on the PTE1/RxD pin. Reset clears the

WAKE bit.

1 = Address mark wake-up

0 = Idle line wake-up

ILTY — Idle line type bit

This read/write bit determines when the SCI starts counting ‘1’s as

idle character bits. The counting begins either after the start bit or after

the stop bit. If the count begins after the start bit, then a string of ‘1’s

preceding the stop bit may cause false recognition of an idle

character. Beginning the count after the stop bit avoids false idle

character recognition, but requires properly synchronized

transmissions. Reset clears the ILTY bit.

1 = Idle character bit count begins after stop bit

0 = Idle character bit count begins after start bit

PEN — Parity enable bit

This read/write bit enables the SCI parity function (see Table 7).

When enabled, the parity function inserts a parity bit in the most

significant bit position (seeFigure 6). Reset clears the PEN bit.

1 = Parity function enabled

0 = Parity function disabled

PTY — Parity bit

This read/write bit determines whether the SCI generates and checks

for odd parity or even parity (see Table 7). Reset clears the PTY bit.

1 = Odd parity

0 = Even parity

NOTE: Changing the PTY bit in the middle of a transmission or reception can

generate a parity error.

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Table 7. Character format selection

Control Bits

Character Format

M

PEN:PTY

Start bits

Data bits

Parity

None

Even

Odd

STOP bits

Character length

10 bits

0

1

0

1

0X

10

11

10

11

1

8

9

7

8

1

11 bits

10 bits

Even

Odd

11 bits

SCI Control

Register 2 (SCC2)

SCI control register 2 does the following:

• Enables the following CPU interrupt requests:

– Enables the SCTE bit to generate transmitter CPU interrupt

requests

– Enables the TC bit to generate transmitter CPU interrupt

requests

– Enables the SCRF bit to generate receiver CPU interrupt

requests

– Enables the IDLE bit to generate receiver CPU interrupt

requests

• Enables the transmitter

• Enables the receiver

• Enables SCI wake-up

• Transmits SCI break characters

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I/O registers

Bit 7

SCTIE

0

6

TCIE

0

5

SCRIE

0

4

ILIE

0

3

TE

0

2

RE

0

1

RWU

0

Bit 0

SBK

0

Read:

Write:

Reset:

SCC2

$0014

Figure 6. SCI control register 2 (SCC2)

SCTIE — SCI transmit interrupt enable bit

This read/write bit enables the SCTE bit to generate SCI transmitter

CPU interrupt requests or DMA service requests. Setting the SCTIE

bit and clearing the DMA transfer enable bit, DMATE, in SCC3

enables the SCTE bit to generate CPU interrupt requests. Setting

both the SCTIE and DMATE bits enables the SCTE bit to generate

DMA service requests. Setting both SCRIE and DMARE enables

SCRF to generate DMA service requests. Reset clears the SCTIE bit.

1 = SCTE enabled to generate CPU interrupt or DMA service

requests

0 = SCTE not enabled to generate CPU interrupt or DMA service

requests

TCIE — Transmission complete interrupt enable bit

This read/write bit enables the TC bit to generate SCI transmitter CPU

interrupt requests. Reset clears the TCIE bit.

1 = TC enabled to generate CPU interrupt requests

0 = TC not enabled to generate CPU interrupt requests

SCRIE — SCI receive interrupt enable bit

This read/write bit enables the SCRF bit to generate SCI receiver

CPU interrupt requests or SCI receiver DMA service requests. Setting

the SCRIE bit and clearing the DMA receive enable bit, DMARE,in

SCC3 enables the SCRF bit to generate CPU interrupt requests.

Reset clears the SCRIE bit.

1 = SCRF enabled to generate CPU interrupt or DMA service

requests

0 = SCRF not enabled to generate CPU interrupt or DMA service

requests

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ILIE — Idle line interrupt enable bit

This read/write bit enables the IDLE bit to generate SCI receiver CPU

interrupt requests. Reset clears the ILIE bit.

1 = IDLE enabled to generate CPU interrupt requests

0 = IDLE not enabled to generate CPU interrupt requests

NOTE: When SCI receiver DMA service requests are enabled (DMARE = 1),

then SCI receiver CPU interrupt requests are disabled, and the state of

the ILIE bit has no effect.

TE — Transmitter enable bit

Setting this read/write bit begins the transmission by sending a

preamble of 10 or 11 ‘1’s from the transmit shift register to the

PTE2/TxD pin. If software clears the TE bit, the transmitter completes

any transmission in progress before the PTE0/TxD returns to the idle

condition (’1’). Clearing and then setting TE during a transmission

queues an idle character to be sent after the character currently being

transmitted. Reset clears the TE bit.

1 = Transmitter enabled

0 = Transmitter disabled

NOTE: Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is

clear. ENSCI is in SCI control register 1.

RE — Receiver enable bit

Setting this read/write bit enables the receiver. Clearing the RE bit

disables the receiver but does not affect receiver interrupt flag bits.

Reset clears the RE bit.

1 = Receiver enabled

0 = Receiver disabled

NOTE: Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is

clear. ENSCI is in SCI control register 1.

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I/O registers

RWU — Receiver wake-up bit

This read/write bit puts the receiver in a standby state during which

receiver interrupts are disabled. The WAKE bit in SCC1 determines

whether an idle input or an address mark brings the receiver out of the

standby state and clears the RWU bit. Reset clears the RWU bit.

1 = Standby state

0 = Normal operation

SBK — Send break bit

Setting and then clearing this read/write bit transmits a break

character followed by a ‘1’. The ‘1’ after the break character

guarantees recognition of a valid start bit. If SBK remains set, the

transmitter continuously transmits break characters with no ‘1’s

between them. Reset clears the SBK bit.

1 = Transmit break characters

0 = No break characters being transmitted

NOTE: Do not toggle the SBK bit immediately after setting the SCTE bit.

Toggling SBK too early causes the SCI to send a break character

instead of a preamble.

SCIcontrolregister

SCI control register 3 does the following:

3 (SCC3)

• Stores the ninth SCI data bit received and the ninth SCI data bit to

be transmitted

• Enables SCI receiver full (SCRF) DMA service requests

• Enables SCI transmitter empty (SCTE) DMA service requests

• Enables the following interrupts:

– Receiver overrun interrupts

– Noise error interrupts

– Framing error interrupts

– Parity error interrupts

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Bit 7

6

5

4

3

ORIE

0

2

NEIE

0

1

FEIE

0

Bit 0

PEIE

0

Read:

Write:

Reset:

R8

SCC3

$0015

T8

U

DMARE DMATE

U

0

= Unimplemented

U = Unaffected

R = Reserved

Figure 7. SCI control register 3 (SCC3)

R8 — Received bit 8

When the SCI is receiving 9-bit characters, R8 is the read-only ninth

bit (bit 8) of the received character. R8 is received at the same time

that the SCDR receives the other 8 bits.

When the SCI is receiving 8-bit characters, R8 is a copy of the eighth

bit (bit 7). Reset has no effect on the R8 bit.

T8 — Transmitted bit 8

When the SCI is transmitting 9-bit characters, T8 is the read/write

ninth bit (bit 8) of the transmitted character. T8 is loaded into the

transmit shift register at the same time that the SCDR is loaded into

the transmit shift register. Reset has no effect on the T8 bit.

DMARE — DMA receive enable bit

This read/write bit enables the DMA to service SCI receiver DMA

service requests generated by the SCRF bit. (See 14.7.4.) Setting the

DMARE bit disables SCI receiver CPU interrupt requests. Reset

clears the DMARE bit.

1 = DMA enabled to service SCI receiver DMA service requests

generated by the SCRF bit

(SCI receiver CPU interrupt requests disabled)

0 = DMA not enabled to service SCI receiver DMA service requests

generated by the SCRF bit

(SCI receiver CPU interrupt requests enabled)

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I/O registers

DMATE — DMA transfer enable bit

This read/write bit enables SCI transmitter empty (SCTE) DMA

service requests. <blue>See SCI status register 1 (SCS1). Setting

the DMATE bit disables SCTE CPU interrupt requests. Reset clears

DMATE.

1 = SCTE DMA service requests enabled (SCTE CPU interrupt

requests disabled)

0 = SCTE DMA service requests disabled (SCTE CPU interrupt

requests enabled)

ORIE — Receiver overrun interrupt enable bit

This read/write bit enables SCI error CPU interrupt requests

generated by the receiver overrun bit, OR.

1 = SCI error CPU interrupt requests from OR bit enabled

0 = SCI error CPU interrupt requests from OR bit disabled

NEIE — Receiver noise error interrupt enable bit

This read/write bit enables SCI error CPU interrupt requests

generated by the noise error bit, NE. Reset clears NEIE.

1 = SCI error CPU interrupt requests from NE bit enabled.

0 = SCI error CPU interrupt requests from NE bit disabled

FEIE — Receiver framing error interrupt enable bit

This read/write bit enables SCI error CPU interrupt requests

generated by the framing error bit, FE. Reset clears FEIE.

1 = SCI error CPU interrupt requests from FE bit enabled

0 = SCI error CPU interrupt requests from FE bit disabled

PEIE — Receiver parity error interrupt enable bit

This read/write bit enables SCI receiver CPU interrupt requests

generated by the parity error bit, PE. (see SCI status register 1

(SCS1) on page 208). Reset clears PEIE.

1 = SCI error CPU interrupt requests from PE bit enabled

0 = SCI error CPU interrupt requests from PE bit disabled

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SCI status register

1 (SCS1)

SCI status register 1 contains flags to signal the following conditions:

• Transfer of SCDR data to transmit shift register complete

• Transmission complete

• Transfer of receive shift register data to SCDR complete

• Receiver input idle

• Receiver overrun

• Noisy data

• Framing error

• Parity error

Bit 7

6

5

4

3

2

1

Bit 0

PE

Read:

Write:

Reset:

SCTE

TC

SCRF

IDLE

OR

NF

FE

SCS1

$0016

1

0

= Unimplemented

Figure 8. SCI status register 1 (SCS1)

SCTE — SCI transmitter empty bit

This clearable, read-only bit is set when the SCDR transfers a

character to the transmit shift register. SCTE can generate an SCI

transmitter CPU interrupt request or an SCI transmitter DMA service

request. When the SCTIE bit in SCC2 is set and the DMATE bit in

SCC3 is clear, SCTE generates an SCI transmitter CPU interrupt

request. With both the SCTIE and DMATE bits set, SCTE generates

an SCI transmitter DMA service request. In normal operation, clear

the SCTE bit by reading SCS1 with SCTE set and then writing to

SCDR. In DMA transfers, the DMA automatically clears the SCTE bit

when it writes to the SCDR. Reset sets the SCTE bit.

1 = SCDR data transferred to transmit shift register

0 = SCDR data not transferred to transmit shift register

NOTE: Setting the TE bit for the first time also sets the SCTE bit. When enabling

SCI transmitter DMA service requests, set the TE bit after setting the

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I/O registers

DMATE bit. Otherwise setting the TE and SCTIE bits generates an SCI

transmitter CPU interrupt request instead of a DMA service request.

TC — Transmission complete bit

This read-only bit is set when the SCTE bit is set, and no data,

preamble, or break character is being transmitted. TC generates an

SCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also

set. When the DMA services an SCI transmitter DMA service request,

the DMA clears the TC bit by writing to the SCDR. TC is automatically

cleared when data, preamble or break is queued and ready to be sent.

There may be up to 1.5 transmitter clocks of latency between

queueing data, preamble, and break and the transmission actually

starting. Reset sets the TC bit.

1 = No transmission in progress

0 = Transmission in progress

SCRF — SCI receiver full bit

This clearable, read-only bit is set when the data in the receive shift

register transfers to the SCI data register. SCRF can generate an SCI

receiver CPU interrupt request or an SCI receiver DMA service

request. When the SCRIE bit in SCC2 is set and the DMARE bit in

SCC3 is clear, SCRF generates a CPU interrupt request. With both

the SCRIE and DMARE bits set, SCRF generates a DMA service

request. In normal operation, clear the SCRF bit by reading SCS1

with SCRF set and then reading the SCDR. In DMA transfers, the

DMA clears the SCRF bit when it reads the SCDR. Reset clears

SCRF.

1 = Received data available in SCDR

0 = Data not available in SCDR

IDLE — Receiver idle bit

This clearable, read-only bit is set when 10 or 11 consecutive ’1’s

appear on the receiver input. IDLE generates an SCI error CPU

interrupt request if the ILIE bit in SCC2 is also set and the DMARE bit

in SCC3 is clear. Clear the IDLE bit by reading SCS1 with IDLE set

and then reading the SCDR. After the receiver is enabled, it must

receive a valid character that sets the SCRF bit before an idle

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condition can set the IDLE bit. Also, after the IDLE bit has been

cleared, a valid character must again set the SCRF bit before an idle

condition can set the IDLE bit. Reset clears the IDLE bit.

1 = Receiver input idle

0 = Receiver input active (or idle since the IDLE bit was cleared)

OR — Receiver overrun bit

This clearable, read-only bit is set when software fails to read the

SCDR before the receive shift register receives the next character.

The OR bit generates an SCI error CPU interrupt request if the ORIE

bit in SCC3 is also set. The data in the shift register is lost, but the data

already in the SCDR is not affected. Clear the OR bit by reading SCS1

with OR set and then reading the SCDR. Reset clears the OR bit.

1 = Receive shift register full and SCRF = 1

0 = No receiver overrun

Software latency may allow an overrun to occur between reads of

SCS1 and SCDR in the flag-clearing sequence. Figure 9 shows the

normal flag-clearing sequence and an example of an overrun caused

by a delayed flag-clearing sequence. The delayed read of SCDR

does not clear the OR bit because OR was not set when SCS1 was

read. Byte 2 caused the overrun and is lost. The next flag-clearing

sequence reads byte 3 in the SCDR instead of byte 2.

In applications that are subject to software latency or in which it is

important to know which byte is lost due to an overrun, the

flag-clearing routine can check the OR bit in a second read of SCS1

after reading the data register.

NF — Receiver noise flag bit

This clearable, read-only bit is set when the SCI detects noise on the

PTE1/RxD pin. NF generates an NF CPU interrupt request if the NEIE

bit in SCC3 is also set. Clear the NF bit by reading SCS1 and then

reading the SCDR. Reset clears the NF bit.

1 = Noise detected

0 = No noise detected

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I/O registers

NORMALFLAGCLEARINGSEQUENCE

BYTE 1

BYTE 2

BYTE 3

BYTE 4

READ SCS1

SCRF = 1

OR = 0

READ SCS1

SCRF = 1

OR = 0

READ SCS1

SCRF = 1

OR = 0

READ SCDR

(BYTE 1)

READ SCDR

(BYTE 2)

READ SCDR

(BYTE 3)

DELAYEDFLAGCLEARINGSEQUENCE

BYTE 1

BYTE 2

BYTE 3

BYTE 4

READ SCS1

SCRF = 1

OR = 0

READ SCS1

SCRF = 1

OR = 1

READ SCDR

(BYTE 3)

READ SCDR

(BYTE 1)

Figure 9. Flag clearing sequence

FE — Receiver framing error bit

This clearable, read-only bit is set when a logic is accepted as the

STOP bit. FE generates an SCI error CPU interrupt request if the

FEIE bit in SCC3 also is set. Clear the FE bit by reading SCS1 with

FE set and then reading the SCDR. Reset clears the FE bit.

1 = Framing error detected

0 = No framing error detected

PE — Receiver parity error bit

This clearable, read-only bit is set when the SCI detects a parity error

in incoming data. PE generates a PE CPU interrupt request if the

PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with

PE set and then reading the SCDR. Reset clears the PE bit.

1 = Parity error detected

0 = No parity error detected

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SCI status register

2 (SCS2)

SCI status register 2 contains flags to signal the following conditions:

• Break character detected

• Incoming data

Bit 7

6

5

4

0

3

0

2

0

1

Bit 0

Read:

Write:

Reset:

BKF

RPF

SCS2

$0017

0

= Unimplemented

Figure 10. SCI status register 2 (SCS2)

BKF — Break flag bit

This clearable, read-only bit is set when the SCI detects a break

character on the PTE1/RxD pin. In SCS1, the FE and SCRF bits are

also set. In 9-bit character transmissions, the R8 bit in SCC3 is

cleared. BKF does not generate a CPU interrupt request. Clear BKF

by reading SCS2 with BKF set and then reading the SCDR. Once

cleared, BKF can become set again only after ‘1’s again appear on

the PTE1/RxD pin followed by another break character. Reset clears

the BKF bit.

1 = Break character detected

0 = No break character detected

RPF — Reception in progress flag bit

This read-only bit is set when the receiver detects a ‘0’ during the RT1

time period of the start bit search. RPF does not generate an interrupt

request. RPF is reset after the receiver detects false start bits (usually

from noise or a baud rate mismatch, or when the receiver detects an

idle character. Polling RPF before disabling the SCI module or

entering STOP mode can show whether a reception is in progress.

1 = Reception in progress

0 = No reception in progress

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I/O registers

SCI data register

(SCDR)

The SCI data register is the buffer between the internal data bus and the

receive and transmit shift registers. Reset has no effect on data in the

SCI data register.

Bit 7

R7

6

5

4

3

2

1

Bit 0

R0

Read:

Write:

Reset:

R6

T6

R5

T5

R4

T4

R3

T3

R2

T2

R1

T1

SCDR

$0018

T7

T0

Unaffected by reset

Figure 11. SCI data register (SCDR)

R7/T7–R0/T0 — Receive/Transmit data bits

Reading address $0018 accesses the read-only received data bits,

R7–R0. Writing to address $0018 writes the data to be transmitted,

T7–T0. Reset has no effect on the SCI data register.

SCI baud rate

register (SCBR)

The baud rate register selects the baud rate for both the receiver and the

transmitter.

Bit 7

6

5

SCP1

0

4

SCP0

0

3

2

SCR2

0

1

SCR1

0

Bit 0

SCR0

0

Read:

Write:

Reset:

SCBR

$0019

0

= Unimplemented

Figure 12. SCI Baud Rate Register (SCBR)

SCP1 and SCP0 — SCI Baud Rate Prescaler Bits

These read/write bits select the baud rate prescaler divisor as shown

in Table 8. Reset clears SCP1 and SCP0.

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Table 8. SCI baud rate prescaling

SCP1:0

Prescaler Divisor (PD)

00

01

10

11

1

3

4

13

SCR2–SCR0 — SCI baud rate select bits

These read/write bits select the SCI baud rate divisor as shown in

Table 9. Reset clears SCR2–SCR0.

Table 9. SCI baud rate selection

SCR2:1:0

000

Baud Rate Divisor (BD)

1

2

001

010

4

011

8

100

16

32

64

128

101

110

111

Use the following formula to calculate the SCI baud rate:

f

XCLK

Baud rate = ----------------------------------

64 × PD × BD

where:

f

= clock frequency

XCLK

PD = prescaler divisor

BD = baud rate divisor

Table 10 shows the SCI baud rates that can be generated with a

4.9152-MHz crystal.

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I/O registers

Table 10. SCI baud rate selection examples

Baud rate

XCLK

Prescaler divisor

Baud rate divisor

(BD)

SCP1:0

SCR2:1:0

(f

= 4.9152 MHz)

(PD)

00

01

10

11

1

000

001

010

011

100

101

110

111

000

001

010

011

100

101

110

111

000

001

010

011

100

101

110

111

000

001

010

011

100

101

110

111

1

2

76,800

38,400

19,200

9600

4800

2400

1200

600

1

4

1

8

1

16

32

64

128

1

3

25,600

12,800

6400

3200

1600

800

3

2

3

4

3

8

3

16

32

64

128

1

3

400

3

200

4

19,200

9600

4800

2400

1200

600

4

2

4

8

4

16

32

64

128

1

4

300

4

150

13

5908

2954

1477

739

2

4

8

16

32

64

128

369

185

92

46

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SPI

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Pin name conventions and I/O register addresses . . . . . . . . . . . . . . 219

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Master mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

Slave mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Clock phase and polarity controls. . . . . . . . . . . . . . . . . . . . . . . . . 225

Transmission format when CPHA = ‘0’. . . . . . . . . . . . . . . . . . . . . 225

Transmission format when CPHA = ‘1’. . . . . . . . . . . . . . . . . . . . . 227

Transmission initiation latency . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Error conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Overflow error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Mode fault error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

Queuing transmission data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

WAIT mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

SPI during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

MISO (Master in/Slave out). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

MOSI (Master out/Slave in). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

SPSCK (serial clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

SS (slave select). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

VSS (clock ground). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

I/O registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

SPI control register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

SPI status and control register (SPSCR) . . . . . . . . . . . . . . . . . . . 246

SPI data register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

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Serial Peripheral Interface Module (SPI)

Introduction

This section describes the serial peripheral interface module (SPI,

Version C), which allows full-duplex, synchronous, serial

communications with peripheral devices.

NOTE: DMA associated functions are only valid if the MCU has a DMA module.

Features

Features of the SPI module include the following:

• Full-duplex operation

• Master and slave modes

• Double-buffered operation with separate transmit and receive

registers

• Four master mode frequencies (maximum = bus frequency ÷ 2)

• Maximum slave mode frequency = bus frequency

• Serial clock with programmable polarity and phase

• Two separately enabled interrupts with CPU service:

– SPRF (SPI receiver full)

– SPTE (SPI transmitter empty)

• Mode fault error flag with CPU interrupt capability

• Overflow error flag with CPU interrupt capability

• Programmable wired-OR mode

2

• I C (inter-integrated circuit) compatibility

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Pin name conventions and I/O register addresses

The text that follows describes both SPI1 and SPI2. The SPI I/O pin

names are SS (slave select), SPSCK (SPI serial clock), V (clock

SS

ground), MOSI (master out slave in), and MISO (master in slave out).

The two SPIs share eight I/O pins with two parallel I/O ports. The full

names of the SPI I/O pins are as follows:

Table 1. Pin name conventions

V

SPI Generic Pin Names:

MISO

MOSI

SS

SCK

SS

Full SPI Pin Names: SPI

PTE5/MISO

PTE6/MOSI

PTE4/SS

PTE7/SPSCK CGND

Table 2. I/O register addresses

Register name

Register address

$0010

SPI Control Register (SPICR)

SPI Status and Control Register (SPISCR)

SPI Data Register (SPIDR)

$0011

$0012

The generic pins names appear in the text that follows.

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Functional description

Figure 1 summarizes the SPI I/O registers and Figure 2 show the

structure of the SPI module.

Register name

R/W Bit 7

6

5

4

3

2

1

Bit 0

Read:

SPRIE

Write:

SPI Control Register (SPCR)

R

0

SPMSTR CPOL CPHA SPWOM SPE SPTIE

Reset:

0

1

0

1

0

Read: SPRF

OVRF MODF SPTE

SPI Status and Control Register

(SPSCR)

ERRIE

MODFEN SPR1 SPR0

Write:

R

0

R

0

R

0

R

1

Reset:

0

Read: R7

Write: T7

Reset:

R6

T6

R5

T5

R4

T4

R3

T3

R2

T2

R1

T1

R0

T0

SPI Data Register (SPDR)

Unaffected by reset

R

= Reserved

Figure 1. SPI I/O register summary

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Serial Peripheral Interface Module (SPI)

Functional description

INTERNAL BUS

TRANSMIT DATA REGISTER

SHIFT REGISTER

CGMOUT ÷ 2

(FROM SIM)

MISO

MOSI

7

6

5

4

3

2

1

0

÷ 2

÷ 8

CLOCK

RECEIVE DATA REGISTER

DIVIDER

÷ 32

CONTROL

LOGIC

÷ 128

CLOCK

SPSCK

SS

SPMSTR

SPE

SELECT

M

CLOCK

LOGIC

S

SPR1

SPR0

SPMSTR CPHA

CPOL

MODFEN

ERRIE

SPTIE

SPWOM

TRANSMITTER CPU INTERRUPT REQUEST

RECEIVER/ERROR CPU INTERRUPT REQUEST

SPI

CONTROL

SPRIE

SPE

SPRF

SPTE

OVRF

MODF

Figure 2. SPI module block diagram

The SPI module allows full-duplex, synchronous, serial communication

between the MCU and peripheral devices, including other MCUs.

Software can poll the SPI status flags or SPI operation can be

interrupt-driven.

The following paragraphs describe the operation of the SPI module.

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Serial Peripheral Interface Module (SPI)

Master mode

The SPI operates in master mode when the SPI master bit, SPMSTR, is

set.

NOTE: The SPI modules should be configured as master and slave before they

are enabled. Also, the master SPI should be enabled before the slave

SPI. Similarly, Disable the slave SPI should be disabled before disabling

the master SPI. See SPI control register (SPCR) on page 243.

Only a master SPI module can initiate transmissions. Software begins

the transmission from a master SPI module by writing to the SPI data

register. If the shift register is empty, the byte immediately transfers to

the shift register, setting the SPI transmitter empty bit, SPTE. The byte

begins shifting out on the MOSI pin under the control of the serial clock.

See Figure 3.

The SPR1 and SPR0 bits control the baud rate generator and determine

the speed of the shift register. See SPI status and control register

(SPSCR) on page 246. Through the SPSCK pin, the baud rate generator

of the master also controls the shift register of the slave peripheral.

As the byte shifts out on the MOSI pin of the master, another byte shifts

in from the slave on the master’s MISO pin. The transmission ends when

the receiver full bit, SPRF, becomes set. At the same time that SPRF

becomes set, the byte from the slave transfers to the receive data

register. In normal operation, SPRF signals the end of a transmission.

Software clears SPRF by reading the SPI status and control register with

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Functional description

SPRF set and then reading the SPI data register. Writing to the SPI data

register clears the SPTIE bit.

MASTER MCU

SLAVE MCU

MISO

MOSI

MISO

MOSI

SHIFT REGISTER

SPSCK

SS

SPSCK

SS

BAUD RATE

GENERATOR

V_DD

Figure 3. Full-duplex master-slave connections

Slave mode

The SPI operates in slave mode when the SPMSTR bit is clear. In slave

mode the SPSCK pin is the input for the serial clock from the master

MCU. Before a data transmission occurs, the SS pin of the slave MCU

must be at ‘0’. SS must remain low until the transmission is complete.

See Mode fault error on page 232.

In a slave SPI module, data enters the shift register under the control of

the serial clock from the master SPI module. After a byte enters the shift

register of a slave SPI, it transfers to the receive data register, and the

SPRF bit is set. To prevent an overflow condition, slave software must

then read the SPI data register before another byte enters the shift

register.

The maximum frequency of the SPSCK for an SPI configured as a slave

is the bus clock speed (which is twice as fast as the fastest master

SPSCK clock that can be generated). The frequency of the SPSCK for

an SPI configured as a slave does not have to correspond to any

particular SPI baud rate. The baud rate only controls the speed of the

SPSCK generated by an SPI configured as a master. Therefore, the

frequency of the SPSCK for an SPI configured as a slave can be any

frequency less than or equal to the bus speed.

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Serial Peripheral Interface Module (SPI)

A slave SPI must complete the write to the data register at least one bus

cycle before the master SPI starts a transmission. When the clock phase

bit (CPHA) is set, the first edge of SPSCK starts a transmission. When

CPHA is clear, the falling edge of SS starts a transmission. See

Transmission formats on page 225.

If the write to the data register is late, the SPI transmits the data already

in the shift register from the previous transmission.

NOTE: SPSCK must be in the proper idle state before the slave is enabled to

prevent SPSCK from appearing as a clock edge.

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Serial Peripheral Interface Module (SPI)

Transmission formats

During an SPI transmission, data is simultaneously transmitted (shifted

out serially) and received (shifted in serially). A serial clock line

synchronizes shifting and sampling on the two serial data lines. A slave

select line allows individual selection of a slave SPI device; slave

devices that are not selected do not interfere with SPI bus activities. On

a master SPI device, the slave select line can optionally be used to

indicate a multiple-master bus contention.

Clock phase and

polarity controls

Software can select any of four combinations of serial clock (SCK) phase

and polarity using two bits in the SPI control register (SPCR). The clock

polarity is specified by the CPOL control bit, which selects an active high

or low clock and has no significant effect on the transmission format.

The clock phase (CPHA) control bit selects one of two fundamentally

different transmission formats. The clock phase and polarity should be

identical for the master SPI device and the communicating slave device.

In some cases, the phase and polarity are changed between

transmissions to allow a master device to communicate with peripheral

slaves having different requirements.

NOTE: Before writing to the CPOL bit or the CPHA bit, the SPI should be

disabled by clearing the SPI enable bit (SPE).

Transmission

format when

CPHA = Ô0Õ

Figure 4 shows an SPI transmission in which CPHA is ‘0’. The figure

should not be used as a replacement for data sheet parametric

information.Two waveforms are shown for SCK: one for CPOL = ‘0’ and

another for CPOL = ‘1’. The diagram may be interpreted as a master or

slave timing diagram since the serial clock (SCK), master in/slave out

(MISO), and master out/slave in (MOSI) pins are directly connected

between the master and the slave. The MISO signal is the output from

the slave, and the MOSI signal is the output from the master. The SS line

is the slave select input to the slave. The slave SPI drives its MISO

output only when its slave select input (SS) is at ‘0’, so that only the

selected slave drives to the master. The SS pin of the master is not

shown but is assumed to be inactive. The SS pin of the master must be

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MC68HC08AZ0

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Serial Peripheral Interface Module (SPI)

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Serial Peripheral Interface Module (SPI)

high or must be reconfigured as general purpose I/O not affecting the

SPI. See Mode fault error on page 232. When CPHA = ‘0’, the first

SPSCK edge is the MSB capture strobe. Therefore the slave must begin

driving its data before the first SPSCK edge, and a falling edge on the

SS pin is used to start the transmission. The SS pin must be toggled high

and then low between each byte transmitted.

SCK CYCLE #

(FOR REFERENCE)

1

2

3

4

5

6

7

8

SCK (CPOL =’0’)

SCK (CPOL =1)

MOSI

MSB

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

LSB

(FROM MASTER)

MISO

(FROM SLAVE)

MSB

SS (TO SLAVE)

CAPTURE STROBE

Figure 4. Transmission format (CPHA = ‘0’)

MISO/MOSI

MASTER SS

BYTE 1

BYTE 2

BYTE 3

SLAVE SS

(CPHA =’0’)

SLAVE SS

(CPHA = 1)

Figure 5. CPHA/SS timing

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MC68HC08AZ0

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Serial Peripheral Interface Module (SPI)

MOTOROLA

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Serial Peripheral Interface Module (SPI)

Transmission formats

Transmission

format when

CPHA = Ô1Õ

Figure 6 shows an SPI transmission in which CPHA is ‘1’. The figure

should not be used as a replacement for data sheet parametric

information. Two waveforms are shown for SCK: one for CPOL = ‘0’ and