MC74HC373ADT [MOTOROLA]
Octal 3-State Non-Inverting Transparent Latch; 八路三态非反相透明锁存器
| 型号： | MC74HC373ADT |
| 厂家： | 
MOTOROLA |
| 描述： | Octal 3-State Non-Inverting Transparent Latch |
| 文件： | 总8页 (文件大小：283K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
High–Performance Silicon–Gate CMOS
20
20
The MC54/74HC373A is identical in pinout to the LS373. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes low,
data meeting the setup and hold time becomes latched.
1
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
1
The Output Enable input does not affect the state of the latches, but when
Output Enable is high, all device outputs are forced to the high–impedance
state. Thus, data may be latched even when the outputs are not enabled.
The HC373A is identical in function to the HC573A which has the data
inputs on the opposite side of the package from the outputs to facilitate PC
board layout.
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
20
20
20
1
SD SUFFIX
SSOP PACKAGE
CASE 940C–03
1
The HC373A is the non–inverting version of the HC533A.
DT SUFFIX
TSSOP PACKAGE
CASE 948E–02
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
1
ORDERING INFORMATION
Low Input Current: 1.0 µA
MC54HCXXXAJ
Ceramic
Plastic
SOIC
SSOP
TSSOP
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
MC74HCXXXAN
MC74HCXXXADW
MC74HCXXXASD
MC74HCXXXADT
•
Chip Complexity: 186 FETs or 46.5 Equivalent Gates
LOGIC DIAGRAM
PIN ASSIGNMENT
OUTPUT
ENABLE
Q0
2
5
1
20
V
3
CC
D0
D1
D2
D3
D4
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
3
19
18
Q7
D7
4
D0
D1
6
7
4
17
D6
8
9
DATA
INPUTS
NONINVERTING
OUTPUTS
Q1
Q2
5
16
15
14
13
12
11
Q6
Q5
D5
D4
Q4
13
12
15
16
19
6
14
17
18
D5
D6
D7
D2
7
D3
8
Q3
9
LATCH
ENABLE
GND
10
11
1
PIN 20 = V
CC
PIN 10 = GND
LATCH ENABLE
OUTPUT ENABLE
FUNCTION TABLE
Inputs
Output
Design Criteria
Internal Gate Count*
Value
46.5
1.5
Units
Output Latch
Enable Enable
ea
ns
D
Q
L
L
L
H
H
L
H
L
X
X
H
Internal Gate Propagation Delay
Internal Gate Power Dissipation
L
No Change
Z
5.0
µW
pJ
H
X
Speed Power Product
0.0075
X = Don’t Care
Z = High Impedance
* Equivalent to a two–input NAND gate.
10/95
REV 6
Motorola, Inc. 1995
MC54/74HC373A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 1.5 to V
+ 1.5
V
in
CC
V
out
– 0.5 to V
+ 0.5
V
CC
I
± 20
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
± 35
± 75
out
V
should be constrained to the
out
range GND (V or V
)
V
CC
.
DC Supply Current, V
CC
and GND Pins
in out
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
750
500
450
level (e.g., either GND or V ).
CC
SSOP or TSSOP Package†
Unused outputs must be left open.
T
Storage Temperature
– 65 to + 150
C
C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC, SSOP or TSSOP Package)
(Ceramic DIP)
L
260
300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
Ceramic DIP: – 10 mW/ C from 100 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
SSOP or TSSOP Package: – 6.1 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
6.0
V , V
in out
V
CC
V
T
A
– 55 + 125
C
t , t
r f
Input Rise and Fall Time
(Figure 1)
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Test Conditions
Unit
85 C
125 C
V
IH
Minimum High–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
out
CC
|I
|
20 µA
out
V
Maximum Low–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
IL
out
CC
|I
|
20 µA
out
V
OH
Minimum High–Level Output
Voltage
V
= V or V
IH
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
in
IL
|I
|
20 µA
out
V
= V or V
in
IH
IL
|I
|I
|
|
6.0 mA
7.8 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
out
out
MOTOROLA
2
MC54/74HC373A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Test Conditions
= 0.1 V or V – 0.1 V
85 C
125 C
Unit
V
OL
Maximum Low–Level Output
Voltage
V
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
out
CC
|I
|
20 µA
out
V
= V or V
|
|
in
IH
6.0 mA
7.8 mA
IL
|I
|I
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
out
out
I
Maximum Input Leakage Current
V
= V or GND
CC
6.0
6.0
± 0.1
± 0.5
± 1.0
± 5.0
± 1.0
± 10
µA
µA
in
in
I
Maximum Three–State
Leakage Current
Output in High–Impedance State
OZ
V
= V or V
in
IL IH
V
out
= V or GND
CC
I
Maximum Quiescent Supply
Current (per Package)
V
= V
or GND
6.0
4.0
40
160
µA
CC
in
CC
|I | = 0 µA
out
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns)
L
r
f
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Unit
85 C
125 C
t
t
Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
PLH
PHL
t
t
Maximum Propagation Delay, Latch Enable to Q
(Figures 2 and 5)
2.0
4.5
6.0
140
28
24
175
35
30
210
42
36
ns
ns
ns
ns
PLH
PHL
t
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
PLZ
t
t
PHZ
t
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
PZL
PZH
t
t
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
TLH
THL
C
Maximum Input Capacitance
10
15
10
15
10
15
pF
pF
in
C
Maximum Three–State Output Capacitance
(Output in High–Impedance State)
out
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
= 5.0 V
CC
C
Power Dissipation Capacitance (Per Enabled Output)*
pF
36
PD
2
* Used to determine the no–load dynamic power consumption: P = C
D
Motorola High–Speed CMOS Data Book (DL129/D).
V
f + I
V
. For load considerations, see Chapter 2 of the
PD CC
CC CC
3
MOTOROLA
MC54/74HC373A
TIMING REQUIREMENTS (C = 50 pF, Input t = t = 6.0 ns)
L
r
f
Guaranteed Limit
85 C
– 55 to 25 C
125 C
Max
V
Volts
CC
Symbol
Parameter
Fig.
Unit
Min
Max
Min
Max
Min
t
Minimum Setup Time, Input D to Latch Enable
Minimum Hold Time, Latch Enable to Input D
Minimum Pulse Width, Latch Enable
4
2.0
4.5
6.0
25
5.0
5.0
30
6.0
6.0
40
8.0
7.0
ns
su
t
4
2
1
2.0
4.5
6.0
5.0
5.0
5.0
5.0
5 0
5.0
5.0
5.0
5.0
ns
ns
ns
h
t
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
w
t , t
r
Maximum Input Rise and Fall Times
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
f
SWITCHING WAVEFORMS
t
t
f
r
t
w
V
V
CC
CC
90%
50%
10%
LATCH ENABLE
50%
INPUT D
Q
GND
GND
t
t
PHL
PLH
t
t
PLH
PHL
90%
50%
10%
Q
50%
t
t
THL
TLH
Figure 1.
Figure 2.
V
CC
OUTPUT
ENABLE
50%
GND
VALID
t
t
PLZ
PZL
V
CC
HIGH
IMPEDANCE
INPUT D
50%
50%
GND
Q
Q
t
t
10%
90%
su
h
V
V
OL
t
t
PHZ
V
PZH
CC
LATCH ENABLE
50%
OH
GND
1.3 V
HIGH
IMPEDANCE
Figure 3.
Figure 4.
MOTOROLA
4
MC54/74HC373A
TEST CIRCUITS
TEST POINT
TEST POINT
1 k
CONNECT TO V
WHEN
CC
OUTPUT
Ω
OUTPUT
TESTING t
PLZ
AND t .
PZL
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CONNECT TO GND WHEN
TESTING t AND t
.
C *
PHZ PZH
L
C *
L
* Includes all probe and jig capacitance
* Includes all probe and jig capacitance
Figure 5.
Figure 6.
EXPANDED LOGIC DIAGRAM
D0
D1
D2
D3
D4
13
D5
14
D6
17
D7
18
3
4
7
8
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LE
LE
LE
LE
LE
LE
LE
LE
11
1
2
5
6
9
12
Q4
15
Q5
16
Q6
19
Q7
Q0
Q1
Q2
Q3
5
MOTOROLA
MC54/74HC373A
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
ISSUE E
NOTES:
1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE
POSITION AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
20
1
11
10
3. DIMENSIONS A AND B INCLUDE MENISCUS.
B
C
MILLIMETERS
INCHES
A
DIM
A
B
C
D
F
MIN
23.88
6.60
3.81
0.38
1.40
MAX
25.15
7.49
5.08
0.56
1.65
MIN
MAX
0.990
0.295
0.200
0.022
0.065
0.940
0.260
0.150
0.015
0.055
L
F
G
H
J
K
L
2.54 BSC
0.100 BSC
0.51
0.20
3.18
1.27
0.30
4.06
0.020
0.008
0.125
0.050
0.012
0.160
N
J
7.62 BSC
0.300 BSC
H
K
M
G
M
N
0
15
0
15
D
0.25
1.02
0.010
0.040
SEATING
PLANE
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ISSUE E
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
20
1
11
10
B
L
C
INCHES
MILLIMETERS
DIM
A
B
C
D
MIN
MAX
1.070
0.260
0.180
0.022
MIN
25.66
6.10
3.81
0.39
MAX
27.17
6.60
4.57
0.55
1.010
0.240
0.150
0.015
–T–
SEATING
PLANE
K
E
0.050 BSC
1.27 BSC
M
0.050
0.070
1.27
1.77
F
G
J
K
L
N
E
0.100 BSC
2.54 BSC
0.008
0.110
0.015
0.140
0.21
2.80
0.38
3.55
G
F
J 20 PL
0.300 BSC
7.62 BSC
D 20 PL
0.25 (0.010)
M
M
0.25 (0.010)
T B
M
N
0
15
0
15
0.020
0.040
0.51
1.01
M
M
T
A
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–04
ISSUE E
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
20
11
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
10X P
–B–
M
M
0.010 (0.25)
B
1
10
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
MILLIMETERS
INCHES
20X D
DIM
A
B
C
D
MIN
12.65
7.40
2.35
0.35
0.50
MAX
12.95
7.60
2.65
0.49
0.90
MIN
MAX
0.510
0.299
0.104
0.019
0.035
J
0.499
0.292
0.093
0.014
0.020
M
S
S
0.010 (0.25)
T
A
B
F
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
0.25
0.10
0
0.32
0.25
7
0.010
0.004
0
0.012
0.009
7
R X 45
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
C
SEATING
PLANE
–T–
M
18X G
K
MOTOROLA
6
MC54/74HC373A
OUTLINE DIMENSIONS
SD SUFFIX
PLASTIC SSOP PACKAGE
CASE 940C–03
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
ISSUE B
Y14.5M, 1982.
20X K REF
0.12 (0.005)
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
0.25 (0.010)
M
S
S
T
U
V
N
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION/INTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF K DIMENSION AT MAXIMUM MATERIAL
CONDITION. DAMBAR INTRUSION SHALL NOT
REDUCE DIMENSION K BY MORE THAN 0.07 (0.002)
AT LEAST MATERIAL CONDITION.
M
20
11
10
L/2
N
B
F
L
DETAIL E
K
PIN 1
IDENT
1
6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE
ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.
–U–
A
–V–
J
J1
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
H
J
J1
K
MIN
7.07
5.20
1.73
0.05
0.63
MAX
7.33
5.38
1.99
0.21
0.95
MIN
MAX
0.288
0.212
0.078
0.008
0.037
K1
M
S
0.20 (0.008)
T U
0.278
0.205
0.068
0.002
0.024
SECTION N–N
–W–
0.65 BSC
0.026 BSC
C
0.59
0.09
0.09
0.25
0.25
7.65
0
0.75
0.20
0.16
0.38
0.33
7.90
8
0.023
0.003
0.003
0.010
0.010
0.301
0
0.030
0.008
0.006
0.015
0.013
0.311
8
0.076 (0.003)
SEATING
PLANE
–T–
D
G
DETAIL E
K1
L
M
H
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
20X K REF
0.10 (0.004)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
T
U
V
S
0.15 (0.006)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
K
K1
20
11
2X L/2
J J1
B
L
–U–
PIN 1
IDENT
SECTION N–N
1
10
0.25 (0.010)
N
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
S
0.15 (0.006)
T U
M
A
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
6.40
4.30
–––
0.05
0.50
MAX
6.60
4.50
1.20
0.15
0.75
MIN
MAX
0.260
0.177
0.047
0.006
0.030
–V–
0.252
0.169
–––
0.002
0.020
N
F
F
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
DETAIL E
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
–W–
C
6.40 BSC
0.252 BSC
G
D
M
0
8
0
8
H
DETAIL E
0.100 (0.004)
–T– SEATING
PLANE
7
MOTOROLA
MC54/74HC373A
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CODELINE
MC54/74HC373A/D
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