MC74HC540 [MOTOROLA]
Octal 3-State Inverting Buffer/Line Driver/Line Receiver; 八路三态缓冲器/线路驱动器/线接收器
| 型号： | MC74HC540 |
| 厂家： | 
MOTOROLA |
| 描述： | Octal 3-State Inverting Buffer/Line Driver/Line Receiver |
| 文件： | 总5页 (文件大小：153K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
High–Performance Silicon–Gate CMOS
The MC74HC540A is identical in pinout to the LS540. The device inputs
are compatible with Standard CMOS outputs. External pullup resistors make
them compatible with LSTTL outputs.
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
20
1
The HC540A is an octal inverting buffer/line driver/line receiver designed
to be used with 3–state memory address drivers, clock drivers, and other
bus–oriented systems. This device features inputs and outputs on opposite
sides of the package and two ANDed active–low output enables.
The HC540A is similar in function to the HC541A, which has non–inverting
outputs.
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
20
1
•
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2 to 6V
ORDERING INFORMATION
MC74HCXXXAN
MC74HCXXXADW
Plastic
SOIC
Low Input Current: 1µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7A Requirements
Chip Complexity: 124 FETs or 31 Equivalent Gates
FUNCTION TABLE
Inputs
LOGIC DIAGRAM
Output Y
OE1 OE2
A
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
L
L
L
L
L
H
X
X
H
L
A1
A2
A3
A4
A5
A6
A7
A8
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
H
X
X
H
Z
Z
Z = High Impedance
X = Don’t Care
Data
Inputs
Inverting
Outputs
1
Output
Enables
OE1
OE2
PIN 20 = V
CC
PIN 10 = GND
19
Pinout: 20–Lead Packages (Top View)
V
OE2
19
Y1
18
Y2
17
Y3
16
Y4
15
Y5
14
Y6
13
Y7
12
Y8
11
CC
20
1
2
3
4
5
6
7
9
8
10
OE1
A1
A2
A3
A4
A5
A6
A7
A8
GND
10/95
REV 6
Motorola, Inc. 1995
MC74HC540A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V
+ 0.5
V
in
CC
V
out
– 0.5 to V
+ 0.5
V
CC
I
± 20
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
± 35
± 75
out
V
should be constrained to the
out
range GND (V or V
)
V
CC
.
DC Supply Current, V
CC
and GND Pins
in out
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air
Plastic DIP†
SOIC Package†
750
500
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
stg
Storage Temperature Range
– 65 to + 150
C
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP or SOIC Package
260
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature Range, All Package Types
6.0
V , V
in out
V
CC
V
T
A
– 55 + 125
C
t , t
r f
Input Rise/Fall Time
(Figure 1)
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
ns
DC CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
V
CC
V
Symbol
Parameter
Condition
–55 to 25°C ≤85°C ≤125°C
Unit
V
IH
Minimum High–Level Input Voltage
V
= 0.1V
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
out
|I | ≤ 20µA
out
V
Maximum Low–Level Input Voltage
V
= V
– 0.1V
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
V
V
IL
out CC
|I | ≤ 20µA
out
V
OH
Minimum High–Level Output
Voltage
V
= V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
in IL
|I | ≤ 20µA
out
V
in
= V
|I | ≤ 3.6mA
out
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
IL
|I | ≤ 6.0mA
out
|I | ≤ 7.8mA
out
V
OL
Maximum Low–Level Output
Voltage
V
= V
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
in
IH
|I | ≤ 20µA
out
V
= V
|I | ≤ 3.6mA
out
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
in
in
IH
|I | ≤ 6.0mA
out
|I | ≤ 7.8mA
out
I
in
Maximum Input Leakage Current
V
= V
or GND
3–2
6.0
±0.1
±1.0
±1.0
µA
CC
MOTOROLA
MC74HC540A
DC CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
–55 to 25°C ≤85°C
V
CC
V
Symbol
Parameter
Condition
≤125°C
±10.0
Unit
I
Maximum Three–State Leakage
Current
Output in High Impedance State
6.0
±0.5
±5.0
µA
OZ
V
= V or V
in
IL IH
V
out
= V or GND
CC
I
Maximum Quiescent Supply
Current (per Package)
V
= V
CC
= 0µA
or GND
6.0
4
40
160
µA
CC
in
I
out
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
AC CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)
L
r
f
Guaranteed Limit
V
CC
V
Symbol
Parameter
–55 to 25°C
≤85°C
≤125°C
Unit
t
t
,
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 3)
2.0
3.0
4.5
6.0
80
30
18
15
100
40
23
120
55
28
ns
PLH
PHL
20
25
t
t
,
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
2.0
3.0
4.5
6.0
110
45
25
140
60
31
165
75
38
ns
ns
ns
PLZ
PHZ
21
26
31
t
t
,
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
2.0
3.0
4.5
6.0
110
45
25
140
60
31
165
75
38
PZL
PZH
21
26
31
t
t
,
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
2.0
3.0
4.5
6.0
60
22
12
10
75
28
15
13
90
34
18
15
TLH
THL
C
Maximum Input Capacitance
10
15
10
15
10
15
pF
pF
in
C
Maximum Three–State Output Capacitance (Output in High
Impedance State)
out
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
= 5.0 V, V = 0 V
EE
CC
C
Power Dissipation Capacitance (Per Buffer)*
pF
35
PD
2
* Used to determine the no–load dynamic power consumption: P = C
D
Motorola High–Speed CMOS Data Book (DL129/D).
V
f + I
V
. For load considerations, see Chapter 2 of the
PD CC
CC CC
SWITCHING WAVEFORMS
V
CC
t
t
f
r
OE1 or OE2
50%
50%
V
CC
90%
50%
10%
GND
INPUT A
t
t
PZL PLZ
HIGH
IMPEDANCE
GND
OUTPUT Y
OUTPUT Y
t
t
PLH
PHL
50%
10%
90%
90%
50%
10%
V
OL
t
t
PZH PHZ
OUTPUT Y
V
OH
50%
t
TLH
t
THL
HIGH
IMPEDANCE
Figure 1.
Figure 2.
3–3
MOTOROLA
MC74HC540A
TEST CIRCUITS
TEST
TEST
POINT
POINT
CONNECT TO V
WHEN
CC
1k
Ω
OUTPUT
OUTPUT
TESTING t
CONNECT TO GND WHEN
TESTING t and t
AND t .
PLZ
PZL
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
.
PHZ PZH
C *
C *
L
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 3.
Figure 4.
PIN DESCRIPTIONS
INPUTS
puts are enabled and the device functions as an inverter.
When a hgih voltage is applied to either input, the outputs
assume the high impedance state.
A1, A2, A3, A4, A5, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8,
9) — Data input pins. Data on these pins appear in inverted
form on the corresponding Y outputs, when the outputs are
enabled.
OUTPUTS
Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14,
13, 12, 11) — Device outputs. Depending upon the state of
the output enable pins, these outputs are either inverting out-
puts or high–impedance outputs.
CONTROLS
OE1, OE2 (PINS 1, 19) — Output enables (active–low).
When a low voltage is applied to both of these pins, the out-
LOGIC DETAIL
To 7 Other
Inverters
V
CC
One of Eight
Inverters
INPUT A
OUTPUT Y
OE1
OE2
MOTOROLA
3–4
MC74HC540A
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ISSUE E
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
20
1
11
10
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
L
C
INCHES
MILLIMETERS
DIM
A
B
C
D
MIN
MAX
1.070
0.260
0.180
0.022
MIN
25.66
6.10
3.81
0.39
MAX
27.17
6.60
4.57
0.55
1.010
0.240
0.150
0.015
–T–
SEATING
PLANE
K
E
0.050 BSC
1.27 BSC
M
0.050
0.070
1.27
1.77
F
G
J
K
L
N
E
0.100 BSC
2.54 BSC
0.008
0.110
0.015
0.140
0.21
2.80
0.38
3.55
G
F
J 20 PL
0.300 BSC
7.62 BSC
D 20 PL
0.25 (0.010)
M
M
0.25 (0.010)
T B
M
N
0
15
0
15
0.020
0.040
0.51
1.01
M
M
T
A
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–04
ISSUE E
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
20
11
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
10X P
–B–
M
M
0.010 (0.25)
B
1
10
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
MILLIMETERS
INCHES
20X D
DIM
A
B
C
D
MIN
12.65
7.40
2.35
0.35
0.50
MAX
12.95
7.60
2.65
0.49
0.90
MIN
MAX
0.510
0.299
0.104
0.019
0.035
J
0.499
0.292
0.093
0.014
0.020
M
S
S
0.010 (0.25)
T
A
B
F
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
0.25
0.10
0
0.32
0.25
7
0.010
0.004
0
0.012
0.009
7
R X 45
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
C
SEATING
PLANE
–T–
M
18X G
K
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MC74HC540A/D
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