MC74HC595ADT [MOTOROLA]
8-Bit Serial-Input/Serial or Parallel-Output Shift Register with 3-State Outputs; 8位串行输入/串行或并行输出移位具有三态输出寄存器
| 型号： | MC74HC595ADT |
| 厂家： | 
MOTOROLA |
| 描述： | 8-Bit Serial-Input/Serial or Parallel-Output Shift Register with 3-State Outputs |
| 文件： | 总10页 (文件大小：227K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
High–Performance Silicon–Gate CMOS
16
1
The MC54/74HC595A is identical in pinout to the LS595. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
The HC595A consists of an 8–bit shift register and an 8–bit D–type latch
with three–state parallel outputs. The shift register accepts serial data and
provides a serial output. The shift register also provides parallel data to the
8–bit latch. The shift register and latch have independent clock inputs. This
device also has an asynchronous reset for the shift register.
The HC595A directly interfaces with the Motorola SPI serial data port on
CMOS MPUs and MCUs.
16
1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
16
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
1
DT SUFFIX
TSSOP PACKAGE
CASE 948F–01
16
1
ORDERING INFORMATION
•
•
Chip Complexity: 328 FETs or 82 Equivalent Gates
Improvements over HC595
— Improved Propagation Delays
— 50% Lower Quiescent Power
— Improved Input Noise and Latchup Immunity
MC54HCXXXAJ
Ceramic
Plastic
SOIC
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT
TSSOP
LOGIC DIAGRAM
PIN ASSIGNMENT
Q
1
2
16
15
V
CC
SERIAL
DATA
INPUT
B
C
D
14
15
1
A
Q
Q
A
B
Q
Q
Q
A
A
3
4
5
6
7
8
14
13
12
11
10
9
2
3
4
5
Q
C
Q
OUTPUT ENABLE
LATCH CLOCK
SHIFT CLOCK
RESET
E
PARALLEL
DATA
OUTPUTS
Q
Q
Q
Q
Q
D
E
F
Q
Q
F
SHIFT
REGISTER
LATCH
G
6
7
Q
H
G
H
GND
SQ
H
SHIFT
CLOCK
11
10
12
13
SERIAL
DATA
9
RESET
SQ
H
OUTPUT
LATCH
CLOCK
OUTPUT
ENABLE
V
= PIN 16
CC
GND = PIN 8
3/97
REV 7
Motorola, Inc. 1997
MC54/74HC595A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V
+ 0.5
V
in
CC
V
out
– 0.5 to V
+ 0.5
V
CC
I
± 20
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
± 35
± 75
out
V
should be constrained to the
out
DC Supply Current, V
and GND Pins
CC
range GND (V or V
)
V
.
CC
in out
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
750
500
450
level (e.g., either GND or V ).
CC
TSSOP Package†
Unused outputs must be left open.
T
Storage Temperature
– 65 to + 150
C
C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
(Ceramic DIP)
L
260
300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
Ceramic DIP: – 10 mW/ C from 100 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
TSSOP Package: – 6.1 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
6.0
V , V
in out
DC Input Voltage, Output Voltage
(Referenced to GND)
V
CC
V
T
A
Operating Temperature, All Package Types
– 55 + 125
C
t , t
r f
Input Rise and Fall Time
(Figure 1)
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
Symbol
Parameter
Test Conditions
25 C
Unit
85 C
125 C
V
IH
Minimum High–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
out
CC
|I
|
20 µA
out
V
Maximum Low–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
V
IL
out
CC
|I
|
20 µA
out
V
OH
Minimum High–Level Output
V
= V or V
IH
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
in
IL
20 µA
Voltage, Q – Q
|I
|
A
H
out
V
in
= V or V
IH
|I
|I
|I
|
|
|
2.4 mA
6.0 mA
7.8 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
IL out
out
out
MOTOROLA
2
MC54/74HC595A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Test Conditions
85 C
125 C
Unit
V
OL
Maximum Low–Level Output
V
= V or V
IL
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
in
IH
20 µA
Voltage, Q – Q
|I
|
A
H
out
V
in
= V or V
IH
|I
|I
|I
|
|
|
2.4 mA
6.0 mA
7.8 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
IL out
out
out
V
Minimum High–Level Output
Voltage, SQ
V
= V or V
IH
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
OH
in
IL
20 µA
II
out
I
H
V
in
= V or V
IH
|I
|
I
2.4 mA
4.0 mA
5.2 mA
3.0
4.5
6.0
2.98
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
IL out
II
out
II
I
out
V
Maximum Low–Level Output
Voltage, SQ
V
= V or V
IH
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
OL
in
IL
20 µA
II
out
I
H
V
V
= V or V
IH
|I
|
I
2.4 mA
4.0 mA
5.2 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
in
in
IL out
II
out
II
I
out
I
Maximum Input Leakage Current
Maximum Three–State Leakage
= V
or GND
CC
6.0
6.0
± 0.1
± 0.5
± 1.0
± 5.0
± 1.0
± 10
µA
µA
in
I
Output in High–Impedance State
OZ
Current, Q – Q
V
= V or V
A
H
in
IL
= V
IH
or GND
V
out
CC
or GND
I
Maximum Quiescent Supply
Current (per Package)
V
= V
CC
= 0 µA
6.0
4.0
40
160
µA
CC
in
l
out
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns)
L
r
f
Guaranteed Limit
– 55 to
V
CC
V
Symbol
Parameter
25 C
Unit
85 C
125 C
f
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 7)
2.0
3.0
4.5
6.0
6.0
15
30
35
4.8
10
24
28
4.0
8.0
20
MHz
max
24
t
t
,
Maximum Propagation Delay, Shift Clock to SQ
(Figures 1 and 7)
2.0
3.0
4.5
6.0
140
100
28
175
125
35
210
150
42
ns
ns
ns
ns
ns
PLH
H
PHL
24
30
36
t
Maximum Propagation Delay, Reset to SQ
(Figures 2 and 7)
2.0
3.0
4.5
6.0
145
100
29
180
125
36
220
150
44
PHL
H
25
31
38
t
t
,
Maximum Propagation Delay, Latch Clock to Q – Q
A
(Figures 3 and 7)
2.0
3.0
4.5
6.0
140
100
28
175
125
35
210
150
42
PLH
H
t
PHL
24
30
36
,
Maximum Propagation Delay, Output Enable to Q – Q
A
(Figures 4 and 8)
2.0
3.0
4.5
6.0
150
100
30
190
125
38
225
150
45
PLZ
H
H
t
PHZ
26
33
38
t
t
,
Maximum Propagation Delay, Output Enable to Q – Q
A
(Figures 4 and 8)
2.0
3.0
4.5
6.0
135
90
27
170
110
34
205
130
41
PZL
PZH
23
29
35
3
MOTOROLA
MC54/74HC595A
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns)
L
r
f
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
85 C
125 C
Unit
t
t
,
Maximum Output Transition Time, Q – Q
A
(Figures 3 and 7)
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
31
18
15
ns
TLH
H
THL
t
t
,
Maximum Output Transition Time, SQ
(Figures 1 and 7)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
ns
TLH
H
THL
19
C
Maximum Input Capacitance
—
—
10
15
10
15
10
15
pF
pF
in
C
Maximum Three–State Output Capacitance (Output in
High–Impedance State), Q – Q
out
A
H
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
= 5.0 V
CC
300
C
Power Dissipation Capacitance (Per Package)*
pF
PD
2
* Used to determine the no–load dynamic power consumption: P = C
D
Motorola High–Speed CMOS Data Book (DL129/D).
V
f + I
V
. For load considerations, see Chapter 2 of the
PD CC
CC CC
TIMING REQUIREMENTS (Input t = t = 6.0 ns)
r
f
Guaranteed Limit
25 C to
V
CC
V
– 55 C
Symbol
Parameter
Unit
85 C
125 C
t
su
Minimum Setup Time, Serial Data Input A to Shift Clock
(Figure 5)
2.0
3.0
4.5
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
ns
t
Minimum Setup Time, Shift Clock to Latch Clock
(Figure 6)
2.0
3.0
4.5
6.0
75
60
15
13
95
70
19
16
110
80
22
ns
ns
ns
ns
ns
ns
ns
su
19
t
Minimum Hold Time, Shift Clock to Serial Data Input A
(Figure 5)
2.0
3.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
h
t
Minimum Recovery Time, Reset Inactive to Shift Clock
(Figure 2)
2.0
3.0
4.5
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
rec
t
t
t
Minimum Pulse Width, Reset
(Figure 2)
2.0
3.0
4.5
6.0
60
45
12
10
75
60
15
13
90
70
18
15
w
w
w
Minimum Pulse Width, Shift Clock
(Figure 1)
2.0
3.0
4.5
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
Minimum Pulse Width, Latch Clock
(Figure 6)
2.0
3.0
4.5
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
t , t
r f
Maximum Input Rise and Fall Times
(Figure 1)
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
MOTOROLA
4
MC54/74HC595A
FUNCTION TABLE
Inputs
Resulting Function
Serial
Input
A
Shift
Register
Contents
Latch
Register
Contents
Serial
Output
Parallel
Outputs
Shift
Clock
Latch
Clock
Output
Enable
Operation
SQ
Q
– Q
Reset
H
A
H
Reset shift register
L
X
D
X
L, H, ↓
L, H, ↓
L
L
L
U
U
L
U
Shift data into shift
register
H
↑
D → SR ;
SR → SR
SR → SR
U
A
N+1
G
H
N
Shift register remains
unchanged
H
H
X
X
X
X
L, H, ↓
L, H, ↓
X
L, H, ↓
↑
L
L
L
U
U
*
U
U
U
*
U
Transfer shift register
contents to latch register
SR → LR
SR
N
N
N
Latch register remains
unchanged
L, H, ↓
U
U
Enable parallel outputs
X
X
X
X
X
X
X
X
L
*
*
**
**
*
*
Enabled
Z
Force outputs into high
impedance state
H
SR = shift register contents
LR = latch register contents
D = data (L, H) logic level
U = remains unchanged
↑ = Low–to–High
↓ = High–to–Low
* = depends on Reset and Shift Clock inputs
** = depends on Latch Clock input
PIN DESCRIPTIONS
INPUTS
Latch Clock (Pin 12)
Storage Latch Clock Input. A low–to–high transition on this
input latches the shift register data.
A (Pin 14)
Serial Data Input. The data on this pin is shifted into the
8–bit serial shift register.
Output Enable (Pin 13)
Active–low Output Enable. A low on this input allows the
data from the latches to be presented at the outputs. A high
CONTROL INPUTS
Shift Clock (Pin 11)
on this input forces the outputs (Q –Q ) into the high–
impedance state. The serial output is not affected by this
control unit.
A
H
Shift Register Clock Input. A low– to–high transition on this
input causes the data at the Serial Input pin to be shifted into
the 8–bit shift register.
OUTPUTS
Q
– Q (Pins 15, 1, 2, 3, 4, 5, 6, 7)
H
A
Noninverted, 3–state, latch outputs.
Reset (Pin 10)
SQ (Pin 9)
H
Active–low, Asynchronous, Shift Register Reset Input. A
low on this pin resets the shift register portion of this device
only. The 8–bit latch is not affected.
Noninverted, Serial Data Output. This is the output of the
eighth stage of the 8–bit shift register. This output does not
have three–state capability.
5
MOTOROLA
MC54/74HC595A
SWITCHING WAVEFORMS
t
t
t
w
r
f
V
CC
V
CC
SHIFT
CLOCK
90%
50%
50%
RESET
GND
GND
10%
t
t
PHL
w
1/f
max
50%
OUTPUT
t
t
PHL
PLH
SQ
H
t
rec
90%
50%
OUTPUT
V
CC
SHIFT
CLOCK
SQ
H
10%
50%
GND
t
t
THL
TLH
Figure 1.
Figure 2.
V
CC
OUTPUT
ENABLE
V
50%
CC
LATCH
CLOCK
50%
GND
GND
t
t
PLZ
PZL
HIGH
IMPEDANCE
50%
t
t
PHL
PLH
OUTPUT Q
OUTPUT Q
10%
90%
V
V
OL
t
t
PHZ
90%
50%
PZH
Q
–Q
H
A
OH
OUTPUTS
10%
50%
HIGH
IMPEDANCE
t
t
THL
TLH
Figure 3.
Figure 4.
V
CC
SHIFT
CLOCK
50%
VALID
V
CC
GND
SERIAL
INPUT A
50%
t
su
GND
V
CC
LATCH
CLOCK
t
t
h
su
50%
V
CC
LATCH
CLOCK
GND
50%
t
w
GND
Figure 5.
Figure 6.
TEST CIRCUITS
TEST POINT
TEST POINT
CONNECT TO V
WHEN
.
PZL
CC
AND t
1 k
Ω
OUTPUT
OUTPUT
TESTING t
PLZ
CONNECT TO GND WHEN
TESTING t AND t
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
.
PZH
PHZ
C *
C *
L
L
* Includes all probe and jig capacitance
* Includes all probe and jig capacitance
Figure 7.
Figure 8.
MOTOROLA
6
MC54/74HC595A
EXPANDED LOGIC DIAGRAM
OUTPUT
ENABLE
13
12
14
LATCH
CLOCK
SERIAL
DATA
15
1
D
Q
Q
Q
Q
Q
Q
Q
Q
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
A
B
INPUT A
SR
SR
SR
SR
SR
LR
LR
LR
LR
LR
A
B
C
D
E
A
B
C
D
E
R
D
R
D
2
3
4
5
6
7
Q
Q
Q
Q
Q
Q
C
D
E
F
R
D
PARALLEL
DATA
OUTPUTS
R
D
R
D
SR
LR
F
G
H
F
R
D
G
H
SR
SR
LR
G
R
D
SHIFT
CLOCK
11
10
LR
H
R
SERIAL
DATA
OUTPUT SQ
9
RESET
H
7
MOTOROLA
MC54/74HC595A
TIMING DIAGRAM
SHIFT
CLOCK
SERIAL DATA
INPUT A
RESET
LATCH
CLOCK
OUTPUT
ENABLE
Q
A
B
C
D
Q
Q
Q
Q
E
Q
F
Q
G
Q
H
SERIAL DATA
OUTPUT SQ
H
NOTE:
implies that the output is in a high–impedance
state.
MOTOROLA
8
MC54/74HC595A
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
ISSUE V
–A
–
NOTES:
16
1
9
8
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
–B
–
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY.
L
C
INCHES
MILLIMETERS
DIM
A
B
C
D
E
MIN
MAX
0.785
0.295
0.200
0.020
MIN
19.05
6.10
—
0.39
1.27 BSC
MAX
19.93
7.49
5.08
0.50
0.750
0.240
—
0.015
0.050 BSC
–T
SEAT
–
ING
N
K
PLANE
F
G
J
K
L
M
N
0.055
0.100 BSC
0.008
0.125
0.065
1.40
2.54 BSC
0.21
3.18
1.65
E
M
0.015
0.170
0.38
4.31
J 16 PL
F
G
0.300 BSC
15
0.040
7.62 BSC
15
1.01
0.51
M
S
0.25 (0.010)
T
B
D 16 PL
°
°
0
°
0
°
M
S
0.25 (0.010)
T
A
0.020
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A
–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
16
9
B
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
1
8
INCHES
MILLIMETERS
DIM
A
B
C
D
F
G
H
J
K
L
MIN
MAX
0.770
0.270
0.175
0.021
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
F
C
L
0.740
0.250
0.145
0.015
0.040
S
0.070
1.77
SEATING
PLANE
–T
0.100 BSC
0.050 BSC
0.015
0.130
0.305
2.54 BSC
1.27 BSC
0.38
3.30
7.74
–
M
K
0.008
0.110
0.295
0.21
2.80
7.50
H
J
G
D 16 PL
0.25 (0.010)
M
S
0°
10°
0°
10°
M
M
T
A
0.020
0.040
0.51
1.01
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A
–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
9
–B
–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
M
0.25 (0.010)
B
1
8
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
J
MIN
9.80
3.80
1.35
0.35
0.40
MAX
10.00
4.00
1.75
0.49
MIN
MAX
0.393
0.157
0.068
0.019
0.049
0.386
0.150
0.054
0.014
0.016
0.050 BSC
0.008
0.004
F
K
R X 45°
C
1.25
1.27 BSC
–T
0.19
0.10
0.25
0.25
0.009
0.009
J
SEAT
–
ING
M
K
PLANE
D 16 PL
M
P
R
0
5.80
0.25
°
7
6.20
0.50
°
0
°
7°
0.244
0.019
0.229
0.010
M
S
S
0.25 (0.010)
T
B
A
9
MOTOROLA
MC54/74HC595A
OUTLINE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F–01
ISSUE O
16X KREF
0.10 (0.004)
M
S
S
T
U
V
NOTES:
S
0.15 (0.006) T
U
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
K
K1
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
16
9
2X L/2
J1
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
B
–U–
SECTION N–N
L
J
PIN 1
IDENT.
8
1
N
0.25 (0.010)
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.
S
0.15 (0.006) T
U
A
M
MILLIMETERS
INCHES
–V–
DIM
A
B
C
D
MIN
4.90
4.30
–––
0.05
0.50
MAX
5.10
4.50
1.20
0.15
0.75
MIN
MAX
0.200
0.177
0.047
0.006
0.030
N
0.193
0.169
–––
0.002
0.020
F
F
DETAIL E
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28
0.20
0.16
0.30
0.25
0.007
0.004
0.004
0.007
0.007
0.011
0.008
0.006
0.012
0.010
–W–
C
6.40 BSC
0.252 BSC
0.10 (0.004)
M
0
8
0
8
DETAIL E
H
SEATING
PLANE
–T–
D
G
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
Opportunity/Affirmative Action Employer.
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Mfax is a trademark of Motorola, Inc.
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;
P.O. Box 5405, Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315
Mfax : RMFAX0@email.sps.mot.com – TOUCHTONE 602–244–6609
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– US & Canada ONLY 1–800–774–1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
INTERNET: http://www.mot.com/SPS/
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