MC74HCXXXADW [MOTOROLA]
OCTAL 3-STATE INVERTING TRANSPARENT LATCH HIGH-PERFORMANCE SILICON-GATE CMOS; 八路三态反演透明锁存器高性能硅栅CMOS
| 型号： | MC74HCXXXADW |
| 厂家： | 
MOTOROLA |
| 描述： | OCTAL 3-STATE INVERTING TRANSPARENT LATCH HIGH-PERFORMANCE SILICON-GATE CMOS |
| 文件： | 总7页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
High–Performance Silicon–Gate CMOS
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
20
20
The MC54/74HC533A is identical in pinout to the LS533. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. The Data appears at the
outputs in inverted form. When Latch Enable goes low, data meeting the
setup and hold time becomes latched.
The Output Enable input does not affect the state of the latches, but when
Output Enable is high, all device outputs are forced to the high-impedance
state. Thus, data may be latched even when the outputs are not enabled.
The HC533A is identical in function to the HC563 but has the data inputs
on the opposite side of the package from the outputs to facilitate PC board
layout.
1
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
1
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
20
1
ORDERING INFORMATION
This device is similar in function to the HC373A, which has noninverting
outputs.
MC54HCXXXAJ
Ceramic
Plastic
SOIC
MC74HCXXXAN
MC74HCXXXADW
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
PIN ASSIGNMENT
OUTPUT
ENABLE
1
20
V
CC
•
Chip Complexity: 256 FETs or 64 Equivalent Gates
Q0
2
3
19
18
Q7
D7
D0
D1
4
17
D6
Q1
Q2
5
16
15
14
13
12
11
Q6
Q5
D5
D4
Q4
LOGIC DIAGRAM
6
D2
7
2
3
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D0
D1
D2
D3
D4
D5
D6
D7
D3
8
5
6
4
Q3
9
7
LATCH
ENABLE
GND
10
8
9
DATA
INPUTS
INVERTING
OUTPUTS
13
14
17
18
12
15
16
19
FUNCTION TABLE
Inputs
Output
Output Latch
Enable Enable
D
Q
L
L
L
H
H
L
H
L
X
X
L
H
No Change
Z
11
1
LATCH ENABLE
PIN 20 = V
CC
PIN 10 = GND
H
X
OUTPUT ENABLE
X = Don’t Care
Z = High Impedance
3/97
REV 3
Motorola, Inc. 1997
MC54/74HC533A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V
+ 0.5
V
in
CC
V
out
– 0.5 to V
+ 0.5
V
CC
I
± 20
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
± 35
± 75
out
V
should be constrained to the
out
range GND (V or V
)
V
.
DC Supply Current, V
and GND Pins
CC
in out
CC
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
750
500
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
stg
Storage Temperature
– 65 to + 150
C
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)
260
300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
Ceramic DIP: – 10 mW/ C from 100 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
6.0
V , V
in out
V
CC
V
T
A
– 55 + 125
C
t , t
r f
Input Rise and Fall Time
(Figure 1)
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Test Conditions
= V – 0.1 V
85 C
125 C
Unit
V
IH
Minimum High–Level Input
Voltage
V
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
out
CC
20 µA
|I
|
out
V
Maximum Low–Level Input
Voltage
V
= 0.1 V
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
V
IL
out
|I
|
20 µA
out
V
OH
Minimum High–Level Output
Voltage
V
= V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
in
IH
20 µA
|I
|
out
V
in
= V
|I
out
|I
out
|I
out
|
|
|
2.4 mA
6.0 mA
7.8 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
IH
V
OL
Maximum Low–Level Output
Voltage
V
= V
|
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
in
IL
20 µA
|I
out
V
in
= V
|I
out
|I
out
|I
out
|
|
|
2.4 mA
6.0 mA
7.8 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
IL
MOTOROLA
2
MC54/74HC533A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25 C
± 0.1
± 0.5
Symbol
Parameter
Test Conditions
= V or GND
CC
85 C
125 C
± 1.0
Unit
µA
I
in
Maximum Input Leakage Current
V
6.0
6.0
± 1.0
in
Output in High–Impedance State
= V or V
I
Maximum Three–State Leakage
Current
± 5.0
± 10
µA
OZ
V
V
in
IL
= V
IH
or GND
out
CC
or GND
I
Maximum Quiescent Supply
Current (per Package)
V
= V
6.0
4.0
40
160
µA
CC
in
CC
= 0 µA
I
out
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns)
L
r
f
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Fig.
Unit
85 C
125 C
t
t
Maximum Propagation Delay, Input D to Q
Maximum Propagation Delay, Latch Enable to Q
Maximum Propagation Delay, Output Enable to Q
Maximum Propagation Delay, Output Enable to Q
Maximum Output Transition Time, Any Output
Maximum Input Capacitance
1, 5
2.0
3.0
4.5
6.0
125
80
25
155
110
31
190
130
38
ns
PLH
PHL
21
26
32
t
t
2, 5
3, 6
3, 6
1, 5
2.0
3.0
4.5
6.0
125
80
25
155
110
31
190
130
38
ns
ns
ns
ns
PLH
PHL
21
26
32
t
2.0
3.0
4.5
6.0
150
100
30
190
125
38
225
150
45
PLZ
t
PHZ
26
33
38
t
t
2.0
3.0
4.5
6.0
150
100
30
190
125
38
225
150
45
PZL
PZH
26
33
38
t
t
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
TLH
THL
19
C
10
15
10
15
10
15
pF
pF
in
C
Maximum Tri–State Output Capacitance (Output in Hi–Impedance State)
out
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
= 5.0 V
CC
C
Power Dissipation Capacitance (Per Enabled Output)*
pF
36
PD
2
* Used to determine the no–load dynamic power consumption: P = C
D
Motorola High–Speed CMOS Data Book (DL129/D).
V
f + I
V
. For load considerations, see Chapter 2 of the
PD CC
CC CC
3
MOTOROLA
MC54/74HC533A
TIMING REQUIREMENTS (C = 50 pF, Input t = t = 6.0 ns)
L
r
f
Guaranteed Limit
85 C
– 55 to 25 C
125 C
Max
V
Volts
CC
Symbol
Parameter
Fig.
Unit
Min
Max
Min
Max
Min
t
Minimum Setup Time, Input D to Latch Enable
Minimum Hold Time, Latch Enable to Input D
Minimum Pulse Width, Latch Enable
4
2.0
3.0
4.5
6.0
25
20
5.0
5.0
30
25
6.0
6.0
40
30
8.0
7.0
ns
su
t
4
2
1
2.0
3.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
ns
ns
ns
h
t
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
32
18
15
w
t , t
r f
Maximum Input Rise and Fall Times
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
SWITCHING WAVEFORMS
t
t
V
r
f
CC
INPUT D
V
CC
LATCH
ENABLE
90%
50%
10%
50%
GND
t
w
GND
t
t
PHL
PLH
t
t
PLH
PHL
90%
Q
50%
50%
10%
Q
t
t
TLH
THL
Figure 1.
Figure 2.
OUTPUT
ENABLE
V
CC
50%
VALID
V
GND
CC
t
t
PLZ
PZL
INPUT D
HIGH
IMPEDANCE
50%
Q
GND
t
t
h
50%
su
V
CC
10%
90%
V
V
OL
LATCH
ENABLE
50%
t
t
PHZ
PZH
OH
GND
1.3 V
HIGH
IMPEDANCE
Q
Figure 3.
Figure 4.
MOTOROLA
4
MC54/74HC533A
TEST CIRCUITS
TEST POINT
TEST POINT
1 k
OUTPUT
CONNECT TO V
WHEN
CC
AND t
Ω
OUTPUT
TESTING t
PLZ
CONNECT TO GND WHEN
TESTING t AND t
PZL
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
PHZ
PZH
C *
C *
L
L
* Includes all probe and jig capacitance
* Includes all probe and jig capacitance
Figure 5.
Figure 6.
EXPANDED LOGIC DIAGRAM
D0
3
D1
4
D2
7
D3
8
D4
13
D5
14
D6
17
D7
18
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LE
LE
LE
LE
LE
LE
LE
LE
11
1
LATCH
ENABLE
OUTPUT
ENABLE
2
5
6
9
12
Q4
15
Q5
16
Q6
19
Q0
Q1
Q2
Q3
Q7
5
MOTOROLA
MC54/74HC533A
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
ISSUE E
NOTES:
1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE
POSITION AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
20
1
11
10
3. DIMENSIONS A AND B INCLUDE MENISCUS.
B
C
MILLIMETERS
INCHES
A
DIM
A
B
C
D
F
MIN
23.88
6.60
3.81
0.38
1.40
MAX
25.15
7.49
5.08
0.56
1.65
MIN
MAX
0.990
0.295
0.200
0.022
0.065
0.940
0.260
0.150
0.015
0.055
L
F
G
H
J
K
L
2.54 BSC
0.100 BSC
0.51
0.20
3.18
1.27
0.30
4.06
0.020
0.008
0.125
0.050
0.012
0.160
N
J
7.62 BSC
0.300 BSC
H
K
M
G
M
N
0
15
0
15
D
0.25
1.02
0.010
0.040
SEATING
PLANE
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ISSUE E
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
20
1
11
10
B
L
C
INCHES
MILLIMETERS
DIM
A
B
C
D
MIN
MAX
1.070
0.260
0.180
0.022
MIN
25.66
6.10
3.81
0.39
MAX
27.17
6.60
4.57
0.55
1.010
0.240
0.150
0.015
–T–
SEATING
PLANE
K
E
0.050 BSC
1.27 BSC
M
0.050
0.070
1.27
1.77
F
G
J
K
L
N
E
0.100 BSC
2.54 BSC
0.008
0.110
0.015
0.140
0.21
2.80
0.38
3.55
G
F
J 20 PL
0.300 BSC
7.62 BSC
D 20 PL
0.25 (0.010)
M
M
0.25 (0.010)
T B
M
N
0
15
0
15
0.020
0.040
0.51
1.01
M
M
T
A
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–04
ISSUE E
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
20
11
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
10X P
–B–
M
M
0.010 (0.25)
B
1
10
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
MILLIMETERS
INCHES
20X D
DIM
A
B
C
D
MIN
12.65
7.40
2.35
0.35
0.50
MAX
12.95
7.60
2.65
0.49
0.90
MIN
MAX
0.510
0.299
0.104
0.019
0.035
J
0.499
0.292
0.093
0.014
0.020
M
S
S
0.010 (0.25)
T
A
B
F
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
0.25
0.10
0
0.32
0.25
7
0.010
0.004
0
0.012
0.009
7
R X 45
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
C
SEATING
PLANE
–T–
M
18X G
K
MOTOROLA
6
MC54/74HC533A
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
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