MC9S12DT512 [MOTOROLA]
16-Bit Microcontroller; 16位微控制器
| 型号： | MC9S12DT512 |
| 厂家： | 
MOTOROLA |
| 描述： | 16-Bit Microcontroller |
| 文件： | 总14页 (文件大小：377K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC9S12D-FamilyPP
Rev 6.1, 23-Oct-02
Freescale Semiconductor, Inc.
MOTOROLA
SEMICONDUCTOR
TECHNICAL DATA
MC9S12D-Family
Product Brief
16-Bit Microcontroller
Designed for automotive multiplexing applications, members of the MC9S12D-Family of 16 bit Flash-
based microcontrollers are fully pin compatible and enable users to choose between different memory
and peripheral options for scalable designs. All MC9S12D-Family members are composed of standard
on-chip peripherals including a 16-bit central processing unit (CPU12), up to 512K bytes of Flash
EEPROM, 14K bytes of RAM, 4K bytes of EEPROM, two asynchronous serial communications
interfaces (SCI), three serial peripheral interfaces (SPI), IIC-bus, an enhanced capture timer (ECT), two
8-channel 10-bit analog-to-digital converters (ADC), an eight-channel pulse-width modulator (PWM),
J1850 interface and up to five CAN 2.0 A, B software compatible modules (MSCAN12). System
resource mapping, clock generation, interrupt control and bus interfacing are managed by the system
integration module (SIM). The MC9S12D-Family has full 16-bit data paths throughout, however, the
external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for
lower cost systems. The inclusion of a PLL circuit allows power consumption and performance to be
adjusted to suit operational requirements. In addition to the I/O ports available in each module, up to 22
I/O ports are available with interrupt capability allowing Wake-Up from STOP or WAIT mode.
Features
NOTE
Not all features listed here are available in all configurations.
Additional information about D and B family inter-operability is given in:
EB386 “HCS12 D-Family Compatibility Considerations” and
EB388 “Using the HCS12 D-Family as a development platform for the HCS12 B family”
• 16-bit CPU12
— Upward compatible with M68HC11 instruction set
— Interrupt stacking and programmer’s model identical to M68HC11
— HCS12 Instruction queue
— Enhanced indexed addressing
• Multiplexed bus
— Single chip or expanded
— 16 address/16 data wide or 16 address/8 data narrow modes
— External address space 1MByte for Data and Program space (112 pin package only)
• Wake-up interrupt inputs depending on the package option
— 8-bit port H
— 2-bit port J1:0
— 2-bit port J7:6 shared with IIC, CAN4 and CAN0 module
— 8-bit port P shared with PWM or SPI1,2
• Memory options
— 32K, 64K, 128K, 256K, 512K Byte Flash EEPROM
— 1K, 2K, 4K Byte EEPROM
— 2K, 4K, 8K, 12K, 14K Byte RAM
This document contains information on a new product. Specifications and information herein are subject to change without notice.
For More Information On This Product,
Go to: www.freescale.com
© MOTOROLA 2002
Freescale Semiconductor, Inc.
• Analog-to-Digital Converters
— One or two 8-channel modules with 10-bit resolution depending on the package option
— External conversion trigger capability
• Up to five 1M bit per second, CAN 2.0 A, B software compatible modules
— Five receive and three transmit buffers
— Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
— Four separate interrupt channels for Receive, Transmit, Error and Wake-up
— Low-pass filter wake-up function in STOP mode
— Loop-back for self test operation
• Enhanced Capture Timer (ECT)
— 16-bit main counter with 7-bit prescaler
— 8 programmable input capture or output compare channels; 4 of the 8 input captures with buffer
— Input capture filters and buffers, three successive captures on four channels, or two captures on four
channels with a capture/compare selectable on the remaining four
— Four 8-bit or two 16-bit pulse accumulators
— 16-bit modulus down-counter with 4-bit prescaler
— Four user-selectable delay counters for signal filtering
• 8 PWM channels with programmable period and duty cycle (7 channels on 80 Pin Packages)
— 8-bit, 8-channel or 16-bit, 4-channel
— Separate control for each pulse width and duty cycle
— Center- or left-aligned outputs
— Programmable clock select logic with a wide range of frequencies
• Serial interfaces
— Two asynchronous serial communications interfaces (SCI)
— Up to three synchronous serial peripheral interfaces (SPI)
— IIC
• SAE J1850 Compatible Module (BDLC)
— 10.4 kbps Variable Pulse Width format
— Byte level receive and transmit
— 4x receive mode supported
• SIM (System Integration Module)
— CRG (windowed COP watchdog, real time interrupt, clock monitor, clock generation and reset)
— MEBI (multiplexed external bus interface)
— INT (interrupt control)
• Clock generation
— Phase-locked loop clock frequency multiplier
— Limp home mode in absence of external clock
— Clock Monitor
— Low power 0.5 to 16 MHz crystal oscillator reference clock
• Operating frequency for ambient temperatures TA -40°C <= TA <= 125°C
— 50MHz equivalent to 25MHz Bus Speed for single chip
40MHz equivalent to 20MHz Bus Speed in expanded bus modes.
• Internal 5V to 2.5V Regulator
• 112-Pin LQFP or 80-Pin QFP package
— I/O lines with 5V input and drive capability
— 5V A/D converter inputs and 5V I/O
— 2.5V logic supply
• Development support
— Single-wire background debug™ mode (BDM)
— On-chip hardware breakpoints
MOTOROLA
2
MC9S12D-Family
PRODUCT PROPOSAL, Rev 6.1, 23-Oct-02
Go to: www.freescale.com
For More Information On This Product,
Freescale Semiconductor, Inc.
Table 1 List of MC9S12D-Family members
Flash RAM EEPROM Package Device CAN J1850 SCI
SPI
3
IIC
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
A/D
2/16
2/16
2/16
2/16
2/16
2/16
1/8
PWM
8
I/O
91
91
91
91
91
91
59
59
91
91
91
59
59
91
91
59
59
59
DP512
112LQFP DT512
DJ512
5
3
2
3
2
2
2
2
3
2
2
2
2
1
1
1
1
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
512K
14K
4K
3
8
3
8
DT256
3
8
112LQFP DJ256
DG256
3
8
256K
12K
4K
3
8
DJ256
80QFP
3
7
DG256
3
1/8
7
DT128
112LQFP DJ128
DG128
2
2/16
2/16
2/16
1/8
8
2
8
128K
8K
2K
2
8
DJ128
80QFP
2
7
DG128
2
1/8
7
DJ64
112LQFP
D64
1
2/16
2/16
1/8
8
1
8
64K
32K
4K
2K
1K
1K
DJ64
80QFP
1
7
D64
1
1/8
7
80QFP D32
1
1/8
7
• Pin out explanations:
— A/D is the number of modules/total number of A/D channels.
— I/O is the sum of ports capable to act as digital input or output.
112 Pin Packages:
Port A = 8, B = 8, E = 6 + 2 input only, H = 8, J = 4, K = 7, M = 8, P = 8, S = 8, T = 8, PAD = 16 input
only.
22 inputs provide Interrupt capability (H =8, P= 8, J = 4, IRQ, XIRQ)
80 Pin Packages:
Port A = 8, B = 8, E = 6 + 2 input only, J = 2, M = 6, P = 7, S = 4, T = 8, PAD = 8 input only.
11 inputs provide Interrupt capability (P= 7, J = 2, IRQ, XIRQ)
— CAN0 pins are shared between J1850 pins.
— CAN0 can be routed under software control from PM1:0 to pins PM3:2 or PM5:4 or PJ7:6.
— CAN4 pins are shared between IIC pins.
— CAN4 can be routed under software control from PJ7:6 to pins PM5:4 or PM7:6.
— Versions with 4 CAN modules will have CAN0, CAN1, CAN2 and CAN4.
— Versions with 3 CANs modules will have CAN0, CAN1 and CAN4.
— Versions with 2 CAN modules will have CAN0 and CAN4.
— Versions with one CAN module will have CAN0.
— Versions with 2 SPI modules will have SPI0 and SPI1.
— Versions with 1 SPI will have SPI0.
— SPI0 can be routed to either Ports PS7:4 or PM5:2.
— SPI2 pins are shared with PWM7:4; In 112 pin versions SPI2 can be routed under software control to
PH7:4. In 80 pin packages SS-signal of SPI2 is not bonded out!
NOTE
CAN and SPI routing features are not available on the 1st PC9S12DP256 mask set 0K36N!
MC9S12D-Family
PRODUCT PROPOSAL, Rev 6.1, 23-Oct-02
Go to: www.freescale.com
MOTOROLA
3
For More Information On This Product,
Freescale Semiconductor, Inc.
VRH
VRH
VRL
VDDA
VSSA
VRH
VRL
VDDA
VSSA
32K - 512K Byte Flash EEPROM
2K - 14K Byte RAM
ATD0
ATD1
VRL
VDDA
VSSA
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
PAD00
PAD01
PAD02
PAD03
PAD04
PAD05
PAD06
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
PAD08
PAD09
PAD10
PAD11
PAD12
PAD13
PAD14
1K - 4K Byte EEPROM
VDDR
VSSR
VREGEN
VDD1,2
VSS1,2
Voltage Regulator
PAD07
PAD15
PIX0
PK0 XADDR14
PK1 XADDR15
Single-wire Background
BKGD
PIX1
PIX2
PIX3
PIX4
PIX5
ECS
CPU12
Debug Module
PPAGE
PK2
XADDR16
XFC
VDDPLL
VSSPLL
EXTAL
XTAL
PK3 XADDR17
PK4 XADDR18
PK5 XADDR19
PK7 ECS/ROMONE
Clock and
Reset
Generation
Module
PLL
Periodic Interrupt
COP Watchdog
Clock Monitor
Breakpoints
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
PT0
PT1
PT2
PT3
PT4
PT5
RESET
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
XIRQ
IRQ
R/W
LSTRB
ECLK
MODA
MODB
Enhanced Capture
Timer
System
Integration
Module
(SIM)
PT6
PT7
NOACC/XCLKS
RXD
TXD
RXD
TXD
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
SCI0
TEST
SCI1
SPI0
MISO
MOSI
SCK
SS
Multiplexed Address/Data Bus
DDRA
PTA
DDRB
PTB
BDLC
RXB
TXB
(J1850)
PM0
PM1
PM2
PM3
PM4
PM5
PM6
PM7
RXCAN
TXCAN
RXCAN
TXCAN
RXCAN
TXCAN
RXCAN
TXCAN
RXCAN
TXCAN
CAN0
CAN1
CAN2
CAN3
CAN4
Multiplexed
Wide Bus
KWJ0
KWJ1
KWJ6
KWJ7
PJ0
PJ1
PJ6
PJ7
Multiplexed
Narrow Bus
SDA
SCL
IIC
Internal Logic 2.5V
VDD1,2
VSS1,2
I/O Driver 5V
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
KWP0
KWP1
KWP2
KWP3
KWP4
KWP5
KWP6
KWP7
PP0
PP1
PP2
PP3
PP4
PP5
VDDX
VSSX
PWM
A/D Converter 5V &
Voltage Regulator Reference
PLL 2.5V
VDDPLL
VSSPLL
VDDA
VSSA
PP6
PP7
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
SS
KWH0
KWH1
KWH2
KWH3
KWH4
KWH5
KWH6
KWH7
PH0
PH1
PH2
PH3
PH4
PH5
Voltage Regulator 5V & I/O
SPI1
SPI2
VDDR
VSSR
PH6
PH7
Not all functionality shown in this
Block diagram is available in all Versions!
MOTOROLA
4
MC9S12D-Family
PRODUCT PROPOSAL, Rev 6.1, 23-Oct-02
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Figure 1 Pin assignments 112 LQFP for MC9S12D-Family
84
SS1/PWM3/KWP3/PP3
SCK1/PWM2/KWP2/PP2
MOSI1/PWM1/KWP1/PP1
MISO1/PWM0/KWP0/PP0
XADDR17/PK3
XADDR16/PK2
XADDR15/PK1
XADDR14/PK0
IOC0/PT0
1
2
3
4
5
6
7
8
VRH
VDDA
PAD15/AN15/ETRIG1
PAD07/AN07/ETRIG0
PAD14/AN14
PAD06/AN06
PAD13/AN13
PAD05/AN05
PAD12/AN12
PAD04/AN04
PAD11/AN11
PAD03/AN03
PAD10/AN10
PAD02/AN02
PAD09/AN09
PAD01/AN01
PAD08/AN08
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
9
IOC1/PT1
IOC2/PT2
IOC3/PT3
VDD1
VSS1
IOC4/PT4
IOC5/PT5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
MC9S12D-Family
112LQFP
IOC6/PT6
IOC7/PT7
PAD00/AN00
VSS2
VDD2
XADDR19/PK5
XADDR18/PK4
KWJ1/PJ1
PA7/ADDR15/DATA15
PA6/ADDR14/DATA14
PA5/ADDR13/DATA13
PA4/ADDR12/DATA12
PA3/ADDR11/DATA11
PA2/ADDR10/DATA10
PA1/ADDR9/DATA9
PA0/ADDR8/DATA8
KWJ0/PJ0
MODC/TAGHI/BKGD
ADDR0/DATA0/PB0
ADDR1/DATA1/PB1
ADDR2/DATA2/PB2
ADDR3/DATA3/PB3
ADDR4/DATA4/PB4
Signals shown in Bold are not available on the 80 Pin Package
MC9S12D-Family
PRODUCT PROPOSAL, Rev 6.1, 23-Oct-02
MOTOROLA
For More Information On This Product,
5
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Figure 2 Pin Assignments in 80 QFP for MC9S12D-Family
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SS1/PWM3/KWP3/PP3
SCK1/PWM2/KWP2/PP2
MOSI1/PWM1/KWP1/PP1
MISO1/PWM0/KWP0/PP0
IOC0/PT0
1
2
3
4
5
6
7
8
VRH
VDDA
PAD07/AN07/ETRIG0
PAD06/AN06
PAD05/AN05
PAD04/AN04
PAD03/AN03
PAD02/AN02
PAD01/AN01
IOC1/PT1
IOC2/PT2
IOC3/PT3
VDD1
VSS1
IOC4/PT4
IOC5/PT5
9
10
11
12
13
14
15
16
17
18
19
20
PAD00/AN00
VSS2
VDD2
MC9S12D-Family
80 QFP
IOC6/PT6
IOC7/PT7
PA7/ADDR15/DATA15
PA6/ADDR14/DATA14
PA5/ADDR13/DATA13
PA4/ADDR12/DATA12
PA3/ADDR11/DATA11
PA2/ADDR10/DATA10
PA1/ADDR9/DATA9
PA0/ADDR8/DATA8
MODC/TAGHI/BKGD
ADDR0/DATA0/PB0
ADDR1/DATA1/PB1
ADDR2/DATA2/PB2
ADDR3/DATA3/PB3
ADDR4/DATA4/PB4
MOTOROLA
6
MC9S12D-Family
PRODUCT PROPOSAL, Rev 6.1, 23-Oct-02
Go to: www.freescale.com
For More Information On This Product,
Freescale Semiconductor, Inc.
Figure 3 MC9S12Dx512 User Configurable Memory Map
$0000
$03FF
1K Register Space
Mappable to any 2K Boundary
$0000
$0400
$0800
$0800
14K Bytes RAM
Alignable to top ($0800 - $3FFF)
or bottom ($0000 - $37FF)
$3FFF
$4000
Mappable to any 16K Boundary
0.5K, 1K, 2K or 4K Protected Sector
12K Fixed Flash EEPROM
$4000
EXT
$6FFF
$7000
4K Flash overlapped by EEPROM in this configuration
4K Bytes EEPROM
$7000
$8000
$7FFF
$8000
Mappable to any 4K Boundary
16K Page Window
thirty two * 16K Flash EEPROM Pages
$BFFF
$C000
EXT
$C000
16K Fixed Flash EEPROM
2K, 4K, 8K or 16K Protected Boot Sector
$FFFF
$FF00
BDM
(If Active)
$FF00
$FFFF
VECTORS
VECTORS
VECTORS
$FFFF
NORMAL
SINGLE CHIP
EXPANDED
SPECIAL
SINGLE CHIP
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0800 - $3FFF: 14K RAM
$0000 - $0FFF: 4K EEPROM (1k $0400 - $07FF visible, $0000 - $03FF and $0800 - $0FFF are not visible)
Various possibilities to make more of the EEPROM fully visible are available, one of them is shown above
MC9S12D-Family
PRODUCT PROPOSAL, Rev 6.1, 23-Oct-02
Go to: www.freescale.com
MOTOROLA
7
For More Information On This Product,
Freescale Semiconductor, Inc.
Figure 4 MC9S12Dx256 User Configurable Memory Map
$0000
1K Register Space
$03FF
$0000
Mappable to any 2K Boundary
$0000
$0400
4K Bytes EEPROM
Initially overlapped by register space
$1000
$0FFF
$1000
Mappable to any 4K Boundary
12K Bytes RAM
Alignable to top ($1000 - $3FFF)
or bottom ($0000 - $2FFF)
$3FFF
$4000
Mappable to any 16K Boundary
$4000
0.5K, 1K, 2K or 4K Protected Sector
16K Fixed Flash EEPROM
$7FFF
$8000
$8000
16K Page Window
sixteen * 16K Flash EEPROM Pages
EXT
$BFFF
$C000
$C000
16K Fixed Flash EEPROM
2K, 4K, 8K or 16K Protected Boot Sector
$FFFF
$FF00
BDM
(If Active)
$FF00
$FFFF
VECTORS
VECTORS
VECTORS
$FFFF
NORMAL
SINGLE CHIP
EXPANDED
SPECIAL
SINGLE CHIP
MOTOROLA
8
MC9S12D-Family
PRODUCT PROPOSAL, Rev 6.1, 23-Oct-02
Go to: www.freescale.com
For More Information On This Product,
Freescale Semiconductor, Inc.
Figure 5 MC9S12Dx128 User Configurable Memory Map
$0000
1K Register Space
$03FF
$0800
Mappable to any 2K Boundary
2K Bytes EEPROM
$0000
$0400
$0800
$1000
$2000
$0FFF
$2000
$3FFF
$4000
Mappable to any 2K Boundary
8K Bytes RAM
Mappable to any 8K Boundary
$4000
$8000
$C000
0.5K, 1K, 2K or 4K Protected Sector
16K Fixed Flash EEPROM
$7FFF
$8000
16K Page Window
eight * 16K Flash EEPROM Pages
EXT
$BFFF
$C000
16K Fixed Flash EEPROM
2K, 4K, 8K or 16K Protected Boot Sector
$FFFF
$FF00
BDM
(If Active)
$FF00
$FFFF
VECTORS
VECTORS
VECTORS
$FFFF
NORMAL
SINGLE CHIP
EXPANDED
SPECIAL
SINGLE CHIP
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0000 - $1FFF: 8K RAM
$0000 - $07FF: 1K EEPROM (not visible)
MC9S12D-Family
PRODUCT PROPOSAL, Rev 6.1, 23-Oct-02
Go to: www.freescale.com
MOTOROLA
9
For More Information On This Product,
Freescale Semiconductor, Inc.
Figure 6 MC9S12Dx64 User Configurable Memory Map
$0000
1K Register Space
$03FF
$0800
Mappable to any 2K Boundary
$0000
$0400
$0800
1K Bytes EEPROM
repeated twice in the 2K space
$0FFF
$3000
Mappable to any 2K Boundary
4K Bytes RAM
$1000
$3000
$3FFF
Mappable to any 4K Boundary
$4000
$8000
$C000
$4000
0.5K, 1K, 2K or 4K Protected Sector
16K Fixed Flash EEPROM
$7FFF
$8000
16K Page Window
four * 16K Flash EEPROM Pages
EXT
$BFFF
$C000
16K Fixed Flash EEPROM
2K, 4K, 8K or 16K Protected Boot Sector
$FFFF
$FF00
BDM
(If Active)
$FF00
$FFFF
VECTORS
VECTORS
VECTORS
$FFFF
NORMAL
SINGLE CHIP
EXPANDED
SPECIAL
SINGLE CHIP
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0000 - $0FFF: 4K RAM
$0000 - $07FF: 1K EEPROM (not visible)
MOTOROLA
10
MC9S12D-Family
PRODUCT PROPOSAL, Rev 6.1, 23-Oct-02
Go to: www.freescale.com
For More Information On This Product,
Freescale Semiconductor, Inc.
Figure 7 MC9S12Dx32 User Configurable Memory Map
$0000
1K Register Space
$03FF
$0800
Mappable to any 2K Boundary
$0000
$0400
$0800
1K Bytes EEPROM
Repeated twice in the 2K space
$0FFF
Mappable to any 2K Boundary
$1000
$3800
$3800
$3FFF
2K Bytes RAM
$4000
Mappable to any 2K Boundary
$8000
$8000
0.5K, 1K, 2K or 4K Protected Sector
two * 16K Flash EEPROM Pages
EXT
16K Fixed Flash EEPROM
$BFFF
$C000
$C000
16K Fixed Flash EEPROM
2K, 4K, 8K or 16K Protected Boot Sector
$FFFF
$FF00
BDM
(If Active)
$FF00
$FFFF
VECTORS
VECTORS
VECTORS
$FFFF
NORMAL
SINGLE CHIP
EXPANDED
SPECIAL
SINGLE CHIP
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0800 - $0FFF: 2K RAM
$0000 - $07FF: 1K EEPROM (not visible)
MC9S12D-Family
PRODUCT PROPOSAL, Rev 6.1, 23-Oct-02
Go to: www.freescale.com
MOTOROLA
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For More Information On This Product,
Freescale Semiconductor, Inc.
4X
0.20 T L-M N
4X 28 TIPS
0.20 T L-M N
J1
4X
P
PIN 1
IDENT
112
85
J1
C
1
84
L
VIEW Y
X
108X
G
X=L, M OR N
VIEW Y
V
B
L
M
AA
J
B1
V1
28
57
BASE
METAL
F
D
29
56
M
0.13
T L-M N
N
SECTION J1-J1
ROTATED 90 COUNTERCLOCKWISE
A1
S1
°
A
NOTES:
S
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DATUMS L, M AND N TO BE DETERMINED AT
SEATING PLANE, DATUM T.
4. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE, DATUM T.
C2
VIEW AB
0.10
5. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B INCLUDE MOLD MISMATCH.
6. DIMENSION D DOES NOT INCLUDE DAMBAR
θ2
θ3
C
0.050
112X
T
SEATING
PLANE
MILLIMETERS
T
DIM MIN
MAX
20.000 BSC
10.000 BSC
A
A1
B
B1
C
20.000 BSC
10.000 BSC
---
1.600
0.150
1.450
0.370
0.750
0.330
θ
C1 0.050
C2 1.350
D
E
F
0.270
0.450
0.270
R R2
G
J
0.650 BSC
0.090
0.170
K
P
0.500 REF
0.325 BSC
0.25
R R1
R1 0.100
R2 0.100
0.200
0.200
GAGE PLANE
S
S1
V
V1
Y
22.000 BSC
11.000 BSC
22.000 BSC
11.000 BSC
0.250 REF
1.000 REF
(K)
E
C1
θ1
Z
(Y)
(Z)
AA 0.090
0.160
8 °
0 °
3 °
11 °
11 °
θ
θ 1
θ 2
θ 3
7 °
VIEW AB
13 °
13 °
Figure 8 112-pin LQFP Mechanical Dimensions (case no. 987)
MOTOROLA
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MC9S12D-Family
PRODUCT PROPOSAL, Rev 6.1, 23-Oct-02
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L
60
41
40
61
B
B
P
-A-
-B-
L
V
B
-A-,-B-,-D-
DETAIL A
DETAIL A
21
80
F
1
20
-D-
A
S
M
S
S
S
0.20
H
A-B
A-B
D
D
0.05 A-B
J
N
M
S
0.20
C
D
M
E
DETAIL C
M
S
S
0.20
C
A-B
D
SECTION B-B
C
DATUM
PLANE
VIEW ROTATED 90
-H-
°
-C-
SEATING
PLANE
0.10
H
M
G
NOTES:
MILLIMETERS
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
DIM MIN
MAX
13.90 14.10
13.90 14.10
A
B
C
D
E
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE
LEAD WHERE THE LEAD EXITS THE PLASTIC
BODY AT THE BOTTOM OF THE PARTING LINE.
4. DATUMS -A-, -B- AND -D- TO BE
DETERMINED AT DATUM PLANE -H-.
5. DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE -C-.
2.15
0.22
2.00
0.22
2.45
0.38
2.40
0.33
U
T
F
G
H
J
K
L
0.65 BSC
DATUM
PLANE
---
0.13
0.65
0.25
0.23
0.95
-H-
R
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
12.35 REF
M
N
P
5
0.13
0.325 BSC
10
0.17
°
°
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B DO INCLUDE MOLD MISMATCH
AND ARE DETERMINED AT DATUM PLANE -H-.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION. DAMBAR CANNOT
BE LOCATED ON THE LOWER RADIUS OR
THE FOOT.
K
Q
R
S
0
0.13
16.95 17.45
7
0.30
Q
°
°
W
X
T
0.13
---
---
DETAIL C
U
V
W
X
0
°
16.95 17.45
0.35 0.45
1.6 REF
Figure 9 80-pin QFP Mechanical Dimensions (case no. 841B)
MC9S12D-Family
PRODUCT PROPOSAL, Rev 6.1, 23-Oct-02
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