MCM69Q618TQ6R [MOTOROLA]
64K x 18 Bit Synchronous Separate I/O SRAM; 64K ×18位同步独立的I / O SRAM
| 型号： | MCM69Q618TQ6R |
| 厂家： | 
MOTOROLA |
| 描述： | 64K x 18 Bit Synchronous Separate I/O SRAM |
| 文件： | 总12页 (文件大小：182K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order this document
by MCM69Q618/D
SEMICONDUCTOR TECHNICAL DATA
MCM69Q618
Advance Information
64K x 18 Bit Synchronous
Separate I/O Fast SRAM
The Motorola MCM69Q618 is a 1 Megabit static random access memory, organized
as 64K words of 18 bits. It features separate data input and data output buffers and
incorporates input and output registers on board with high speed SRAM.
The MCM69Q618 allows the user to perform transparent write and data pass
through. Two data bus ports are provided – a data input (D) and a data output (Q) port.
The synchronous design allows for precise cycle control with the use of an external
single clock (K). Address port, data input (D0 – D17), data output (Q0 – Q17), write en-
able (W), chip enables (E1, E2), and pass–through enable (PT) are registered on the
rising edge of clock (K).
TQ PACKAGE
100 PIN TQFP
CASE 983A–01
Any given cycle operates on only one address. However, for any cycle, reads and
writes can be intermixed. Thus, one can perform a read, a write, or a combination read/
write during any one cycle. For a combination read/write, the contents of the array are
read before the new data is written.
By using the pass–through function, the output port Q can be made to reflect either
the contents of the array or the data presented to the input port D. For read/write or a
read cycle with G low, the Q port will output the contents of the array. However, if PT
is asserted, the Q port will instead output the data presented at the D input port.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Single 3.3 V ± 5% Power Supply
Fast Access Times: 6/8/10 ns Max
Sustained Throughput of 1.49 Gigabits/Second
Single Clock Operation
Address, Data Input, E1, E2, PT, W, and Data Output Registers on Chip
83 MHz Maximum Clock Cycle Time
Self Timed Write
Separate Data Input and Data Output Pins
Pass–Through Feature
Asynchronous Output Enable (G)
LVTTL Compatible I/O
No Dead Cycles Required for Reads after Writes or for Writes after Reads
100 Pin TQFP Package
Simultaneous Reads and Writes
Suggested Applications
— ATM
— Ethernet Switches — Routers
— Cell/Frame Buffers — SNA Switches
— Shared Memory
Product Family Configurations
Part
Number
Dual
Address
Single
Address
Dual
I/O
Separate
I/O
MCM69D536
Note 1
Note 1
Note 2
Note 2
MCM69D618
MCM69Q536
MCM69Q618
MCM67Q709
MCM67Q909
NOTES:
1. Tie AX and AY address ports together for the part to function as a single address part.
2. Tie GX high for DQX to be inputs and tie WY high and GY low for DQY to be outputs.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 5
11/24/97
Motorola, Inc. 1997
BLOCK DIAGRAM
K
16
ADDRESS
REGISTER
64K x 18 ARRAY
A0 – A15
SENSE
AMP
WRITE
DRIVER
WRITE
REGISTER
W
PT
PT
PASS–THROUGH
REGISTER
DATA OUTPUT
REGISTER
DATA INPUT
REGISTER
ENABLE
REGISTER 2
ENABLE
REGISTER 1
E1
E2
G
D0 – D17
Q0 – Q17
MCM69Q618
MOTOROLA FAST SRAM
2
PIN ASSIGNMENT
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
V
1
DD
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
NC
V
2
SS
D9
Q9
V
V
SS
DD
3
4
D8
D10
Q10
5
6
7
Q8
D7
Q7
V
DD
V
D11
SS
8
9
10
V
V
SS
DD
Q11
D12
Q12
D6
Q6
D5
Q5
11
12
13
14
15
V
DD
V
Q13
D13
Q14
D14
SS
V
V
Q4
D4
Q3
D3
SS
DD
16
17
65
64
63
18
19
20
V
DD
62
61
V
SS
V
V
SS
DD
Q15
21
22
23
24
25
26
60
59
58
D15
Q16
D16
Q2
D2
Q1
57
56
V
DD
D1
V
V
Q17
SS
55
54
53
52
51
SS
DD
V
27
28
29
D17
NC
A5
Q0
D0
NC
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MCM69Q618
3
MOTOROLA FAST SRAM
PIN DESCRIPTIONS
Pin Locations
Symbol
Type
Description
30, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50,
81, 83, 85, 98, 100
A0 – A15
Input
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
3, 5, 9, 11, 16, 18, 22, 24, 28, 52, 56, 58,
62, 64, 69, 71, 75, 77
D0 – D17
Input
Synchronous Data Input.
90
91
92
E1
E2
G
Input
Input
Input
Synchronous Chip Enable: Active low for depth expansion.
Synchronous Chip Enable: Active high for depth expansion.
Asynchronous Output Enable Input:
Low — enables output buffers (Qx pins).
High — Qx pins are high impedance.
96
86
K
Input
Input
Clock: This signal registers the address, data in, and all control signals
except G.
PT
Pass–through enable: Synchronous.
4, 6, 10, 12, 15, 17, 21, 23, 27, 53, 57,
59, 63, 65, 68, 70, 74, 76
Q0 – Q17
Output Synchronous Data Output.
88
W
Input
Synchronous Write.
1, 7, 13, 19, 25, 41, 54, 60, 66, 72, 78, 95
2, 8, 14, 20, 26, 55, 61, 67, 73, 79, 94
V
Supply + 3.3 V Power Supply.
Supply Ground.
DD
V
SS
29, 31, 33, 35, 37, 39, 43, 45, 47, 49, 51,
80, 82, 84, 87, 89, 93, 97, 99
NC
—
No Connection: There is no connection to the chip.
TRUTH TABLE
Input at t Clock
Result from t
n + 1
Clock
Notes
n
Operation
Write and Pass–Through
Write/Read
E1
L
E2
H
H
H
H
L
W
PT
L
Data Input D
D written to A
D written to A
D data
Data Output Q
D data appears
Q out from A
D data appears
Q out from A
Q is high–Z
L
L
1
2
3
4
5
6
L
H
L
Pass–Through
Read
L
H
H
X
X
L
H
X
Don’t Care
Don’t Care
Don’t Care
Deselected
X
H
Deselected
X
X
Q is high–Z
NOTES:
1. Write D to array and output D at Q.
2. Output contents of array to Q then write D to array.
3. Output D at Q. Do not write.
4. Output contents of array to Q. Do not write.
5. No operation.
6. No operation.
t
t
n + 1
n
K
VALID
ADDRESS & CONTROL
PIPELINED READ ACCESS
DATA INPUT D
VALID
PASS–THROUGH
DATA OUTPUT Q
VALID
MCM69Q618
4
MOTOROLA FAST SRAM
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating Symbol
Power Supply Voltage
Voltage Relative to V
This is a synchronous device. All synchro-
nousinputsmustmeetspecifiedsetupandhold
times with stable logic levels for ALL rising
edges of clock (K) while the device is selected.
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to these high–impedance
circuits.
Value
Unit
V
V
– 0.5 to + 4.6
DD
for Any Pin
V , V
in out
– 0.5 to V
DD
+ 0.5
V
SS
Except V
DD
Output Current
I
± 20
mA
W
out
Power Dissipation
P
D
TBD
Temperature Under Bias
Operating Temperature
T
– 10 to + 85
0 to + 70
°C
°C
°C
bias
T
A
Storage Temperature — Plastic
T
stg
– 55 to + 125
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (See Note 1)
Rating
Symbol
TQFP
Unit
Notes
Junction to Ambient (@ 200 lfm)
Single Layer Board
Four Layer Board
R
40
25
°C/W
2
θJA
Junction to Board (Bottom)
Junction to Case (Top)
NOTES:
R
R
17
9
°C/W
°C/W
3
4
θJB
θJC
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, board population, and board thermal resistance.
2. Per SEMI G38–87.
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1).
MCM69Q618
5
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 3.3 V ± 5%, T = 0 to + 70°C, Unless Otherwise Noted)
DD
A
RECOMMENDED OPERATING CONDITIONS AND SUPPLY CURRENTS
Parameter
Supply Voltage (Operating Voltage Range)
Input High Voltage
Symbol
Min
3.135
2.0
Max
Unit
V
V
DD
3.465
V
IH
V
+ 0.5**
V
DD
Input Low Voltage
V
– 0.5*
—
0.8
V
IL
Input Leakage Current (All Inputs, V = 0 to V
)
I
± 1.0
± 1.0
µA
µA
mA
in
DD
lkg(I)
Output Leakage Current (E = V , V
IH out
= 0 to V
)
I
—
DD
lkg(O)
AC Supply Current (I
= 0 mA) (V
= max, f = f
)
MCM69Q618–6 ns
MCM69Q618–8 ns
MCM69Q618–10 ns
I
DDA
—
—
—
TBD
TBD
TBD
out
DD
max
CMOS Standby Supply Current (Deselected, Clock (K)
Cycle Time ≥ t , All Inputs Toggling at CMOS Levels
MCM69Q618–6 ns
MCM69Q618–8 ns
MCM69Q618–10 ns
I
—
—
—
TBD
TBD
TBD
mA
SB1
KHKH
+ 0.2 V or ≥ V
V
≤ V
– 0.2 V)
in
SS
DD
= + 8.0 mA)
Output Low Voltage (I
V
—
0.4
V
V
OL
OL
Output High Voltage (I
= – 4.0 mA)
V
2.4
V
DD
OH
OH
*V ≥ –1.5 V for t ≤ t
/2.
/2.
KHKH
IL
KHKH
**V ≤ V
IH
+ 1.0 V for t ≤ t
DD
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T = 0 to 70°C, Periodically Sampled Rather Than 100% Tested)
A
Parameter
Symbol
Max
Unit
pF
Address and Data Input Capacitance
Control Pin Input Capacitance
Output Capacitance
C
C
6
6
8
in
in
pF
C
pF
out
MCM69Q618
6
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 3.3 V ± 5%, T = 0 to + 70°C, Unless Otherwise Noted)
DD
A
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . . . Figure 1 Unless Otherwise Noted
READ/WRITE CYCLE TIMING
MCM69Q618–6
MCM69Q618–8
MCM69Q618–10
Parameter
Symbol
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Min
12
—
4
Max
—
6
Min
15
—
6
Max
—
8
Min
20
—
8
Max
—
10
—
—
—
7
Cycle Time
t
1
2
KHKH
Clock Access Time
t
KHQV
Clock Low Pulse Width
t
—
—
—
5
—
—
—
6
KLKH
KHKL
KHQX
Clock High Pulse Width
t
4
6
8
Clock High to Data Output Invalid
Clock High to Data Output High–Z
Output Enable to Output Valid
Output Enable to Output Active
Output Disable to Output High–Z
t
0
0
0
t
t
t
—
—
0
—
—
0
—
—
0
3
KHQZ
GLQV
GLQX
GHQZ
6
8
10
—
7
—
—
5
3
3
4
t
—
2.5
—
3
6
—
3
Setup Times:
Hold Times:
NOTES:
A0 – A15
W
PT
E1, E2
D0 – D17
t
—
—
—
AVKH
t
WVKH
t
PTVKH
t
t
EVKH
DVKH
A0 – A15
W
PT
E1, E2
D0 – D17
t
0.5
—
2
—
2
—
ns
4
KHAX
t
KHWX
t
KHPTX
t
KHEX
KHDX
t
1. All read and write cycles are referenced from K.
2. Valid data from Clock High will be the data stored at the address or the last valid read cycle.
3. This parameter is sampled and not 100% tested.
4. This is a synchronous device. All synchronous inputs must meet the specified setup and hold times with stable logic levels for ALL rising
edges of clock (K) while the device is selected.
R
= 50 Ω
L
OUTPUT
Z
= 50 Ω
0
V
= 1.5 V
L
Figure 1. AC Test Load
MCM69Q618
7
MOTOROLA FAST SRAM
READ CYCLE TIMING
t
t
t
KHKL
KHKH
KLKH
K
t
AVKH
A
B
C
D
E
F
G
H
A0 – A15
t
KHEX
t
EVKH
E
G
Q
t
GLQV
t
KHQV
t
t
GHQZ
KHQZ
t
KHQX
t
GLQX
Q(E)
Q(A)
Q(B)
Q(C)
Q(F)
E low = E1 low, E2 high. E high = E1 high or E2 low.
MCM69Q618
MOTOROLA FAST SRAM
8
COMBINATION READ/WRITE CYCLE TIMING
t
t
t
KHKL
KHKH
KLKH
K
t
KHAX
A0 – A15
A
B
C
D
E
F
G
H
E
G
Q
Q[B]
Q[A]
Q[C]
Q(D)
Q(E)
D(F)
t
WVKH
t
KHWX
W
t
t
KHAX
PTVKH
PT
D
t
DVKH
t
KHDX
D(B)
D(D)
D(E)
D(F)
D(G)
NOTES:
1. E low = E1 low and E2 high. E high = E1 high or E2 low.
2. Q[A] = Previous contents of array at address A.
3. Q(A) = Data presented at input port.
MCM69Q618
9
MOTOROLA FAST SRAM
E CONTROLLED WRITE
K
A
B
C
D
E
F
G
H
A0 – A15
W
E
D
D(A)
D(B)
D(C)
D(D)
D(E)
D(F)
D(G)
D(H)
NOTES:
1. E low = E1 low, E2 high. E high = E1 high or E2 low.
2. Only D(B) and D(D) are written to the array.
ORDERING INFORMATION
(Order by Full Part Number)
MCM 69Q618 XX XX
X
Motorola Memory Prefix
Part Number
Shipping Method (R = Tape and Reel, Blank = Rails)
Speed (6 = 6 ns, 8 = 8 ns, 10 = 10 ns)
Package (TQ = TQFP)
Full Part Numbers — MCM69Q618TQ6
MCM69Q618TQ8 MCM69Q618TQ10
MCM69Q618TQ6R MCM69Q618TQ8R MCM69Q618TQ10R
MCM69Q618
10
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
TQFP PACKAGE
100 PIN
CASE 983A–01
4X
80
e
0.20 (0.008)
H
A–B
D
2X 30 TIPS
e/2
0.20 (0.008)
C
A–B
D
–D–
51
50
81
B
B
–X–
E/2
X=A, B, OR D
–A–
–B–
VIEW Y
E1
E
BASE
METAL
PLATING
E1/2
b1
31
100
1
30
c1
c
D1/2
D/2
b
D1
D
M
S
S
0.13 (0.005)
C
A–B
D
2X 20 TIPS
0.20 (0.008)
SECTION B–B
C
A–B
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
A
2
3
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –A–, –B– AND –D– TO BE DETERMINED
AT DATUM PLANE –H–.
0.10 (0.004)
C
–H–
–C–
SEATING
PLANE
5. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE –C–.
VIEW AB
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS D1 AND B1 DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –H–.
7. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE b DIMENSION TO EXCEED 0.45
(0.018).
S
0.05 (0.002)
S
1
0.25 (0.010)
GAGE PLANE
R2
A2
MILLIMETERS
INCHES
MIN
DIM
A
MIN
–––
MAX
1.60
0.15
1.45
0.38
0.33
0.20
0.16
MAX
0.063
0.006
0.057
0.015
0.013
0.008
0.006
–––
0.002
0.053
0.009
0.009
0.004
0.004
A1
A2
b
b1
c
0.05
1.35
0.22
0.22
0.09
0.09
L2
L
R1
A1
L1
c1
D
D1
E
E1
e
VIEW AB
22.00 BSC
0.866 BSC
20.00 BSC
16.00 BSC
14.00 BSC
0.65 BSC
0.787 BSC
0.630 BSC
0.551 BSC
0.026 BSC
L
0.45
1.00 REF
0.50 REF
0.75
0.018
0.039 REF
0.020 REF
0.030
L1
L2
S
R1
R2
0.20
–––
–––
0.20
7
0.008
–––
–––
0.008
7
0.08
0.08
0
0.003
0.003
0
1
2
3
0
11
11
–––
13
13
0
11
11
–––
13
13
MCM69Q618
11
MOTOROLA FAST SRAM
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
Opportunity/Affirmative Action Employer.
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Mfax is a trademark of Motorola, Inc.
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;
JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141,
P.O. Box 5405, Denver, Colorado, 80217. 1-303-675-2140 or 1-800-441-2447 4-32-1 Nishi-Gotanda, Shagawa-ku, Tokyo, Japan. 03-5487-8488
Mfax : RMFAX0@email.sps.mot.com – TOUCHTONE 1-602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
Motorola Fax Back System
– US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
– http://sps.motorola.com/mfax/
HOME PAGE: http://motorola.com/sps/
CUSTOMER FOCUS CENTER: 1-800-521-6274
MCM69Q618/D
◊
相关型号：
MCM69R536ZP4.4
Late-Write SRAM, 32KX36, 2.2ns, BICMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
MOTOROLA
MCM69R536ZP5
32KX36 LATE-WRITE SRAM, 2.5ns, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
NXP
MCM69R536ZP5R
Late-Write SRAM, 32KX36, 2.5ns, BICMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
MOTOROLA
MCM69R536ZP6R
32KX36 LATE-WRITE SRAM, 3ns, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
MOTOROLA
MCM69R536ZP7R
Late-Write SRAM, 32KX36, 3.5ns, BICMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
MOTOROLA
MCM69R537ZP7
Cache SRAM, 32KX36, 3.5ns, BICMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
MOTOROLA
©2020 ICPDF网 联系我们和版权申明