MMBT5089LT1 [MOTOROLA]
Low Noise Transistors; 低噪声晶体管
| 型号： | MMBT5089LT1 |
| 厂家： | 
MOTOROLA |
| 描述： | Low Noise Transistors |
| 文件： | 总6页 (文件大小：301K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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by MMBT5088LT1/D
SEMICONDUCTOR TECHNICAL DATA
COLLECTOR
3
NPN Silicon
*Motorola Preferred Device
1
BASE
2
3
EMITTER
MAXIMUM RATINGS
1
Rating
Collector–Emitter Voltage
Collector–Base Voltage
Symbol
5088LT1 5089LT1
Unit
Vdc
2
V
CEO
V
CBO
V
EBO
30
35
25
30
CASE 318–08, STYLE 6
SOT–23 (TO–236AB)
Vdc
Emitter–Base Voltage
4.5
50
Vdc
Collector Current — Continuous
THERMAL CHARACTERISTICS
Characteristic
I
C
mAdc
Symbol
Max
Unit
(1)
Total Device Dissipation FR–5 Board
P
225
mW
D
T
= 25°C
A
Derate above 25°C
1.8
556
300
mW/°C
°C/W
mW
Thermal Resistance, Junction to Ambient
Total Device Dissipation
R
JA
D
P
(2)
Alumina Substrate,
T
A
= 25°C
Derate above 25°C
2.4
mW/°C
°C/W
°C
Thermal Resistance, Junction to Ambient
Junction and Storage Temperature
DEVICE MARKING
R
417
JA
T , T
J stg
–55 to +150
MMBT5088LT1 = 1Q; MMBT5089LT1 = 1R
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
A
Characteristic
Symbol
Min
Max
Unit
OFF CHARACTERISTICS
Collector–Emitter Breakdown Voltage
V
Vdc
(BR)CEO
(I = 1.0 mAdc, I = 0)
MMBT5088
MMBT5089
30
25
—
—
C
B
Collector–Base Breakdown Voltage
(I = 100 Adc, I = 0)
V
Vdc
nAdc
nAdc
(BR)CBO
MMBT5088
MMBT5089
35
30
—
—
C
E
Collector Cutoff Current
I
CBO
(V
CB
(V
CB
= 20 Vdc, I = 0)
MMBT5088
MMBT5089
—
—
50
50
E
= 15 Vdc, I = 0)
E
Emitter Cutoff Current
I
EBO
(V
EB(off)
(V
EB(off)
= 3.0 Vdc, I = 0)
MMBT5088
MMBT5089
—
—
50
100
C
= 4.5 Vdc, I = 0)
C
1. FR–5 = 1.0
0.75 0.062 in.
2. Alumina = 0.4 0.3 0.024 in. 99.5% alumina.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
Motorola, Inc. 1996
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted) (Continued)
A
Characteristic
ON CHARACTERISTICS
Symbol
Min
Max
Unit
DC Current Gain
(I = 100 µAdc, V
C
h
FE
—
= 5.0 Vdc)
= 5.0 Vdc)
= 5.0 Vdc)
MMBT5088
MMBT5089
300
400
900
1200
CE
CE
CE
(I = 1.0 mAdc, V
C
MMBT5088
MMBT5089
350
450
—
—
(I = 10 mAdc, V
C
MMBT5088
MMBT5089
300
400
—
—
Collector–Emitter Saturation Voltage
(I = 10 mAdc, I = 1.0 mAdc)
V
V
Vdc
Vdc
CE(sat)
—
—
0.5
0.8
C
B
Base–Emitter Saturation Voltage
(I = 10 mAdc, I = 1.0 mAdc)
BE(sat)
C
B
SMALL–SIGNAL CHARACTERISTICS
Current–Gain — Bandwidth Product
f
C
C
MHz
pF
T
(I = 500 µAdc, V
C CE
= 5.0 Vdc, f = 20 MHz)
50
—
—
—
4.0
10
Collector–Base Capacitance
(V = 5.0 Vdc, I = 0, f = 1.0 MHz emitter guarded)
cb
eb
CB
Emitter–Base Capacitance
(V = 0.5 Vdc, I = 0, f = 1.0 MHz collector guarded)
E
pF
EB
C
Small Signal Current Gain
h
fe
—
(I = 1.0 mAdc, V
C
= 5.0 Vdc, f = 1.0 kHz)
MMBT5088
MMBT5089
350
450
1400
1800
CE
Noise Figure
NF
dB
(I = 100 Adc, V
C
= 5.0 Vdc, R = 10 kΩ, f = 1.0 kHz)
MMBT5088
MMBT5089
—
—
3.0
2.0
CE
S
R
S
i
n
e
n
IDEAL
TRANSISTOR
Figure 1. Transistor Noise Model
2
Motorola Small–Signal Transistors, FETs and Diodes Device Data
NOISE CHARACTERISTICS
(V
= 5.0 Vdc, T = 25°C)
CE
A
NOISE VOLTAGE
30
20
30
BANDWIDTH = 1.0 Hz
BANDWIDTH = 1.0 Hz
20
I
= 10 mA
R
≈ 0
R
≈ 0
C
S
S
f = 10 Hz
10 kHz
3.0 mA
10
10
100 Hz
1.0 mA
7.0
5.0
7.0
5.0
1.0 kHz
300 µA
100 kHz
5.0
3.0
3.0
0.01 0.02
10 20
50 100 200 500 1 k 2 k
5 k 10 k 20 k 50 k 100 k
0.05 0.1
0.2
0.5
1.0
2.0
10
f, FREQUENCY (Hz)
I
, COLLECTOR CURRENT (mA)
C
Figure 2. Effects of Frequency
Figure 3. Effects of Collector Current
10
20
16
BANDWIDTH = 1.0 Hz
= 10 mA
7.0
5.0
I
C
3.0
2.0
BANDWIDTH = 10 Hz to 15.7 kHz
3.0 mA
1.0 mA
12
1.0
0.7
0.5
I
= 1.0 mA
C
500 µA
8.0
4.0
0
300
100
µA
100
10
µ
A
µA
0.3
0.2
µ
A
10 µA
30 µA
R
≈ 0
S
0.1
10 20
50 100 200 500 1 k 2 k
f, FREQUENCY (Hz)
5 k 10 k 20 k 50 k 100 k
10 20
50 100 200 500 1 k 2 k
5 k 10 k 20 k 50 k 100 k
R
, SOURCE RESISTANCE (OHMS)
S
Figure 4. Noise Current
Figure 5. Wideband Noise Figure
100 Hz NOISE DATA
300
200
20
BANDWIDTH = 1.0 Hz
I = 10 mA
C
3.0 mA
16
12
I
= 10 mA
C
100 µA
100
70
50
3.0 mA
1.0 mA
1.0 mA
300
30
20
µA
300 µA
8.0
30 µA
100 µA
10
10 µA
4.0
0
30 µA
7.0
5.0
10 µA
BANDWIDTH = 1.0 Hz
3.0
10 20
50 100 200 500 1 k 2 k
5 k 10 k 20 k 50 k 100 k
10 20
50 100 200 500 1 k 2 k
5 k 10 k 20 k 50 k 100 k
R
, SOURCE RESISTANCE (OHMS)
R , SOURCE RESISTANCE (OHMS)
S
S
Figure 6. Total Noise Voltage
Figure 7. Noise Figure
Motorola Small–Signal Transistors, FETs and Diodes Device Data
3
4.0
3.0
V
= 5.0 V
CE
2.0
T
= 125°C
A
25°C
1.0
0.7
–55°C
0.5
0.4
0.3
0.2
0.01
0.02
0.03
0.05
0.1
0.2
0.3
0.5
1.0
2.0
3.0
5.0
10
I
, COLLECTOR CURRENT (mA)
C
Figure 8. DC Current Gain
1.0
0.8
–0.4
–0.8
T
= 25°C
J
0.6
0.4
0.2
0
V
@ V
CE
= 5.0 V
–1.2
–1.6
–2.0
–2.4
BE
T
= 25°C to 125°C
J
–55°C to 25°C
V
@ I /I = 10
C B
CE(sat)
0.01 0.02 0.05 0.1 0.2
1.0 2.0 5.0
0.01 0.02 0.05 0.1 0.2
1.0 2.0 5.0
0.5
10 20
50 100
0.5
10 20
50 100
I
, COLLECTOR CURRENT (mA)
I , COLLECTOR CURRENT (mA)
C
C
Figure 9. “On” Voltages
Figure 10. Temperature Coefficients
8.0
6.0
500
T
= 25°C
J
300
200
C
ob
C
ib
4.0
3.0
C
eb
C
cb
2.0
100
V
= 5.0 V
CE
= 25°C
70
50
T
J
1.0
0.8
0.1
0.2
1.0
2.0
5.0
1.0
2.0 3.0
5.0 7.0
I , COLLECTOR CURRENT (mA)
C
0.5
10
20
50
100
10
20
30
50 70 100
V
, REVERSE VOLTAGE (VOLTS)
R
Figure 11. Capacitance
Figure 12. Current–Gain — Bandwidth Product
4
Motorola Small–Signal Transistors, FETs and Diodes Device Data
INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to insure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.037
0.95
0.037
0.95
0.079
2.0
0.035
0.9
0.031
0.8
inches
mm
SOT–23
SOT–23 POWER DISSIPATION
The power dissipation of the SOT–23 is a function of the
SOLDERING PRECAUTIONS
pad size. This can vary from the minimum pad size for
soldering to a pad size given for maximum power dissipation.
Power dissipation for a surface mount device is determined
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
by T
, the maximum rated junction temperature of the
, the thermal resistance from the device junction to
J(max)
die, R
θJA
ambient, and the operating temperature, T . Using the
A
values provided on the data sheet for the SOT–23 package,
P
can be calculated as follows:
D
•
•
Always preheat the device.
The delta temperature between the preheat and
soldering should be 100°C or less.*
T
– T
A
J(max)
P
=
D
R
θJA
•
When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature T of 25°C, one can
A
calculate the power dissipation of the device which in this
case is 225 milliwatts.
•
•
•
The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
150°C – 25°C
556°C/W
P
=
= 225 milliwatts
D
The 556°C/W for the SOT–23 package assumes the use
of the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 225 milliwatts. There
are other alternatives to achieving higher power dissipation
from the SOT–23 package. Another alternative would be to
use a ceramic substrate or an aluminum core board such as
Thermal Clad . Using a board material such as Thermal
Clad, an aluminum core board, the power dissipation can be
doubled using the same footprint.
•
Mechanical stress or shock should not be applied during
cooling.
* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.
Motorola Small–Signal Transistors, FETs and Diodes Device Data
5
PACKAGE DIMENSIONS
NOTES:
A
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
L
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
3
S
B
1
2
INCHES
MIN MAX
MILLIMETERS
DIM
A
B
C
D
G
H
J
MIN
2.80
1.20
0.89
0.37
1.78
0.013
0.085
0.45
0.89
2.10
0.45
MAX
3.04
1.40
1.11
0.50
2.04
0.100
0.177
0.60
1.02
2.50
0.60
V
G
0.1102 0.1197
0.0472 0.0551
0.0350 0.0440
0.0150 0.0200
0.0701 0.0807
0.0005 0.0040
0.0034 0.0070
0.0180 0.0236
0.0350 0.0401
0.0830 0.0984
0.0177 0.0236
C
K
L
S
H
J
D
V
K
STYLE 6:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
CASE 318–08
SOT–23 (TO–236AB)
ISSUE AE
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MMBT5088LT1/D
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