MMSF5N02HD [MOTOROLA]
SINGLE TMOS POWER MOSFET 5.0 AMPERES 20 VOLTS; 单TMOS功率MOSFET 5.0安培20伏
| 型号： | MMSF5N02HD |
| 厂家： | 
MOTOROLA |
| 描述： | SINGLE TMOS POWER MOSFET 5.0 AMPERES 20 VOLTS |
| 文件： | 总10页 (文件大小：296K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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by MMSF5N02HD/D
SEMICONDUCTOR TECHNICAL DATA
Medium Power Surface Mount Products
Motorola Preferred Device
SINGLE TMOS
POWER MOSFET
5.0 AMPERES
20 VOLTS
MiniMOS devices are an advanced series of power MOSFETs
which utilize Motorola’s High Cell Density HDTMOS process.
TheseminiaturesurfacemountMOSFETsfeatureultralowR
DS(on)
R
= 0.025 OHM
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
drain–to–source diode has a very low reverse recovery time.
MiniMOS devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dc–dc converters, and power management in
portable and battery powered products such as computers,
printers, cellular and cordless phones. They can also be used for
low voltage motor controls in mass storage products such as disk
drives and tape drives. The avalanche energy is specified to
eliminate the guesswork in designs where inductive loads are
switched and offer additional safety margin against unexpected
voltage transients.
DS(on)
D
CASE 751–05, Style 13
SO–8
G
S
1
2
3
4
8
7
6
5
Drain
Drain
Drain
Drain
N–C
Source
Source
Gate
•
•
•
•
•
•
•
•
Ultra Low R Provides Higher Efficiency and Extends Battery Life
DS(on)
Logic Level Gate Drive — Can Be Driven by Logic ICs
Miniature SO–8 Surface Mount Package — Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
Top View
I
Specified at Elevated Temperature
DSS
Avalanche Energy Specified
Mounting Information for SO–8 Package Provided
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Rating
Symbol
Value
20
Unit
Vdc
Vdc
Vdc
Adc
Drain–to–Source Voltage
V
DSS
Drain–to–Gate Voltage (R
GS
= 1.0 MΩ)
V
DGR
20
Gate–to–Source Voltage — Continuous
V
GS
± 20
Drain Current — Continuous @ T = 25°C
Drain Current — Continuous @ T = 100°C
Drain Current — Single Pulse (t ≤ 10 µs)
I
I
8.2
5.6
41
A
A
D
D
I
Apk
Watts
°C
p
DM
(1)
Total Power Dissipation @ T = 25°C
P
D
2.5
– 55 to 150
675
A
Operating and Storage Temperature Range
T , T
J stg
Single Pulse Drain–to–Source Avalanche Energy — Starting T = 25°C
E
AS
mJ
J
(V
DD
= 20 Vdc, V = 5.0 Vdc, Peak I = 15 Apk, L = 6.0 mH, R = 25 Ω)
GS L G
(1)
Thermal Resistance — Junction to Ambient
R
50
°C/W
°C
θJA
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
T
260
L
DEVICE MARKING
S5N02
(1) Mounted on 2” square FR4 board (1” sq. 2 oz. Cu 0.06” thick single sided), 10 sec. max.
ORDERING INFORMATION
Device
Reel Size
Tape Width
Quantity
MMSF5N02HDR2
13″
12 mm embossed tape
2500 units
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s, HDTMOS and MiniMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 5
Motorola, Inc. 1996
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
C
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
V
Vdc
(BR)DSS
(V
GS
= 0 Vdc, I = 250 µAdc)
Temperature Coefficient (Positive)
20
—
—
41
—
—
D
mV/°C
µAdc
Zero Gate Voltage Drain Current
I
DSS
(V
DS
(V
DS
= 20 Vdc, V
= 20 Vdc, V
= 0 Vdc)
= 0 Vdc, T = 125°C)
—
—
0.02
—
1.0
10
GS
GS
J
Gate–Body Leakage Current (V
GS
= ± 20 Vdc, V
DS
= 0)
I
—
—
100
nAdc
Vdc
GSS
(1)
ON CHARACTERISTICS
Gate Threshold Voltage
V
GS(th)
(V
DS
= V , I = 250 µAdc)
Temperature Coefficient (Negative)
1.0
—
1.5
4.0
2.0
—
GS
D
mV/°C
Static Drain–to–Source On–Resistance
R
Ohm
DS(on)
(V
GS
(V
GS
= 10 Vdc, I = 5.0 Adc)
—
—
0.0185
0.0219
0.025
0.040
D
= 4.5 Vdc, I = 2.5 Adc)
D
Forward Transconductance (V
DS
= 15 Vdc, I = 2.5 Adc)
g
3.0
12
—
Mhos
pF
D
FS
DYNAMIC CHARACTERISTICS
Input Capacitance
C
—
—
—
1130
464
117
1582
650
iss
(V
DS
= 16 Vdc, V = 0 Vdc,
GS
f = 1.0 MHz)
Output Capacitance
C
oss
Transfer Capacitance
C
235
rss
(2)
SWITCHING CHARACTERISTICS
Turn–On Delay Time
t
—
—
—
—
—
—
—
—
—
—
—
—
15
93
30
185
70
80
—
ns
d(on)
(V
= 10 Vdc, I = 5.0 Adc,
D
Rise Time
DD
DD
t
r
V
= 4.5 Vdc,
GS
G
Turn–Off Delay Time
Fall Time
t
t
t
35
d(off)
R
= 6.0 Ω)
t
f
40
Turn–On Delay Time
Rise Time
9.0
53
d(on)
(V
= 10 Vdc, I = 5.0 Adc,
D
t
r
—
V
R
= 10 Vdc,
GS
G
Turn–Off Delay Time
Fall Time
56
—
d(off)
= 6.0 Ω)
t
f
39
—
Gate Charge
See Figure 8
Q
T
Q
1
Q
2
Q
3
30.3
3.0
7.5
6.0
43
—
nC
(V
= 16 Vdc, I = 5.0 Adc,
D
DS
V
GS
= 10 Vdc)
—
—
SOURCE–DRAIN DIODE CHARACTERISTICS
(1)
Forward On–Voltage
V
Vdc
ns
SD
(I = 5.0 Adc, V
= 0 Vdc)
= 0 Vdc, T = 125°C)
S
GS
—
—
0.82
0.69
1.0
—
(I = 5.0 Adc, V
S
GS
J
Reverse Recovery Time
See Figure 15
t
—
—
—
—
32
24
—
—
—
—
rr
t
a
(I = 5.0 Adc, V
= 0 Vdc,
dI /dt = 100 A/µs)
S
GS
S
t
8.0
b
Reverse Recovery Stored Charge
Q
0.045
µC
RR
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
2
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
10
8
10
V
= 10 V
T
= 25
°C
V
≥
10 V
GS
J
DS
3.1 V
4.5 V
8
6
4
2
0
3.8 V
6
4
2
0
T
= 100°C
J
25°C
–55°C
2.4 V
1.4
0
0.2
0.4
0.6
0.8
1
1.2
1.6
1.8
2
1.5
1.7
1.9
2.1
2.3
2.5
2.7
2.9
3.1
3.3
V
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
V
, GATE–TO–SOURCE VOLTAGE (VOLTS)
DS
GS
Figure 1. On–Region Characteristics
Figure 2. Transfer Characteristics
0.2
0.023
0.021
I
= 2.5 A
D
T
= 25°C
V
= 4.5 V
J
GS
0.16
0.12
0.08
0.04
0
0.019
0.017
10 V
0
1
2
3
4
5
6
7
8
9
10
0
2
4
6
8
10
V
, GATE–TO–SOURCE VOLTAGE (VOLTS)
I , DRAIN CURRENT (AMPS)
D
GS
Figure 3. On–Resistance versus
Gate–to–Source Voltage
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
1.6
1.4
1.2
1
1000
100
V
= 0 V
GS
V
= 10 V
= 2.5 A
GS
I
D
T
= 125°C
J
100°C
25°C
10
1
0.8
0.6
–50
–25
0
25
50
75
100
C)
125
150
8
0
4
12
16
20
T , JUNCTION TEMPERATURE (
°
V , DRAIN–TO–SOURCE VOLTAGE (VOLTS)
DS
J
Figure 5. On–Resistance Variation with
Temperature
Figure 6. Drain–To–Source Leakage
Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
3
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The capacitance (C ) is read from the capacitance curve at
iss
a voltage corresponding to the off–state condition when cal-
culating t
and is read at a voltage corresponding to the
d(on)
on–state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (I
the drive circuit so that
) can be made from a rudimentary analysis of
G(AV)
t = Q/I
G(AV)
During the rise and fall time interval when switching a resis-
tive load, V remains virtually constant at a level known as
GS
the plateau voltage, V
. Therefore, rise and fall times may
SGP
be approximated by the following:
t = Q x R /(V
– V )
GSP
r
2
G
GG
t = Q x R /V
f
2
G
GSP
where
V
= the gate drive voltage, which varies from zero to V
= the gate drive resistance
GG
GG
R
G
and Q and V
GSP
are read from the gate charge curve.
2
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
t
= R
= R
C
C
In [V
/(V
GG GG
– V
)
)]
d(on)
G
iss
GSP
In (V
/V
GG GSP
d(off)
G
iss
3500
V
= 0 V
V
= 0 V
T = 25°C
J
DS
GS
3000
2500
2000
C
iss
1500
1000
C
rss
C
iss
C
oss
500
0
C
rss
10
5
0
5
10
15
20
V
V
DS
GS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (Volts)
Figure 7. Capacitance Variation
4
Motorola TMOS Power MOSFET Transistor Device Data
1000
12
10
24
20
QT
V
= 10 V
= 5 A
= 10 V
= 25°C
DD
I
V
T
D
td(off)
GS
V
GS
t
f
r
J
8
6
4
16
12
8
100
10
1
t
I
T
= 5 A
D
= 25°C
Q1
t
Q2
J
d(on)
2
0
4
0
V
Q3
DS
1
10
100
0
4
8
12
16
20
24
28
32
Q , TOTAL CHARGE (nC)
R
, GATE RESISTANCE (OHMS)
T
G
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse re-
covery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
di/dts. The diode’s negative di/dt during t is directly con-
a
trolled by the device clearing the stored charge. However,
the positive di/dt during t is an uncontrollable diode charac-
b
teristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of t /t serves
b a
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier de-
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
vice, therefore it has a finite reverse recovery time, t , due to
rr
the storage of minority carrier charge, Q , as shown in the
RR
typical reverse recovery wave form of Figure 15. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
(shorter t ), have less stored charge and a softer reverse re-
rr
covery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise gen-
erated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.
diode with short t and low Q
these losses.
specifications to minimize
rr
RR
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ring-
ing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high
5
V
= 0 V
GS
= 25
T
°C
J
4
3
2
1
0
0.5
0.55
V
0.6
0.65
0.7
0.75
0.8
0.85
, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
SD
Figure 10. Diode Forward Voltage versus Current
Motorola TMOS Power MOSFET Transistor Device Data
5
di/dt = 300 A/µs
Standard Cell Density
t
rr
High Cell Density
t
rr
t
b
t
a
t, TIME
Figure 11. Reverse Recovery Time (t )
rr
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction tem-
perature.
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is for-
ward biased. Curves are based upon maximum peak junc-
tion temperature and a case temperature (T ) of 25°C. Peak
C
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance – Gen-
eral Data and Its Use.”
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
Switching between the off–state and the on–state may tra-
verse any load line provided neither rated peak current (I
)
DM
) is exceeded, and that the transition
(I
), the energy rating is specified at rated continuous cur-
DM
nor rated voltage (V
DSS
rent (I ), in accordance with industry custom. The energy rat-
D
time (t , t ) does not exceed 10 µs. In addition the total power
r f
ing must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at cur-
averaged over a complete switching cycle must not exceed
(T
– T )/(R ).
J(MAX)
C
θJC
rents below rated continuous I can safely be assumed to
A power MOSFET designated E–FET can be safely used
D
in switching circuits with unclamped inductive loads. For reli-
equal the values indicated.
675
100
V
= 10 V
I = 15 A
D
GS
SINGLE PULSE
= 25
575
475
375
275
175
100
1 ms
µs
T
°C
C
10
1
10 ms
dc
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
0.1
75
Mounted on 2” sq. FR4 board (1” sq. 2 oz. Cu 0.06”
thick single sided), 10s max.
–25
0.01
25
50
75
100
125
C)
150
0.1
1
10
100
T , STARTING JUNCTION TEMPERATURE (
°
V
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
J
DS
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
Figure 13. Maximum Avalanche Energy versus
Starting Junction Temperature
6
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
10
1
D = 0.5
0.2
0.1
0.1
Normalized to θja at 10s.
0.05
0.02
0.01
0.0163
Ω
0.0652
Ω
0.1988
Ω
0.6411
Ω
0.9502 Ω
Chip
0.01
0.0307 F
0.1668 F
1.0E+00
0.5541 F
1.9437 F
72.416 F
Ambient
SINGLE PULSE
1.0E–04
0.001
1.0E–05
1.0E–03
1.0E–02
1.0E–01
t, TIME (s)
1.0E+01
1.0E+02
1.0E+03
Figure 14. Thermal Response
di/dt
I
S
t
rr
t
t
a
b
TIME
0.25 I
t
S
p
I
S
Figure 15. Diode Reverse Recovery Waveform
Motorola TMOS Power MOSFET Transistor Device Data
7
INFORMATION FOR USING THE SO–8 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must be
the correct size to ensure proper solder connection interface
between the board and the package. With the correct pad
geometry, the packages will self–align when subjected to a
solder reflow process.
0.060
1.52
0.275
7.0
0.155
4.0
0.024
0.6
0.050
1.270
inches
mm
SO–8 POWER DISSIPATION
The power dissipation of the SO–8 is a function of the input
pad size. This can vary from the minimum pad size for
soldering to the pad size given for maximum power
dissipation. Power dissipation for a surface mount device is
the equation for an ambient temperature T of 25°C, one can
calculatethe power dissipation of the device which in this case
is 2.5 Watts.
A
determined by T
, the maximum rated junction
J(max)
temperature of the die, R
150°C – 25°C
, the thermal resistance from the
θJA
P
=
= 2.5 Watts
D
50°C/W
devicejunctiontoambient;andtheoperatingtemperature,T .
Using the values provided on the data sheet for the SO–8
A
package, P can be calculated as follows:
D
The 50°C/W for the SO–8 package assumes the
recommended footprint on a glass epoxy printed circuit board
to achieve a power dissipation of 2.5 Watts using the footprint
shown. Another alternative would be to use a ceramic
substrate or an aluminum core board such as Thermal Clad .
Using board material such as Thermal Clad, the power
dissipation can be doubled using the same footprint.
T
– T
A
J(max)
R
P
=
D
θJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and soldering
should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
• When shifting from preheating to soldering, the maximum
temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should be
allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied during
cooling.
* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.
8
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of control
line on the graph shows the actual temperature that might be
experienced on the surface of a test board at or near a central
solder joint. The two profiles are based on a high density and
a low density board. The Vitronics SMD310 convection/in-
frared reflow soldering system was used to generate this
profile. The type of solder used was 62/36/2 Tin Lead Silver
with a melting point between 177–189°C. When this type of
furnace is used for solder reflow work, the circuit boards and
solder joints tend to heat first. The components on the board
are then heated by conduction. The circuit board, because it
has a large surface area, absorbs the thermal energy more
efficiently, then distributes this energy to the components.
Because of this effect, the main body of a component may be
up to 30 degrees cooler than the adjacent solder joints.
settings that will give the desired heat pattern. The operator
must set temperatures for several heating zones and a figure
for belt speed. Taken together, these control settings make up
a heating “profile” for that particular circuit board. On
machines controlled by a computer, the computer remembers
these profiles from one operating session to the next. Figure
16 shows a typical heating profile for use when soldering a
surface mount device to a printed circuit board. This profile will
vary among soldering systems, but it is a good starting point.
Factors that can affect the profile include the type of soldering
system in use, density and types of components on the board,
typeofsolderused, andthetypeofboardorsubstratematerial
being used. This profile shows temperature versus time. The
STEP 5
HEATING
ZONES 4 & 7
“SPIKE”
STEP 6
VENT
STEP 7
COOLING
STEP 1
PREHEAT
ZONE 1
“RAMP”
STEP 4
HEATING
ZONES 3 & 6
“SOAK”
STEP 2
VENT
“SOAK” ZONES 2 & 5
“RAMP”
STEP 3
HEATING
205
PEAK AT
SOLDER JOINT
° TO 219°C
200
°
C
C
170°C
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
160°C
150°C
150°
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
100°C
140°C
MASS OF ASSEMBLY)
100
°
C
C
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
50°
TIME (3 TO 7 MINUTES TOTAL)
T
MAX
Figure 16. Typical Solder Heating Profile
Motorola TMOS Power MOSFET Transistor Device Data
9
PACKAGE DIMENSIONS
NOTES:
–A–
J
1. DIMENSIONS A AND B ARE DATUMS AND T IS A
DATUM SURFACE.
2. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
3. DIMENSIONS ARE IN MILLIMETER.
4. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
6. DIMENSION D DOES NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE D DIMENSION AT MAXIMUM MATERIAL
CONDITION.
8
1
5
4
–B–
M
G
MILLIMETERS
DIM
A
B
C
D
MIN
4.80
3.80
1.35
0.35
0.40
MAX
5.00
4.00
1.75
0.49
1.25
–T–
SEATING
PLANE
F
G
J
K
M
P
R
1.27 BSC
8X D
0.18
0.10
0
0.25
0.25
7
M
S
S
0.25 (0.010)
T
B
A
5.80
0.25
6.20
0.50
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
CASE 751–05
SO–8
ISSUE P
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