MPC755BPX400LX [MOTOROLA]
32-BIT, 400MHz, RISC PROCESSOR, PBGA360, 25 X 25 MM, 2.77 MM HEIGHT, 1.27 MM PITCH, PLASTIC, BGA-360;
| 型号： | MPC755BPX400LX |
| 厂家： | 
MOTOROLA |
| 描述： | 32-BIT, 400MHz, RISC PROCESSOR, PBGA360, 25 X 25 MM, 2.77 MM HEIGHT, 1.27 MM PITCH, PLASTIC, BGA-360 时钟 外围集成电路 |
| 文件： | 总48页 (文件大小：1265K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order Number: MPC755EC/D
Rev. 2, 4/2001
Semiconductor Products Sector
Advance Information
MPC755 RISC Microprocessor
Hardware Specifications
This document is primarily concerned with the MPC755, however, unless otherwise noted, all information
here also applies to the MPC745. The MPC755 and MPC745 are implementations of the PowerPC™ family
of reduced instruction set computing (RISC) microprocessors. This document describes pertinent physical
characteristics of the MPC755. For functional characteristics of the processor, refer to the MPC750 RISC
Microprocessor User’s Manual and MPC755 RISC Microprocessor User’s Manual Addendum.
This document contains the following topics:
Topic
Page
Section 1.1, “Overview”
2
Section 1.2, “Features”
3
Section 1.3, “General Parameters”
Section 1.4, “Electrical and Thermal Characteristics”
Section 1.5, “Pin Assignments”
5
6
22
24
29
33
46
47
Section 1.6, “Pinout Listings”
Section 1.7, “Package Description”
Section 1.8, “System Design Information”
Section 1.9, “Document Revision History”
Section 1.10, “Ordering Information”
To locate any published errata or updates for this document, refer to the website at
http://www.motorola.com/semiconductors.
This document contains information on a new product under development by Motorola.
Motorola reserves the right to change or discontinue this product without notice.
© Motorola, Inc., 2001. All rights reserved.
Overview
1.1 Overview
The MPC755 is targeted for low-cost, low-power systems and supports the following power management
features—doze, nap, sleep, and dynamic power management. The MPC755 consists of a processor core and
an internal L2 Tag combined with a dedicated L2 cache interface and a 60x bus. The MPC745 is identical
to the MPC755 except it does not support the L2 cache interface.
Figure 1 shows a block diagram of the MPC755.
Control Unit
Instruction Fetch
Branch Unit
Completion
32K ICache
BHT/BTIC
System Unit
Dispatch
GPRs
FPRs
FXU1
FXU2
LSU
FPU
Rename
Buffers
Rename
Buffers
L2 Cache
BIU
32K DCache
L2 Tags
60x BIU
Not in the MPC745.
Figure 1. MPC755 Block Diagram
2
MPC755 RISC Microprocessor Hardware Specifications
Features
1.2 Features
This section summarizes features of the MPC755 implementation of the PowerPC architecture. Major
features of the MPC755 are as follows:
•
Branch processing unit
— Four instructions fetched per clock
— One branch processed per cycle (plus resolving two speculations)
— Up to one speculative stream in execution, one additional speculative stream in fetch
— 512-entry branch history table (BHT) for dynamic prediction
— 64-entry, 4-way set associative Branch Target Instruction Cache (BTIC) for eliminating branch
delay slots
•
Dispatch unit
— Full hardware detection of dependencies (resolved in the execution units)
— Dispatch two instructions to six independent units (system, branch, load/store, fixed-point
unit 1, fixed-point unit 2, floating-point)
— Serialization control (predispatch, postdispatch, execution serialization)
•
•
Decode
— Register file access
— Forwarding control
— Partial instruction decode
Completion
— 6-entry completion buffer
— Instruction tracking and peak completion of two instructions per cycle
— Completion of instructions in program order while supporting out-of-order instruction
execution, completion serialization and all instruction flow changes
•
•
Fixed Point Units (FXUs) that share 32 GPRs for integer operands
— Fixed Point Unit 1 (FXU1)—multiply, divide, shift, rotate, arithmetic, logical
— Fixed Point Unit 2 (FXU2)—shift, rotate, arithmetic, logical
— Single-cycle arithmetic, shifts, rotates, logical
— Multiply and divide support (multi-cycle)
— Early out multiply
Floating-point unit and a 32-entry FPR file
— Support for IEEE-754 standard single- and double-precision floating point arithmetic
— Hardware support for divide
— Hardware support for denormalized numbers
— Single-entry reservation station
— Supports non-IEEE mode for time-critical operations
— 3-cycle latency, 1-cycle throughput, single-precision multiply-add
— 3-cycle latency, 1-cycle throughput, double-precision add
— 4-cycle latency, 2-cycle throughput, double-precision multiply-add
MPC755 RISC Microprocessor Hardware Specifications
3
Features
•
System unit
— Executes CR logical instructions and miscellaneous system instructions
— Special register transfer instructions
•
Load/store unit
— 1-cycle load or store cache access (byte, half-word, word, double-word)
— Effective address generation
— Hits under misses (one outstanding miss)
— Single-cycle unaligned access within double word boundary
— Alignment, zero padding, sign extend for integer register file
— Floating point internal format conversion (alignment, normalization)
— Sequencing for load/store multiples and string operations
— Store gathering
— Cache and TLB instructions
— Big- and little-endian byte addressing supported
Level 1 Cache structure
•
— 32K, 32-byte line, 8-way set associative instruction cache (iL1)
— 32K, 32-byte line, 8-way set associative data cache (dL1)
— Cache locking for both instruction and data caches, selectable by group of ways
— Single-cycle cache access
— Pseudo least recently used (PLRU) replacement
— Copy-back or write through data cache (on a page per page basis)
— Supports all PowerPC memory coherency modes
— Non-blocking instruction and data cache (one outstanding miss under hits)
— No snooping of instruction cache
•
Level 2 (L2) Cache Interface (not implemented on MPC745)
— Internal L2 cache controller and tags; external data SRAMs
— 256K, 512K, and 1 Mbyte 2-way set associative L2 cache support
— Copy-back or write through data cache (on a page basis, or for all L2)
— Instruction-only mode and data-only mode.
— 64-byte (256K/512K) or 128-byte (1M) sectored line size
— Supports flow through (register-buffer) synchronous BurstRAMs, pipelined (register-register)
synchronous BurstRAMs (3-1-1-1 or strobeless 4-1-1-1) and pipelined (register-register) late
write synchronous BurstRAMs
— L2 configurable to cache, private memory, or split cache/private memory
— Core-to-L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5, and ÷3 supported
— 64-bit data bus
— Selectable interface voltages of 2.5 V and 3.3 V
— Parity checking on both L2 address and data
Memory Management Unit
•
— 128-entry, 2-way set associative instruction TLB
— 128-entry, 2-way set associative data TLB
4
MPC755 RISC Microprocessor Hardware Specifications
General Parameters
— Hardware reload for TLBs
— Hardware or optional software tablewalk support
— 8 instruction BATs and 8 data BATs
— 8 SPRGs, for assistance with software tablewalks
52
— Virtual memory support for up to 4 exabytes (2 ) of virtual memory
32
— Real memory support for up to 4 gigabytes (2 ) of physical memory
•
Bus Interface
— Compatible with 60X processor interface
— 32-bit address bus
— 64-bit data bus, 32-bit mode selectable
— Bus-to-core frequency multipliers of 2x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x, 10x
supported
— Selectable interface voltages of 2.5 V and 3.3 V
— Parity checking on both address and data busses
Power management
•
— Low-power design with thermal requirements very similar to MPC740/750.
— Three static power saving modes: doze, nap, and sleep
— Dynamic power management
•
•
Integrated Thermal Management Assist Unit
— On-chip thermal sensor and control logic
— Thermal management interrupt for software regulation of junction temperature
Testability
— LSSD scan design
— IEEE 1149.1 JTAG interface
1.3 General Parameters
The following list provides a summary of the general parameters of the MPC755:
Technology
Die size
0.22 µm CMOS, six-layer metal
2
6.61 mm x 7.73 mm (51 mm )
Transistor count
Logic design
Packages
6.75 million
Fully static
MPC745: Surface mount 255 plastic ball grid array (PBGA)
MPC755: Surface mount 360 ceramic ball grid array (CBGA)
Surface mount 360 plastic ball grid array (PBGA)
Core power supply
I/O power supply
2.0 V ± 100 mV DC (nominal; some parts support core voltages down to
1.8 V; see Table 3 for recommended operating conditions)
2.5 V ± 100 mV DC or
3.3 V ± 165 mV DC (input thresholds are configuration pin selectable)
MPC755 RISC Microprocessor Hardware Specifications
5
Electrical and Thermal Characteristics
1.4 Electrical and Thermal Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the MPC755.
1.4.1 DC Electrical Characteristics
Table 1 to Table 7 describe the MPC755 DC electrical characteristics. Table 1 provides the absolute
maximum ratings.
Table 1. Absolute Maximum Ratings1
Characteristic
Core supply voltage
Symbol
Vdd
Maximum Value
–0.3 to 2.5
Unit
V
Note
4
PLL supply voltage
AVdd
L2AVdd
OVdd
L2OVdd
Vin
–0.3 to 2.5
V
4
L2 DLL supply voltage
Processor bus supply voltage
L2 bus supply voltage
Input voltage
–0.3 to 2.5
V
4
–0.3 to 3.465
–0.3 to 3.465
–0.3 to OVdd + 0.3 V
–0.3 to L2OVdd + 0.3 V
–0.3 to 3.6
V
3
V
3
Processor bus
L2 Bus
V
2, 5
2, 5
Vin
V
JTAG Signals
Vin
V
Storage temperature range
Tstg
–55 to 150
°C
Notes:
1. Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings
only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect
device reliability or cause permanent damage to the device.
2. Caution: V must not exceed OVdd or L2OVdd by more than 0.3 V at any time including during power-on
in
reset.
3. Caution: L2OVdd/OVdd must not exceed Vdd/AVdd/L2AVdd by more than 1.6 V at any time including during
power-on reset.
4. Caution: Vdd/AVdd/L2AVdd must not exceed L2OVdd/OVdd by more than 0.4 V at any time including during
power-on reset.
5. Vin may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
Figure 2 shows the allowable undershoot and overshoot voltage on the MPC755.
6
MPC755 RISC Microprocessor Hardware Specifications
Electrical and Thermal Characteristics
(L2)OVdd + 20%
(L2)OVdd + 5%
(L2)OVdd
VIH
VIL
GND
GND – 0.3 V
GND – 0.7 V
Not to Exceed 10%
of tSYSCLK
Figure 2. Overshoot/Undershoot Voltage
The MPC755 provides several I/O voltages to support both compatibility with existing systems and
migration to future systems. The MPC755 core voltage must always be provided at nominal 2.0 V (see
Table 3 for actual recommended core voltage). Voltage to the L2 I/Os and Processor Interface I/Os are
provided through separate sets of supply pins and may be provided at the voltages shown in Table 2. The
input voltage threshold for each bus is selected by sampling the state of the voltage select pins BVSEL and
L2VSEL during operation. These signals must remain stable during part operation and cannot change. The
output voltage will swing from GND to the maximum voltage applied to the OVdd or L2OVdd power pins.
Table 2 describes the input threshold voltage setting.
Table 2. Input Threshold Voltage Setting
Part
Revision
Processor Bus Interface
Voltage
L2 Bus
Interface Voltage
BVSEL Signal
L2VSEL Signal
E
0
0
1
1
0
1
0
1
Not Available
Not Available
2.5 V / 3.3 V
2.5 V / 3.3 V
Not Available
2.5 V / 3.3 V
Not Available
2.5 V / 3.3 V
Caution: The input threshold selection must agree with the OVdd/L2OVdd voltages supplied.
Note: The input threshold settings above are different for all revisions prior to Rev 2.8 (Rev E). For more
information, contact your local Motorola sales office.
Table 3 provides the recommended operating conditions for the MPC755.
MPC755 RISC Microprocessor Hardware Specifications
7
Electrical and Thermal Characteristics
Table 3. Recommended Operating Conditions1
Recommended Value
Characteristic
Symbol
300 MHz, 350 MHz
400 MHz
Unit Note
Min
Max
Min
Max
Core supply voltage
Vdd
AVdd
1.80
1.80
1.80
2.375
3.135
2.375
3.135
GND
GND
GND
0
2.10
2.10
1.90
1.90
1.90
2.10
2.10
V
V
V
V
3
3
PLL supply voltage
L2 DLL supply voltage
L2AVdd
OVdd
2.10
2.10
3
Processor bus
supply voltage
BVSEL = 1
2.625
3.465
2.625
3.465
OVdd
L2Ovdd
OVdd
105
2.375
3.135
2.375
3.135
GND
GND
GND
0
2.625
3.465
2.625
3.465
OVdd
L2Ovdd
OVdd
105
2, 4
5
L2 bus supply
voltage
L2VSEL = 1
L2OVdd
V
2, 4
5
Input voltage
Processor bus
L2 Bus
Vin
Vin
Vin
Tj
V
V
JTAG Signals
V
Die-junction
temperature
°C
Notes:
1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions
is not guaranteed.
2. Revisions prior to Rev 2.8 (Rev E) offered different I/O voltage support. For more information, contact your local
Motorola sales office.
3. 2.0 V nominal.
4. 2.5 V nominal.
5. 3.3 V nominal.
Table 4 provides the package thermal characteristics for the MPC755. The MPC755 was initially sampled
in a CBGA package, but production units are currently provided in both a CBGA and a PBGA package.
Because of the better long-term device-to-board interconnect reliability of the PBGA package, Motorola
recommends use of a PBGA package except where circumstances dictate use of a CBGA package.
Table 4. Package Thermal Characteristics
Characteristic
Symbol
Value
Rating
PBGA package typical thermal resistance, junction-to-case thermal
resistance
θJC
0.03
°C/W
PBGA package typical thermal resistance, die junction-to-lead thermal
resistance
θJB
θJA
θJA
θJC
12
33
°C/W
°C/W
°C/W
°C/W
PBGA package typical thermal resistance, die junction-to-ambient
resistance (convection only on 2S2P board)
PBGA package typical thermal resistance, die junction-to-ambient
resistance (100 ft/min airflow on 2S2P board)
30
CBGA package typical thermal resistance, junction-to-case thermal
resistance
0.03
8
MPC755 RISC Microprocessor Hardware Specifications
Electrical and Thermal Characteristics
Table 4. Package Thermal Characteristics (Continued)
Characteristic
Symbol
Value
Rating
CBGA package typical thermal resistance, die junction-to-lead thermal
resistance
θJB
3.8
°C/W
CBGA package typical thermal resistance, die junction-to-ambient
resistance (convection only on 2S2P board)
θJA
θJA
17.9
15
°C/W
°C/W
CBGA package typical thermal resistance, die junction-to-ambient
resistance (100 ft/min airflow on 2S2P board)
Note: Refer to Section 1.8.9, “Thermal Management Information,” for more details about thermal management.
The MPC755 incorporates a thermal management assist unit (TAU) composed of a thermal sensor,
digital-to-analog converter, comparator, control logic, and dedicated special-purpose registers (SPRs). See
the MPC750 RISC Microprocessor User’s Manual for more information on the use of this feature.
Specifications for the thermal sensor portion of the TAU are found in Table 5.
Table 5. Thermal Sensor Specifications
At recommended operating conditions (See Table 3)
Characteristic
Min
0
Max
127
—
Unit
°C
Notes
Temperature range
Comparator settling time
Resolution
1
2, 3
3
20
4
µs
—
°C
Accuracy
–12
+12
°C
3
Notes:
1. The temperature is the junction temperature of the die. The thermal assist unit’s raw output does not indicate an
absolute temperature, but must be interpreted by software to derive the absolute junction temperature. For
information about the use and calibration of the TAU, see Motorola Application Note AN1800/D, “Programming
the Thermal Assist Unit in the MPC750 Microprocessor”.
2. The comparator settling time value must be converted into the number of CPU clocks that need to be written into
the THRM3 SPR.
3. Guaranteed by design and characterization.
Table 6 provides the DC electrical characteristics for the MPC755.
Table 6. DC Electrical Specifications
At recommended operating conditions (See Table 3)
Nominal
Characteristic
Bus
Symbol
Min
Max
Unit
Notes
Voltage1
Input high voltage (all inputs except
SYSCLK)
2.5
3.3
2.5
3.3
2.5
3.3
VIH
VIH
1.6
2.0
(L2)OVdd + 0.3
(L2)OVdd + 0.3
0.6
V
V
V
V
V
V
2, 3
2, 3
2
Input low voltage (all inputs except
SYSCLK)
VIL
–0.3
–0.3
1.8
VIL
0.8
SYSCLK input high voltage
KVIH
KVIH
OVdd + 0.3
OVdd + 0.3
2.4
MPC755 RISC Microprocessor Hardware Specifications
9
Electrical and Thermal Characteristics
Table 6. DC Electrical Specifications (Continued)
At recommended operating conditions (See Table 3)
Nominal
Characteristic
Bus
Symbol
Min
Max
Unit
Notes
Voltage1
SYSCLK input low voltage
2.5
KVIL
KVIL
Iin
–0.3
–0.3
—
0.4
0.4
10
V
V
3.3
Input leakage current,
µA
2, 3
Vin = L2OVdd/OVdd
Hi-Z (off-state) leakage current,
Vin = L2OVdd/OVdd
ITSI
—
10
µA
2, 3, 5
Output high voltage, IOH = –6 mA
2.5
3.3
2.5
3.3
VOH
VOH
VOL
VOL
Cin
1.7
2.4
—
—
—
V
V
Output low voltage, IOL = 6 mA
0.45
0.4
5.0
V
—
V
Capacitance, Vin = 0 V, f = 1 MHz
—
pF
3, 4
Notes:
1. Nominal voltages; See Table 3 for recommended operating conditions.
2. For processor bus signals, the reference is OVdd while L2OVdd is the reference for the L2 bus signals.
3. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK) and IEEE 1149.1 boundary scan (JTAG) signals.
4. Capacitance is periodically sampled rather than 100% tested.
5. The leakage is measured for nominal OVdd and Vdd, or both OVdd and Vdd must vary in the same direction (for
example, both OVdd and Vdd vary by either +5% or –5%).
Table 7 provides the power consumption for the MPC755.
Table 7. Power Consumption for MPC755
Processor (CPU) Frequency
Unit
Notes
300 MHz
350 MHz
400 MHz
Full-On Mode
Typical
3.1
4.5
3.6
5.3
4.0
6.0
W
W
1, 3
1, 2
Maximum
Doze Mode
1.8
Nap Mode
Maximum
Maximum
Maximum
Typical
2.0
1.0
2.3
1.0
W
W
1, 2
1, 2
1, 2
1, 3
1.0
Sleep Mode
460
470
470
340
mW
mW
Sleep Mode—PLL and DLL Disabled
340 340
10
MPC755 RISC Microprocessor Hardware Specifications
Electrical and Thermal Characteristics
Table 7. Power Consumption for MPC755
Processor (CPU) Frequency
Unit
Notes
300 MHz
430
350 MHz
400 MHz
430
Maximum
430
mW
1, 2
Notes:
1. These values apply for all valid processor bus and L2 bus ratios. The values do not include I/O Supply Power
(OVdd and L2OVdd) or PLL/DLL supply power (AVdd and L2AVdd). OVdd and L2OVdd power is system
dependent, but is typically <10% of Vdd power. Worst case power consumption for AVdd = 15 mW and L2AVdd
= 15 mW.
2. Maximum power is measured at 105°C and Vdd = 2.0 V while running an entirely cache-resident, contrived
sequence of instructions which keep the execution units maximally busy.
3. Typical power is an average value measured at 65°C and Vdd = 2.0 V in a system executing typical applications
and benchmark sequences.
1.4.2 AC Electrical Characteristics
This section provides the AC electrical characteristics for the MPC755. After fabrication, functional parts
are sorted by maximum processor core frequency as shown in Section 1.4.2.1, “Clock AC Specifications”
and tested for conformance to the AC specifications for that frequency. The processor core frequency is
determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[0:3] signals. Parts are sold
by maximum processor core frequency; see Section 1.10, “Ordering Information”.
1.4.2.1 Clock AC Specifications
Table 8 provides the clock AC timing specifications as defined in Figure 3.
Table 8. Clock AC Timing Specifications
At recommended operating conditions (See Table 3)
Maximum Processor Core Frequency
Characteristic
Symbol
300 MHz
350 MHz
400 MHz
Unit
Notes
Min
Max
300
600
100
40
Min
Max
350
700
100
40
Min
Max
400
800
100
40
Processor frequency
VCO frequency
fcore
fVCO
200
400
25
200
400
25
200
400
25
MHz
MHz
MHz
ns
1
1
1
SYSCLK frequency
SYSCLK cycle time
SYSCLK rise and fall time
fSYSCLK
tSYSCLK
tKR & tKF
10
10
10
—
2.0
1.0
60
—
2.0
1.0
60
—
2.0
1.0
60
ns
2
2
3
t
KR & tKF
tKHKL
—
—
—
ns
SYSCLK duty cycle measured
at OVdd/2
/
40
40
40
%
tSYSCLK
SYSCLK jitter
—
±150
—
±150
—
±150
ps
3, 4
MPC755 RISC Microprocessor Hardware Specifications
11
Electrical and Thermal Characteristics
Table 8. Clock AC Timing Specifications (Continued)
At recommended operating conditions (See Table 3)
Maximum Processor Core Frequency
300 MHz 350 MHz 400 MHz
Characteristic
Symbol
Unit
Notes
Min
Max
Min
Max
Min
Max
Internal PLL relock time
—
100
—
100
—
100
µs
3, 5
Notes:
1. Caution: The SYSCLK frequency and PLL_CFG[0:3] settings must be chosen such that the resulting SYSCLK
(bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or
minimum operating frequencies. Refer to the PLL_CFG[0:3] signal description in Table 16,” for valid
PLL_CFG[0:3] settings
2. Rise and fall times measurements are now specified in terms of slew rates, rather than time to account for
selectable I/O bus interface levels. The minimum slew rate of 1 V/ns is equivalent to a 2 ns maximum rise/fall time
measured at 0.4 V and 2.4 V or a rise/fall time of 1 ns measured at 0.4 V to 1.4 V.
3. Timing is guaranteed by design and characterization.
4. This represents total input jitter—short term and long term combined—and is guaranteed by design.
5. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time
required for PLL lock after a stable Vdd and SYSCLK are reached during the power-on reset sequence. This
specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also
note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the
power-on reset sequence.
Figure 3 provides the SYSCLK input timing diagram.
KV
IH
SYSCLK
VM
VM
VM
KV
IL
tKHKL
tSYSCLK
tKR
tKF
VM = Midpoint Voltage (OV /2)
DD
Figure 3. SYSCLK Input Timing Diagram
1.4.2.2 Processor Bus AC Specifications
Table 9 provides the processor bus AC timing specifications for the MPC755 as defined in Figure 4 and
Figure 6. Timing specifications for the L2 bus are provided in Section 1.4.2.3, “L2 Clock AC Specifications.
12
MPC755 RISC Microprocessor Hardware Specifications
Electrical and Thermal Characteristics
Table 9. Processor Bus Mode Selection AC Timing Specifications1
At recommended operating conditions (See Table 3)
300, 350, 400 MHz
Parameter
Symbols2
Unit
Notes
Min
Max
Mode select input setup to HRESET
HRESET to mode select input hold
Notes:
tMVRH
8
—
tsysclk 3,4,5,6,7
ns 3,4,6,7,8
tMXRH
0
—
1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge
of the input SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to
the midpoint of the signal in question. All output timings assume a purely resistive 50-ohm load (See Figure 5).
Input and output timings are measured at the pin; time-of-flight delays must be added for trace lengths, vias, and
connectors in the system.
2. The symbology used for timing specifications herein follows the pattern of t(signal)(state)(reference)(state) for inputs
and t(reference)(state)(signal)(state) for outputs. For example, tIVKH symbolizes the time input signals (I) reach the valid
state (V) relative to the SYSCLK reference (K) going to the high(H) state or input setup time. And tKHOV
symbolizes the time from SYSCLK(K) going high(H) until outputs (O) are valid (V) or output valid time. Input hold
time can be read as the time that the input signal (I) went invalid (X) with respect to the rising clock edge
(KH)—note the position of the reference and its state for inputs—and output hold time can be read as the time
from the rising edge (KH) until the output went invalid (OX).
3. The setup and hold time is with respect to the rising edge of HRESET (see Figure 4).
4. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a
minimum of 255 bus clocks after the PLL re-lock time during the power-on reset sequence.
5. tsysclk is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be
multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in
question.
6. Mode select signals are BVSEL, L2VSEL, PLL_CFG[0:3], and TLBISYNC
7. Guaranteed by design and characterization.
8. Bus mode select pins must remain stable during operation. Changing the logic states of BVSEL or L2VSEL during
operation will cause the bus mode voltage selection to change. Changing the logic states of the PLL_CFG pins
during operation will cause the PLL division ratio selection to change. Both of these conditions are considered
outside the specification and are not supported. Once HRESET is negated the states of the bus mode selection
pins must remain stable.
Figure 4 provides the mode select input timing diagram for the MPC755.
VM
HRESET
t
MVRH
t
MXRH
MODE SIGNALS
VM = Midpoint Voltage (OV /2)
DD
Figure 4. Mode Input Timing Diagram
Figure 5 provides the AC test load for the MPC755.
MPC755 RISC Microprocessor Hardware Specifications
13
Electrical and Thermal Characteristics
Z0 = 50Ω
OUTPUT
OVdd/2
R
= 50Ω
L
Figure 5. AC Test Load
Table 10. Processor Bus AC Timing Specifications 1
At recommended operating conditions (See Table 3)
300, 350, 400 MHz
Parameter
Symbols
Unit Notes
Min
2.5
0.6
0.2
—
Max
—
Setup Times: All Inputs
tIVKH
tIXKH
ns
ns
ns
ns
ns
Input Hold Times: TLBISYNC, MCP, SMI
Input Hold Times: All Inputs, except TLBISYNC, MCP, SMI
Valid Times: All Outputs
—
tIXKH
—
tKHOV
tKHOX
tKHOE
tKHOZ
4.1
—
Output Hold Times: All Outputs
SYSCLK to Output Enable
1.0
0.5
—
—
ns
ns
2
2
SYSCLK to Output High Impedance (all except ABB,
ARTRY, DBB)
6.0
SYSCLK to ABB, DBB High Impedance After Precharge
Maximum Delay to ARTRY Precharge
tKHABPZ
tKHARP
—
—
—
1.0
1
tsysclk 2, 3, 4
tsysclk 2, 3, 5
tsysclk 2, 3, 5
SYSCLK to ARTRY High Impedance After Precharge
tKHARPZ
2
Notes:
1. Revisions prior to Rev 2.8 (Rev E) were limited in performance and did not conform to this specification.
Contact your local Motorola sales office for more information.
2. Guaranteed by design and characterization.
3. tsysclk is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be
multiplied by the period of SYSCLK to compute the actual time duration (in ns) of the parameter in question.
4. Per the 60x bus protocol, TS, ABB and DBB are driven only by the currently active bus master. They are asserted
low then precharged high before returning to high-Z as shown in Figure 6. The nominal precharge width for TS,
ABB or DBB is 0.5 x tSYSCLK, i.e. less than the minimum tSYSCLK period, to ensure that another master asserting
TS, ABB, or DBB on the following clock will not contend with the precharge. Output valid and output hold timing is
tested for the signal asserted. Output valid time is tested for precharge.The high-Z behavior is guaranteed by
design.
5. Per the 60x bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately
following AACK. Bus contention is not an issue since any master asserting ARTRY will be driving it low. Any
master asserting it low in the first clock following AACK will then go to high-Z for one clock before precharging it
high during the second cycle after the assertion of AACK. The nominal precharge width for ARTRY is 1.0 tsysclk
;
i.e., it should be high-Z as shown in Figure 6 before the first opportunity for another master to assert ARTRY.
Output valid and output hold timing is tested for the signal asserted. Output valid time is tested for precharge.The
high-Z and precharge behavior is guaranteed by design.
Figure 6 provides the input/output timing diagram for the MPC755.
14
MPC755 RISC Microprocessor Hardware Specifications
Electrical and Thermal Characteristics
SYSCLK
VM
VM
VM
tIXKH
t
IVKH
ALL INPUTS
tKHOE
tKHOV
tKHOZ
tKHOX
ALL OUTPUTS
(Except TS, ABB,
ARTRY, DBB)
tKHABPZ
tKHOV
tKHOZ
tKHOX
tKHOV
TS,ABB,DBB
tKHARPZ
tKHOV
tKHOV
tKHARP
tKHOX
ARTRY
VM = Midpoint Voltage (OV /2 or V /2)
DD
in
Figure 6. Input/Output Timing Diagram
1.4.2.3 L2 Clock AC Specifications
The L2CLK frequency is programmed by the L2 Configuration Register (L2CR[4-6]) core-to-L2 divisor
ratio. See Table 17 for example core and L2 frequencies at various divisors. Table 11 provides the potential
range of L2CLK output AC timing specifications as defined in Figure 7.
The minimum L2CLK frequency of Table 11 is specified by the maximum delay of the internal DLL. The
variable-tap DLL introduces up to a full clock period delay in the L2CLKOUTA, L2CLKOUTB, and
L2SYNC_OUT signals so that the returning L2SYNC_IN signal is phase aligned with the next core clock
(divided by the L2 divisor ratio). Do not choose a core-to-L2 divisor which results in an L2 frequency below
this minimum, or the L2CLKOUT signals provided for SRAM clocking will not be phase aligned with the
MPC755 core clock at the SRAMs.
The maximum L2CLK frequency shown in Table 11 is the core frequency divided by one. Very few L2
SRAM designs will be able to operate in this mode. Most designs will select a greater core-to-L2 divisor to
provide a longer L2CLK period for read and write access to the L2 SRAMs. The maximum L2CLK
frequency for any application of the MPC755 will be a function of the AC timings of the MPC755, the AC
timings for the SRAM, bus loading, and printed circuit board trace length. The current AC timing of the
MPC755 supports up to 200 MHz with typical, similarly-rated SRAM parts, provided careful design
practices are observed. Clock trace lengths must be matched and all trace lengths should be as short as
possible. Higher frequencies can be achieved by using better performing SRAM. Note: Revisions of the
MPC755 prior to Rev 2.8 (Rev E) were limited in performance, and were typically limited to 175 MHz with
similarly-rated SRAM. For more information, contact your local Motorola sales office.
Motorola is similarly limited by system constraints and cannot perform tests of the L2 interface on a
MPC755 RISC Microprocessor Hardware Specifications
15
Electrical and Thermal Characteristics
socketed part on a functional tester at the maximum frequencies of Table 11. Therefore functional operation
and AC timing information are tested at core-to-L2 divisors of 2 or greater. Functionality of core-to-L2
divisors of 1 or 1.5 is verified at less than maximum rated frequencies.
L2 input and output signals are latched or enabled respectively by the internal L2CLK (which is SYSCLK
multiplied up to the core frequency and divided down to the L2CLK frequency). In other words, the AC
timings of Table 12 and Table 13 are entirely independent of L2SYNC_IN. In a closed loop system, where
L2SYNC_IN is driven through the board trace by L2SYNC_OUT, L2SYNC_IN only controls the output
phase of L2CLKOUTA and L2CLKOUTB which are used to latch or enable data at the SRAMs. However,
since in a closed loop system L2SYNC_IN is held in phase alignment with the internal L2CLK, the signals
of Table 12 and Table 13 are referenced to this signal rather than the not-externally-visible internal L2CLK.
During manufacturing test, these times are actually measured relative to SYSCLK.
The L2SYNC_OUT signal is intended to be routed halfway out to the SRAMs and then returned to the
L2SYNC_IN input of the MPC755 to synchronize L2CLKOUT at the SRAM with the processor’s internal
clock. L2CLKOUT at the SRAM can be offset forward or backward in time by shortening or lengthening
the routing of L2SYNC_OUT to L2SYNC_IN. See Motorola Application Note AN179/D “PowerPC
Backside L2 Timing Analysis for the PCB Design Engineer.”
The L2CLKOUTA and L2CLKOUTB signals should not have more than two loads.
Table 11. L2CLK Output AC Timing Specification
At recommended operating conditions (See Table 3)
300, 350, 400 MHz
Parameter
Symbol
Unit
Notes
Min
80
Max
400
L2CLK Frequency
L2CLK Cycle Time
L2CLK Duty Cycle
fL2CLK
tL2CLK
tCHCL/tL2CLK
MHz
ns
1, 4
2.5
12.5
50
%
2, 7
3, 7
5, 7
6, 7
6, 7
Internal DLL-Relock Time
DLL Capture Window
L2CLKOUT Output-to-Output Skew
L2CLKOUT Output Jitter
Notes:
640
—
10
L2CLK
ns
0
tL2CSKW
50
ps
±150
ps
1. L2CLK outputs are L2CLK_OUTA, L2CLK_OUTB, L2CLK_OUT and L2SYNC_OUT pins. The L2CLK frequency to
core frequency settings must be chosen such that the resulting L2CLK frequency and core frequency do not
exceed their respective maximum or minimum operating frequencies. The maximum L2LCK frequency will be
system dependent. L2CLK_OUTA and L2CLK_OUTB must have equal loading.
2. The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage.
3. The DLL re-lock time is specified in terms of L2CLKs. The number in the table must be multiplied by the period of
L2CLK to compute the actual time duration in nanoseconds. Re-lock timing is guaranteed by design and
characterization.
4. The L2CR[L2SL] bit should be set for L2CLK frequencies less than 110 MHz. This adds more delay to each tap of
the DLL.
5. Allowable skew between L2SYNC_OUT and L2SYNC_IN.
6. This output jitter number represents the maximum delay of one tap forward or one tap back from the current DLL
tap as the phase comparator seeks to minimize the phase difference between L2SYNC_IN and the internal
L2CLK. This number must be comprehended in the L2 timing analysis. The input jitter on SYSCLK affects
L2CLKOUT and the L2 address/data/control signals equally and, therefore, is already comprehended in the AC
timing and does not have to be considered in the L2 timing analysis.
7. Guaranteed by design and characterization.
16
MPC755 RISC Microprocessor Hardware Specifications
Electrical and Thermal Characteristics
The L2CLK_OUT timing diagram is shown in Figure 7.
L2 Single-Ended Clock Mode
tL2CR
tL2CF
tL2CLK
tCHCL
L2CLK_OUTA
L2CLK_OUTB
VM
VM
VM
VM
VM
VM
VM
VM
VM
VM
VM
tL2CSKW
L2SYNC_OUT
L2 Differential Clock Mode
tL2CLK
tCHCL
L2CLK_OUTB
L2CLK_OUTA
VM
VM
VM
VM
VM
VM
L2SYNC_OUT
VM = Midpoint Voltage (L2OVdd/2)
Figure 7. L2CLK_OUT Output Timing Diagram
1.4.2.4 L2 Bus AC Specifications
Table 12 provides the L2 bus interface AC timing specifications for the MPC755 as defined in Figure 8 and
Figure 9 for the loading conditions described in Figure 10.
Table 12. L2 Bus Interface AC Timing Specifications
At recommended operating conditions (See Table 3)
300 MHz
350 MHz
400 MHz
Parameter
Symbol
tL2CR
Unit
Notes
Min
Max
Min
Max
Min
Max
L2SYNC_IN rise and Fall Time
&
—
1.0
—
1.0
—
1.0
ns
1
tL2CF
Setup Times: Data and Parity
tDVL2CH
tDXL2CH
tL2CHOV
1.2
0
—
—
1.2
0
—
—
1.2
0
—
—
ns
ns
ns
2
2
Input Hold Times: Data and Parity
Valid Times:
3, 4
—
—
—
—
3.1
3.2
3.3
3.7
—
—
—
—
3.1
3.2
3.3
3.7
—
—
—
—
3.1
3.2
3.3
3.7
All Outputs when L2CR[14-15] = 00
All Outputs when L2CR[14-15] = 01
All Outputs when L2CR[14-15] = 10
All Outputs when L2CR[14-15] = 11
MPC755 RISC Microprocessor Hardware Specifications
17
Electrical and Thermal Characteristics
Table 12. L2 Bus Interface AC Timing Specifications (Continued)
At recommended operating conditions (See Table 3)
300 MHz
350 MHz
400 MHz
Parameter
Output Hold Times
Symbol
Unit
Notes
Min
Max
Min
Max
Min
Max
tL2CHOX
ns
3
0.5
0.7
0.9
1.1
—
—
—
—
0.5
0.7
0.9
1.1
—
—
—
—
0.5
0.7
0.9
1.1
—
—
—
—
All outputs when L2CR[14-15] = 00
All outputs when L2CR[14-15] = 01
All outputs when L2CR[14-15] = 10
All outputs when L2CR[14-15] = 11
L2SYNC_IN to High Impedance:
All outputs when L2CR[14-15] = 00
All outputs when L2CR[14-15] = 01
All outputs when L2CR[14-15] = 10
All outputs when L2CR[14-15] = 11
tL2CHOZ
ns
3, 5
—
—
—
—
2.4
2.6
2.8
3.0
—
—
—
—
2.4
2.6
2.8
3.0
—
—
—
—
2.4
2.6
2.8
3.0
Notes:
1. Rise and fall times for the L2SYNC_IN input are measured from 20% to 80% of L2OVdd.
2. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the
rising edge of the input L2SYNC_IN (see Figure 8). Input timings are measured at the pins.
3. All output specifications are measured from the midpoint voltage of the rising edge of L2SYNC_IN to the midpoint
of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive
50-ohm load (See Figure 10).
4. The outputs are valid for both single-ended and differential L2CLK modes. For pipelined registered synchronous
BurstRAMs, L2CR[14–15] = 01 or 10 is recommended. For pipelined late write synchronous BurstRAMs,
L2CR[14–15] = 11 is recommended.
5. Guaranteed by design and characterization.
6. Revisions prior to Rev 2.8 (Rev E) were limited in performance.and did not conform to this specification. Contact
your local Motorola sales office for more information.
Figure 8 shows the L2 bus input timing diagrams for the MPC755.
tL2CR
tL2CF
L2SYNC_IN
VM
tDVL2CH
tDXL2CH
L2 DATA AND DATA
PARITY INPUTS
VM = Midpoint Voltage (L2OV /2)
DD
Figure 8. L2 Bus Input Timing Diagrams
Figure 9 shows the L2 bus output timing diagrams for the MPC755.
18
MPC755 RISC Microprocessor Hardware Specifications
Electrical and Thermal Characteristics
L2SYNC_IN
ALL OUTPUTS
L2DATA BUS
VM
VM
tL2CHOV
tL2CHOX
tL2CHOZ
VM = Midpoint Voltage (L2OV /2)
DD
Figure 9. L2 Bus Output Timing Diagrams
Figure 10 provides the AC test load for L2 interface of the MPC755.
Z0 = 50Ω
OUTPUT
L2OVdd/2
RL = 50Ω
Figure 10. AC Test Load for the L2 Interface
1.4.2.5 IEEE 1149.1 AC Timing Specifications
Table 13 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 12, Figure 13,
Figure 14, and Figure 15.
Table 13. JTAG AC Timing Specifications (Independent of SYSCLK)1
At recommended operating conditions (See Table 3)
Parameter
TCK Frequency of Operation
Symbol
fTCLK
Min
0
Max
16
—
Unit
MHz
ns
Notes
TCK Cycle Time
tTCLK
62.5
31
0
TCK Clock Pulse Width Measured at 1.4 V
TCK Rise and Fall Times
TRST Assert Time
tJHJL
—
ns
tJR & tJF
tTRST
2
ns
25
—
ns
2
3
Input Setup Times:
ns
tDVJH
tIVJH
4
0
—
—
Boundary-scan data
TMS, TDI
Input Hold Times:
ns
tDXJH
tIXJH
15
12
—
—
3
Boundary-scan data
TMS, TDI
MPC755 RISC Microprocessor Hardware Specifications
19
Electrical and Thermal Characteristics
Table 13. JTAG AC Timing Specifications (Independent of SYSCLK)1 (Continued)
At recommended operating conditions (See Table 3)
Parameter
Symbol
Min
Max
Unit
Notes
Valid Times:
ns
tJLDV
tJLOV
—
—
4
4
4
Boundary-scan data
TDO
Output Hold Times:
ns
ns
tJLDH
tJLOH
25
12
—
—
4
Boundary-scan data
TDO
TCK to Output High Impedance:
tJLDZ
tJLOZ
3
3
19
9
4,5
Boundary-scan data
TDO
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal
in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-ohm load
(See Figure 11). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. TRST is an asynchronous level sensitive signal which must be asserted for this minimum time to be recognized.
3. Non-JTAG signal input timing with respect to TCK.
4. Non-JTAG signal output timing with respect to TCK.
5. Guaranteed by design and characterization.
Figure 11 provides the AC test load for TDO and the boundary-scan outputs of the MPC755.
Z0 = 50Ω
OVdd/2
OUTPUT
RL = 50Ω
Figure 11. AC Test Load for the JTAG Interface
Figure 12 provides the JTAG clock input timing diagram.
TCLK
VM
tJHJL
VM
VM
tJR
tJF
tTCLK
VM = Midpoint Voltage (OV /2)
DD
Figure 12. JTAG Clock Input Timing Diagram
Figure 13 provides the TRST timing diagram.
20
MPC755 RISC Microprocessor Hardware Specifications
Electrical and Thermal Characteristics
VM
VM
TRST
tTRST
VM = Midpoint Voltage (OV /2)
DD
Figure 13. TRST Timing Diagram
Figure 14 provides the boundary-scan timing diagram.
VM
VM
TCK
tDVJH
tDXJH
INPUT
DATA VALID
BOUNDARY
DATA INPUTS
tJLDV
tJLDH
OUTPUT
BOUNDARY
DATA OUTPUTS
DATA
VALID
tJLDZ
BOUNDARY
DATA OUTPUTS
OUTPUT DATA VALID
VM = Midpoint Voltage (OV /2)
DD
Figure 14. Boundary-Scan Timing Diagram
Figure 15 provides the test access port timing diagram.
VM
TCK
TDI, TMS
TDO
VM
tIVJH
tIXJH
INPUT
DATA VALID
tJLOV
tJLOH
OUTPUT
DATA
VALID
tJLOZ
OUTPUT DATA VALID
TDO
VM = Midpoint Voltage (OV /2)
DD
Figure 15. Test Access Port Timing Diagram
MPC755 RISC Microprocessor Hardware Specifications
21
Pin Assignments
1.5 Pin Assignments
Figure 16 (in part A) shows the pinout of the MPC745, 255 PBGA package as viewed from the top surface.
Part B shows the side profile of the PBGA package to indicate the direction of the top surface view.
Part A
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Not to Scale
Part B
View
Substrate Assembly
Encapsulant
Die
Figure 16. Pinout of the MPC745, 255 PBGA Package as Viewed from the Top Surface
22
MPC755 RISC Microprocessor Hardware Specifications
Pin Assignments
Figure 17 (in part A) shows the pinout of the MPC755, 360 PBGA and 360 CBGA packages as viewed from
the top surface. Part B shows the side profile of the PBGA and CBGA package to indicate the direction of
the top surface view.
Part A
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Not to Scale
Part B
View
Substrate Assembly
Encapsulant
Die
Figure 17. Pinout of the MPC755, 360 PBGA and CBGA Packages as Viewed from the Top Surface
MPC755 RISC Microprocessor Hardware Specifications
23
Pinout Listings
1.6 Pinout Listings
Table 14 provides the pinout listing for the MPC745, 255 PBGA package.
Table 14. Pinout Listing for the MPC745, 255 PBGA Package
Signal Name
A[0:31]
Pin Number
Active
High
I/O
I/F Voltage1
Notes
C16, E4, D13, F2, D14, G1, D15, E2, D16,
D4, E13, G2, E15, H1, E16, H2, F13, J1, F14,
J2, F15, H3, F16, F4, G13, K1, G15, K2, H16,
M1, J15, P1
I/O
OVdd
AACK
L2
Low
Low
High
Low
—
Input
I/O
OVdd
OVdd
OVdd
OVdd
2.0 V
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
ABB
K4
AP[0:3]
ARTRY
AVDD
C1, B4, B3, B2
I/O
J4
I/O
A10
L1
—
BG
Low
Low
High
Low
Low
Low
—
Input
Output
Input
Output
Input
Output
Output
I/O
BR
B6
B1
E1
D8
A6
D7
J14
N1
H15
G4
BVSEL
CI
3, 4, 5
CKSTP_IN
CKSTP_OUT
CLK_OUT
DBB
Low
Low
Low
Low
High
DBG
Input
Input
Input
I/O
DBDIS
DBWO
DH[0:31]
P14, T16, R15, T15, R13, R12, P11, N11,
R11, T12, T11, R10, P9, N9, T10, R9, T9, P8,
N8, R8, T8, N7, R7, T7, P6, N6, R6, T6, R5,
N5, T5, T4
DL[0:31]
K13, K15, K16, L16, L15, L13, L14, M16,
M15, M13, N16, N15, N13, N14, P16, P15,
R16, R14, T14, N10, P13, N12, T13, P3, N3,
N4, R3, T1, T2, P4, T3, R4
High
I/O
OVdd
DP[0:7]
DRTRY
GBL
M2, L3, N2, L4, R1, P2, M4, R2
High
Low
Low
I/O
OVdd
OVdd
OVdd
G16
F1
Input
I/O
24
MPC755 RISC Microprocessor Hardware Specifications
Pinout Listings
Table 14. Pinout Listing for the MPC745, 255 PBGA Package (Continued)
Signal Name
GND
Pin Number
Active
I/O
I/F Voltage1
Notes
C5, C12, E3, E6, E8, E9, E11, E14, F5, F7,
F10, F12, G6, G8, G9, G11, H5, H7, H10,
H12, J5, J7, J10, J12, K6, K8, K9, K11, L5,
L7, L10, L12, M3, M6, M8, M9, M11, M14, P5,
P12
—
—
GND
HRESET
A7
Low
Low
High
High
Low
Low
—
Input
Input
Input
Input
Input
Input
—
OVdd
OVdd
—
INT
B15
D11
D12
B10
C13
L1_TSTCLK
L2_TSTCLK
LSSD_MODE
MCP
2
2
2
—
—
OVdd
—
NC (No–Connect)
B7, B8, C3, C6, C8, D5, D6, H4, J16, A4, A5,
A2, A3, B5
OVDD
C7, E5, E7, E10, E12, G3, G5, G12, G14, K3,
K5, K12, K14, M5, M7, M10, M12, P7, P10
—
—
2.5 V/3.3 V
PLL_CFG[0:3]
QACK
QREQ
RSRV
SMI
A8, B9, A9, D9
High
Low
Low
Low
Low
Low
—
Input
Input
Output
Output
Input
Input
Input
Input
Input
I/O
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
D3
J3
D1
A16
B14
C9
SRESET
SYSCLK
TA
H14
C2
Low
High
Low
High
High
High
Low
Low
High
Low
Low
High
TBEN
TBST
A14
C11
A11
A12
H13
C4
TCK
Input
Input
Output
Input
Input
Input
Input
I/O
TDI
5
TDO
TEA
TLBISYNC
TMS
B11
C10
J13
5
5
TRST
TS
TSIZ[0:2]
A13, D10, B12
Output
MPC755 RISC Microprocessor Hardware Specifications
25
Pinout Listings
Table 14. Pinout Listing for the MPC745, 255 PBGA Package (Continued)
Signal Name
TT[0:4]
Pin Number
B13, A15, B16, C14, C15
Active
High
I/O
I/F Voltage1
OVdd
Notes
I/O
WT
D2
Low
Output
OVdd
VDD
F6, F8, F9, F11, G7, G10, H6, H8, H9, H11,
J6, J8, J9, J11, K7, K10, L6, L8, L9, L11
—
—
2.0 V
VOLTDET
F3
High
Output
—
6
Notes:
1. OVdd supplies power to the processor bus, JTAG, and all control signals and Vdd supplies power to the processor
core and the PLL (after filtering to become AVDD). These columns serve as a reference for the nominal voltage
supported on a given signal as selected by the BVSEL pin configuration of Table 2 and the voltage supplied. For
actual recommended value of Vin or supply voltages see Table 3.
2. These are test signals for factory use only and must be pulled up to OVdd for normal machine operation.
3. This pin must be pulled up to OVdd for proper operation of the processor interface. To allow for future I/O voltage
changes, provide the option to connect BVSEL independently to either OVDD or to GND.
4. Uses 1 of 15 existing no-connects in MPC740 255 BGA package.
5. Internal pull up on die.
6. Internally tied to GND in the MPC745 255 BGA package to indicate to the power supply that a low-voltage
processor is present. This signal is not a power supply input.
Caution: This differs from the MPC755 360 BGA package.
Table 15 provides the pinout listing for the MPC755, 360 PBGA and CBGA packages.
Table 15. Pinout Listing for the MPC755, 360 BGA Package
I/F Voltage1
Signal Name
A[0:31]
Pin Number
Active
High
I/O
Notes
A13, D2, H11, C1, B13, F2, C13, E5, D13,
G7, F12, G3, G6, H2, E2, L3, G5, L4, G4, J4,
H7, E1, G2, F3, J7, M3, H3, J2, J6, K3, K2,
L2
I/O
OVdd
AACK
N3
Low
Low
High
Low
—
Input
I/O
OVdd
OVdd
OVdd
OVdd
2.0 V
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
ABB
L7
AP[0:3]
ARTRY
AVDD
C4, C5, C6, C7
I/O
L6
I/O
A8
H1
E7
W1
C2
B8
D7
E3
—
BG
Low
Low
High
Low
Low
Low
—
Input
Output
Input
Output
Input
Output
Output
BR
BVSEL
CI
3, 5, 6
CKSTP_IN
CKSTP_OUT
CLK_OUT
26
MPC755 RISC Microprocessor Hardware Specifications
Pinout Listings
Table 15. Pinout Listing for the MPC755, 360 BGA Package (Continued)
I/F Voltage1
Signal Name
Pin Number
Active
I/O
Notes
DBB
K5
G1
K1
D1
Low
I/O
OVdd
OVdd
OVdd
OVdd
OVdd
DBDIS
DBG
Low
Low
Low
Input
Input
Input
I/O
DBWO
DH[0:31]
W12, W11, V11, T9, W10, U9, U10, M11, M9, High
P8, W7, P9, W9, R10, W6, V7, V6, U8, V9,
T7, U7, R7, U6, W5, U5, W4, P7, V5, V4, W3,
U4, R5
DL[0:31]
M6, P3, N4, N5, R3, M7, T2, N6, U2, N7, P11, High
V13, U12, P12, T13, W13, U13, V10, W8,
T11, U11, V12, V8, T1, P1, V1, U1, N1, R2,
V3, U3, W2
I/O
OVdd
DP[0:7]
DRTRY
GBL
L1, P2, M2, V2, M1, N2, T3, R1
High
Low
Low
—
I/O
OVdd
OVdd
OVdd
GND
H6
B1
Input
I/O
GND
D10, D14, D16, D4, D6, E12, E8, F4, F6, F10,
F14, F16, G9, G11, H5, H8, H10, H12, H15,
J9, J11, K4, K6, K8, K10, K12, K14, K16, L9,
L11, M5, M8, M10, M12, M15, N9, N11, P4,
P6, P10, P14, P16, R8, R12, T4, T6, T10,
T14, T16
—
HRESET
INT
B6
Low
Low
High
Input
Input
Input
Output
OVdd
OVdd
—
C11
F8
L1_TSTCLK
L2ADDR[0:16]
2
L17, L18, L19, M19, K18, K17, K15, J19, J18, High
J17, J16, H18, H17, J14, J13, H19, G18
L2OVdd
L2AVDD
L13
P17
N15
L16
—
—
2.0 V
L2CE
Low
—
Output
Output
Output
I/O
L2OVdd
L2OVdd
L2OVdd
L2OVdd
L2CLKOUTA
L2CLKOUTB
L2DATA[0:63]
—
U14, R13, W14, W15, V15, U15, W16, V16, High
W17, V17, U17, W18, V18, U18, V19, U19,
T18, T17, R19, R18, R17, R15, P19, P18,
P13, N14, N13, N19, N17, M17, M13, M18,
H13, G19, G16, G15, G14, G13, F19, F18,
F13, E19, E18, E17, E15, D19, D18, D17,
C18, C17, B19, B18, B17, A18, A17, A16,
B16, C16, A14, A15, C15, B14, C14, E13
L2DP[0:7]
V14, U16, T19, N18, H14, F17, C19, B15
High
I/O
L2OVdd
MPC755 RISC Microprocessor Hardware Specifications
27
Pinout Listings
Table 15. Pinout Listing for the MPC755, 360 BGA Package (Continued)
I/F Voltage1
Signal Name
L2OVDD
Pin Number
Active
I/O
Notes
D15, E14, E16, H16, J15, L15, M16, P15,
R14, R16, T15, F15
—
—
L2OVdd
L2SYNC_IN
L2SYNC_OUT
L2_TSTCLK
L2VSEL
L14
M14
F7
—
Input
Output
Input
Input
L2OVdd
L2OVdd
—
—
High
High
2
A19
L2OVdd
1, 5, 6,
7
L2WE
N16
Low
High
Low
Low
—
Output
Output
Input
Input
—
L2OVdd
L2OVdd
—
L2ZZ
G17
LSSD_MODE
MCP
F9
2
B11
OVdd
—
NC (No-Connect)
OVDD
B3, B4, B5, W19, K9, K114, K194
D5, D8, D12, E4, E6, E9, E11, F5, H4, J5, L5,
M4, P5, R4, R6, R9, R11, T5, T8, T12
—
—
OVdd
PLL_CFG[0:3]
QACK
QREQ
RSRV
SMI
A4, A5, A6, A7
High
Low
Low
Low
Low
Low
—
Input
Input
Output
Output
Input
Input
Input
Input
Input
I/O
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
B2
J3
D3
A12
E10
H9
F1
SRESET
SYSCLK
TA
Low
High
Low
High
High
High
Low
Low
High
Low
Low
TBEN
TBST
TCK
A2
A11
B10
B7
Input
Input
Output
Input
Input
Input
Input
I/O
TDI
6
TDO
D9
J1
TEA
TLBISYNC
TMS
A3
C8
A10
K7
6
6
TRST
TS
28
MPC755 RISC Microprocessor Hardware Specifications
Package Description
Table 15. Pinout Listing for the MPC755, 360 BGA Package (Continued)
I/F Voltage1
Signal Name
TSIZ[0:2]
Pin Number
Active
High
I/O
Notes
A9, B9, C9
Output
I/O
OVdd
OVdd
OVdd
2.0 V
TT[0:4]
WT
C10, D11, B12, C12, F11
C3
High
Low
—
Output
—
VDD
G8, G10, G12, J8, J10, J12, L8, L10, L12, N8,
N10, N12
VOLTDET
K13
High
Output
L2OVdd
8
Notes:
1. OVdd supplies power to the processor bus, JTAG, and all control signals except the L2 cache controls (L2CE,
L2WE, and L2ZZ); L2OVDD supplies power to the L2 cache interface (L2ADDR[0:16], L2DATA[0-63], L2DP[0:7]
and L2SYNC_OUT) and the L2 control signals; and Vdd supplies power to the processor core and the PLL and
DLL (after filtering to become AVDD and L2AVDD respectively). These columns serve as a reference for the
nominal voltage supported on a given signal as selected by the BVSEL/L2VSEL pin configurations of Table 2 and
the voltage supplied. For actual recommended value of Vin or supply voltages see Table 3.
2. These are test signals for factory use only and must be pulled up to OVdd for normal machine operation.
3. This pin must be pulled up to OVdd for proper operation of the processor interface. To allow for future I/O voltage
changes, provide the option to connect BVSEL independently to either OVDD or to GND.
4. These pins are reserved for potential future use as additional L2 address pins.
5. Uses one of nine existing no-connects in MPC750 360 BGA package.
6. Internal pull up on die.
7. This pin must be pulled up to L2OVdd for proper operation of the processor interface. To allow for future I/O
voltage changes, provide the option to connect L2VSEL independently to either L2OVDD or to GND.
8. Internally tied to L2OVDD in the MPC755 360 BGA package to indicate the power present at the L2 cache
interface. This signal is not a power supply input.
Caution: This differs from the MPC745 255 BGA package.
1.7 Package Description
The following sections provide the package parameters and mechanical dimensions for the MPC745, 255
PBGA package, as well as the MPC755 360 CBGA and PBGA packages. While both the MPC755 plastic
and the ceramic packages are described here, both packages are not guaranteed to be available at the same
time. All new designs should allow for either ceramic or plastic BGA packages for this device. For more
information on designing a common footprint for both plastic and ceramic package types, see the document
“Motorola Flip-Chip Plastic Ball Grid Array Presentation”, available on the web at
http://www.mot.com/SPS/PowerPC/teksupport/teklibrary. The MPC755 was initially sampled in a CBGA
package, but production units are currently provided in both a CBGA and a PBGA package. Because of the
better long-term device-to-board interconnect reliability of the PBGA package, Motorola recommends use
of a PBGA package except where circumstances dictate use of a CBGA package.
1.7.1 Package Parameters for the MPC745 PBGA
The package parameters are as provided in the following list. The package type is 21 x 21 mm, 255-lead
plastic ball grid array (PBGA).
Package outline
Interconnects
21 x 21 mm
255 (16 x 16 ball array – 1)
MPC755 RISC Microprocessor Hardware Specifications
29
Package Description
Pitch
1.27 mm (50 mil)
2.25 mm
Minimum module height
Maximum module height 2.80 mm
Ball diameter (typical)
0.75 mm (29.5 mil)
1.7.2 Mechanical Dimensions of the MPC745 PBGA
Table 18 provides the mechanical dimensions and bottom surface nomenclature of the MPC745, 255 PBGA
package.
0.2
D
A
A1 CORNER
C
NOTES:
0.2 C
1. DIMENSIONING AND TOLERANCING
PER ASME Y14.5M, 1994.
E
2. DIMENSIONS IN MILLIMETERS.
3. TOP SIDE A1 CORNER INDEX IS A
METALIZED FEATURE WITH VARIOUS
SHAPES. BOTTOM SIDE A1 CORNER IS
DESIGNATED WITH A BALL MISSING
FROM THE ARRAY.
2X
0.2
4. CAPACITOR PADS MAY BE
UNPOPULATED.
B
Table 1
1
2
3
4
5
6
7
8
9 10 111213141516
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
Millimeters
DIM
A
Min
2.25
0.50
1.00
0.60
Max
2.80
0.70
1.20
0.90
M
A1
A2
b
A2
A1
D
21.00 BSC
A
E
21.00 BSC
1.27 BSC
e
255X
b
e
0.3 C A B
C
0.15
Figure 18. Mechanical Dimensions and Bottom Surface Nomenclature of the MPC745 PBGA
30
MPC755 RISC Microprocessor Hardware Specifications
Package Description
1.7.3 Package Parameters for the MPC755 CBGA
The package parameters are as provided in the following list. The package type is 25 x 25 mm, 360-lead
ceramic ball grid array (CBGA).
Package outline
Interconnects
25 x 25 mm
360 (19 x 19 ball array – 1)
1.27 mm (50 mil)
2.65 mm
Pitch
Minimum module height
Maximum module height 3.20 mm
Ball diameter
0.89 mm (35 mil)
1.7.4 Mechanical Dimensions of the MPC755 CBGA
Figure 19 provides the mechanical dimensions and bottom surface nomenclature of the MPC755, 360
CBGA package.
2X
0.2
D
A
A1 CORNER
C
0.2 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
E
2. DIMENSIONS IN MILLIMETERS.
3. TOP SIDE A1 CORNER INDEX IS A
METALIZED FEATURE WITH VARIOUS
SHAPES. BOTTOM SIDE A1 CORNER IS
DESIGNATED WITH A BALL MISSING
FROM THE ARRAY.
2X
0.2
1
2
3
4
5
6
7
8
9 10 111213141516 171819
B
W
V
U
Millimeters
DIM
A
Min
2.65
0.79
1.10
0.82
Max
3.20
0.99
1.30
0.93
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
M
A1
A2
b
D
25.00 BSC
A2
A1
E
25.00 BSC
1.27 BSC
A
e
e
0.3 C A B
360X
b
C
0.15
Figure 19. Mechanical Dimensions and Bottom Surface Nomenclature of the MPC755 CBGA
MPC755 RISC Microprocessor Hardware Specifications
31
Package Description
1.7.5 Package Parameters for the MPC755 PBGA
The package parameters are as provided in the following list. The package type is 25 x 25 mm, 360-lead
plastic ball grid array (PBGA).
Package outline
Interconnects
25 x 25 mm
360 (19 x 19 ball array – 1)
1.27 mm (50 mil)
2.22 mm
Pitch
Minimum module height
Maximum module height 2.77 mm
Ball diameter
0.75 mm (29.5 mil)
1.7.6 Mechanical Dimensions of the MPC755
Figure 19 provides the mechanical dimensions and bottom surface nomenclature of the MPC755, 360
PBGA package.
2X
0.2
D
A
A1 CORNER
C
0.2 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. TOP SIDE A1 CORNER INDEX IS A
METALIZED FEATURE WITH VARIOUS
SHAPES. BOTTOM SIDE A1 CORNER IS
DESIGNATED WITH A BALL MISSING
FROM THE ARRAY.
E
2X
0.2
Millimeters
B
1
2
3
4
5
6
7
8
9 10 111213141516 171819
DIM
A
Min
2.22
0.50
1.00
0.60
Max
2.77
0.70
1.20
0.90
W
V
U
M
A1
A2
b
T
R
P
N
M
L
K
J
D
25.00 BSC
H
G
F
E
D
C
B
A
E
25.00 BSC
1.27 BSC
A2
A1
e
A
e
0.3 C A B
360X
b
C
0.15
Figure 20. Mechanical Dimensions and Bottom Surface Nomenclature of the MPC755 PBGA
MPC755 RISC Microprocessor Hardware Specifications
32
System Design Information
1.8 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC755.
1.8.1 PLL Configuration
The MPC755 PLL is configured by the PLL_CFG[0:3] signals. For a given SYSCLK (bus) frequency, the
PLL configuration signals set the internal CPU and VCO frequency of operation. The PLL configuration
for the MPC755 is shown in Table 16 for example frequencies.
Table 16. MPC755 Microprocessor PLL Configuration
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
PLL_CFG
Bus-to-
Core
Core-to
VCO
Bus
Bus
Bus
Bus
Bus
Bus
100 MHz
[0:3]
33 MHz
50 MHz
66 MHz
75 MHz
80 MHz
Multiplier
Multiplier
0100
1000
1110
1010
0111
1011
1001
1101
0101
0010
0001
1100
0110
0011
2x
3x
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
—
—
—
—
—
—
—
—
—
—
—
—
—
200
(400)
200
(400)
225
(450)
240
(480)
300
(600)
3.5x
4x
233
(466)
263
(525)
280
(560)
350
(700)
200
(400)
266
(533)
300
(600)
320
(640)
400
(800)
4.5x
5x
225
(450)
300
(600)
338
(675)
360
(720)
—
—
—
—
—
—
—
—
—
250
(500)
333
(666)
375
(750)
400
(800)
5.5x
6x
275
(550)
366
(733)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
200
(400)
300
(600)
400
(800)
6.5x
7x
216
(433)
325
(650)
—
—
—
—
—
233
(466)
350
(700)
7.5x
8x
250
(500)
375
(750)
266
(533)
400
(800)
10x
333
(666)
—
PLL off/bypass
PLL off, SYSCLK clocks core circuitry directly, 1x bus-to-core implied
MPC755 RISC Microprocessor Hardware Specifications
33
System Design Information
Table 16. MPC755 Microprocessor PLL Configuration (Continued)
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
Core-to
PLL_CFG
[0:3]
Bus-to-
Core
Multiplier
Bus
Bus
Bus
Bus
Bus
Bus
100 MHz
VCO
33 MHz
50 MHz
66 MHz
75 MHz
80 MHz
Multiplier
1111
PLL off
PLL off, no core clocking occurs
Notes:
1. PLL_CFG[0:3] settings not listed are reserved.
2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core,
or VCO frequencies which are not useful, not supported, or not tested for by the MPC755; see Section 1.4.2.1,
“Clock AC Specifications,” for valid SYSCLK, core, and VCO frequencies.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the
bus mode is set for 1:1 mode operation. This mode is intended for factory use and emulator tool use only.
Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.
4. In PLL-off mode, no clocking occurs inside the MPC755 regardless of the SYSCLK input.
The MPC755 generates the clock for the external L2 synchronous data SRAMs by dividing the core clock
frequency of the MPC755. The divided-down clock is then phase-adjusted by an on-chip delay-lock-loop
(DLL) circuit and should be routed from the MPC755 to the external RAMs. A separate clock output,
L2SYNC_OUT is sent out half the distance to the SRAMs and then returned as an input to the DLL on pin
L2SYNC_IN so that the rising-edge of the clock as seen at the external RAMs can be aligned to the clocking
of the internal latches in the L2 bus interface.
The core-to-L2 frequency divisor for the L2 PLL is selected through the L2CLK bits of the L2CR register.
Generally, the divisor must be chosen according to the frequency supported by the external RAMs, the
frequency of the MPC755 core, and the phase adjustment range that the L2 DLL supports. Table 17 shows
various example L2 clock frequencies that can be obtained for a given set of core frequencies. The minimum
L2 frequency target is 80 MHz.
Table 17. Sample Core-to-L2 Frequencies
Core Frequency
÷1
÷1.5
÷2
÷2.5
÷3
in MHz
250
266
275
300
325
333
350
366
375
400
250
266
275
300
325
333
350
366
375
400
166
177
183
200
217
222
233
244
250
266
125
133
138
150
163
167
175
183
188
200
100
106
110
120
130
133
140
146
150
160
83
89
92
100
108
111
117
122
125
133
Note: The core and L2 frequencies are for reference only. Some examples
may represent core or L2 frequencies which are not useful, not
supported, or not tested for by the MPC755; see Section 1.4.2.3, “L2
Clock AC Specifications,” for valid L2CLK frequencies. The
L2CR[L2SL] bit should be set for L2CLK frequencies less than
110 MHz.
34
MPC755 RISC Microprocessor Hardware Specifications
System Design Information
1.8.2 PLL Power Supply Filtering
The AVdd and L2AVdd power signals are provided on the MPC755 to provide power to the clock generation
phase-locked loop and L2 cache delay-locked loop respectively. To ensure stability of the internal clock, the
power supplied to the AVdd input signal should be filtered of any noise in the 500 kHz to 10 MHz resonant
frequency range of the PLL. A circuit similar to the one shown in Figure 21 using surface mount capacitors
with minimum Effective Series Inductance (ESL) is recommended. Consistent with the recommendations
of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993),
multiple small capacitors of equal value are recommended over a single large value capacitor.
The circuit should be placed as close as possible to the AVdd pin to minimize noise coupled from nearby
circuits. An identical but separate circuit should be placed as close as possible to the L2AVdd pin. It is often
possible to route directly from the capacitors to the AVdd pin, which is on the periphery of the 360 BGA
footprint, without the inductance of vias. The L2AVdd pin may be more difficult to route, but is
proportionately less critical.
FIgure 21 shows the PLL power supply filter circuit.
10 Ω
Vdd
AVdd (or L2AVdd)
2.2 µF
2.2 µF
Low ESL surface mount capacitors
GND
Figure 21. PLL Power Supply Filter Circuit
1.8.3 Power Supply Voltage Sequencing
The notes in Figure 1 contain cautions about the sequencing of the external bus voltages and core voltage
of the MPC755 (when they are different). These cautions are necessary for the long term reliability of the
part. If they are violated, the ESD (Electrostatic Discharge) protection diodes will be forward biased and
excessive current can flow through these diodes. If the system power supply design does not control the
voltage sequencing, the circuit of Figure 22 can be added to meet these requirements. The MURS320
Schottky diodes of Figure 22 control the maximum potential difference between the external bus and core
power supplies on power-up and the 1N5820 diodes regulate the maximum potential difference on
power-down.
3.3 V
2.0 V
MURS320
MURS320
1N5820
1N5820
Figure 22. Example Voltage Sequencing Circuit
1.8.4 Decoupling Recommendations
Due to the MPC755 dynamic power management feature, large address and data buses, and high operating
frequencies, the MPC755 can generate transient power surges and high frequency noise in its power supply,
MPC755 RISC Microprocessor Hardware Specifications
35
System Design Information
especially while driving large capacitive loads. This noise must be prevented from reaching other
components in the MPC755 system, and the MPC755 itself requires a clean, tightly regulated source of
power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each
Vdd, OVdd, and L2OVdd pin of the MPC755. It is also recommended that these decoupling capacitors
receive their power from separate Vdd, (L2)OVdd, and GND power planes in the PCB, utilizing short traces
to minimize inductance.
These capacitors should have a value of 0.01 µF or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0508 or 0603 orientations where
connections are made along the length of the part.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the Vdd, L2OVdd, and OVdd planes, to enable quick recharging of the smaller chip capacitors.
These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick
response time necessary. They should also be connected to the power and ground planes through two vias
to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS tantalum or Sanyo OSCON).
1.8.5 Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level through a resistor. Unused active low inputs should be tied to OVdd. Unused active high inputs should
be connected to GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external Vdd, OVdd, L2OVdd, and GND pins of the
MPC755.
1.8.6 Output Buffer DC Impedance
The MPC755 60x and L2 I/O drivers are characterized over process, voltage, and temperature. To measure
Z , an external resistor is connected from the chip pad to (L2)OVdd or GND. Then, the value of each resistor
0
is varied until the pad voltage is (L2)OVdd/2 (See Figure 23).
The output impedance is the average of two components, the resistances of the pull-up and pull-down
devices. When Data is held low, SW2 is closed (SW1 is open), and R is trimmed until the voltage at the
N
pad equals (L2)OVdd/2. R then becomes the resistance of the pull-down devices. When Data is held high,
N
SW1 is closed (SW2 is open), and R is trimmed until the voltage at the pad equals (L2)OVdd/2. R then
P
P
becomes the resistance of the pull-up devices.
Figure 23 describes the driver impedance measurement circuit described above.
36
MPC755 RISC Microprocessor Hardware Specifications
System Design Information
(L2)OVdd
RN
(L2)OVdd
SW2
SW1
Pad
Data
RP
OGND
Figure 23. Driver Impedance Measurement Circuit
Alternately, the following is another method to determine the output impedance of the MPC755. A voltage
source, V
, is connected to the output of the MPC755 as in Figure 24. Data is held low, the voltage source
force
is set to a value that is equal to (L2)OVdd/2 and the current sourced by V
is measured. The voltage drop
force
across the pulldown device, which is equal to (L2)OVdd/2, is divided by the measured current to determine
the output impedance of the pulldown device, R . Similarly, the impedance of the pullup device is
N
determined by dividing the voltage drop of the pullup, (L2)OVdd/2, by the current sank by the pullup when
the data is high and Vforce is equal to (L2)OVdd/2. This method can be employed with either empirical data
from a test set up or with data from simulation models, such as IBIS.
R and R are designed to be close to each other in value. Then Z = (R + R )/2.
P
N
0
P
N
Figure 24 describes the alternate driver impedance measurement circuit.
(L2)OVdd
BGA
Pin
Data
Vforce
OGND
Figure 24. Alternate Driver Impedance Measurement Circuit
Table 18 summarizes the signal impedance results. The driver impedance values were characterized at 0°,
65°, and 105°C. The impedance increases with junction temperature and is relatively unaffected by bus
voltage.
MPC755 RISC Microprocessor Hardware Specifications
37
System Design Information
Table 18. Impedance Characteristics
Vdd = 2.0 V, OVdd = 3.3 V, Tj = 0–105°C
Impedance
Processor Bus
25–36
L2 Bus
25-36
Symbol
Z0
Unit
ohms
ohms
R
N
R
26–39
26-39
Z0
P
1.8.7 Pull-up Resistor Requirements
The MPC755 requires high-resistive (weak: 10 kΩ) pull-up resistors on several control pins of the bus
interface to maintain the control signals in the negated state after they have been actively negated and
released by the MPC755 or other bus masters. These pins are TS, ABB, DBB, and ARTRY.
Three test pins also require pull-up resistors (weak or stronger: 4.7 kΩ–10 kΩ). These pins are
L1_TSTCLK, L2_TSTCLK, and LSSD_MODE. These signals are for factory use only and must be
pulled up to OVdd for normal machine operation.
In addition, the MPC755 has one open-drain style output that requires a pull-up resistor (weak or stronger:
4.7 kΩ–10 kΩ) if it is used by the system. This pin is CKSTP_OUT.
During inactive periods on the bus, the address and transfer attributes may not be driven by any master and
may, therefore, float in the high-impedance state for relatively long periods of time. Since the MPC755 must
continually monitor these signals for snooping, this float condition may cause excessive power draw by the
input receivers on the MPC755 or by other receivers in the system. It is recommended that these signals be
pulled up through weak (10 kΩ) pull-up resistors by the system, or that they may be otherwise driven by the
system during inactive periods of the bus. The snooped address and transfer attribute inputs are: A[0:31],
AP[0:3], TT[0:4], TBST, and GBL.
The data bus input receivers are normally turned off when no read operation is in progress and, therefore,
do not require pull-up resistors on the bus. Other data bus receivers in the system, however, may require
pullups, or that those signals be otherwise driven by the system during inactive periods by the system. The
data bus signals are: DH[0:31], DL[0:31], and DP[0:7].
If 32-bit data bus mode is selected, the input receivers of the unused data and parity bits will be disabled,
and their outputs will drive logic zeros when they would otherwise normally be driven. For this mode, these
pins do not require pull-up resistors, and should be left unconnected by the system to minimize possible
output switching.
If address or data parity is not used by the system, and the respective parity checking is disabled through
HID0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and
should be left unconnected by the system. If all parity generation is disabled through HID0, then all parity
checking should also be disabled through HID0, and all parity pins may be left unconnected by the system.
The L2 interface does not normally require pull-up resistors.
1.8.8 JTAG Configuration Signals
Boundary scan testing is enabled through the JTAG interface signals. (BSDL descriptions of the MPC755
are available on the internet at www.mot.com/PowerPC/teksupport.) The TRST signal is optional in the
IEEE 1149.1 specification but is provided on all PowerPC implementations. While it is possible to force the
TAP controller to the reset state using only the TCK and TMS signals, more reliable power-on reset
performance will be obtained if the TRST signal is asserted during power-on reset. Since the JTAG interface
is also used for accessing the common on-chip processor (COP) function of PowerPC processors, simply
tying TRST to HRESET isn’t practical.
38
MPC755 RISC Microprocessor Hardware Specifications
System Design Information
The common on-chip processor (COP) function of PowerPC processors allows a remote computer system
(typically a PC with dedicated hardware and debugging software) to access and control the internal
operations of the processor. The COP interface connects primarily through the JTAG port of the processor,
with some additional status monitoring signals. The COP port requires the ability to independently assert
HRESET or TRST in order to fully control the processor. If the target system has independent reset sources,
such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the COP
reset signals must be merged into these signals with logic.
The arrangement shown in Figure 25 allows the COP to independently assert HRESET or TRST, while
ensuring that the target can drive HRESET as well. The pull-down resistor on TRST ensures that the JTAG
scan chain is initialized during power-on if a JTAG interface cable is not attached; if it is, it is responsible
for driving TRST when needed.
Figure 25 shows the suggested TRST connection.
MPC755
HRESET
HRESET
From Target
Board
Sources
QACK
QACK
TRST
2 kΩ 2 kΩ
COP Header
Figure 25. Suggested TRST Connection
The COP header shown in Figure 25 adds many benefits—breakpoints, watchpoints, register and memory
examination/modification, and other standard debugger features are possible through this interface—and
can be as inexpensive as an unpopulated footprint for a header to be added when needed.
The COP interface has a standard header for connection to the target system, based on the 0.025"
square-post 0.100" centered header assembly (often called a “Berg” header). The connector typically has
pin 14 removed as a connector key.
Figure 26 shows the COP connector diagram.
MPC755 RISC Microprocessor Hardware Specifications
39
System Design Information
TOP VIEW
13
15
16
11
9
7
8
5
6
3
4
1
2
KEY
Pins 10, 12 and 14 are no-connects.
Pin 14 is not physically present
12 10
No pin
Figure 26. COP Connector Diagram
There is no standardized way to number the COP header shown in Figure 26; consequently, many different
pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then
left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter
clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in
Figure 26 is common to all known emulators.
The QACK signal shown in Table 19 is usually hooked up to the PCI bridge chip in a system and is an input
to the MPC755 informing it that it can go into the quiescent state. Under normal operation this occurs during
a low power mode selection. In order for COP to work the MPC755 must see this signal asserted (pulled
down). While shown on the COP header, not all emulator products drive this signal. To preserve correct
power down operation, QACK should be merged so that it also can be driven by the PCI bridge.
Table 19 shows the pin definitions.
Table 19. COP Pin Definitions
Pins
Signal
Connection
TDO
Special Notes
1
2
TDO
QACK
QACK
Add 2k pulldown to ground. Must be merged with on-board QACK, if
any.
3
4
TDI
TDI
TRST
TRST
Add 2k pulldown to ground. Must be merged with on-board TRST, if any.
See Figure 25.
5
6
7
8
RUN/STOP
VDD_SENSE
TCK
No Connect
VDD
Used on 604e; leave no-connect for all other processors.
Add 2k pullup to OVDD (for short circuit limiting protection only).
TCK
CKSTP_IN
CKSTP_IN
Optional. Add 10k pullup to OVDD. Used on several emulator products.
Useful for checkstopping the processor from a logic analyzer of other
external trigger.
9
TMS
TMS
40
MPC755 RISC Microprocessor Hardware Specifications
System Design Information
Table 19. COP Pin Definitions (Continued)
Connection Special Notes
Pins
10
Signal
N/A
11
12
13
14
15
16
SRESET
N/A
SRESET
HRESET
Merge with on-board SRESET, if any.
HRESET
N/A
Merge with on-board HRESET.
Key location; pin should be removed.
Add 10k pullup to OVDD.
CKSTP_OUT
Ground
CKSTP_OUT
Digital Ground
1.8.9 Thermal Management Information
This section provides thermal management information for the ceramic ball grid array (CBGA) package for
air-cooled applications. Proper thermal control design is primarily dependent upon the system-level
design—the heat sink, airflow and thermal interface material. To reduce the die-junction temperature, heat
sinks may be attached to the package by several methods—adhesive, spring clip to holes in the
printed-circuit board or package, and mounting clip and screw assembly; see Figure 27. This spring force
should not exceed 5.5 pounds of force.
Figure 27 describes the package exploded cross-sectional view with several heat sink options.
CBGA Package
Heat Sink
Heat Sink
Clip
Adhesive
or
Thermal Interface Material
Printed-Circuit Board
Option
Figure 27. Package Exploded Cross-Sectional View with Several Heat Sink Options
The board designer can choose between several types of heat sinks to place on the MPC755. There are
several commercially-available heat sinks for the MPC755 provided by the following vendors:
Chip Coolers Inc.
333 Strawberry Field Rd.
Warwick, RI 02887-6979
800-227-0254 (USA/Canada)
401-739-7600
International Electronic Research Corporation (IERC)
818-842-7277
MPC755 RISC Microprocessor Hardware Specifications
41
System Design Information
135 W. Magnolia Blvd.
Burbank, CA 91502
Thermalloy
214-243-4321
2021 W. Valley View Lane
P.O. Box 810839
Dallas, TX 75731
Wakefield Engineering
60 Audubon Rd.
Wakefield, MA 01880
617-245-5900
603-528-3400
Aavid Engineering
One Kool Path
Laconia, NH 03247-0440
Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal
performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost.
1.8.9.1 Internal Package Conduction Resistance
For the exposed-die packaging technology, shown in Table 4, the intrinsic conduction thermal resistance
paths are as follows:
•
•
The die junction-to-case (or top-of-die for exposed silicon) thermal resistance
The die junction-to-ball thermal resistance
Figure 28 depicts the primary heat transfer path for a package with an attached heat sink mounted to a
printed-circuit board.
External Resistance
Radiation
Convection
Heat Sink
Thermal Interface Material
Die/Package
Die Junction
Internal Resistance
Package/Leads
Printed-Circuit Board
Radiation
Convection
External Resistance
(Note the internal versus external package resistance)
Figure 28. C4 Package with Heat Sink Mounted to a Printed-Circuit Board
Heat generated on the active side of the chip is conducted through the silicon, then through the heat sink
attach material (or thermal interface material), and finally to the heat sink where it is removed by forced-air
convection.
Since the silicon thermal resistance is quite small, for a first-order analysis, the temperature drop in the
silicon may be neglected. Thus, the heat sink attach material and the heat sink conduction/convective
42
MPC755 RISC Microprocessor Hardware Specifications
System Design Information
thermal resistances are the dominant terms.
1.8.9.2 Adhesives and Thermal Interface Materials
A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the
thermal contact resistance. For those applications where the heat sink is attached by spring clip mechanism,
Figure 29 shows the thermal performance of three thin-sheet thermal-interface materials (silicone,
graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure.
As shown, the performance of these thermal interface materials improves with increasing contact pressure.
The use of thermal grease significantly reduces the interface thermal resistance. That is, the bare joint results
in a thermal resistance approximately seven times greater than the thermal grease joint.
Heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see
Figure 27). This spring force should not exceed 5.5 pounds of force. Therefore, the synthetic grease offers
the best thermal performance, considering the low interface pressure. Of course, the selection of any thermal
interface material depends on many factors—thermal performance requirements, manufacturability, service
temperature, dielectric properties, cost, etc.
Figure 29 describes the thermal performance of select thermal interface materials.
Silicone Sheet (0.006 inch)
Bare Joint
2
Floroether Oil Sheet (0.007 inch)
Graphite/Oil Sheet (0.005 inch)
Synthetic Grease
1.5
1
0.5
0
0
10
20
30
Contact Pressure (psi)
Figure 29. Thermal Performance of Select Thermal Interface Materials
40
50
60
70
80
The board designer can choose between several types of thermal interface. Heat sink adhesive materials
should be selected based upon high conductivity, yet adequate mechanical strength to meet equipment
shock/vibration requirements. There are several commercially-available thermal interfaces and adhesive
materials provided by the following vendors:
MPC755 RISC Microprocessor Hardware Specifications
43
System Design Information
Dow-Corning Corporation
Dow-Corning Electronic Materials
PO Box 0997
517-496-4000
Midland, MI 48686-0997
Chomerics, Inc.
77 Dragon Court
Woburn, MA 01888-4850
617-935-4850
216-741-7659
860-571-5100
609-882-2332
Thermagon Inc.
3256 West 25th Street
Cleveland, OH 44109-1668
Loctite Corporation
1001 Trout Brook Crossing
Rocky Hill, CT 06067
AI Technology (e.g. EG7655)
1425 Lower Ferry Rd.
Trent, NJ 08618
1.8.9.3 Heat Sink Selection Example
This section provides a heat sink selection example using one of the commercially available heat sinks. For
preliminary heat sink sizing, the die-junction temperature can be expressed as follows:
T = T + T + (θ + θ + θ ) * P
d
j
a
r
jc
int
sa
Where:
T is the die-junction temperature
j
T is the inlet cabinet ambient temperature
a
T is the air temperature rise within the computer cabinet
r
θ is the junction-to-case thermal resistance
jc
θ
θ
is the adhesive or interface material thermal resistance
is the heat sink base-to-ambient thermal resistance
int
sa
P is the power dissipated by the device
d
During operation the die-junction temperatures (T ) should be maintained less than the value specified in
j
Table 3. The temperature of the air cooling the component greatly depends upon the ambient inlet air
temperature and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air
temperature (T ) may range from 30° to 40°C. The air temperature rise within a cabinet (T ) may be in the
a
r
range of 5° to 10°C. The thermal resistance of the thermal interface material (θ ) is typically about 1°C/W.
int
Assuming a T of 30°C, a T of 5°C, a CBGA package θ = 0.03, and a power consumption (P ) of 5.0 W,
a
r
jc
d
the following expression for T is obtained:
j
Die-junction temperature: T = 30°C + 5°C + (0.03°C/W + 1.0°C/W + θ ) * 5.0 W
j
sa
For a Thermalloy heat sink #2328B, the heat sink-to-ambient thermal resistance (θ ) versus airflow
sa
velocity is shown in Figure 30.
44
MPC755 RISC Microprocessor Hardware Specifications
System Design Information
8
7
6
5
4
3
2
1
Thermalloy #2328B Pin-fin Heat Sink
(25 x28 x 15 mm)
0
0.5
1
1.5
2
2.5
3
3.5
Approach Air Velocity (m/s)
Figure 30. Thermalloy #2328B Heat Sink-to-Ambient Thermal Resistance Versus Airflow Velocity
Assuming an air velocity of 0.5 m/s, we have an effective R of 7°C/W, thus
sa
Tj = 30°C + 5°C + (0.03°C/W +1.0°C/W + 7°C/W) * 5.0 W,
resulting in a die-junction temperature of approximately 75°C which is well within the maximum operating
temperature of the component.
Other heat sinks offered by Chip Coolers, IERC, Thermalloy, Wakefield Engineering, and Aavid
Engineering offer different heat sink-to-ambient thermal resistances, and may or may not need air flow.
Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common
figure-of-merit used for comparing the thermal performance of various microelectronic packaging
technologies, one should exercise caution when only using this metric in determining thermal management
because no single parameter can adequately describe three-dimensional heat flow. The final die-junction
operating temperature, is not only a function of the component-level thermal resistance, but the system-level
design and its operating conditions. In addition to the component's power consumption, a number of factors
affect the final operating die-junction temperature—airflow, board population (local heat flux of adjacent
components), heat sink efficiency, heat sink attach, heat sink placement, next-level interconnect technology,
system air temperature rise, altitude, etc.
Due to the complexity and the many variations of system-level boundary conditions for today's
microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection,
and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models
for the board, as well as, system-level designs. To expedite system-level thermal analysis, several
“compact” thermal-package models are available within FLOTHERM®. These are available upon request.
MPC755 RISC Microprocessor Hardware Specifications
45
Document Revision History
1.9 Document Revision History
Table 20 provides a revision history for this hardware specification.
Table 20. Document Revision History
Document Revision
Substantive Change(s)
Rev 0
Rev 1
Product announced. Documentation made publicly available.
Corrected errors in Section 1.2, “Features”.
Removed references to MPC745 CBGA package in Sections 1.3 and 1.4.
Added airflow values for θJA to Table 5.
Corrected VIH maximum for 1.8V mode in Table 6.
Power consumption values added to Table 7.
Corrected tMXRH in Table 9, deleted Note 2 application note reference.
Added Max fL2CLK and Min tL2CLK values to Table 11.
Updated timing values in Table 12.
Corrected Note 2 of Table 13.
Changed Table 14 to reflect I/F voltages supported.
Removed 133 MHz and 150 MHz columns from Table 16.
Added document reference to Section 1.7.
Added DBB to list of signals requiring pull-ups in Section 1.8.7.
Removed log entries from Table 20 for revisions prior to public release.
1.8 V/2.0 V mode no longer supported; added 2.5 V support.
Removed 1.8 V/2.0 V mode data from Table 2, Table 3, and Table 6.
Added 2.5 V mode data to Table 2, Table 3, and Table 6.
Rev 2
Extended recommended operating voltage (down to 1.8 V) for Vdd, AVdd,
and L2AVdd for 300 MHz and 350 MHz parts in Table 3.
Updated Table 7 and test conditions for power consumption specifications.
Corrected Note 6 of Table 9 to include TLBISYNC as a mode-select signal.
Updated AC timing specifications in Table 10.
Updated AC timing specifications in Table 12.
Corrected AC timing specifications in Table 13.
Added L1_TSTCLK, L2_TSTCLK, and LSSD_MODE pull-up requirements
to Section 1.8.7, “Pull-up Resistor Requirements”.
Corrected Figure 22.
46
MPC755 RISC Microprocessor Hardware Specifications
Ordering Information
1.10 Ordering Information
This section provides the part numbering nomenclature for the MPC755. Note that the individual part
numbers correspond to a maximum processor core frequency. For available frequencies, contact your local
Motorola sales office.
Figure 31 provides the Motorola part numbering nomenclature for the MPC755. In addition to the processor
frequency, the part numbering scheme also consists of a part modifier and application modifier. The part
modifier indicates any enhancement(s) in the part from the original production design. The application
modifier may specify special bus frequencies or application conditions. Each part number also contains a
revision code. This refers to the die mask revision number and is specified in the part numbering scheme for
identification purposes only.
MPC 755 B PX XXX L X
Revision Level
(Contact Local Motorola Sales Office)
Product Code
Application Modifier
Part Identifier
(745 or 755)
(L = 2.0 V ± 100 mV, 0° to 100°C)
Process Descriptor
(B = HiP4DP)
Processor Frequency
Package
(RX = CBGA)
(PX = PBGA)
Figure 31. Motorola Part Number Key
MPC755 RISC Microprocessor Hardware Specifications
47
DigitalDNA is a trademark of Motorola, Inc.
The PowerPC name, the PowerPC logotype, and PowerPC 603e are trademarks of International Business Machines Corporation used by Motorola
under license from International Business Machines Corporation.
Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors. There are no express
or implied copyright licenses granted hereunder to design or fabricate PowerPC integrated circuits or integrated circuits based on the information in
this document.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee
regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any
product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters
which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as
components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other
application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or
use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
is an Equal Opportunity/Affirmative Action Employer.
are registered trademarks of Motorola, Inc. Motorola, Inc.
HOW TO REACH US:
USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or
1-800-441-2447
JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569
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